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On Aug 7, 6:30 pm, austin <aus...@xilinx.com> wrote: > Symon, > > Well, all I can say, is that this is an attempt to improve our service. > > As everyone here knows, c.a.f. is open to everyone, and anyone, and > there is no censorship (so most Xilinx employees will not post here). > > It was felt that a true Xilinx sponsored forum might be beneficial - > allow direct communication. > > Obviously, Peter and I feel a little odd, as we felt we were doing a > good job here on c.a.f. (Perhaps we are, but more is needed?). > > But, in defense of those who feel that a "real Xilinx forum" has value, > I am going to advise folks to give it a try. > > After all, if people use it, and find it valuable, then it serves a purpose. > > If it is of no utility, it will die a natural 'Internet Death', and go away. > > Take it as an opportunity. After all, there will be 'real' applications > engineers and hotline folks who will be monitoring this new forum (whose > job it is to make customers happy). > > For every post here, I must consider my competition is reading every > word, and just waiting to pounce. That does not allow me the freedom > that some other forum might offer. > > Austin Xilinx has had private forums for years (http://toolbox.xilinx.com/cgi- bin/forum). I read them for a while, but it seemed that many people were posting questions, but very few were answered. What will be different about this new deal? BarryArticle: 122851
>> >> Could you use the mch_opb_sdram controller from Xilinx EDK in >> your >> application ? > > The mch_opb_sdram controller is the same shit. He would only get a > bunch of stuff that he does not need and low bandwidth. Has anybody tried the new version of the Multi Port Memory Controller ? Now comes with many interfaces, among them OPB and a simple general purpose... http://www.xilinx.com/esp/wired/optical/xlnx_net/mpmc.htm (require registration) Waiting for some spare time to give it a try...Article: 122852
Barry, What will be new? I really don't know. I have looked at the webpages, and templates, and it seems to me, that since staff are assigned to reply and participate, this might be very useful. AustinArticle: 122853
> >I'm sorry, but this doesn't make sense. We (Xilinx) can provide an EDK 8.1i >release if necessary. We would prefer not to unless there as a really good >reason to do so as the later version of the software would be much better >choice. > >But, your original post mentioned that you were targeting a MK325 board which >is a Virtex-II Pro X FF1704 RocketIO Characterization Platform and that you >needed EDK to be able to program this board. Why do you need to use EDK >at all for this board as it has very little to do with the use of the PPC405 >that is in the device? The current generation of iMPACT and ChipScope should >all be able to download images into these devices. > >Ed McGettigan >-- >Xilinx Inc. > Ed Thanks for the response. I agree that we could have used iMPACT and ChipScope to download images (although we are not very proficient with ChipScope). This whole thing started out with trying to modify the default programs that came with the flash card. We are trying to do pattern generation and one simple alternative that was suggested was to modify the default pattern and generate the new system.xmp. We needed EDK to do that. We could not find our EDK 8.1, which is when I posted the first message. Since then we got ISE and EDK 9.1 and used that. Unfortunately the 9.1 XPS gave an error when we tried to read the XMP. The error was something like the GPIO_IN and GPIO_OUT that are part of BUS_IF have no default connection. It turned out that the original file was generated using EDK6.3 and that there might be compatibility problems. So now we have gone back to using 6.3 and hoping that it all works out. This seems so complicated and I have a feeling that there are simpler solutions to this than we know. So any feedback is appreciated. Thanks EchoArticle: 122854
Hello, I have designed a IP Slave connected to the PLB bus.
My IP Slave to the PLB is a Bus bridge which connect the PLB to
another Bus and a Coprocessor connected to this other Bus. My second
bus allow transfer of 64 bits and there is a DMA conected to this bus.
I want to write to data of 64 bits to the addres 0x2000 and 0x2001,
the addres of the DMA. If I write this data the DMA start to work and
copy from a memory to a Bram conected to the plb in the memory addres
FF000000
I need to transfer these data:
addr= 0x00002000 data=0x00000000FF000000 // source (bram) in the
second bus and Destination (bram in the plb)
addr= 0x00002001 data=0x0000000100000005 //start data and Frame
relay ( a burst of 5 double words stored previously in the bram of the
second bus)
I want to do it from the PowerPC, that means I have to create a C
program to do it. The drivers created for Xilinxs Platform Studio make
transaction of 32 bits. They make also transaction of a Struct of 64
bits, with lower and Upper part. This transaction takes place in two
operations. First copy to addr 0x00002000 the data 0x00000000 00000000
and with a BE byte enable to choose only the first 32 bits and write
to the address 0x2004 of the data 0x FF000000 FF000000. with byte
enable. But this is not the operation that I need to run the DMA.
Have someone any idea?
I saw this information in this forum, that was written in 2006, I
would like to know if one year later have someone a solution. Thank
you
Question:
I have a piece of IP that acts as a slave on the PLB. I would like
writes to this IP to be 64bits, while reads from it are OK at 32bits.
The sample driver that was generated by the IP wizard gives functions
for reads/writes or 32 bits as expected (by mapping them to
XIo_In/Out32). Do I need to do writes in two transfers? If not, how
do I write 64bits? I've looked over the PPC 405 Block Reference
Guide
and it seems that it should be possible to read/write 64 bits all at
once just by virtue of having that wide of a bus coming in and out of
the block. The cacheline transfers are discussed in that document as
possibly being doublewords. I am a bit confused by all of this (if
that
wasn't clear already). I would probably be able to find my answer
after a good deal of time/pain, but hopefully someone out there can
clarify things a little for me. Just knowing if it was possible or
not
for a user program to do the 64bit write would help me move forward.
I'd appreciate any clarification and/or pointers to relevant
documentation. I can provide more info about my design or my
confusion
if it is useful.
Answer:
The fundamental limitation here is that the PowerPC-405 is a 32-bit
core. So
there are no instructions to load/store 64 bits of data at a time as
an
atomic unit. So from the processor core's perspective, you have to do
two
32-bit stores. (The XIo_In and XIo_Out functions are basically just a
wrapper around load/store instructions, but with an added "eieio" to
make
sure the operations don't get re-ordered by the hardware.)
As you say, the PLB is in fact capable of doing multi-word transfers,
and is
wide enough to do 64-bit transfers in a single data beat. However,
aside
from enabling this functionality in the first place, the prWocessor
has no
control over whether this actually occurs.
Without having done any experiments, my gut feeling is that using two
calls
to XIo_Out() back to back will not result in a 64-bit transfer,
because of
these "eieio"s. Your best bet is probably to try something like:
typedef unsigned long long bits64;
volatile bits64 *my_reg = (volatile bits64 *)(REG_ADDRESS);
*my_reg = some_value;
...and then watch the bus and see what happens.
Hope that helps, or least makes sense... :)
typedef unsigned long long My_Xuint64 ;
I tried with this, but the result is the same.
volatile My_Xuint64 *my_reg = (volatile My_Xuint64 *)
(XPAR_P2O_0_BASEADDR);
*my_reg = 0x0000000100000002;
I get a warning which says that the value is too big for a "long"
type, but I defined it like a long long. I do not. I am also confused
like the other guy.
Article: 122855Hi, Can someone please point me in the right direction. I attempted to define my LVDS inputs via the UCF file for my Xilinx spartan xc3s1500. NET data_in LOC = F19 | IOSTANDARD = LVDS_25 ; the Xilinx answer record impies that this will work OK. http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=8187 Unfortunately I get the following warning, and the input is set to a standard LVCMOS25. WARNING:Pack:946 - The I/O component data_in has an illegal I/O standard value. Components of type IOB do not support I/O standard LVDS_25. Please correct the IOSTANDARD property value. I am using ISE 8.2 (Release 8.2.03i Map I.34) Any ideas what I am doing wrong? Do I need to istantiate the I/O buffers? Thanks for any input, StevenArticle: 122856
<moogyd@yahoo.co.uk> wrote in message news:1186593169.119748.316150@q75g2000hsh.googlegroups.com... > Hi, > I attempted to define my LVDS inputs via the UCF file for my Xilinx > spartan xc3s1500. > > NET data_in LOC = F19 | IOSTANDARD = LVDS_25 ; > > > WARNING:Pack:946 - The I/O component data_in has an illegal I/O > standard value. Components of type IOB do not support I/O standard > LVDS_25. > Please correct the IOSTANDARD property value. > Hi Steven, I usually instantiate the IBUFDS (see libraries guide) in my HDL and go from there. Don't forget your terminations... INST "LVDS_P" DIFF_TERM = TRUE; INST "LVDS_N" DIFF_TERM = TRUE; Also, the tools sometimes get their knickers in a twist about 3.3V and 2.5V banks. Googling should solve that for you. HTH., Syms.Article: 122857
> > I'm uncomfortable with an FPGA forum controlled by one of the de facto > duopoly. (Sorry 'L' :-| ) I'd prefer they spent their effort on the public > forum we already have. > Symon, Altera has been involved in several web forums for customers discussing its products for quite a while now. The Nios forum (www.niosforum.com) has been around since about 2004 as I recall. About the only moderating I've seen done was removing spam before the forum software could be updated to filter out bogus registrations. Many people voice their design problems, questions, rants, etc., as you would expect. There has been a great involvement with users helping each other as well as employees fielding questions. I'm not as active there as I used to be but I don't see any signs of that changing. It has seen quite a lot of traffic and a large user base develop over the years. More recently, Altera launched another forum site for general Altera tools/devices/etc (www.alteraforum.com). Anyway, I cannot speak for how X will run their new forum site, but before casting blanket judgment I invite you to browse around at the existing sites to see how they are run and what people are posting/ what support they're getting out of it. At the same time, I can see how a brand-agnostic technology forum would be great. For now, it seems that this news group continues to fill that void. I've seen several FPGA related but non-brand-specific web sites start over the past several years but have not seen many take root. There is a great deal of functionality that a modern web based forum can provide that leaves usenet in the dust anyways. For example, being able to freely host design files showing an example, screen shot of a problem, etc.; things usenet will ultimately die off to. (Nothing against c.a.f per se; this is about the only of several news groups I used to read that still looks interesting at all). Jesse Kempa AlteraArticle: 122858
austin wrote: > DJ, > > Xilinx has policies about employees communicating in any public forum > (like any company). Anything posted here by an employee has to be in > compliance with Xilinx policies. Violation of these policies is grounds > for dismissal. Only for FPGA related topics or for anything ? In anycase, that doesn't sounds quite right to me ... but maybe it's common in the US ... SylvainArticle: 122859
<kempaj@yahoo.com> wrote in message
news:1186594403.794741.205010@x40g2000prg.googlegroups.com...
> >
>> I'm uncomfortable with an FPGA forum controlled by one of the de facto
>> duopoly. (Sorry 'L' :-| ) I'd prefer they spent their effort on the
>> public
>> forum we already have.
>>
>
> Symon,
>
<snip>
> what support they're getting out of it. At the same time, I can see
> how a brand-agnostic technology forum would be great. For now, it
> seems that this news group continues to fill that void. I've seen
> several FPGA related but non-brand-specific web sites start over the
> past several years but have not seen many take root.
>
> There is a great deal of functionality that a modern web based forum
> can provide that leaves usenet in the dust anyways. For example, being
> able to freely host design files showing an example, screen shot of a
> problem, etc.; things usenet will ultimately die off to. (Nothing
> against c.a.f per se; this is about the only of several news groups I
> used to read that still looks interesting at all).
>
> Jesse Kempa
> Altera
>
Hi Jesse,
Thanks for those good points in your post. I agree that pictures may be a
help, that ASCII art sometimes runs out of steam.
However, even today when I've not just returned from the pub {ahem}, I still
think the 'brand-agnostic' argument still swings it for me at the moment. It
might be hard for a company to leave critical comments on its own website.
Those bloody shareholders might start complaining...
Anyway, time will tell.
Thanks again for replying.
Cheers, Syms.
Article: 122860
kempaj@yahoo.com wrote:
> For example, being
> able to freely host design files showing an example, screen shot of a
> problem, etc.; things usenet will ultimately die off to.
Usenet is not yet moribund.
Ideas work fine in text, and
it's quite easy to post an http link
to a pdf/graphic file when need be.
Most internet providers allow
customers a free ftp account and a
moderate amount of free space
to play with.
-- Mike Treseler
Article: 122861Do you realize that the LVDS *is* a differential signals and requires two pins to be defined in the design file? <moogyd@yahoo.co.uk> wrote in message news:1186593169.119748.316150@q75g2000hsh.googlegroups.com... > Hi, > > Can someone please point me in the right direction. > > I attempted to define my LVDS inputs via the UCF file for my Xilinx > spartan xc3s1500. > > NET data_in LOC = F19 | IOSTANDARD = LVDS_25 ; > > the Xilinx answer record impies that this will work OK. > > http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=8187 > > Unfortunately I get the following warning, and the input is set to a > standard LVCMOS25. > > WARNING:Pack:946 - The I/O component data_in has an illegal I/O > standard value. Components of type IOB do not support I/O standard > LVDS_25. > Please correct the IOSTANDARD property value. > > I am using ISE 8.2 (Release 8.2.03i Map I.34) > > Any ideas what I am doing wrong? Do I need to istantiate the I/O > buffers? > > Thanks for any input, > > StevenArticle: 122862
I heard about this forum a while ago, and I will participate there as well as here at comp.arch.fpga. I am sure that more Xilinx employees will participate in the forum, since it is a more sheltered environment. I like analogies: Participating in c.a.f. is like standing on a soapbox at Hyde Park Corner, surrounded by people who throw questions (friendly or nasty, open or anonymous) at you, and you want to answer them as best as possible, while you sometimes get quite annoyed by certain questions. Keeping your cool, keeping your professional reputation, and staying loyal to your employer is not an easy juggling task, in a critical and sometimes hostile environment. That's why so few people from Xilinx or Altera appear here. A forum is more like inviting some people for a beer in a pub, to have a sensible conversation, where you can let your hair down, and maintain a more civilized atmosphere, ans use more than only ASCII characters. We'll see how it turns out. I will join both parties, as will Austin. PeterArticle: 122863
austin <austin@xilinx.com> wrote: >Symon, > >Well, all I can say, is that this is an attempt to improve our service. > >As everyone here knows, c.a.f. is open to everyone, and anyone, and >there is no censorship (so most Xilinx employees will not post here). > >It was felt that a true Xilinx sponsored forum might be beneficial - >allow direct communication. > >Obviously, Peter and I feel a little odd, as we felt we were doing a >good job here on c.a.f. (Perhaps we are, but more is needed?). More would be nice. The Xilinx website ain't the most user friendly and fastest website. In fact, I try to avoid it if possible. Okay, it is not so bad as NXP's website (which is about the worst possible website). <rant> 'Let's make things better' didn't happen and 'sense and simplicity'... well they should get a dictionary... </rant> >But, in defense of those who feel that a "real Xilinx forum" has value, >I am going to advise folks to give it a try. > >After all, if people use it, and find it valuable, then it serves a purpose. > >If it is of no utility, it will die a natural 'Internet Death', and go away. > >Take it as an opportunity. After all, there will be 'real' applications >engineers and hotline folks who will be monitoring this new forum (whose >job it is to make customers happy). > >For every post here, I must consider my competition is reading every >word, and just waiting to pounce. That does not allow me the freedom >that some other forum might offer. > >Austin And what makes you so sure the competition is not reading Xilinx's own forum? I bet the people from Altera and Lattice (to name some in alphabetical order) already have their logins. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 122864
Hi, I'm trying to synthesize a design with the fixed_pkg package in Xilinx ISE 9.2. I'm using the version adapted for Xilinx from http://www.eda-stds.org/fphdl/vhdl.html. Compilation works fine, but after that I get the following, not exactly helpful error message: ========================================================================= * Design Hierarchy Analysis * ========================================================================= ERROR:Xst:2683 - Unexpected error found while building hierarchy. --> This happens both with the synthesis test from the website above and with my own trivial example (attached at the end of the post). You can get the complete test project from http://www.mikrocontroller.net/attachment/25445/fixpt-test.zip. Has anyone found a workaround to use fixed_pkg with ISE? Thanks, Andreas Attachment: architecture rtl of top is signal x, y : sfixed (3 downto -3); begin x <= to_sfixed(in1, 3, -3); y <= x * 2; out1 <= to_slv(y); end rtl;Article: 122865
Hi all: I am trying to reconstruct a periodic exponential signal curve. The signal is in the order of 10-20mV. The total length of this curve is 100ns. Even though the total length is 100ns, the peak bandwidth of the signal maybe in the order of 100MHz. I thought about getting only one data point for each period and delay the sampling instance and collect further points (similar to time-interleaved sampling). I have a programmable delay line, which can produce delays in the multiples of 200ps. The goal is to reconstruct the signal curve, no matter how slow the reconstruction is. I thought about using high speed ADC like ADS5463 from TI, the reason is that it can handle very high Analog input frequency. Or can I use a slower ADC? The sharpness/jitter of the clock-signal and ADC sample/ hold is very important, I feel. Should I consider anything else? I dont know how could I interface the ADC to collect the digital data. Does FPGA work? Is there any FPGA boards which can be programmed to handle this situation. Is there any ideas. I am pretty new to FPGA and ADCs. Thanks, JoeArticle: 122866
On Aug 8, 10:12 am, ferorcue <le_m...@hotmail.com> wrote: <I clipped everything because the question is in the subject> As the answer you provided in your post says, you can't generate a 64 bit access from the 32 bit powerpc core. The data cache or the instruction cache can but you can't. You could write to the data cache and then flush it, but this is probably not what you want, nor is it recommended. You probably need to control your dma controller using multiple 32 bit accesses. And if that is not allowed, you need to re-design your dma controller. Alan NishiokaArticle: 122867
ferorcue <le_marq@hotmail.com> writes: > I want to write to data of 64 bits to the addres 0x2000 and 0x2001, 64 bits would be addresses 0x2000 through 0x2007.Article: 122868
defparam buf_100.IOSTANDARD = "LVPECL_25"; defparam buf_103.IOSTANDARD = "LVPECL_25"; IBUFDS buf_100 (.I(pad_dsp_adc_fsync_cmd_p), .IB (pad_dsp_adc_fsync_cmd_n), .O(dsp_adc_fsync_cmd) ); OBUFDS buf_103 (.I(adc_dsp_sdo_q_p), .O(pad_adc_dsp_sdo_p), .OB(pad_adc_dsp_sdo_n) ); Always check the following doc file for good reference to primitives : /Xilinx/doc/useglish/books/lib/lib.pdf -- Regards, John Retta Owner and Designer Retta Technical Consulting Inc. Colorado Based Xilinx Consultant email : jretta@rtc-inc.com web : www.rtc-inc.com <moogyd@yahoo.co.uk> wrote in message news:1186593169.119748.316150@q75g2000hsh.googlegroups.com... > Hi, > > Can someone please point me in the right direction. > > I attempted to define my LVDS inputs via the UCF file for my Xilinx > spartan xc3s1500. > > NET data_in LOC = F19 | IOSTANDARD = LVDS_25 ; > > the Xilinx answer record impies that this will work OK. > > http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=8187 > > Unfortunately I get the following warning, and the input is set to a > standard LVCMOS25. > > WARNING:Pack:946 - The I/O component data_in has an illegal I/O > standard value. Components of type IOB do not support I/O standard > LVDS_25. > Please correct the IOSTANDARD property value. > > I am using ISE 8.2 (Release 8.2.03i Map I.34) > > Any ideas what I am doing wrong? Do I need to istantiate the I/O > buffers? > > Thanks for any input, > > Steven >Article: 122869
On 8 8 , 10 43 , IDDLife <xing.starw...@gmail.com> wrote: > Recently, I read the source code of OR1200. But I am a little confused > about the Exception part. > > When a exception occurs, the correct execution PC value is found and > stored in the "epcr" register. And the "except_type" is set correctly. > Then in the next clock, all the instructions in the pipeline are > flushed. At the same time, the PC value is set to the exception > handling address according to the different exception types in the > or1200_genpc.v. > > However, I don't understand why the FSM in the or1200_except.v almost > set the "extend_flush" signal for 5 clocks. It seems not necessary. > > Does anybody know the answer? Does anybody knows why the exception handling should flush the whole pipeline for almost 5 clocks? Thanks a lot.Article: 122870
hi, I can't find the exact mean of AC in this phrase "AC-non-redundant fault" that refered in following abstract: can anyone tell me... AC means: alternative current, or Automatic Check, or Access Cycle, or Add Carry or something else... Thanks=A3=A1 -- Neil =3D=3D abstract =3D=3D The objective of this paper is to generate a Application-Oriented Test Procedure to be used by a FPGA user in a given application. General definitions concerning the specific problem of testing RAM-based FPGAs are first given such as the important concept of 'AC-non-redundant fault.' Using a set of circuits implemented on a XILINX 4000E, it is shown that a classical test pattern generation performed on the circuit netlist gives a low AC-non-redundant fault coverage and it is pointed out that test pattern generation performed on a FPGA representation is required. It is then demonstrated that test pattern generation performed on the FPGA representation can be significantly accelerated by removing most of the AC-redundant faults. Finally, a technique is proposed to even more accelerate the test pattern generation process by using a reduced FPGA description.Article: 122871
I've searched Xilnx's website and documentation for help on creating your
own IP-cores (for distribution to third-parties) -- but I didn't find
anything.
So I'm asking here....
I want to develop an IP-core, and allow FPGA-customers evaluate it.
I tried (without success) to synthesize the toplevel module ("my_ipcore"),
until I
get the .NGC file.
In a brand new Webpack session, different project, I set the toplevel module
type
from 'HDL' to 'NGC,' I added the .NGC file into the project hierarchy. In
the project
view, the file seems to register correctly. The test-design "my_test"
instantiates 1
instance my_ipcore. When I try to synthesize my_test, Xilinx XST issues the
error "cannot find module my_ipcore."
At first, I thought it was a Windows directory/path issue. So I temporarily
set the
toplevel module to "my_ipcore" The process-flow options change: I no longer
have
a 'synthesize' command. But If I run through map/place/route, that process
starts successfully, proving to me that Webpack can read the my_test.NGC
file
just fine. (It eventually throws some unrelated errors.)
what's the proper way to generate a netlist? I understand there is no
security
in a netlist (i.e. it can be used by anyone), but I'm not worried about that
right now. I just need a way to give my ip-core to someone else for
evaluation, without showing them the source RTL.
Article: 122872I have - MY_FPGA <--parallel bus--> DEVICE I want to make it so that the DEVICE operates only if MY_FPGA is connected to it. I need to make this connection secure enough to pass Military Export controls. Any ideas? I am thinking an AES based symmetric key operation that would encrypt the output of the DEVICE. But I want to get away from encrypting the data once the DEVICE has been unlocked if possible. Mainly for power and resource contraints on the DEVICE. TIA. SanjayArticle: 122873
I'm a newbie in fpga design, and am really struggling to create a bmm
file that works. I am using an Spartan-3A starter kit, with ISE 9.2.0i
on Linux. I am working with the dna reader project, and am capable of
downloading the design, as well as modifying the assembly program
(dna_ctrl.psm), and updating it via the whole "implement design" route.
I'm really interested in the direct modification of the bit file via
data2mem because it promises much faster turnaround times when updating
the picoblaze program, but I'm stuck with the bmm file generation.
I've told ISE to Locate the bram at X0Y0, and from the FPGA Editor i can
see that this works. It has implemented a BRAMB16BWE at site
RAMB16_X0_Y0
I've created a file my.bmm with these contents:
ADDRESS_SPACE ram RAMB16 [0x0000:0x07FF]
BUS_BLOCK top/ram/program_rom/ ram_1024_x_18_1 [7:0] LOC = X0Y0;
END_BUS_BLOCK; END_ADDRESS_SPACE;
which seems to be syntactically correct and has the correct number of
bits (16kb)
When I try to merge the file with the mem file from kcpsm3.exe I get an
error
data2mem -bm my.bmm -bd dna_ctrl.mem -bt reading_dna.bit -o b new.bit
ERROR:Data2MEM:31 - Out of bounds code segment for ram space in
'my.bmm'.
Memory space 'ram' occupies [0x00000000:0x000007FF]
Code segment #0 occupies [0x00000000:0x000009FF]
This same assembly file is assembled into dna_ctrl.vhd which is
correctly built into the final bitfile.
So what am I doing wrong? Any help would be highly appreciated!
Bart
Article: 122874Hi here is the start and end of the mem file line# 1 @00000000 2 00000 3 2E004 4 2C080 ... 1025 340FD I presume the first nibble of the 5 is the 2 bit parity, at least it only has values 0,1,2 and 3. So this is an 18 bit data file. So how come the FPGA editor shows that it's a RAMB16BWE block? Getting confused by now :-) Bart (poster original question)
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