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Authors (P)
p:
66745: 04/02/26: Re: SmartMedia writer (implments using VHDL)....
66746: 04/02/26: Re: SmartMedia writer (implments using VHDL)....
66747: 04/02/26: Re: FSM in fpga's
66825: 04/02/27: Re: SmartMedia writer (implments using VHDL)....
P:
25309: 00/09/06: Program & Readback Spartan II from 188
26987: 00/11/06: Re: CoolRunner news :(
27494: 00/11/24: Re: CoolRunner news :(
P Little:
20608: 00/02/16: Re: coregen-bug produces bad blockram > 16 bit
20665: 00/02/17: Re: Logiblox and virtex
23015: 00/06/09: Simulation of VIRTEX BLOCKRAM
P Nibbs:
4590: 96/11/19: Advantage of third party software?
4600: 96/11/20: Course/fine grain netlists?
5406: 97/02/14: Mealy/Moore state machines
5543: 97/02/24: Market share - synthesis tools?
6364: 97/05/19: Aust: Electronics at Work Exhibition
6892: 97/07/07: Re: Verilog Simulation and Synthesis for FPGA Devices
P. Athanas:
3425: 96/05/28: New book on FPGA computing
4228: 96/10/02: Research Position in Configurable Computing
P. Joeste:
54348: 03/04/08: Reset problem
54376: 03/04/09: Re: Reset problem
P. Knijnenburg:
12203: 98/10/05: info requested for design course
P. Prasad:
57038: 03/06/21: Interfaces in Handelc
57231: 03/06/26: Handelc, Plzzz help
P. Royla:
84940: 05/06/01: Chipscope and LVDS clock (IBUFGDS)
86119: 05/06/22: Area_Group
P.C.R. Beukelman:
16113: 99/05/04: web synthesis
<p.kootsookos@remove.ieee.org>:
24620: 00/08/15: Re: Non-disclosures in job interviews
24669: 00/08/16: Re: Non-disclosures in job interviews
24708: 00/08/17: Re: Non-disclosures in job interviews, Round One
24730: 00/08/17: Re: Non-disclosures in job interviews
24781: 00/08/18: Re: NDA's outside the US.
27709: 00/12/04: Re: ANNOUNCE: Checksum and CRC Code/Article
29990: 01/03/20: Re: TOA measurement
29991: 01/03/20: Re: TOA measurement
<p.taylor@ukonline.co.uk>:
3106: 96/04/02: Q: Multiplier & Subtractor in Xilinx 5204 FPGA ?
p.tucci <a t> gmail.com:
137464: 09/01/18: VHDL: Process vs concurrent stataments?
137465: 09/01/18: Re: VHDL: Process vs concurrent stataments?
P.W. Dowd:
1320: 95/06/01: faculty positions
p1v1t1=p2v2t2:
9070: 98/02/18: Virtual Chips PCI core in FPGA
10324: 98/05/12: Re: Chicken & egg problem in PCI/CardBus designs using FPGA
<p25486@my-deja.com>:
26508: 00/10/18: Off subjuct, VHDL question
26986: 00/11/06: Coregen instantiation help!!
29140: 01/02/07: Mentor Advice
<p52mofej@uco.es>:
13062: 98/11/13: Board for FPGA ?
<p_sin@my-dejanews.com>:
16162: 99/05/07: "DACafe.com: The ultimate resource for the EDA customers"
paas:
136594: 08/11/24: Re: FMC/VITA 57
Pablo:
113321: 06/12/11: Integrate VHDL Cores in Microblaze (Spartan 3E Starter Kit)
113467: 06/12/14: SDRAM in SPARTAN 3E
113608: 06/12/18: VHDL CODE FOR SDRAM IN SPARTAN 3E
113619: 06/12/18: Re: VHDL CODE FOR SDRAM IN SPARTAN 3E
113664: 06/12/19: Re: Operate on RAM through FPGA
113735: 06/12/20: MICROBLAZE AND OPB: TOO SLOW FOR VGA
113742: 06/12/20: Re: MICROBLAZE AND OPB: TOO SLOW FOR VGA
113781: 06/12/21: XILKERNEL and MICROBLAZE (how to probe this)
113786: 06/12/21: Re: How to simulate from the xilinx ISE
113862: 06/12/26: Problem in Xilkernel
113873: 06/12/27: Re: Problem in Xilkernel
113919: 06/12/29: SUNDANCE FPGA CONFIGURATION
114030: 07/01/03: FPGA-CPU THROUG ETHERNET
114128: 07/01/05: Re: SUNDANCE FPGA CONFIGURATION
114224: 07/01/08: Re: Build an FPGA programmer cable
114228: 07/01/08: CREATE FPGA-PC CONNECTION (LWIP, XILNET)
114278: 07/01/10: LWIP EXAMPLE??
114339: 07/01/12: Re: LWIP EXAMPLE??
114407: 07/01/15: Re: Gigabit Ethernet UDP/IP
114527: 07/01/18: TESTAPP_PERIPHERAL FAILED IN ETHERNET
114845: 07/01/25: CONDITION VARIABLES IN XILKERNEL
115158: 07/02/01: Condition Variable in pthread.h
115309: 07/02/07: Re: Spartan-3E starter kit : trouble with configuration from NOR Flash
115324: 07/02/07: Compile uCLinux for Spartan 3e
115353: 07/02/08: Re: Compile uCLinux for Spartan 3e
115354: 07/02/08: Re: Compile uCLinux for Spartan 3e
115400: 07/02/09: Xilinx Platform Studio Evaluation Trial Expired (included in Spartan 3E Starter Kit)
115468: 07/02/12: PETALINUX-COPY-AUTOCONFIG ERROR
115788: 07/02/20: PETALINUX AUTO-BOOT
116232: 07/03/05: Ise foundation and Ise Webpack
116272: 07/03/06: Xilinx Ise 6.3i
116525: 07/03/12: Power PC embeded in Virtex II Pro. Could I erase it with a new bitstream?
116547: 07/03/12: Re: Power PC embeded in Virtex II Pro. Could I erase it with a new bitstream?
116599: 07/03/13: Re: Power PC embeded in Virtex II Pro. Could I erase it with a new bitstream?
116649: 07/03/14: Does anybody work with Sundance Module (smt338vp30-> Virtex II Pro 30)
117053: 07/03/22: Parallel Cable IV in Spartan 3E???
117064: 07/03/22: Re: Parallel Cable IV in Spartan 3E???
117105: 07/03/23: Re: Parallel Cable IV in Spartan 3E???
117354: 07/03/29: Watershed Transform
117534: 07/04/03: Boot PowerPC on VirtexIIPro
117562: 07/04/04: Can I boot PowerPC without JTAG?
117772: 07/04/10: SetJmp/LongJmp for Microblaze
117912: 07/04/13: No login in uClinux (Petalinux)
118349: 07/04/24: Increase memory resource at Xil_malloc.
118380: 07/04/25: Increase Memory Resource in SDRAM.
118407: 07/04/26: Re: Increase Memory Resource in SDRAM.
118419: 07/04/26: Is microblaze able to change heap_size?
118436: 07/04/26: Re: Increase Memory Resource in SDRAM.
118464: 07/04/27: Re: Is microblaze able to change heap_size?
118574: 07/04/30: Re: Is microblaze able to change heap_size?
118621: 07/05/01: Re: Is microblaze able to change heap_size?
119083: 07/05/11: Re: Accessing SRAM on the Spartan-3 Starter Board
119351: 07/05/17: Semaphores in xilkernel?
119597: 07/05/23: DDR SDRAM in custom board
119650: 07/05/24: Ddr sdram feedback pin
119736: 07/05/25: Has anyone used Sundance Boards?.
119751: 07/05/25: Re: Has anyone used Sundance Boards?.
119757: 07/05/25: Re: Has anyone used Sundance Boards?.
119860: 07/05/28: Re: Ddr sdram feedback pin
119881: 07/05/29: Re: Ddr sdram feedback pin
119883: 07/05/29: Re: Has anyone used Sundance Boards?.
120013: 07/05/31: Re: Has anyone used Sundance Boards?.
120019: 07/05/31: Ise Flow with PowerPC
120039: 07/05/31: Re: Spartan 3E Starter Kit and EDK 8.2
120043: 07/05/31: Re: Ise Flow with PowerPC
120124: 07/06/01: Bootloader in BRAM to run a program loaded in the DDR
120130: 07/06/01: Re: Bootloader in BRAM to run a program loaded in the DDR
120233: 07/06/04: Re: Create and Import Peripheral in EDK
120325: 07/06/05: Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000
120374: 07/06/06: Install two version of EDK/ISE (8.1, 8.2) in my windows xp?
120388: 07/06/06: Re: Install two version of EDK/ISE (8.1, 8.2) in my windows xp?
120394: 07/06/06: Re: Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000
120435: 07/06/07: Re: Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000
120442: 07/06/07: JTAG as UART for PowerPC in XMD.
120447: 07/06/07: Re: JTAG as UART for PowerPC in XMD.
120455: 07/06/07: Re: JTAG as UART for PowerPC in XMD.
120586: 07/06/11: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
120612: 07/06/12: Re: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
120613: 07/06/12: Re: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
120617: 07/06/12: Apart from IEEE, is there some another journals for publishing an FPGA article?
120625: 07/06/12: Re: Could malloc/calloc get memory from SDRAM, while main program loads from BRAM?.
120684: 07/06/13: Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
120712: 07/06/14: Re: Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
120739: 07/06/15: Re: Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
120750: 07/06/15: Re: Recommendation for creating a DDR Sdram core for custom board and integrate in XPS
120861: 07/06/19: Could I use the opencore ddr_sdr core (for SDRAM) in Xilinx Platform Studio (C code)?
120878: 07/06/19: Re: Could I use the opencore ddr_sdr core (for SDRAM) in Xilinx Platform Studio (C code)?
120954: 07/06/21: Does anyone modify the opencore ddr_sdr for DDR Sdram for internal feedback?
120957: 07/06/21: Re: Does anyone modify the opencore ddr_sdr for DDR Sdram for internal feedback?
120962: 07/06/21: Re: Does anyone modify the opencore ddr_sdr for DDR Sdram for internal feedback?
121435: 07/07/04: Add DMA support to a custom core?
121473: 07/07/05: Re: Add DMA support to a custom core?
121584: 07/07/09: Re: Add DMA support to a custom core?
122001: 07/07/17: Unisim versus Virtex2 Xilinx Library
123339: 07/08/23: Speed test between FPGA and DSP or PC.
123495: 07/08/29: VHDL core to read/write to Bram_Block.
123727: 07/09/03: Re: VHDL core to read/write to Bram_Block.
124591: 07/09/27: UCF Constraints: drive and slew
124612: 07/09/28: Re: UCF Constraints: drive and slew
125652: 07/10/31: Is it possible to debug a vhdl design over jtag?
125814: 07/11/06: Re: Is it possible to debug a vhdl design over jtag?
127957: 08/01/11: Is it possible to define an Integer so it could be incremented and
128031: 08/01/14: Re: Is it possible to define an Integer so it could be incremented
128329: 08/01/22: Re: Is it possible to define an Integer so it could be incremented
128331: 08/01/22: Re: Is it possible to define an Integer so it could be incremented
128335: 08/01/22: Re: Is it possible to define an Integer so it could be incremented
128337: 08/01/22: Re: Is it possible to define an Integer so it could be incremented
128363: 08/01/23: Re: Is it possible to define an Integer so it could be incremented
128364: 08/01/23: Re: Is it possible to define an Integer so it could be incremented
128373: 08/01/23: Re: Is it possible to define an Integer so it could be incremented
128379: 08/01/23: Re: Is it possible to define an Integer so it could be incremented
129530: 08/02/27: OPB_MDM as UART in a PowerPC design
129830: 08/03/06: I could run my program at DDR Sdram.
129837: 08/03/06: Re: I could run my program at DDR Sdram.
130527: 08/03/26: Is it possible to set Instruction PowerPC Bus ONLY for 32 bits
130530: 08/03/26: Re: EDK9.2 microblaze tutorial
130713: 08/03/31: Re: Writing to DDR RAM on Virtex II Pro Board on PLB Bus
130805: 08/04/02: "Number of BSCANs: 2 out of 1 200%"
130848: 08/04/03: Re: "Number of BSCANs: 2 out of 1 200%"
130876: 08/04/04: Re: "Number of BSCANs: 2 out of 1 200%"
131395: 08/04/21: XmdStub fails when connecting via JTAG.
131397: 08/04/21: OPB_MDM functionality
132165: 08/05/16: What could be the problem?
132170: 08/05/16: Re: What could be the problem?
132247: 08/05/19: I cannot find how to map a "record type" in my ucf file.
132270: 08/05/20: Re: I cannot find how to map a "record type" in my ucf file.
132434: 08/05/27: Ph.D Student
132505: 08/05/29: Re: Ph.D Student
133549: 08/07/03: Have you ever experimented some problem with External Memory?
133551: 08/07/03: OPB_CENTRAL_DMA
133558: 08/07/03: Xilinx XPS and Multiple Microblaze
133576: 08/07/04: Re: Have you ever experimented some problem with External Memory?
133577: 08/07/04: Re: OPB_CENTRAL_DMA
133625: 08/07/07: Re: OPB_CENTRAL_DMA
134865: 08/09/04: Hide VHDL code.
134895: 08/09/05: Re: Hide VHDL code.
135017: 08/09/10: Load Application from External Memory without the use of XMD???
135036: 08/09/11: Re: Load Application from External Memory without the use of XMD???
135046: 08/09/12: Re: Load Application from External Memory without the use of XMD???
135080: 08/09/15: Re: Load Application from External Memory without the use of XMD???
135103: 08/09/16: Two JTAG Parallel IV Cable in a single PC.
135130: 08/09/17: Re: Two JTAG Parallel IV Cable in a single PC.
139767: 09/04/13: XUPV2P + uClinux
140767: 09/05/25: Re: Doubt about a Microblaze Based Multiprocessor SoC
140784: 09/05/26: Re: Doubt about a Microblaze Based Multiprocessor SoC
140811: 09/05/26: Re: Doubt about a Microblaze Based Multiprocessor SoC
141182: 09/06/10: Use XMD to configure more than one board
141185: 09/06/10: Re: Use XMD to configure more than one board
141186: 09/06/10: Error in FSL Bus
141204: 09/06/11: Re: Use XMD to configure more than one board
141205: 09/06/11: Re: Error in FSL Bus
pablo:
80596: 05/03/08: Re: Using BUFG with internally generated clocks
80598: 05/03/08: Re: Good, affordable verilog simulator
97641: 06/02/25: A dev board supporting partial/dynamic reconf.
97687: 06/02/26: Re: A dev board supporting partial/dynamic reconf.
103479: 06/06/03: partial reconfiguration protocol on Spartan II and self reconfiguration
pablo aimar:
71089: 04/07/07: Re: How to add clock delay in CPLD?
71595: 04/07/23: Re: How to program a spartan-3
72613: 04/08/26: Re: JTAG software
72726: 04/08/30: Re: how can I simulate the vhdl and verilog mixed design in modelsim?
72898: 04/09/07: Re: how to get the data from ADC
73022: 04/09/10: MAX II CPLD(fpga ?) Board
73033: 04/09/10: Re: New to FpGa ; At configuring the device error cmes
73044: 04/09/11: Re: New to FpGa ; At configuring the device error cmes
Pablo Alvarez Sanchez:
87640: 05/07/27: Reset and Power-On Reset Activation XCFxxP PROMs
87681: 05/07/28: Re: Reset and Power-On Reset Activation XCFxxP PROMs
Pablo Bleyer:
65196: 04/01/22: Re: Spirit on Mars
65526: 04/02/01: Re: New USB chip for fast FPGA bitstream download
66147: 04/02/13: RFC: ARM+FPGA tiny board
66201: 04/02/13: Re: RFC: ARM+FPGA tiny board
66202: 04/02/13: Re: RFC: ARM+FPGA tiny board
66209: 04/02/14: Re: ARM+FPGA tiny board
66225: 04/02/15: Re: RFC: ARM+FPGA tiny board
67235: 04/03/09: Re: NEWS: Xilinx announces acquisition of Triscend
Pablo Bleyer Kocik:
24156: 00/07/27: Re: XCS05XL de Xilinx
36733: 01/11/17: WebPACK 4.1 under Win95
36742: 01/11/18: WebPACK 4.1 under Win95 : solved
59618: 03/08/24: Reusing CCLK line after configuration for Spartan-II
59661: 03/08/25: Re: Reusing CCLK line after configuration for Spartan-II
59709: 03/08/26: Re: Reusing CCLK line after configuration for Spartan-II
61109: 03/09/28: Re: Free WebPack 6.1i Download Available Now for Spartan-3
61133: 03/09/29: Re: Free WebPack 6.1i Download Available Now for Spartan-3
62321: 03/10/26: Picky WebPACK 6.1
65538: 04/02/01: Re: New USB chip for fast FPGA bitstream download
66191: 04/02/13: Re: RFC: ARM+FPGA tiny board
66203: 04/02/13: Re: ARM+FPGA tiny board
66204: 04/02/13: Re: RFC: ARM+FPGA tiny board
66248: 04/02/15: Re: RFC: ARM+FPGA tiny board
66715: 04/02/25: ARM+FPGA tiny board
69510: 04/05/12: Re: FPGA + CF
71137: 04/07/09: Icarus Verilog for Windows
71163: 04/07/10: Re: Icarus Verilog for Windows
72391: 04/08/17: PacoBlaze
72472: 04/08/19: XST: init inferred block RAM. Possible now?
75002: 04/10/24: PacoBlaze 1.3b
75023: 04/10/24: Re: PacoBlaze 1.3b
77630: 05/01/12: Re: Programming and copyright
77675: 05/01/13: Re: Programming and copyright
79133: 05/02/14: Re: SimmStick FPGA module
79698: 05/02/23: Spartan-3 partial reconfiguration trouble
79725: 05/02/23: Re: Spartan-3 partial reconfiguration trouble
79728: 05/02/23: Re: Spartan-3 partial reconfiguration trouble
79732: 05/02/23: Re: The real performance leader: V4
79754: 05/02/23: Re: Spartan-3 partial reconfiguration trouble
79791: 05/02/24: Re: Spartan-3 partial reconfiguration trouble
79792: 05/02/24: Re: The real performance leader: V4
80059: 05/02/28: Re: FPGA interface to an asynchronous microcontroller memory bus
80104: 05/03/01: Re: FPGA interface to an asynchronous microcontroller memory bus
80122: 05/03/01: Re: Memory or registers and JTAG
80143: 05/03/01: Re: Memory or registers and JTAG
80147: 05/03/02: Spartan-3E and SPI Flash bootstrap
80238: 05/03/02: Re: Spartan-3E and SPI Flash bootstrap
80623: 05/03/09: [ANN] jjtag - Java JTAG interface
80626: 05/03/09: Re: jjtag - Java JTAG interface
80730: 05/03/10: Re: Xilinx vs Altera high-end solutions
80931: 05/03/14: Re: editing waveforms under Linux
81450: 05/03/23: Re: Xilinx ISE 7.1 - Can this get any worse?
82515: 05/04/13: "The ISE 7.1 Experience"
82521: 05/04/13: Re: Flowcharts and diagrams
82526: 05/04/13: Re: "The ISE 7.1 Experience"
96888: 06/02/12: PacoBlaze updated
96928: 06/02/13: Re: PacoBlaze updated
98654: 06/03/14: PacoBlaze update
99135: 06/03/20: PacoBlaze with multiply and 16-bit add/sub instructions
99150: 06/03/20: Re: PacoBlaze with multiply and 16-bit add/sub instructions
99208: 06/03/21: OpenSPARC released
99327: 06/03/22: Re: OpenSPARC released
99328: 06/03/22: Re: PacoBlaze with multiply and 16-bit add/sub instructions
99522: 06/03/25: Re: OpenSPARC released
99523: 06/03/25: Re: PacoBlaze with multiply and 16-bit add/sub instructions
119880: 07/05/29: PacoBlaze 2.2
119923: 07/05/29: Re: PacoBlaze 2.2
119954: 07/05/30: Re: PacoBlaze 2.2
120004: 07/05/30: Re: PacoBlaze 2.2
120049: 07/05/31: Re: PacoBlaze 2.2
120657: 07/06/12: KCAsm beta
Pablo H:
132463: 08/05/28: Re: Ph.D Student
133591: 08/07/04: Re: Xilinx XPS and Multiple Microblaze
133592: 08/07/04: Re: Xilinx XPS and Multiple Microblaze
134005: 08/07/21: Re: Strange behaviour with Xilkernel
134029: 08/07/22: Re: Strange behaviour with Xilkernel
135321: 08/09/26: MicroBlaze SMP system DEMO
+Pablo+:
20051: 00/01/25: XC9500 0,5u Mask: Errors?
20082: 00/01/26: Design security
<pablo.huerta@gmail.com>:
127287: 07/12/17: Re: Xilinx Dual processor design
pac1:
5265: 97/02/03: Q is Xilinx Foundation BASE worth buying?
<pac1@waikato.ac.nz>:
1870: 95/09/13: XC3030 XC1736 "Done still low"
2690: 96/01/25: Qn on XC3030 and XC3164 'Divide By Two'
2694: 96/01/25: Re: Qn on XC3030 and XC3164 'Divide By Two'
Pacbell User:
58879: 03/08/03: opencores.org - Question on project licensing?
Pacem:
12477: 98/10/14: VHDL Editor
12946: 98/11/06: Intelligent VHDL editor for Windows
pacman101:
149600: 10/11/10: Building a Software Defined Radio
pad007:
157831: 15/04/07: Microblaze with AXI streaming interfaces
Paddy:
118221: 07/04/19: xilprofile for edk 8.2
118223: 07/04/19: Re: xilprofile for edk 8.2
Paddy Mullan:
38630: 02/01/19: JBits: Partial Reconfiguration
<paddy3118@netscape.net>:
92597: 05/12/01: Info on packing regular tree-like structures into rectangles?
Padelis Trakas:
2016: 95/10/03: (no subject)
2017: 95/10/03: (no subject)
2018: 95/10/03: QUICKSIM & XBLOX HELP
Padraig FitzGerald:
53302: 03/03/10: comp.arch.fpga : VCC shorted to GND within FPGA???
padudle:
155353: 13/06/24: Re: VHDL syntheses timestamp
<padudle@gmail.com>:
140149: 09/04/30: Re: offset out
154903: 13/02/12: Vivado - Pack I/O Registers?
Pai Chou:
20734: 00/02/19: Call for Participation: SIGDA Ph.D. Forum at DAC'2000
Pai H Chou:
21237: 00/03/12: SIGDA Ph.D. Forum at DAC'2000 -- new deadline Fri Mar.17
29525: 01/02/25: Call for Participation: PhD Forum at DAC (deadline March 16)
<paik@webnexus.com>:
12892: 98/11/03: Re: New free FPGA CPU
Pak K. Chan:
343: 94/10/25: Re: I/O pin currents on Xilinx FPGAs?
592: 95/01/13: FPGA '95 Advance Program/ time to send in your registration
3970: 96/08/26: Re: Anyone know about Viewlogic v4 with QEMM?
4189: 96/09/24: Re: Source for FPGA and PCI prototype board ???
4278: 96/10/09: Re: Viewlogic v4.1 Plotter.exe cmd line usage?
4309: 96/10/12: Re: Viewlogic v4.1 Plotter.exe cmd line usage?
11896: 98/09/17: Re: lookup table for mult/div
12701: 98/10/23: Re: Xilinx may not support schematics for Virtex/or Rita
27050: 00/11/08: Re: Encoding of FSMs internal states
35440: 01/10/04: Re: Prototyping with BGA's
Pak Khong:
12503: 98/10/14: Re: VHDL Editor
12529: 98/10/15: Re: VHDL Editor
pallav:
115138: 07/01/31: EDA course development
115143: 07/01/31: EDA course development
143356: 09/10/05: Multiplier design with carry-save adder + Booth encoding
143362: 09/10/05: Re: Multiplier design with carry-save adder + Booth encoding
143419: 09/10/10: Re: Multiplier design with carry-save adder + Booth encoding
146882: 10/03/30: Re: Any advice on which is the best book on CMOS digital circuit
Pallavi:
49717: 02/11/19: design of LVDS
142668: 09/08/25: Timing properties of FPGA devices at sub-clock frequencies
142879: 09/09/05: Clock multiplication using DCM in FPGA
145072: 10/01/24: timing properties of fpga devices at sub-clock frequencies
145076: 10/01/25: Re: timing properties of fpga devices at sub-clock frequencies
145086: 10/01/26: Re: timing properties of fpga devices at sub-clock frequencies
145446: 10/02/09: To get higher clock frequencies at output using propagation delays.
145465: 10/02/10: Re: To get higher clock frequencies at output using propagation delays.
145579: 10/02/14: Re: To get higher clock frequencies at output using propagation delays.
145587: 10/02/15: Re: To get higher clock frequencies at output using propagation delays.
146260: 10/03/10: Translate Error: ngd build 604
146340: 10/03/12: Re: Translate Error: ngd build 604
pallavi:
128677: 08/02/03: Starting problems with ISE 9.2.04i (WebPack+ServicePack)...unable to
128869: 08/02/07: Re: Starting problems with ISE 9.2.04i (WebPack+ServicePack)...unable
128942: 08/02/11: Re: Downloading codes to FPGA development Board
Pallek, Andrew [CAR:CN34:EXCH]:
36472: 01/11/09: Re: Counter detects both edge of clock?? (verilog)
37339: 01/12/07: Re: What do you like/dislike about place and route tools?
37608: 01/12/17: Re: division 64
38583: 02/01/18: Re: verilog/vhdl codeing style
palvarez:
136591: 08/11/24: FMC/VITA 57
136601: 08/11/24: Re: FMC/VITA 57
136620: 08/11/26: added jitter on FPGAs
136654: 08/11/28: Re: added jitter on FPGAs
136655: 08/11/28: Re: FMC/VITA 57
136677: 08/11/30: Re: FMC/VITA 57
139466: 09/03/31: clock distribution on VITA 57 (FMC)
144245: 09/11/23: Spartan6 PCIe and multiboot
144319: 09/11/26: Re: Spartan6 PCIe and multiboot
pamma:
98011: 06/03/03: Re: FPGA - software or hardware?
Panci Gianpiero:
14308: 99/01/25: Re: Power Consumption in FPGAs
<pandey@my-dejanews.com>:
14310: 99/01/25: Xilinx flip flops hold time
14311: 99/01/25: Metastability implementation
14331: 99/01/26: FPGA architecture
15144: 99/03/09: Function generator in Xilinx
15628: 99/04/04: Levels of logic
Panic:
59889: 03/08/31: Question conserning Altera's Quartus II
61458: 03/10/04: Reusing code (Altera Quartus II 3.0)
61479: 03/10/05: Re: Reusing code (Altera Quartus II 3.0)
61532: 03/10/06: Design question (Working with Altera EPXA1F484C1)
62040: 03/10/17: Xilinx Slice and Altera ...?
62049: 03/10/17: Re: Xilinx Slice and Altera ...?
62055: 03/10/17: Re: Xilinx Slice and Altera ...?
62075: 03/10/18: Re: Xilinx Slice and Altera ...?
62106: 03/10/20: Several Quartus II 3.0 questions
62125: 03/10/20: Re: Several Quartus II 3.0 questions
62186: 03/10/21: Strange error in Quartus II 3.0
62209: 03/10/22: Re: Strange error in Quartus II 3.0
62210: 03/10/22: Re: Strange error in Quartus II 3.0
62231: 03/10/22: Re: Strange error in Quartus II 3.0
PanJuHwa:
56865: 03/06/17: CRC check in Configuration Bitstream
56869: 03/06/17: CRC check in Virtex Bitstream
56870: 03/06/17: Configuring Virtex with rbt files
56927: 03/06/18: Re: Configuring Virtex with rbt files
56929: 03/06/18: Partial Reconfiguration with BITGEN
57044: 03/06/21: Convert rbt to bit
57050: 03/06/22: Re: Convert rbt to bit
57236: 03/06/26: Partial Reconfiguration of RC1000
58309: 03/07/19: Readback of RC100
60238: 03/09/08: Targetting RC1000 with Mediabench JPEG Application
61952: 03/10/15: ICAP Virtex2
63361: 03/11/20: Virtex Benchmarks
Pankaj:
92348: 05/11/28: instruction counts and cache hits/misses on FPGA
92659: 05/12/03: Using RiscWatch with Xilinx FPGA's for powerpc
Pankaj Rodey:
58892: 03/08/03: Re: Gates Counting?
Pankaj Sharma:
70053: 04/05/31: EDK 6.1
<pant_nagar@tatanagar.com>:
76762: 04/12/10: Re: Open source FPGA EDA Tools
<panteltje@yahoo.com>:
85874: 05/06/17: Re: Idea exploration - Image stabilization by means of software.
91396: 05/11/04: Re: icarus verilog
91407: 05/11/05: Re: icarus verilog
95315: 06/01/22: Re: FPGA-Programmable power supply
98978: 06/03/18: Re: Where are FPGAs heading?
100254: 06/04/05: Re: Xilinx Schematic Entry
105581: 06/07/26: Re: 2Khz clock signal from 50Hz main frequency with ADPLL
108657: 06/09/14: Re: Linear Interploation Algorithms
120969: 07/06/21: Re: Can anyone identify the manufacturer of this Chip ?
<pantgom@gmail.com>:
118385: 07/04/25: Memory Resource in SDRAM
140756: 09/05/25: Doubt about a Microblaze Based Multiprocessor SoC
pantxoa:
103700: 06/06/08: Re: Incrmental Compilation in Quartus 5.1
Panu =?iso-8859-1?Q?H=E4m=E4l=E4inen?=:
29148: 01/02/08: AES (Rijndael) in FPGAs
29367: 01/02/16: Re: Rijndael
Panu H:
35069: 01/09/20: Re: Clockin on rising AND falling edge
35633: 01/10/12: Re: PWM Signal in VHDL ?
35637: 01/10/12: Re: PWM Signal in VHDL ?
36403: 01/11/08: Re: Hex numbers in VHDL
40018: 02/02/25: Re: Implementing MD5 in hardware (Handel C, VHDL)
panwh:
64288: 03/12/25: a question about flex10 configure
panzo:
52926: 03/02/26: Is anyone working with JBits there ?
53167: 03/03/05: Re: Is anyone working with JBits there ?
Paolo:
83223: 05/04/26: Re: Another Altera FPGA Development Board
83233: 05/04/26: Re: Another Altera FPGA Development Board
Paolo Roberto Grassi:
144587: 09/12/17: Actel Igloo Partial Reconfiguration
146527: 10/03/22: Core8051s on Actel IGLOO AGL-DEV-KIT-SCS-SA
147622: 10/05/08: Microblaze: Boot Program from SDRAM
Paolo Spazzini:
5741: 97/03/11: Re: Introducing Renoir
5908: 97/03/25: Re: RENOIR DEMO CD
Paolo Tardivel:
55555: 03/05/12: ModelSim and Specman: on the fly generation
paolo.furia:
133849: 08/07/17: Read files from Compact Flash
<paolo.furia@gmail.com>:
133382: 08/06/26: SYSACE problems on ML402 (virtex 4)
133701: 08/07/10: Dynamic partial reconfiguration on virtex devices
Paparao Palacharla:
11566: 98/08/24: 8B/10B coding
papppanas:
136704: 08/12/02: how to read images from a microSD card ?
136708: 08/12/02: Re: how to read images from a microSD card ?
136709: 08/12/02: Re: how to read images from a microSD card ?
136721: 08/12/03: Re: how to read images from a microSD card ?
Papu:
81820: 05/04/01: ABEL alias names
papu:
80297: 05/03/03: XC9572 64 pin VQFP package
Par Ligander:
39228: 02/02/04: Re: JTAG Boundary Scan with the XDS510
paraag:
54813: 03/04/18: synthesinzing xilinxcorelib in ISE 5.1
54818: 03/04/18: how to synthesize Xilinxcorelib in leonardo or ISE 5.1
54875: 03/04/21: help required in ISE 5.1 -----ERROR:NgdBuild:604 - logical block 'filtercore'
55340: 03/05/04: materail needed on Dynamic Reconfiguration of IP core
58351: 03/07/21: help needed..... ERROR:MapLib:30 - Bad format for LOC constraint AB12 on rx.
58503: 03/07/24: heel needed--Bad format for LOC constraint B8 on leds<6>. To bypass this
58602: 03/07/28: help neede-----Error Pack 1107 -Unable to combine the following .........
60277: 03/09/09: ERROR:Pack:679 - Unable to obey design constraints ....can anyone help
64077: 03/12/15: PIN naming confusion xilinx spartan 2E XC2S200E
65266: 04/01/22: asic vs fpga comparison issues
67616: 04/03/15: what technology is the mcnc.genlib in the SIS package
Parag:
75381: 04/11/03: need an fpga board
75537: 04/11/08: Performing floating point in VHDL
Paragon:
144103: 09/11/11: Having trouble with Xilinx timing constraints
<paragon.john@gmail.com>:
125021: 07/10/15: Xilinx timing constraints incorrect?
125116: 07/10/16: Re: Xilinx timing constraints incorrect?
125119: 07/10/16: Re: Xilinx timing constraints incorrect?
125139: 07/10/16: Re: Xilinx timing constraints incorrect?
125152: 07/10/16: Re: Xilinx timing constraints incorrect?
125190: 07/10/17: Re: Xilinx timing constraints incorrect?
125389: 07/10/24: Paper about selecting fixed point bit widths?
127935: 08/01/10: How to view resource utilization by hierarchy?
127964: 08/01/11: Resource utilization broken down by hierarchy?
127973: 08/01/11: Re: Resource utilization broken down by hierarchy?
128951: 08/02/11: ModelSim versus Active-HDL....redux
129236: 08/02/19: Re: Which Linux Distro to use for Xilinx tools
129833: 08/03/06: 802.16d with Xilinx Viterbi Decoder
130786: 08/04/01: Re: now I can talk about it...
130810: 08/04/02: Re: now I can talk about it...
132640: 08/06/04: Xilinx Fifo Generator Direct Instantiation?
132722: 08/06/05: Re: Xilinx Fifo Generator Direct Instantiation?
<parekh.sh@gmail.com>:
125005: 07/10/15: Re: Altera devices connecting to DDR memory.
132540: 08/05/30: Re: delta sigma adc.....
133249: 08/06/22: Re: Newbie Verilog Question / ModelSim
<parekhsanjayh@gmail.com>:
154945: 13/02/27: Experience with Tektronix's FPGAview
PARESH K. JOSHI:
8497: 97/12/25: Re: Xilinx Copy Protection
paris:
67702: 04/03/17: Re: newbie question about fpga internals
67736: 04/03/18: Re: newbie question about fpga internals
68066: 04/03/25: Re: Clock divider preserving duty-cycle ?
68082: 04/03/26: Re: Clock divider preserving duty-cycle ?
68133: 04/03/27: Re: study verilog or vhdl?
68156: 04/03/28: Re: Clock divider preserving duty-cycle ?
68632: 04/04/11: Re: Free Arm Version 0.8
68851: 04/04/20: Re: Trouble with rising edge signals in functional simulation
68873: 04/04/21: reading files in vhdl
68943: 04/04/22: Re: Trouble with rising edge signals in functional simulation
69079: 04/04/27: Re: Simulating two clock domains
69080: 04/04/27: Re: transport applications
69159: 04/04/28: Re: Simulating two clock domains
69183: 04/04/29: Re: Post-Place & Route Simulation with ISE
parity:
81894: 05/04/04: Xilinx XPower - Accuracy Information
82637: 05/04/15: re:Xilinx XPower - Accuracy Information
82900: 05/04/19: UCF File - How to define this Constraint?
82965: 05/04/20: Power Estimation without Pad Connection (XPower)
Park Chan Ik:
10090: 98/04/27: FPGA pin assignment for I/O
11640: 98/08/28: lookup table for mult/div
Park, DongHwan:
11305: 98/08/04: Dual-edge clocking device for Rambus DRAM...
Parkov:
94017: 06/01/04: Schematic Entry, Xilinx or Altera?
94030: 06/01/04: Re: Schematic Entry, Xilinx or Altera?
94038: 06/01/04: Re: Schematic Entry, Xilinx or Altera?
Parry:
46444: 02/08/29: Re: discrepancies in Xilinx xapp253, DDR SDRAM controller.
Partha:
131838: 08/05/03: Using SRL16
131883: 08/05/06: Using Sysgen v8.2
139862: 09/04/17: Mapping FIFO into BRAM
Partha Biswas:
79821: 05/02/24: Problems with XPower
79822: 05/02/24: Re: NiosII Vs MicroBlaze
79846: 05/02/24: Questions on XPower: "Confidence level is shown as inaccurate"
PARTICLEREDDY (STRAYDOG):
108417: 06/09/11: Re: Performance Appraisals
parvathi69:
148997: 10/09/20: xilinx FFT core simulation
149254: 10/10/12: store data into fpga
Parvathy Uma:
34865: 01/09/12: Re: Question concerning Verilog scheduling
Pasacco:
88129: 05/08/10: How to setup Analyzer in ChipScope Pro
88140: 05/08/10: Re: How to setup Analyzer in ChipScope Pro
88396: 05/08/17: Chipscope pro : timing constraint?
88413: 05/08/17: Re: Chipscope pro : timing constraint?
88433: 05/08/18: Re: Chipscope pro : timing constraint?
88478: 05/08/19: Re: Chipscope pro : timing constraint?
88487: 05/08/19: Re: Chipscope pro : timing constraint?
89341: 05/09/13: Re: Post synthesis simulation errors
89809: 05/09/27: Re: chipscope pro
90548: 05/10/16: Error (XST): translate terminal to FCT
90836: 05/10/22: clock frequency after RTL synthesis vs PAR
90843: 05/10/22: Re: clock frequency after RTL synthesis vs PAR
90912: 05/10/25: xpower : logic power=0
90927: 05/10/25: Re: xpower : logic power=0
95022: 06/01/20: VHDL Bus Macro for V2Pro
95671: 06/01/25: How to generate ILA with ChipScope pro in Linux
96261: 06/02/01: ISE 8.1.01i does not implement new BUS macro
96414: 06/02/03: [map error] unable to pack a IBUF into the IOB
96427: 06/02/03: Re: unable to pack a IBUF into the IOB
97335: 06/02/20: "par.exe" halted without error (partial configuratio)
103492: 06/06/04: Asynchronous BRAM input ?
103522: 06/06/05: Re: Asynchronous BRAM input ?
103530: 06/06/05: Re: Asynchronous BRAM input ?
105024: 06/07/12: how to implement multi-port memory
105073: 06/07/13: Re: how to implement multi-port memory
105074: 06/07/13: Re: how to implement multi-port memory
105449: 06/07/23: <EDK> PORT .... not found in MPD
105942: 06/08/03: EDK, user IP, how to use user-functions
106017: 06/08/05: Post PAR simulation, type not match
107962: 06/09/03: wiring resource utilization?
113575: 06/12/17: EDK, header file modified and problem
115822: 07/02/21: how to use STD_LOGIC_VECTOR2
116974: 07/03/21: Manual LUT - AND function mapping problem
118235: 07/04/20: Virtex-4 module based partial reconfiguration problem
118374: 07/04/25: physical chip size
118375: 07/04/25: Physical chip size
118509: 07/04/28: Re: physical chip size
118526: 07/04/29: Re: physical chip size
118527: 07/04/29: Macro modified after Map ?
119555: 07/05/22: how 33-bit BRAM?
120173: 07/06/02: FIFO : Synchronous WRITE, Asynchronous READ ?
120184: 07/06/02: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
120521: 07/06/08: Module LOCK possible in VHDL?
120784: 07/06/16: How to measure clock fequency
120891: 07/06/19: [ISE] how to synthesize XilinxProcessorIP/pcore
121891: 07/07/14: [ISE] How to create and map user library in command-line?
121917: 07/07/15: Re: How to create and map user library in command-line?
121924: 07/07/15: Re: How to create and map user library in command-line?
121975: 07/07/16: How to obtain (accurate) critical path delay?
122165: 07/07/21: FIFO : Synchronous WRITE, Asynchronous READ ?
122173: 07/07/22: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
122913: 07/08/10: Amount of wire and logic
122916: 07/08/10: Re: Amount of wire and logic
122937: 07/08/11: Re: Amount of wire and logic
123069: 07/08/15: Re: Amount of wire and logic
123105: 07/08/16: Re: Amount of wire and logic
123198: 07/08/19: Globally Asynchronous in FPGA
123234: 07/08/20: Re: Globally Asynchronous in FPGA
123237: 07/08/20: Re: Amount of wire and logic
123239: 07/08/20: Re: Amount of wire and logic
123585: 07/08/30: Die size, pitch size?
123599: 07/08/30: Re: Die size, pitch size?
123616: 07/08/31: Re: Die size, pitch size?
123654: 07/08/31: Re: Die size, pitch size?
123659: 07/08/31: Re: Die size, pitch size?
123810: 07/09/05: Re: Die size, pitch size?
124291: 07/09/17: Virtex-4 SELECT MAP configuration
125865: 07/11/07: [Linker script : EDK6.3 -> EDK 8.2] Parse error
125999: 07/11/12: [EDK tool] simulation setup
126000: 07/11/12: EDK 8.2 tool : simulator set up
126059: 07/11/13: [EDK simulation] synopsys translate_off
126060: 07/11/13: Re: EDK 8.2 tool : simulator set up
126150: 07/11/15: Re: synopsys translate_off
126154: 07/11/15: Re: synopsys translate_off
126156: 07/11/15: Re: synopsys translate_off
126175: 07/11/16: Re: synopsys translate_off
126227: 07/11/17: how to KEEP_HIERARCHY [EDK]
126417: 07/11/21: EDK + Modelsim simulation : Memory allocation failure
126442: 07/11/22: Re: EDK + Modelsim simulation : Memory allocation failure
126463: 07/11/23: Re: EDK + Modelsim simulation : Memory allocation failure
128977: 08/02/12: Partial reconfiguration reference design?
134150: 08/07/28: IP core initialization ?
pasacco:
81019: 05/03/16: 2 microblazes, 1 opb, 2 BRAMs
81088: 05/03/17: Re: 2 microblazes, 1 opb, 2 BRAMs
81154: 05/03/18: Re: 2 microblazes, 1 opb, 2 BRAMs
84145: 05/05/13: Q)BRAM VHDL simulation in modelsim
84151: 05/05/13: Re: Q)BRAM VHDL simulation in modelsim
84393: 05/05/18: Q, BRAM initializing using INIT_0X
84470: 05/05/19: Re: Q, BRAM initializing using INIT_0X
84637: 05/05/23: Project Navigator mapping problem with CLK and BRAM
84722: 05/05/25: Re: Project Navigator mapping problem with CLK and BRAM
85972: 05/06/19: globally asyncronous vs locally syncronous?
86352: 05/06/26: unisim for synthesis?
87142: 05/07/17: Serial vs Chipscope
87145: 05/07/17: Re: Serial vs Chipscope
87213: 05/07/19: Re: ISE7.1 Map:Portability/export/Port_Main.h:127:1.22.234.1
87215: 05/07/19: ChipScope Pro : how to set up trigger
87245: 05/07/20: Re: ChipScope Pro : how to set up trigger
87317: 05/07/21: Re: ChipScope Pro : how to set up trigger
87326: 05/07/21: Re: ChipScope Pro : how to set up trigger
87643: 05/07/27: simulatable but not synthesizable (verifiable)
87648: 05/07/27: Re: simulatable but not synthesizable (verifiable)
87691: 05/07/28: Re: ChipScope Pro : how to set up trigger
87722: 05/07/29: Re: ChipScope Pro : how to set up trigger
87727: 05/07/29: Re: ChipScope Pro : how to set up trigger
87757: 05/07/31: Re: ChipScope Pro : how to set up trigger
87790: 05/08/01: Re: ChipScope Pro : how to set up trigger
87840: 05/08/02: How to manage user 'reset' for post-synthesis simulation
88026: 05/08/06: How to properly use Analyzer, ILA ChipScopePro
pascal:
66797: 04/02/26: Re: VHDL FSM Problem
Pascal Buseyne:
16138: 99/05/05: connecting an PS/2-mouse with an Altera FLEX10K20
Pascal C.:
28010: 00/12/19: Question about Xilinx pins at high-frequency
28022: 00/12/19: Re: Question about Xilinx pins at high-frequency
28069: 00/12/20: Re: Question about Xilinx pins at high-frequency
28108: 00/12/21: Re: Question about Xilinx pins at high-frequency
28245: 01/01/03: Re: Question about Xilinx pins at high-frequency
Pascal CADIC:
52651: 03/02/18: Simulation of FIFO in Spartan IIE
Pascal Chamberland:
65668: 04/02/04: Re: Soft failures (?) 9536XL
Pascal Delouche:
29323: 01/02/14: Problem with pipelined divider in Virtex
45488: 02/07/24: Re: Power-Up sequencing problem with Altera Apex20KE
Pascal Dornier:
6109: 97/04/12: Re: Seeking PALASM/ABEL/CUPL/?
6615: 97/06/05: Re: Fine Pitch PQFP : anyone any hassles?
12018: 98/09/24: Re: easier testing for PCI cards??
14408: 99/01/28: Re: Off topic DRAM/SIMM question....
14490: 99/02/01: Re: Off topic DRAM/SIMM question....
14773: 99/02/16: Re: Flex6016 config. problem.
16149: 99/05/06: Re: BGA Prototyping ?
19200: 99/12/05: Re: hobbyist friendly pld?
Pascal Lacroix:
32992: 01/07/14: Real beginner
Pascal Merkel:
32255: 01/06/21: Trouble with IOB Cells
33649: 01/08/01: LUT as Buffer?
33953: 01/08/09: Re: LUT as Buffer?
Pascal Peyremorte:
126787: 07/12/02: Re: lossless compression in hardware: what to do in case of uncompressibility?
Pascal_Olive:
145283: 10/02/04: Issue with Altera flash programmer
pascal_sweden:
153046: 11/11/22: RTOS with support for TCP/IP sockets on Spartan 3E
Pasi Ojala:
126785: 07/12/02: Re: lossless compression in hardware: what to do in case of uncompressibility?
pasquale:
15881: 99/04/18: flex10k 1 gate change
Pasquale Corsonello:
3773: 96/07/29: Re: Signed digit arithmetic on FPGA's
3789: 96/08/01: Reconfigurable Hardware
4248: 96/10/04: Reconfigurable hardware
4667: 96/11/27: WVoffice and ACTEL Design Series
4669: 96/11/27: Reconfigurable chip
5874: 97/03/21: Re: 8-bit divider in FPGA
8488: 97/12/22: Asynchronous square root.
11151: 98/07/21: Re: Partial reprogramming
24019: 00/07/23: Announcement: New high-speed low-power adders
24030: 00/07/24: Re: Announcement: New high-speed low-power adders
Pat:
17774: 99/09/02: Re: FPGA/PLD in fine pitch BGA or chip scale package ???
17879: 99/09/15: Re: ACTEL Viewlogic Problem
19096: 99/11/29: ClearLogic Vs. Altera
19750: 00/01/11: Re: Design security
19749: 00/01/11: Re: HW resources increased
30969: 01/05/05: Altera Consultant
130341: 08/03/20: Re: timing and timing reports (again)
Pat Ford:
44081: 02/06/11: fpga and ultra highspeed counters
44233: 02/06/14: Re: fpga and ultra highspeed counters
44276: 02/06/15: Strathnuey kit from Nallatech
44504: 02/06/21: Re: fpga and ultra highspeed counters
50182: 02/12/04: Re: ISA bus VGA
51460: 03/01/14: Cesys xc2s_eval opinions
51889: 03/01/24: Re: SChematic design approach compared to VHDL entry approach
55015: 03/04/24: ise4.2i and wine
Pat G.:
53428: 03/03/13: Re: [Xilinx] Looking for Parallel Cable III ...
53431: 03/03/13: Homemade Xilinx Parallel JTAG Download Cable
53452: 03/03/13: Re: [Xilinx] Looking for Parallel Cable III ...
53495: 03/03/14: Question about the schematic?
Pat Hennessy:
18452: 99/10/25: Altera newbie simulation problem
Pat Kling:
11514: 98/08/20: Re: vector product minimization problem
11539: 98/08/21: Re: vector product minimization problem
Pat Leary:
2084: 95/10/11: Re: Good materials schools?
Pat Magnet:
132770: 08/06/06: Re: Using ethernet on a Xilnx board (Help appreciated)
Pat Magnits:
127620: 08/01/04: Ethernet on recent FPGAs
Pat McGuirk:
32765: 01/07/08: Shift and Add Multiplier With Signed Numbers
Patatralla:
30547: 01/04/14: Xilinx LUT's and Synopsys DC
PatC:
126800: 07/12/02: Re: Asynchronous FIFO and almost empty - bug?
126801: 07/12/02: Re: ise timing analysis + different clock domains
126922: 07/12/05: Re: clock lines
127092: 07/12/11: Re: Chipscope 7.1 and JTAG TAP
127093: 07/12/11: Re: Xilinx : Incorrect PACE file generation from schematic
127110: 07/12/11: Re: Poor quality Xilinx boards ? Your experience ?
127199: 07/12/13: Re: ML505 board Compact Flash
129113: 08/02/14: Re: signal generation in VHDL on FPGA.... Check my code please
129430: 08/02/23: Planahead IP export
129432: 08/02/23: Re: Xilinx DCM for frequency synthesis -- newbie question
129443: 08/02/24: Re: Xilinx DCM for frequency synthesis -- newbie question
129766: 08/03/04: Re: Planahead IP export
129819: 08/03/05: Re: could use some help with verilog/vhdl
130262: 08/03/19: Re: Optimizing an inferred counter
130529: 08/03/26: Re: VHDL document generation utilities
132334: 08/05/21: Re: timing constraint is impossible to meet
133477: 08/06/30: Re: Translate problem
133520: 08/07/02: Timing Analyzer report for IOBs -- 1GSPS DAC interface
133528: 08/07/02: Re: Timing Analyzer report for IOBs -- 1GSPS DAC interface
135169: 08/09/19: Re: Clock Enable safe?
135760: 08/10/14: Re: Virtex 5, DDR2 access
135859: 08/10/17: Re: Literature on 100Base-TX request
135943: 08/10/23: Re: Multiple GTPs used in a Virtex 5
135996: 08/10/26: Re: "Out of Order" problem in Xilinx V5 used as a PCI Express Endpoint
patcher:
72286: 04/08/13: Do you know how to reconfig the DFS of Spartan DCM at runtime
<patches11@gmail.com>:
102669: 06/05/18: Processing DVI signals with an FPGA
Patrice Favreau:
61142: 03/09/29: using the FALLING constrain with cores (coregen)
<patrice.ulrich@evc.net>:
114005: 07/01/02: Re: SPI Flash on Avnet Spartan 3E Eval Kit
Patricia Shanahan:
109385: 06/09/26: Re: An algorithm with Minimum vertex cover without considering its
109401: 06/09/26: Re: An algorithm with Minimum vertex cover without considering its
109422: 06/09/26: Re: An algorithm with Minimum vertex cover without considering its
Patrick:
41096: 02/03/20: Re: XPOWER accuracy?
44417: 02/06/19: Re: ISE Webpack Basics
44419: 02/06/19: Re: Heat Sink/Fan for XC2V3000-4BF957
53674: 03/03/19: GCK, GTS and GSR pins on Xilinx XC9500 devices
76819: 04/12/13: pausing execution on ppc405
76881: 04/12/15: DMA-capable opb ipif
77415: 05/01/06: xil_printf not working as expected
77537: 05/01/10: xil_printf not working as expected (cont.)
78513: 05/02/02: xil_malloc vs malloc
78677: 05/02/05: Coprocessor "Standalone"
84006: 05/05/11: strange Microblaze error
85045: 05/06/03: Boot problem Stratix Kit EP1S25
85360: 05/06/08: Boot problem Stratix Kit EP1S25
85413: 05/06/09: Re: Boot problem Stratix Kit EP1S25
85746: 05/06/15: Stratix Kit EP1S25 Boot problem
86004: 05/06/20: BIG PROBLEM : Configuration Boot Problem Stratix
86043: 05/06/21: Re: BIG PROBLEM : Configuration Boot Problem Stratix
86151: 05/06/22: Re: BIG PROBLEM : Configuration Boot Problem Stratix
87314: 05/07/21: Heat Sink for Stratix
115790: 07/02/20: Looking for a superscalar simulator
117211: 07/03/26: RISC implementation questions
117218: 07/03/26: Re: RISC implementation questions
117384: 07/03/29: Re: RISC implementation questions
117389: 07/03/29: Re: RISC implementation questions
117396: 07/03/29: Re: RISC implementation questions
117404: 07/03/30: Re: RISC implementation questions
117410: 07/03/30: Re: RISC implementation questions
149098: 10/10/01: SPI ROM use for holding bitstreams
150869: 11/02/17: Simulation vs. Hardware mismatch
150871: 11/02/17: Re: Simulation vs. Hardware mismatch
150992: 11/02/27: Re: Simulation vs. Hardware mismatch
Patrick Birger:
65045: 04/01/19: Altera/Xilinx Distributor in Europe?
65117: 04/01/20: Re: Altera/Xilinx Distributor in Europe?
Patrick Browne:
64938: 04/01/16: Can XILINX run in multiple instances?
65044: 04/01/19: Re: Can XILINX run in multiple instances?
65109: 04/01/20: Re: Can XILINX run in multiple instances?
Patrick Dano:
34397: 01/08/23: Actel Pad locations
Patrick Drolet:
2195: 95/10/30: Re: AT&T vs. Xilinx
2205: 95/11/01: Re: AT&T vs. Xilinx
3204: 96/04/24: Re: high gate count FPGA for small volumn production?
3397: 96/05/24: Re: Xilinx and Viewlogic
6655: 97/06/09: Re: Fine Pitch PQFP : anyone any hassles?
Patrick Dubois:
106766: 06/08/18: Re: Ultracontroller II: PROM solution in EDK 8.1
107195: 06/08/25: Re: Ultracontroller II: PROM solution in EDK 8.1
107202: 06/08/25: UltraController II + SystemAce
107220: 06/08/25: Re: UltraController II + SystemAce
107229: 06/08/25: Re: UltraController II + SystemAce
107236: 06/08/25: Re: UltraController II + SystemAce
107327: 06/08/26: Re: UltraController II + SystemAce
107360: 06/08/27: Re: UltraController II + SystemAce
107502: 06/08/29: Re: UltraController II + SystemAce
108605: 06/09/13: csptool : Chipscope Pro perl script to group buses automatically
109434: 06/09/26: Pack registers (from submodule) into IOB for bidirectionnal signal
109451: 06/09/26: Re: Pack registers (from submodule) into IOB for bidirectionnal signal
109478: 06/09/27: Re: Aurora UCF problem
109497: 06/09/27: Re: Pack registers (from submodule) into IOB for bidirectionnal signal
109524: 06/09/27: Re: Pack registers (from submodule) into IOB for bidirectionnal signal
112008: 06/11/14: Pipelining can reduce the slice usage
112118: 06/11/16: Re: Pipelining can reduce the slice usage
112376: 06/11/21: Re: DDR_SDRAM_VHDL_models
114929: 07/01/26: Re: Timing Diagram Tool
116035: 07/02/28: SCons build tool as an alternative to makefiles
116086: 07/03/01: Re: Potential problem in batch files for Xilinx [was SCons build tool as an alternative to makefiles]
116226: 07/03/05: Re: SCons build tool as an alternative to makefiles
116296: 07/03/06: Re: SCons build tool as an alternative to makefiles
116298: 07/03/06: Re: How to implement pipeline in this case?
116303: 07/03/06: Re: How to implement pipeline in this case?
116305: 07/03/06: Re: How to implement pipeline in this case?
116331: 07/03/07: Re: SCons build tool as an alternative to makefiles
116360: 07/03/07: Re: How to implement pipeline in this case?
116760: 07/03/16: Xilinx ISE support for dual/quad core CPUs?
116839: 07/03/19: Re: Xilinx ISE support for dual/quad core CPUs?
116840: 07/03/19: Re: Xilinx ISE support for dual/quad core CPUs?
116846: 07/03/19: Re: Xilinx ISE support for dual/quad core CPUs?
116850: 07/03/19: Re: Xilinx ISE support for dual/quad core CPUs?
116986: 07/03/21: Re: Xilinx ISE support for dual/quad core CPUs?
117504: 07/04/02: Re: Help with a face recognition system
117508: 07/04/02: Re: Help with a face recognition system
117528: 07/04/03: Re: Help with a face recognition system
117572: 07/04/04: Re: Help with a face recognition system
117576: 07/04/04: Re: Help with a face recognition system
117777: 07/04/10: Re: is there any opensource alternatives to platformstudio and microblaze development?
118810: 07/05/03: lwIP RAW mode support for V4 temac
118910: 07/05/07: Re: lwIP RAW mode support for V4 temac
119009: 07/05/09: Re: lwIP RAW mode support for V4 temac
119011: 07/05/09: Re: lwIP RAW mode support for V4 temac
119089: 07/05/11: Re: How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4
119861: 07/05/28: MPMC2 + flash bootloader problem
119918: 07/05/29: Re: MPMC2 + flash bootloader problem
119975: 07/05/30: Re: MPMC2 + flash bootloader problem
120252: 07/06/04: Re: ise9.1 : partitions with edif flow
120258: 07/06/04: Re: ise9.1 : partitions with edif flow
120273: 07/06/04: XST sythesizes fifos instead of creating black boxes
120328: 07/06/05: Re: mig 1.7 for SDRAM DDR 1 or 2 controller : watch your ISE properties
120337: 07/06/05: Re: XST sythesizes fifos instead of creating black boxes
120339: 07/06/05: Re: XST sythesizes fifos instead of creating black boxes
120343: 07/06/05: Re: Unable to connect to PowerPC target. Invalid Processor Version No 0x00000000
120386: 07/06/06: Re: Install two version of EDK/ISE (8.1, 8.2) in my windows xp?
120409: 07/06/06: Re: EDK9.1: XTemac + LwIP + Xilkernel + unistd.h = possible?
120448: 07/06/07: Re: EDK9.1: XTemac + LwIP + Xilkernel + unistd.h = possible?
120449: 07/06/07: Re: JTAG as UART for PowerPC in XMD.
120460: 07/06/07: Re: JTAG as UART for PowerPC in XMD.
120513: 07/06/08: Re: FPGA / Virtex II Pro / LWIP
120515: 07/06/08: Re: EDK9.1: XTemac + LwIP + Xilkernel + unistd.h = possible?
120888: 07/06/19: MIG for Virtex-4 DDR dimm, only 165 Hz?
120933: 07/06/20: Re: MIG for Virtex-4 DDR dimm, only 165 Hz?
121403: 07/07/03: Re: Rocketio connection Virtex2pro-Virtex4
121775: 07/07/13: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121802: 07/07/13: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121809: 07/07/13: Re: SystemC in modeling HW/SW
121843: 07/07/13: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121954: 07/07/16: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
122441: 07/07/27: Re: Best CPU platform(s) for FPGA synthesis
122694: 07/08/03: Re: Best CPU platform(s) for FPGA synthesis
125121: 07/10/16: Re: Graphical VHDL Viewer ?
125263: 07/10/18: Re: Wishbone Specification in Action
125493: 07/10/26: XMD with CableServer OR remote EDK solution
125564: 07/10/29: Re: XMD with CableServer OR remote EDK solution
125573: 07/10/29: Re: 2 FPGAs /w programming FLASH in one JTAG chain
125604: 07/10/29: FFT for an arbitrary number of points (not power of 2)
125616: 07/10/30: Re: FFT for an arbitrary number of points (not power of 2)
125620: 07/10/30: Re: FFT for an arbitrary number of points (not power of 2)
125621: 07/10/30: Re: FFT for an arbitrary number of points (not power of 2)
125629: 07/10/30: Re: FFT for an arbitrary number of points (not power of 2)
125660: 07/10/31: Re: FFT for an arbitrary number of points (not power of 2)
126201: 07/11/16: Re: jitter-sensitive multi-output clk distribution for
127057: 07/12/10: Re: Net hierarchy with Xilinx 9.1
129037: 08/02/13: Re: floating point arithmetic in vhdl
129280: 08/02/19: Re: Synthesis-Place-Route benchmark for i386-32bit
130230: 08/03/18: Re: dual clock fifo
130290: 08/03/19: Re: dual clock fifo
130294: 08/03/19: Re: dual clock fifo
130841: 08/04/03: Re: EDK 10.1 first impressions
131123: 08/04/11: Re: Xilinx FFT C-sim model
131248: 08/04/16: Re: chipscope pro , lower level signals not visible
131897: 08/05/06: Re: Aldec Active-HDL 7.3 sp1 [stimulators]
133132: 08/06/18: =?windows-1252?Q?NVIDIA=92s_Tesla_T10P_Blurs_Some_Lines?=
133171: 08/06/19: =?windows-1252?Q?Re=3A_NVIDIA=92s_Tesla_T10P_Blurs_Some_Lines?=
133178: 08/06/19: Re: which commercial HDL-Simulator for FPGA?
133205: 08/06/20: Re: which commercial HDL-Simulator for FPGA?
134555: 08/08/18: Re: XMD & Ultracontroller
135047: 08/09/12: Re: Quartus II compile speedup with New Quad Core Intel machine
135073: 08/09/13: Re: Quartus II compile speedup with New Quad Core Intel machine
142999: 09/09/14: Sharing multiple ZBT between PowerPC and FPGA fabric at maximum
Patrick Gao:
75486: 04/11/08: SpartanII + ARM7 Question
75583: 04/11/10: SpartanII + ARM7 Question
Patrick Hibbs:
35220: 01/09/26: Re: Virtex II current consumption
35221: 01/09/26: Re: Logical constraints of LUT
35972: 01/10/25: Re: SpartanXL Device Utilization Summary
35974: 01/10/25: Re: Recommend a book
35975: 01/10/25: Re: transferring data between related clocks
35986: 01/10/25: Re: 2/3 trellis code in vhdl
35993: 01/10/25: Re: SpartanXL Device Utilization Summary
Patrick Hopper:
72642: 04/08/27: DSP & FPGA Resource Guide
Patrick Jarry:
4048: 96/09/05: Warp2 realease 4.0 ??
Patrick Johnson:
110242: 06/10/12: New Electronic Design Web site
Patrick Kane:
33170: 01/07/18: Re: Coolrunner: availability
Patrick Klacka:
65111: 04/01/20: changing values in a fifo
65125: 04/01/21: Re: changing values in a fifo
65187: 04/01/21: Re: changing values in a fifo
65370: 04/01/26: Re: changing values in a fifo
Patrick Kulle:
76378: 04/12/01: Weird XPower results for FSMs and different FPGAs
76419: 04/12/01: Re: Weird XPower results for FSMs and different FPGAs
76436: 04/12/02: Re: Weird XPower results for FSMs and different FPGAs
Patrick Liu:
58306: 03/07/20: With regard of FPGA Express v3.7
Patrick Loschmidt:
37631: 01/12/18: Re: SPI interface in VHDL
46230: 02/08/22: Re: How to include Xilinx library for both ModelSim and Synplify?
48734: 02/10/23: Re: High Performance FPGA's - Xilinx and ??????
48776: 02/10/24: Re: High Performance FPGA's - Xilinx and ??????
Patrick Lysaght:
13620: 98/12/14: CFP: Ninth International Workshop on Field Programmable Logic and Applications
Patrick MacGregor:
53375: 03/03/12: Development boards with optics
56260: 03/06/01: Re: SONET/SDH chipset on FPGA
56821: 03/06/16: BGA Xray inspection costs?
57221: 03/06/25: Re: Xilinx Webpack bugs bugs bugs
57247: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
57248: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
57251: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
57267: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
58533: 03/07/25: Re: temux
58554: 03/07/25: Re: temux
59042: 03/08/06: Re: Using 3rd Party IP Cores...
60162: 03/09/05: Re: Schematic simulation and then FPGA programming?
60242: 03/09/08: Re: Schematic simulation and then FPGA programming?
61173: 03/09/29: Re: Wirelessly Connecting two FPGA development boards (Celoxica RC100 boards)
61352: 03/10/02: Re: Wirelessly Connecting two FPGA development boards (Celoxica RC100 boards)
61686: 03/10/08: Re: Visualizing VHDL
64174: 03/12/18: Re: Spartan3 availability
64206: 03/12/19: Re: Spartan3 availability
64207: 03/12/19: Re: Spartan3 availability
64222: 03/12/21: Re: Spartan3 availability
64608: 04/01/08: Anybody know what the REAL story is?
64630: 04/01/09: Re: Anybody know what the REAL story is? Jim figured it out.
Patrick Madden:
3598: 96/07/02: Re: INDUSTRY GADFLY "Why I Hate Wally"
Patrick Maheral:
36223: 01/11/02: Open configuration bitstreams
Patrick Maupin:
144594: 09/12/18: Questions about Spartan 3A
144595: 09/12/18: Re: Trouble with Xilinx DCM - Spartan3
144600: 09/12/19: Re: Questions about Spartan 3A
144602: 09/12/19: Re: Trouble with Xilinx DCM - Spartan3
144605: 09/12/19: Re: Best "bang for buck" Student Starter board for image/video
144610: 09/12/20: Re: Trouble with Xilinx DCM - Spartan3
145292: 10/02/04: Simulating Spartan 3A pins in ltspice
145335: 10/02/05: Re: Simulating Spartan 3A pins in ltspice
145337: 10/02/05: Re: Simulating Spartan 3A pins in ltspice
145338: 10/02/05: Re: Simulating Spartan 3A pins in ltspice
145342: 10/02/05: Re: Simulating Spartan 3A pins in ltspice
145343: 10/02/05: Re: Simulating Spartan 3A pins in ltspice
145345: 10/02/05: Re: Simulating Spartan 3A pins in ltspice
145386: 10/02/07: Re: Simulating Spartan 3A pins in ltspice
145387: 10/02/07: Re: Simulating Spartan 3A pins in ltspice
145488: 10/02/11: Re: What is the basis on flip-flops replaced by a latch
145514: 10/02/12: Re: What is the basis on flip-flops replaced by a latch
145515: 10/02/12: Re: What is the basis on flip-flops replaced by a latch
145547: 10/02/13: Re: What is the basis on flip-flops replaced by a latch
145548: 10/02/13: Re: What is the basis on flip-flops replaced by a latch
145549: 10/02/13: Re: 28nm FPGAs are coming...
145573: 10/02/14: Re: 28nm FPGAs are coming...
145574: 10/02/14: Re: 28nm FPGAs are coming...
146516: 10/03/21: Re: Update init data in dualport BRAM without re-run anything?
146518: 10/03/21: Re: Digilent Nexys2 board
146522: 10/03/21: Re: Digilent Nexys2 board
146563: 10/03/22: Re: Why hardware designers should switch to Eclipse
146613: 10/03/23: Re: Why hardware designers should switch to Eclipse
146632: 10/03/24: Re: Why hardware designers should switch to Eclipse
146642: 10/03/24: Re: Why hardware designers should switch to Eclipse
146733: 10/03/26: Re: Any advice on which is the best book on CMOS digital circuit
146791: 10/03/28: Re: USB 3.0 implementation on FPGA
146822: 10/03/29: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
146823: 10/03/29: Re: Free VHDL or Verilog Simulator
146824: 10/03/29: Re: XST optimization
146825: 10/03/29: Re: infering BRAM for a FIFO in XST(spartan 3)
146836: 10/03/29: Re: XST optimization
146837: 10/03/29: Re: upgrading to ISE 11.x
146842: 10/03/29: Re: infering BRAM for a FIFO in XST(spartan 3)
146854: 10/03/30: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
146877: 10/03/30: Re: Spartan 6 PLL - Why such a strict input jitter requirement?
146894: 10/03/31: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
146896: 10/03/31: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
146899: 10/03/31: Re: Spartan 3E: MAX_STEPS as a function of CLKIN frequency
146938: 10/04/02: Re: ISE block RAM inference
147016: 10/04/09: Re: Problems with data2mem
147017: 10/04/09: Re: I'd rather switch than fight!
147020: 10/04/09: Re: Problems with data2mem
147021: 10/04/09: Re: Problems with data2mem
147028: 10/04/09: Re: I'd rather switch than fight!
147029: 10/04/09: Re: I'd rather switch than fight!
147039: 10/04/10: Re: I'd rather switch than fight!
147044: 10/04/11: Re: I'd rather switch than fight!
147056: 10/04/12: Re: I'd rather switch than fight!
147058: 10/04/12: Re: I'd rather switch than fight!
147139: 10/04/15: Re: I'd rather switch than fight!
147140: 10/04/15: Re: I'd rather switch than fight!
147147: 10/04/15: Re: I'd rather switch than fight!
147148: 10/04/15: Re: I'd rather switch than fight!
147152: 10/04/15: Re: I'd rather switch than fight!
147155: 10/04/15: Re: I'd rather switch than fight!
147170: 10/04/16: Re: I'd rather switch than fight!
147183: 10/04/16: Re: I'd rather switch than fight!
147184: 10/04/16: Re: I'd rather switch than fight!
147246: 10/04/20: Re: I'd rather switch than fight!
147247: 10/04/20: Re: I'd rather switch than fight!
147250: 10/04/20: Re: I'd rather switch than fight!
147263: 10/04/21: Re: I'd rather switch than fight!
147271: 10/04/21: Re: Polmaddie Family CPLD and FPGA Teaching Boards
147301: 10/04/22: Re: I'd rather switch than fight!
147302: 10/04/22: Re: I'd rather switch than fight!
147303: 10/04/22: Re: I'd rather switch than fight!
147314: 10/04/22: Re: I'd rather switch than fight!
147319: 10/04/22: Re: I'd rather switch than fight!
147320: 10/04/22: Re: I'd rather switch than fight!
147323: 10/04/22: Re: I'd rather switch than fight!
147329: 10/04/22: Re: I'd rather switch than fight!
147331: 10/04/22: Re: I'd rather switch than fight!
147345: 10/04/23: Re: I'd rather switch than fight!
147346: 10/04/23: Re: I'd rather switch than fight!
147356: 10/04/23: Re: I'd rather switch than fight!
147357: 10/04/23: Re: I'd rather switch than fight!
147358: 10/04/23: Re: I'd rather switch than fight!
147359: 10/04/23: Re: I'd rather switch than fight!
147367: 10/04/23: Re: I'd rather switch than fight!
147371: 10/04/23: Re: I'd rather switch than fight!
147372: 10/04/23: Re: I'd rather switch than fight!
147381: 10/04/24: Re: Helping tools
147385: 10/04/25: Re: Helping tools
147422: 10/04/26: Re: I'd rather switch than fight!
147502: 10/04/28: Re: xilinx arm finally announced
147543: 10/04/30: Re: ISE tools not detecting IOSTANDARD conflicts within bank
147553: 10/05/01: Re: Cheap FPGAs for tutorial
147597: 10/05/05: Re: FIFO Depth Calculation
147598: 10/05/05: Re: Xilinx project failed timing constraints
147600: 10/05/05: Re: FPGA Compilation Time Windows vs Linux
147645: 10/05/11: Re: I'd rather switch than fight!
147811: 10/05/25: Re: mux behavior
147875: 10/05/28: Re: Programming Digilent Nexys 2 from Linux
Patrick McCabe:
3330: 96/05/14: Re: Xilinx 4013 80% utilized but won't route
Patrick McGuirk:
38059: 02/01/03: Re: Cable for multiple LVDS signals - ?
Patrick Meuser:
53416: 03/03/13: Re: Issues in Outsourcing?
Patrick Mueller:
9516: 98/03/20: Synthesizable 8B/10B Encoder/Decoder wanted
Patrick Mullarky:
51584: 03/01/16: Re: adaptive filter with many zero input
51628: 03/01/17: Re: copy of a project
51629: 03/01/17: Re: Booting Spartan IIE from SPI
51631: 03/01/17: Re: Modelsim crashes
52316: 03/02/06: Re: Xilinx Foundation 5.1: reasons to upgrade
52379: 03/02/07: Re: HELP NEEDED
53632: 03/03/18: Re: Strict Priority scheduling
Patrick Muller:
31151: 01/05/13: Re: Nasty "register ordering" in map
35346: 01/09/30: Xilinx Virtex-II reconfiguration
38007: 01/12/30: Re: Innoveda Speedwave vs. Modelsim?
Patrick Murphy:
947: 95/04/01: Re: Excuse me while I vent about Data I/O & Abe
Patrick Müller:
10766: 98/06/17: 62.5MHz 128x17Bit Dualport-Fifo in Xilinx
Patrick n' Nicole Miller:
6817: 97/06/30: Development Proposals
Patrick Pangaud:
62220: 03/10/22: Amplify under Windows server 2003
Patrick Robin:
44104: 02/06/11: virtual ground in Xilinx XC9572 CPLD?
44127: 02/06/12: Re: virtual ground in Xilinx XC9572 CPLD?
61831: 03/10/13: Xilinx "Programming failed" message
68155: 04/03/27: Help with Xilinx Ram16X1S example VHDL code
68168: 04/03/28: Re: Help with Xilinx Ram16X1S example VHDL code
Patrick Scheible:
146143: 10/03/06: Re: using an FPGA to emulate a vintage computer
146156: 10/03/06: Re: using an FPGA to emulate a vintage computer
Patrick Schulz:
22225: 00/05/02: Performance of Xilinx LogiCORE PCI Real 64/66
22495: 00/05/10: appropriate ASIC Prototyping Board
22532: 00/05/11: Re: appropriate ASIC Prototyping Board
22533: 00/05/11: Re: appropriate ASIC Prototyping Board
22562: 00/05/12: Re: Reccomend an ASIC emulation board
22648: 00/05/16: Re: PC104+ FPGA Board
22697: 00/05/18: Re: Reccomend an ASIC emulation board
22698: 00/05/18: Re: Best choice between FPGA and CPLD
22938: 00/06/05: Synopsis DesignWare PCI-Core (DWPCI) implemented on FPGA?
22990: 00/06/07: Re: Where's OptiMagic?
23095: 00/06/14: Re: Free tools "OpenTech cdrom"
24504: 00/08/11: Re: what does 0.35 micron mean
24505: 00/08/11: Re: Getting into FPGAs
24506: 00/08/11: Re: ASIC SCAN TEST
24580: 00/08/14: Re: what does 0.35 micron mean
24581: 00/08/14: Re: ASIC SCAN TEST
24583: 00/08/14: Re: Crossing Clock Domains.
24624: 00/08/15: Re: what does 0.35 micron mean
24648: 00/08/16: Re: what does 0.35 micron mean
26223: 00/10/09: BIST: Testing embedded RAMs
26301: 00/10/11: Re: Testing embedded RAMs
32301: 01/06/22: Re: ATPG tools for FPGA
32369: 01/06/25: Re: [Q]ATPG - using bidir as scan in
Patrick Siegel:
77115: 04/12/23: timer-interrupt not recognized
77215: 04/12/30: Re: timer-interrupt not recognized
77541: 05/01/10: PartialMask-Option of bitgen
77841: 05/01/18: confusing wordcount in virtex2pro-bitstream
Patrick Twomey:
51839: 03/01/23: Celoxica RC100 Demo Board: Video In
53113: 03/03/04: xilinx Dsgnmgr does not support Asynchronous Fifo on Spartan II XCS200-fg456
61121: 03/09/29: Wirelessly Connecting two FPGA development boards (Celoxica RC100 boards)
61221: 03/09/30: Re: Wirelessly Connecting two FPGA development boards (Celoxica RC100 boards)
66574: 04/02/23: Inova Semiconductor Gigastar Link between two FPGAs
<patrick.melet@dmradiocom.fr>:
88138: 05/08/10: Re: How to setup Analyzer in ChipScope Pro
90319: 05/10/10: Clock routing
96246: 06/02/01: Quartus Fitter Warning
98730: 06/03/15: Multiple clocks design
98757: 06/03/16: Re: Spread Spectrum Cores ??
105392: 06/07/21: PLL clock in in Stratix
106913: 06/08/22: Detect failure in Berlekamp algorithm
115629: 07/02/15: FFT IP ALTERA FORMAT
116966: 07/03/21: gated clock
116978: 07/03/21: Re: gated clock
116982: 07/03/21: Re: gated clock
<Patrick>:
7295: 97/08/22: VHDL model for VME Slave Interface
<patrick@pluto.e-technik.uni-dortmund.de>:
4247: 96/10/04: Re: VHDL for Xilinx designs?
<PatrickHarold>:
72882: 04/09/07: VHDL code for 16-32 bit counter for quadrature encoder signals (A-B)
72923: 04/09/08: Re: VHDL code for 16-32 bit counter for quadrature encoder signals (A-B)
72924: 04/09/08: Re: VHDL code for 16-32 bit counter for quadrature encoder signals (A-B)
72929: 04/09/09: Re: VHDL code for 16-32 bit counter for quadrature encoder signals (A-B)
Patrik:
66630: 04/02/24: JTAG Opcodes for Altera MAX7000S
66775: 04/02/26: Re: JTAG Opcodes for Altera MAX7000S
Patrik Eriksson:
29278: 01/02/12: Xilinx PAR core dump
42271: 02/04/19: Using Virtex-II DCM to determine clock activity
42361: 02/04/22: Re: Using Virtex-II DCM to determine clock activity
42405: 02/04/23: DCM off chip deskew
43233: 02/05/17: Accessing TAP registers from within the FPGA (VirtexII)
43666: 02/05/29: Re: FPGA, VHDL : RAM initialization
46101: 02/08/19: BRAM simulation model error?
46138: 02/08/20: Re: BRAM simulation model error?
46140: 02/08/20: Re: BRAM simulation model error?
49008: 02/10/29: Virtex-II, Clocking a register without any clock
49029: 02/10/30: Re: Virtex-II, Clocking a register without any clock
55169: 03/04/29: Virtex-II DCM frequency synthesizer
55194: 03/04/30: Re: Virtex-II DCM frequency synthesizer
55195: 03/04/30: Re: Virtex-II DCM frequency synthesizer
55866: 03/05/22: Re: CLKDLL: Dividing
56015: 03/05/27: Multiply 19.44MHz with Virtex-II DCM
56199: 03/05/30: Re: Multiply 19.44MHz with Virtex-II DCM
56478: 03/06/06: Re: Xilinx Block RAM
60597: 03/09/17: Xilinx ISE 6.1i DCM is dead
64552: 04/01/07: Re: Clock domains
67087: 04/03/05: Re: CASCADING DCM
69694: 04/05/18: 64B/66B at sub 10Gbps in Xilinx MGT
71000: 04/07/05: Re: crc32 vhdl implementation (4 bit data)
71352: 04/07/15: Clock generation
94015: 06/01/04: URGENT: Virtex-II Pro X - Clock correction questions
105287: 06/07/19: Specify Clock Correction Sequence for Virtex-II ProX MGT (Rocket
113179: 06/12/07: Recursive component instantiation
113207: 06/12/08: Re: Recursive component instantiation
113307: 06/12/11: Re: Recursive component instantiation
134681: 08/08/26: xlicmgr vs lmutil/lmstat and floating licenses
Patrik Kramer:
77458: 05/01/07: [REQ] Hat jemand erfahrung mit dem USB IP-core von Trenz?
<patrik.camilleri@gmail.com>:
104614: 06/07/01: Xilinx System Generator Part List Problem
Paul:
9538: 98/03/21: To Richard Schwarz of APS
9539: 98/03/21: Re: To Richard Schwarz of APS
34877: 01/09/12: Problems with Xilinx VirtexE (Newbie)
38585: 02/01/18: Quartus 2 and bus ripping
38658: 02/01/21: Re: Quartus 2 and bus ripping
38671: 02/01/21: Re: Quartus 2 and bus ripping
38688: 02/01/22: Re: Quartus 2 and bus ripping
38733: 02/01/23: Re: Quartus 2 and bus ripping
38790: 02/01/25: Question on synthesis
38833: 02/01/26: Re: Synthesis Tools for Xilinx
38843: 02/01/26: Altera support sites
38910: 02/01/28: Re: Xilinx webpack
38912: 02/01/28: Re: configuring an FPGA from an Hard-drive with a 80c51 (Stupid idea ?)
38972: 02/01/29: Re: Quartus 2 and bus ripping
39087: 02/01/31: Re: ProcWizard by Gidel
39295: 02/02/05: Making Altera development quicker
39297: 02/02/05: Re: FPGA vs GAL : Lattice
39329: 02/02/06: Re: Making Altera development quicker
39352: 02/02/07: Re: Making Altera development quicker
39364: 02/02/07: Re: MC6800 vhdl design
39367: 02/02/07: Re: Which PC for ALTERA development tools ?
39502: 02/02/12: Re: Making Altera development quicker
39523: 02/02/12: Re: Making Altera development quicker
39577: 02/02/13: Re: Is Leonardo spectrum OEM version for Altera limited?
39737: 02/02/18: Altera library problems.
39740: 02/02/18: Timing constraints
39761: 02/02/19: "DONT TOUCH" with Xilinx XST?
39956: 02/02/22: Re: Pin assignments in QUARTUS
40036: 02/02/25: Creation of FPGA tips and tricks forum - help required
40038: 02/02/25: Re: Pin assignments in QUARTUS
40097: 02/02/27: Re: Creation of FPGA tips and tricks forum - help required
40205: 02/03/01: Re: Altera Excalibur
40234: 02/03/02: Re: What FPGA to use?
40262: 02/03/04: Re: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to work correctly?
40311: 02/03/05: FPGA problems
40383: 02/03/06: Re: FPGA or DSP in a power supply?
40400: 02/03/06: Re: FPGA problems
40443: 02/03/07: Re: FPGA problems
40492: 02/03/07: Re: share two months salary with you if you have job information
40511: 02/03/08: Re: FPGA or DSP in a power supply?
40850: 02/03/16: Re: just bought
41255: 02/03/23: Re: High speed clock routing
41257: 02/03/23: Re: Clock termination affecting JTAG interface
41258: 02/03/23: Re: Ligthning strikes & EMI - SPARTAN II design in flight
41270: 02/03/23: Re: High speed clock routing
42446: 02/04/24: Changing ROM contents
44052: 02/06/11: IBIS to Spice Translation (part1)
44054: 02/06/11: IBIS to Spice Translation (part2)
44055: 02/06/11: IBIS to Spice Translation (part2)
44089: 02/06/11: IBIS to Spice Translation (part2)
44105: 02/06/11: Re: IBIS to Spice Translation (part1)
44106: 02/06/11: Re: IBIS to Spice Translation (part1)
44107: 02/06/11: IBIS to Spice translation (part2)
44164: 02/06/12: Re: What properties has FPGA?
45096: 02/07/12: Re: Getting started with FPGAs
45097: 02/07/12: Security features
46098: 02/08/19: Re: rising_edge detector?
46177: 02/08/21: Re: Academics vs 'real' FPGA use
46196: 02/08/21: Re: Academics vs 'real' FPGA use
46219: 02/08/21: Re: Logic Analyzers with an Altera Board
46548: 02/09/03: Re: In 2 clk domains. How to xfer data from 1 bus to the another ?
47627: 02/10/01: SPDE problems
48369: 02/10/16: Re: Virtex2 5V tolerant I/O ??
48407: 02/10/17: Re: multiple clocks
48409: 02/10/17: Re: FPGA fail when Electrostatic discharge Occurs
49251: 02/11/06: Quicklogic PAsic problem
53208: 03/03/06: Re: Issues in Outsourcing?
57541: 03/07/02: PCB Problem
57631: 03/07/03: Re: PCB Problem
64430: 04/01/04: is this a good idea
64431: 04/01/04: rs-232 trouble
64439: 04/01/04: Re: rs-232 trouble
64440: 04/01/04: Re: rs-232 trouble
64448: 04/01/05: Re: is this a good idea
64581: 04/01/08: submodules with their own constraint files
64992: 04/01/18: fpga4fun
65002: 04/01/18: 802.3 mii
65010: 04/01/18: fpga4fun ethernet
65527: 04/02/01: OS-less first executable how to? Please help!
65542: 04/02/01: binary file to bram tool
78887: 05/02/09: Re: ASIC vs DSP vs FPGA
79333: 05/02/17: Re: binary constant divider theory
79338: 05/02/17: Re: binary constant divider theory
80572: 05/03/08: Re: Good, affordable verilog simulator
89819: 05/09/27: Re: Version Control Software
89855: 05/09/28: Re: Version Control Software
101669: 06/05/04: =?utf-8?q?how_to_set_a_I/O_as_3-state_in_xilinx_FPGA=EF=BC=9F?=
102341: 06/05/15: Need help with old Xilinx project
102343: 06/05/15: Xilinx XC4000 series
108729: 06/09/15: Re: USB programming cables
108730: 06/09/15: Re: net skew
111585: 06/11/06: Re: Global Clocks in Xilinx Virtex-4
111750: 06/11/09: Re: Xilinx ISE ucf management
111751: 06/11/09: Re: abel to vhdl converter
111939: 06/11/13: Re: Virtex-5 Webpack?
111954: 06/11/13: Re: SPI module in FPGA
116426: 07/03/08: Re: Multiplication operation
116457: 07/03/09: Re: Introducing picosecond delay between two output signals
116458: 07/03/09: Re: Spartan3AN - Roadmap
116544: 07/03/12: Re: odd warning in Xilinx ISE webpack
116558: 07/03/12: Re: Addressing scheme in Block RAM
116609: 07/03/13: Re: Estimating number of FPGAs needed for an application
116837: 07/03/19: Re: What official function should I call to genertate a sum of products in VHDL
116867: 07/03/20: Re: How to use the DDR SDRAM instead of Block RAM?
116899: 07/03/20: Re: create test bench of video
117120: 07/03/23: Re: Austin the Altera Mole
117190: 07/03/26: Re: Austin the Altera Mole
117244: 07/03/27: Re: help needed
117247: 07/03/27: Re: Spartan 3E Not enough block ram.
117317: 07/03/28: Re: Confuse on Spartan speed
117519: 07/04/03: Re: Does the XC3S250E-VQ100 exist?
117573: 07/04/04: Re: FPGA with 5V and PLCC package
117665: 07/04/06: Re: Looking for Memory Recommendation for Spartan 3E 1200
117730: 07/04/09: Re: Xilinx ISE constanly asking to regenerate a core file.
117851: 07/04/11: Re: VIrtex-4 FIFO16
118010: 07/04/16: Re: picoblaze C compiler download wanted
118585: 07/04/30: Re: Please help me fast !!!!!
118729: 07/05/02: Re: Xilinx Spartan 3 XC3S200 and Xilinx Foundation Series 3.1i beginner problems
118777: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118778: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118784: 07/05/03: Re: Video scaler for Spartan 3E?
118796: 07/05/03: Re: Wait-for / until won't work ? Xilinx Spartan 3
118835: 07/05/04: Re: Video scaler for Spartan 3E?
118923: 07/05/07: Re: About DDR SDRAM
119006: 07/05/09: Re: About memory interface generater 007 tool
119018: 07/05/09: 'EVENT (or rising_edge) static prefix requirement....
119020: 07/05/09: Re: 'EVENT (or rising_edge) static prefix requirement....
119060: 07/05/10: Re: 'EVENT (or rising_edge) static prefix requirement....
119087: 07/05/11: Re: Video scaler for Spartan 3E?
119168: 07/05/14: Re: Digital gain and offset correction
119296: 07/05/16: Re: clock wide pulse transfer b/w clock domains
119363: 07/05/17: Re: clock wide pulse transfer b/w clock domains
119385: 07/05/17: Re: clock wide pulse transfer b/w clock domains
122219: 07/07/24: hard_temac : mdio conflict
122246: 07/07/24: Re: hard_temac : mdio conflict
122260: 07/07/24: Re: hard_temac : mdio conflict
122302: 07/07/25: Re: hard_temac : mdio conflict
122381: 07/07/26: plb_temac with lwip and sgdma
127085: 07/12/11: Chipscope 7.1 and JTAG TAP
127127: 07/12/12: Debugging designs that are running on FPGA
127174: 07/12/13: Re: Debugging designs that are running on FPGA
127927: 08/01/10: Cant capture data with Chipscope 7.1
127959: 08/01/11: Re: Cant capture data with Chipscope 7.1
127966: 08/01/11: Re: Cant capture data with Chipscope 7.1
145539: 10/02/13: Re: VHDL vs Verilog
145559: 10/02/14: Re: VHDL vs Verilog
145563: 10/02/14: Re: VHDL vs Verilog
145569: 10/02/14: Re: VHDL vs Verilog
146624: 10/03/24: Re: Xilinx ISE Tcl Script Error
147064: 10/04/12: Re: I'd rather switch than fight!
147087: 10/04/13: Re: I'd rather switch than fight!
147159: 10/04/16: Re: I'd rather switch than fight!
147187: 10/04/16: Re: I'd rather switch than fight!
148936: 10/09/13: Re: Question about OC PCI Cores
148939: 10/09/13: Re: Question about OC PCI Cores
paul:
53148: 03/03/04: Re: Implementation of latch in FPGA
80444: 05/03/05: Spartan 3 - insurge current
80494: 05/03/07: Re: Spartan 3 - insurge current
Paul Graham:
433: 94/11/15: Re: Anybody used FPGA as Encryption Device?
Paul Tobias:
110503: 06/10/16: Missing Xilinx EDK Temac example
118986: 07/05/08: Re: lwIP RAW mode support for V4 temac
119801: 07/05/26: Re: EDK9.1: XTemac + LwIP + Xilkernel + unistd.h = possible?
Paul A. Clayton:
121192: 07/06/27: Re: Bit error counter - how to make it faster
Paul Amblard:
3298: 96/05/10: Re: Synario Universal FPGA Design System
Paul Attilla Richards:
14346: 99/01/26: Xilinx - Questions on clock & Async delays.
14387: 99/01/28: Re: Xilinx - Questions on clock & Async delays.
Paul Augart:
24728: 00/08/17: Re: Non-disclosures in job interviews
Paul Barton:
18122: 99/10/01: Moto 6809E
Paul Bateson:
28073: 00/12/20: Samsung SDRAM behavioural models
Paul Baxter:
6173: 97/04/22: Re: The FreeCore Library is here!
6872: 97/07/04: Fast sampling techniques. Was: Fast scopes, How?
8342: 97/12/09: Re: Need a fast ADC
8640: 98/01/15: Re: Byteblaster
14795: 99/02/17: Re: "Altera FreeCore Library" back on the web
17357: 99/07/22: Re: Solaris vs. NT
17358: 99/07/22: Re: Solaris vs. NT
38581: 02/01/18: Re: DDR-Interface
41067: 02/03/20: Re: Modelsim or Quartus II Simulator
41157: 02/03/21: Re: synplify, quartus II 2.0
41403: 02/03/27: Quartus 2, ActiveHDL and megafunctions like altclklock
41518: 02/04/01: Re: ALTERA Apex Device
41786: 02/04/08: Re: signal delay in altera 20KE
41791: 02/04/08: Re: Modelsim from Altera vs Modelsim from Menthors
41986: 02/04/12: Re: problems with Nios 2.0
42127: 02/04/16: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
42157: 02/04/17: Re: GND Outputs being optimized out using FPGA Express 3.6.1 in ISE4.2.01
42193: 02/04/18: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
42195: 02/04/18: Re: 1000 I/O Pins -- What is cheapest FPGA?
42242: 02/04/18: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
42645: 02/04/30: Re: Loading values in Quartus II Waveform editor
43067: 02/05/12: Re: dual port fifo
43490: 02/05/22: Re: Aldec Active-HDL 5.1 + Xilinx ISE 4.1 - how to simulate ?
43498: 02/05/22: Re: Time for a new computer. Suggestions?
43952: 02/06/07: Re: Quartus v/s Leonardo
44692: 02/06/27: Re: Loops in Quartus II
44865: 02/07/03: Re: Anyone use the full Aldec 5.1 flow?
45139: 02/07/13: Re: Accurate Oscillator
45153: 02/07/13: Re: Accurate Oscillator
46014: 02/08/14: Re: Altera APEX clock problem
46180: 02/08/21: Re: Multiple Nios ...
46322: 02/08/26: Re: Export from ModelSim to Excel?
46456: 02/08/30: SDRAM - is concurrent auto precharge common?
46477: 02/08/31: Re: The Prodigal Son
46514: 02/09/02: Re: high-speed design rule on FPGAs?
46614: 02/09/04: Re: Altera APEX clock problem
46666: 02/09/05: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46701: 02/09/06: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46727: 02/09/06: Measuring FPGA performance eg max clock speed
46738: 02/09/06: Re: Measuring FPGA performance eg max clock speed
46793: 02/09/09: Altera counter - want an unregistered cout
47009: 02/09/14: Re: sustainable rate for Random Read of DDR SDRAM
47549: 02/09/28: Re: FPDP
47596: 02/09/30: Re: Large Multiplexer
47629: 02/10/01: Re: FFT in FPGA?
47661: 02/10/01: Re: USB2 in FPGA?
48136: 02/10/11: Re: Active HDL
48137: 02/10/11: Re: Quartus design question
48844: 02/10/25: Re: FPGA board recommendation
50359: 02/12/09: Re: question about fft vs. cross corelation in fpga
52088: 03/01/31: Re: Quartus
52095: 03/01/31: Re: Quartus
52394: 03/02/07: Re: FFT Size and speed
52395: 03/02/07: Re: FFT Size and speed
52596: 03/02/15: Re: Quartus / ModelSim
53591: 03/03/17: Re: FPGA dev boards
54164: 03/04/03: Altera not supplying Leonardo any more
54472: 03/04/11: Re: Altera not supplying Leonardo any more
54636: 03/04/15: Re: Verilog to VHDL or vice-versa converters ??
54764: 03/04/17: Re: Boycott All Xilinx products untill they correct all ISE software errors
55313: 03/05/03: Re: use of DRAM as massive FIFO
55512: 03/05/11: Re: PacMan game in FPGA
56480: 03/06/06: Re: Quartus II time delay
58978: 03/08/05: Re: Conflict found between ActiveHDL6.1 and ModelSim SE
59147: 03/08/10: Re: speeding up quartus
59276: 03/08/13: Re: Limitations of Quartus II V3.0 Web
59898: 03/08/31: Re: HDL Designer from Mentor
59929: 03/09/01: Re: HDL Designer from Mentor
Paul Bealing:
49689: 02/11/20: Re: Programming Altera EPC16
Paul Bobko:
85767: 05/06/15: Using BUFGMUX component in Spartan-3
Paul Boven:
82763: 05/04/18: Re: LUT in fpga
82799: 05/04/18: Re: LUT in fpga
83568: 05/05/03: DCM, constraints and routing (Xilinx Spartan 3)
84229: 05/05/15: Re: floorplanning
84358: 05/05/18: Re: Is a gated oscillator using NAND okay within a Cyclone FPGA?
86906: 05/07/08: Timespec for DCM outputs (Spartan 3) ?
86914: 05/07/08: Re: Timespec for DCM outputs (Spartan 3) ?
86916: 05/07/09: Re: Timespec for DCM outputs (Spartan 3) ?
89081: 05/09/05: Fastest input IOB on a Spartan-3?
90014: 05/10/02: Xilinx/Linux: sch2vhdl not working very hard
90016: 05/10/02: Re: Xilinx/Linux: sch2vhdl not working very hard
93698: 05/12/28: What is 'drive strength' for? (Spartan 3)
128770: 08/02/06: Simulator error 607
128819: 08/02/07: Re: Simulator error 607
129289: 08/02/20: Re: Which Linux Distro to use for Xilinx tools
129940: 08/03/11: BRAM synthesis question
129959: 08/03/11: Re: BRAM synthesis question
130326: 08/03/20: Configuring a Spartan 3A1800 ExtremeDSP from Spartan3 cable?
130483: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130689: 08/03/30: Re: Configuring a Spartan 3A1800 ExtremeDSP from Spartan3 cable?
130739: 08/03/31: Impact won't program XC3S200, does program XC3SD1800A
134156: 08/07/28: Re: Spartan-3A DSP 1800A Dev Board JTAG Cable and Programming Software
134696: 08/08/26: Side-BUFG, BRAMS and clock routing
134704: 08/08/27: Re: Side-BUFG, BRAMS and clock routing
135900: 08/10/21: Question on timing constraints
136010: 08/10/27: Re: Question on timing constraints
136383: 08/11/13: Re: platform cable usb II problem
136624: 08/11/27: Re: ip core connection
143598: 09/10/17: Re: Any interest in a group Xilinx FPGA board build/buy ??
Paul Brown:
368: 94/10/31: Re: about ALTERA
387: 94/11/04: Re: about ALTERA
600: 95/01/16: Re: PCB design with Xilinx
2247: 95/11/09: JTAG IEEE std 1149.1
Paul Bunyk:
9279: 98/03/05: Re: The case for Linux and EDA
22323: 00/05/04: Q: simplest FPGA structure for novel technology demonstration
22352: 00/05/05: Re: Q: simplest FPGA structure for novel technology demonstration
22409: 00/05/08: Re: Q: simplest FPGA structure for novel technology demonstration
22410: 00/05/08: Re: Q: simplest FPGA structure for novel technology demonstration
Paul Burke:
22670: 00/05/17: Re: SMT 7 segment display ??
31440: 01/05/24: Re: frequency ramp
41178: 02/03/22: Re: Clock termination affecting JTAG interface
47741: 02/10/03: Re: Need advice wiring up a CPLD
54466: 03/04/11: Re: Using DP RAM for message passing
59010: 03/08/06: Re: Questions in Altera FPGA MegaCore Compact-PCI Configuration Space
64500: 04/01/06: Re: 4-bit binary divider circuit PLEASE!!!!!!!
72885: 04/09/07: Re: VHDL code for 16-32 bit counter for quadrature encoder signals
72960: 04/09/09: Re: VHDL code for 16-32 bit counter for quadrature encoder signals
76933: 04/12/16: Re: Exportability of EDA industry from North America?
94992: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95051: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95182: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95183: 06/01/21: Re: OT:Shooting Ourselves in the Foot
110640: 06/10/19: Re: Cheapest FPGA board to study VHDL on
Paul Burridge:
67497: 04/03/13: Re: ANN: new Pulsonix version 3 PCB software released
Paul Butler:
15667: 99/04/07: Data Types and Synthesis
15685: 99/04/08: Re: Data Types and Synthesis
15686: 99/04/08: Re: Data Types and Synthesis
17417: 99/07/26: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
17422: 99/07/26: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
17475: 99/07/30: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
17702: 99/08/25: Re: Virtex BRAM Initialization
18757: 99/11/12: Re: FPGA Expess vs. Synplify vs. Leonardo Spectrum
19756: 00/01/11: Re: HW resources increased
19771: 00/01/11: Re: HW resources increased
20352: 00/02/07: Re: ADC to DSP... FIFO?
20383: 00/02/08: Re: ADC to DSP... FIFO?
20385: 00/02/08: Re: ADC to DSP... FIFO?
35498: 01/10/08: Synplify and internal tristate
40210: 02/03/01: Re: cross clock domain signals
40277: 02/03/04: Minimum Size and Logic Sharing
41128: 02/03/21: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41908: 02/04/10: Re: Checking Synthesis tools.
41935: 02/04/11: Re: Checking Synthesis tools.
42457: 02/04/24: Re: Xilinx Easypath- Selling parts with known defects
42977: 02/05/08: Re: FIFO
44185: 02/06/13: Re: fpga and ultra highspeed counters
44593: 02/06/24: Re: CIC filter
50831: 02/12/20: Re: Gray code comparisons
Paul Campbell:
28614: 01/01/18: Re: revision control tools ??
28836: 01/01/26: Re: looping and ranges
28877: 01/01/26: Re: looping and ranges
31584: 01/05/30: Re: [Q]setup-time violation
31682: 01/06/02: Re: [Q]setup-time violation
33618: 01/08/01: Re: Spanning the heirarchy
48154: 02/10/12: Re: Quartus design question
Paul Carpenter:
68463: 04/04/05: Re: ATMEL support / Are they serious ?
95196: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95197: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95266: 06/01/21: Re: OT:Shooting Ourselves in the Foot
102761: 06/05/19: Re: CPLD (CoolRunner failures)
102816: 06/05/21: Re: CPLD (CoolRunner failures)
135744: 08/10/14: Re: XMOS XC-1 kits are shipping
135745: 08/10/14: Re: XMOS XC-1 kits are shipping
147783: 10/05/24: Re: Xilinx Xact software for XC2018 Logic Cell Array
paul chai:
1092: 95/04/27: Altera Vs Xilinx
Paul Chien:
11859: 98/09/15: Re: ASIC -> FPGA async issues
11860: 98/09/15: Re: ASIC -> FPGA async issues
Paul Clapis:
17892: 99/09/16: Xilinx on PMC?
Paul Colin Gloster:
150170: 10/12/24: Re: spacewire project on opencores.org
151645: 11/04/30: Re: Anti-benchmarking clauses
152681: 11/09/29: Re: The Manifest Destiny of Computer Architectures
152704: 11/10/04: Re: FPGA acceleration v.s. GPU acceleration
154145: 12/08/21: Re: recruit FPGA design engineer in Scotland
154154: 12/08/22: Re: recruit FPGA design engineer in Scotland
154155: 12/08/22: Re: recruit FPGA design engineer in Scotland
154156: 12/08/22: Re: recruit FPGA design engineer in Scotland
154163: 12/08/23: Re: recruit FPGA design engineer in Scotland
154713: 12/12/28: Re: Looking for evaluators for NEW Vector Processor for FPGAs,
154714: 12/12/28: Re: Where to move for an embedded software engineer.
154715: 12/12/28: Re: Where to move for an embedded software engineer.
154724: 12/12/29: Re: Where to move for an embedded software engineer.
154753: 13/01/04: Re: Chisel as alternative HDL
154880: 13/01/26: Re: Ray Andraka's Book?
Paul Costa:
53200: 03/03/06: Re: filter coefficients from sig. proc. toolbox to xilinx
Paul Cousoulis:
51686: 03/01/19: PLX PCI DMA address
51695: 03/01/20: Re: PLX PCI DMA address
51700: 03/01/20: Re: PLX PCI DMA address
51727: 03/01/20: Re: PLX PCI DMA address
55851: 03/05/21: tms34010 fpga core
56956: 03/06/19: Re: Altera FPGA
Paul Dankoski:
55186: 03/04/29: Re: Challenge: (n mod 3) in hardware???
Paul Davis:
80581: 05/03/08: Async FIFO problem...
80589: 05/03/08: Re: Async FIFO problem...
80592: 05/03/08: Re: Async FIFO problem...
Paul DeMone:
7049: 97/07/27: Re: PCI burst transfers
7106: 97/07/31: Re: PCI burst transfers
21149: 00/03/08: Re: Microprocessor architecture (6800, 4004? PA-RISC, PPC, MIPS, x86,
28277: 01/01/04: Re: Nondeterministic FSMs in hardware?
Paul Dietrich:
4641: 96/11/25: Re: How to utilize XC4000e IOB FFs in Synopsys?
4666: 96/11/27: Re: How to utilize XC4000e IOB FFs in Synopsys?
Paul Donachy:
22: 94/07/29: Question: Using FPGA as onboard controller
4051: 96/09/06: XC6200 based image processing coprocessor
4095: 96/09/10: Feedback on Xilinx XC6200 image processing coprocessor
4417: 96/10/25: New user
Paul Dunn:
24012: 00/07/21: RE: HELP!! Nallatech Virtex Board.
Paul E. Bennett:
2657: 96/01/20: Re: PLD JDEC Files
82259: 05/04/09: Re: Reverse engineering masked ROMs, PLAs
85218: 05/06/06: Re: Sch & Layout Free Program
117711: 07/04/08: Re: A new way to define systems of systems?
117715: 07/04/08: Re: A new way to define systems of systems?
147225: 10/04/19: Re: Need to run old 8051 firmware
149195: 10/10/06: Re: Driving a design via TCP/IP
"Paul E. Bennett":
5838: 97/03/19: Re: PLC
6798: 97/06/28: Re: Smart Card Design and Interface. How?
9603: 98/03/25: Re: New radix-4 CORDIC for computing sine and cosine
24761: 00/08/17: Re: Non-disclosures in job interviews, Round One
24762: 00/08/17: Re: Non-disclosures in job interviews
24764: 00/08/17: Re: Non-disclosures in job interviews, Round One
24776: 00/08/18: Re: Non-disclosures in job interviews
24966: 00/08/23: Re: Non-disclosures in job interviews, Round One
25019: 00/08/24: Re: Non-disclosures in job interviews, Round Two
31114: 01/05/12: Re: [Q]CardBus PC Card with PCI device
67635: 04/03/16: Re: Schematic Edition Tool : Suggestions
68861: 04/04/20: Re: What does a "background check" mean? ...
68970: 04/04/23: Re: transport applications
Paul E. Black:
66779: 04/02/26: Re: Automatic Placement algorithm, help needed
Paul Elliott:
163: 94/09/05: Re: bitsteams and freeware translators
Paul F. Mondello:
9859: 98/04/09: Re: Implementation of Shift Registers and Buffers
Paul Floyd:
104874: 06/07/07: Re: How much time does it need to sort 1 million random 64-bit/32-bit integers?
105496: 06/07/24: Re: Hardware book like "Code Complete"?
105700: 06/07/28: Re: Hardware book like "Code Complete"?
124672: 07/09/29: Re: Does Modelsim work under Windows Vista?
Paul Franklin:
2945: 96/03/04: Re: Comp.Arch.FPGA
66359: 04/02/18: FPGA vendors and their patents
66638: 04/02/24: Re: FPGA vendors and their patents
67746: 04/03/18: Synthesis algorithm - help needed
Paul Freda:
10678: 98/06/10: Re: Example of 8051 codes to configure Xilinx fpga
Paul Fulghum:
70677: 04/06/23: Re: 5V board in a 3.3V PCI slot
70684: 04/06/23: Re: 5V board in a 3.3V PCI slot
72650: 04/08/27: Re: Xilinx Spartan II and 5V PCI
72753: 04/08/31: Re: Xilinx Spartan II and 5V PCI
72774: 04/09/01: Re: Xilinx Spartan II and 5V PCI
72775: 04/09/01: Re: Xilinx Spartan II and 5V PCI
Paul Gentieu:
59118: 03/08/08: Virtex-II RocketIO: Serial ATA?
89336: 05/09/13: CPU benchmark for Xilinx PAR
Paul Gigliotti:
21843: 00/04/03: Re: Virtex Secondary Clock Nets
Paul Glover:
41140: 02/03/21: Re: Maximum device usage for successful PAR
41142: 02/03/21: Re: simulation issues
Paul Gotch:
152801: 11/10/24: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152803: 11/10/25: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152824: 11/10/26: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
152828: 11/10/26: Re: Patent Reform Town Hall Meeting (Balt/Washington Area IEEE Consultants Network)
Paul Graham:
33087: 01/07/17: Using the Xilinx Alliance 3.1i/3.3i Tools under Linux
33105: 01/07/17: Re: Using the Xilinx Alliance 3.1i/3.3i Tools under Linux
Paul Gray:
73057: 04/09/13: Adding a Delay
73104: 04/09/14: Adding a Delay2
Paul Grems Duncan:
7840: 97/10/21: Re: Help on coding numerical algorithms using VHDL
Paul Hands:
17383: 99/07/23: Re: Workstation with Synopsys license server
Paul Hardy:
6143: 97/04/17: Re: Xilinx 4KE's and SBUS
34925: 01/09/14: Re: Clock Multiplication
34928: 01/09/14: Re: Segmented interconnects
34934: 01/09/14: Re: Clock Multiplication
34937: 01/09/14: Re: Clock Multiplication
50042: 02/11/29: Re: System Generator and 18x18 multipliers
Paul Hartke:
55513: 03/05/11: Re: PacMan game in FPGA
63654: 03/11/27: Re: what is the fastest speed that FPGA deals with CPU?
71436: 04/07/18: Re: Memory width on Spartan-3 boards
71437: 04/07/18: Re: Memory width on Spartan-3 boards
71439: 04/07/18: Re: Memory width on Spartan-3 boards
71758: 04/07/29: Re: pci X open core
72097: 04/08/08: Re: Xilinx Student Edition 6.x?
73072: 04/09/13: Re: Xilinx EDK and plb master
73083: 04/09/13: Re: ML300 Ethernet question.
73130: 04/09/14: Re: Xilinx EDK and plb master
78359: 05/01/30: FPGAs used to crack RFID crypto
78564: 05/02/03: Re: Q, compile option, mb-gcc
78687: 05/02/05: Re: OPB ZBT
79799: 05/02/24: Implementing Multi-Processor Systems
81876: 05/04/03: Re: Spartan 3, Microblaze and FPU
81877: 05/04/03: Re: IPIF Signals
81878: 05/04/03: Re: OPB Master
81972: 05/04/05: Re: RAMB16_S9
82018: 05/04/05: Re: EDK-Creating new peripheral
82198: 05/04/08: Re: Simualtion of Rocket I/O MGT in ModelSim XE
82199: 05/04/08: Re: running microblaze from bram through OPB-bus
82263: 05/04/09: Re: EDK: Microblaze with XMdstub
82375: 05/04/11: Re: Application using coprocessor interface
82424: 05/04/12: Re: running microblaze from bram through OPB-bus
82490: 05/04/13: Re: opb_ethernet timing constraints
82534: 05/04/13: Re: PPC405 Performance Monitoring
82767: 05/04/17: Re: Microblaze Functions (Xilinx Specific)
82768: 05/04/17: Re: EDK: microblaze local memory
83024: 05/04/21: Re: PPCs sharing an OCM BRAM
83095: 05/04/23: Re: DDR SODIMM on Avnet Virtex II PRO development kit
83127: 05/04/24: Re: OCM interface to SDRAM
83500: 05/05/01: Re: Microblaze FSL interface timing diagram
83612: 05/05/03: Re: ERROR: NgdBuild:604 - logical block
83867: 05/05/08: Re: EDK: user logic on opb bus in microblaze system
83903: 05/05/09: Re: Simulating custom peripherals
84024: 05/05/11: Re: Frequency limitations?
84025: 05/05/11: Re: how to use libm.a and libc.a
84027: 05/05/11: Re: strange Microblaze error
84070: 05/05/11: Re: How to use XMD debugger
84592: 05/05/22: Re: Custom IP and BFM simulation help
85564: 05/06/10: Re: xmodem/kermit for edk/ppc
85674: 05/06/13: Re: Adding Verilog processing core to Viretx2Pro at ML310
86008: 05/06/20: Re: Speeding up FPGA designs
86028: 05/06/20: Re: How to reset a PLB/OPB Peripheral
86203: 05/06/22: Re: User Core to PLB Bus example for Virtex 2P in EDK.
87138: 05/07/16: Re: Can't run Xilinx 7.1SP3 on FC3
87180: 05/07/18: Re: setting XUP new board
87705: 05/07/28: Re: Digilent's JTAG-USB cable with chipscope
88106: 05/08/09: Re: Linux driver for Embedded TEMAC in Virtex4
88107: 05/08/09: Re: Incorporating Cores to the Virtex2Pro PLB
88114: 05/08/09: Re: Incorporating Cores to the Virtex2Pro PLB
88170: 05/08/10: Re: EDK and ISE questions
88187: 05/08/11: Re: XILINX POWERPC <-> Embedded tri-mode-MAC connection
88203: 05/08/11: Re: fpga- DDR or DDR2
88284: 05/08/14: Re: EDK IPIF + User Core
88450: 05/08/18: Re: Two microblaze in EDK
88457: 05/08/18: Re: Two microblaze in EDK
88469: 05/08/18: Re: Download bit stream onto ml310 ( virtex 2 pro ) using uart cable
88482: 05/08/19: Re: Two microblaze in EDK
88672: 05/08/24: Re: Single PPC with DES on V2P
88696: 05/08/25: Re: Single PPC with DES on V2P
88966: 05/09/01: Re: Using the XUP Virtex-II Pro with EDK 6.3 => errors during platform
89010: 05/09/02: Re: XUP Virtex-II Pro "invalid target architecture"
89057: 05/09/04: Re: Partial Reconfiguration : New Forum
89101: 05/09/05: Re: XUP Virtex-II Pro "invalid target architecture"
89215: 05/09/07: Re: PCI on ML310 Xilinx board
89236: 05/09/08: Re: digilent web site?
89241: 05/09/08: Re: Microblaze and LMB
89282: 05/09/10: Re: creating a custom opb bus master
89358: 05/09/13: Re: Followup: USB cable, Xilinx XUP, EDK/ISE 7.1, Fedora Core 3
89359: 05/09/13: Re: XUP Virtex-II Pro "invalid target architecture"
90663: 05/10/18: Re: Linux and Platform USB Cable
90840: 05/10/22: Re: EDK on Virtex4 FX using embedded ethernet MAC
90841: 05/10/22: Re: EDK/ISE : unroutable design
90842: 05/10/22: Re: to write the driver for my own ip core
91249: 05/11/02: Re: differential clock in EDK
92364: 05/11/28: Re: instruction counts and cache hits/misses on FPGA
92495: 05/11/30: Re: Merging the ML403 refence design and the GSRD design
92496: 05/11/30: Re: Xilinx EDK GPIO IP with FIFO function (input only)
92764: 05/12/06: Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS
92770: 05/12/06: Re: XUP PLATFORM USB CHIPSCOPE COMPATIBILITY PROBLEMS
92876: 05/12/08: Re: FPGA development board with digital image camera
93157: 05/12/14: Re: Xst Error
93529: 05/12/23: Re: Virtex-4FX and ethernet mac
93530: 05/12/23: Re: Is there anybody that have ported the linux to the nios or
93638: 05/12/27: Re: Microblaze in a EDK pcore
93676: 05/12/28: Re: Xilinx ISE Simulator
93832: 06/01/01: Re: Microbalze program initialization ...
94507: 06/01/12: Re: Xilinx Vertex II Pro with tow VDEC videodevices
94704: 06/01/16: Re: BRAM/XMD strangeness?
94854: 06/01/18: Re: data2bram and coregen
94949: 06/01/19: Re: data2bram and coregen
96350: 06/02/02: Re: xilinx linux source?
96473: 06/02/03: Re: core generator
96487: 06/02/04: Re: multi-processor linux on xilinx
96769: 06/02/09: Re: Simulation of MicroBlaze embedded system
96788: 06/02/10: Re: ANTTI*HAPPY: building MicroBlaze uClinux on WinXP full sucess !!
96789: 06/02/10: Re: Simulation of MicroBlaze embedded system
97201: 06/02/18: Re: ISE Simulator Price
97215: 06/02/18: Re: MontaVista Linux and Virtex-II & 4
97231: 06/02/19: Re: help with VGA timings
97646: 06/02/25: Re: A dev board supporting partial/dynamic reconf.
97647: 06/02/25: Re: Module-based partial reconfiguration in ISE Webpack
97786: 06/02/27: Re: NGCBUILD .. MDT error on Virtex 4
98867: 06/03/17: Re: EDK : PPC405 Interrupt question
98868: 06/03/17: Re: SerialATA with Virtex-II Pro
98932: 06/03/17: Re: HWICAP with the Virtex II Pro. Anybody? Bueller?
98934: 06/03/17: Re: Getting started w/ Aurora Core
98947: 06/03/17: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
99981: 06/03/31: Re: hwicap can be used in the virtex4
99983: 06/03/31: Re: Testing sample Aurora design on ML321 board
100117: 06/04/03: Re: Virtex-4 readback via ICAP
100118: 06/04/03: Re: hwicap can be used in the virtex4
100155: 06/04/04: Re: XUPV2P
101276: 06/04/28: Re: Assigning MGT's in sample Aurora Design
101827: 06/05/07: Re: Xilinx 3s8000?
Paul Hartley:
4265: 96/10/07: Re: Q on Xilinx/Viewsim macros
Paul Hatcher:
6668: 97/06/11: XC1700 programming algorithm
paul hill:
45187: 02/07/15: dsp v fpga
Paul Hoepping:
3432: 96/05/30: Do you use Atmel FPGA?
Paul Hohle:
42609: 02/04/29: SMI (Software Model Interface)
Paul Hollingworth:
77395: 05/01/05: Re: Tracking down HardWired History
79652: 05/02/22: Re: Hardcopy Vs ASIC
79724: 05/02/23: Re: Hardcopy Vs ASIC
85689: 05/06/13: Re: Synplify/Quartus used to support direct to Hardcopy?
97128: 06/02/16: Re: User masks in HardCopy and HardCopy II
Paul Hovnanian:
53233: 03/03/07: Re: Issues in Outsourcing?
Paul Hovnanian P.E.:
95377: 06/01/22: Re: OT:Shooting Ourselves in the Foot
Paul Hovnanian ®:
25616: 00/09/15: Re: hardware compatibility and patent infringement
25632: 00/09/15: Re: hardware compatibility and patent infringement
Paul Hsieh:
11512: 98/08/20: Re: vector product minimization problem
Paul Hunter:
912: 95/03/29: Re: Excuse me while I vent about Data I/O & Abe
Paul J Menchini - Menchini and Associates:
697: 95/02/09: Re: VERILOG
3146: 96/04/12: Re: VHDL conversion function from int to time ...?
Paul J. Menchini:
10035: 98/04/23: Re: Ask
10986: 98/07/08: Re: Simulation at powerup
10987: 98/07/08: Re: Simulation at powerup
11163: 98/07/22: Re: How to write a VHDL counter of up & down
35203: 01/09/25: Re: SmartMedia
Paul J. White:
15668: 99/04/07: Re: LCD Ip Core
Paul Jansen:
114541: 07/01/18: Re: Different Modelsim versions disagree in same backannotation!
114754: 07/01/23: Re: Different Modelsim versions disagree in same backannotation!
Paul Johnson:
96279: 06/02/01: Re: Die Area
96300: 06/02/01: Re: Die Area
96244: 06/02/01: Gbit technology selection?
96303: 06/02/01: Re: don't care condition
96375: 06/02/02: Re: BGA central ground matrix
96405: 06/02/03: Re: BGA central ground matrix
96406: 06/02/03: Re: BGA central ground matrix
96407: 06/02/03: Re: FPGA growth vs. ASIC growth
96447: 06/02/03: Re: BGA central ground matrix
96454: 06/02/03: Re: FPGA growth vs. ASIC growth
96457: 06/02/03: Re: Looking for literature on microprogrammed machines
96461: 06/02/03: Re: FPGA growth vs. ASIC growth
96512: 06/02/05: Re: FPGA growth vs. ASIC growth
96513: 06/02/05: RocketIO & Infiniband BERs?
96543: 06/02/06: Re: FPGA growth vs. ASIC growth
96772: 06/02/10: Re: Async Processors
96773: 06/02/10: Re: Async Processors
Paul Jones:
5825: 97/03/18: Re: PLC
Paul K:
70375: 04/06/14: Atmel WinCupl
70406: 04/06/15: Re: Atmel WinCupl
70499: 04/06/17: Re: Atmel WinCupl
Paul Keinanen:
27409: 00/11/21: Re: ANNOUNCE: Checksum and CRC Code/Article
85817: 05/06/16: Re: Idea exploration - Image stabilization by means of software.
85862: 05/06/17: Re: Idea exploration - Image stabilization by means of software.
85967: 05/06/19: Re: Idea exploration - Image stabilization by means of software.
85968: 05/06/19: Re: Idea exploration - Image stabilization by means of software.
92749: 05/12/06: Re: Quick question, how do I supply +-5V?
95186: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95187: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95194: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95378: 06/01/23: Re: OT:Shooting Ourselves in the Foot
123856: 07/09/06: Re: high bandwitch ethernet communication
123873: 07/09/06: Re: high bandwitch ethernet communication
123965: 07/09/08: Re: high bandwitch ethernet communication
124096: 07/09/12: Re: Uses of Gray code in digital design
124133: 07/09/12: Re: precision errors. microblaze vs matlab single precision... huh?
125412: 07/10/25: Re: Changing refresh rate for DRAM while in operation?
130925: 08/04/05: Re: A Challenge for serialized processor design and implementation
Paul Kraszewski:
10250: 98/05/07: CPLD devices
Paul Krotchen:
8636: 98/01/15: Altera FLEX10K Prototype/Development Platform
Paul Lee:
83445: 05/04/29: Median Filter for floating points
86322: 05/06/24: Re: Mapping Dual Port Ram into Microblaze address space
86323: 05/06/24: Re: Memory Controller and State Machine
89575: 05/09/19: Re: Using BRAMs in VHDL on Virtex II FPGAs
100142: 06/04/04: XUPV2P
100309: 06/04/06: XUPv"P DDR failure log
100374: 06/04/07: Re: XUPv"P DDR failure log
103393: 06/06/01: Re: RocketIO signal polarity swap
103592: 06/06/06: Re: GPIO problem
Paul Leventis:
54253: 03/04/06: Re: Matrix multiply in FPGA
54393: 03/04/10: Re: Cheap(er) FPGA configuration?
54407: 03/04/10: Re: $4000 FPGAs
54409: 03/04/10: Re: Cheap(er) FPGA configuration?
54612: 03/04/14: Re: NIOS 3.0 Fmax and other Issues
54613: 03/04/15: Re: NIOS 3.0 Fmax and other Issues
54739: 03/04/17: Re: spartan2e vs cyclone
54746: 03/04/17: Re: spartan2e vs cyclone
54768: 03/04/17: Re: spartan2e vs cyclone
54772: 03/04/17: Re: NIOS 3.0 Fmax and other Issues
54801: 03/04/18: Re: spartan2e vs cyclone
54943: 03/04/22: Re: NIOS 3.0 Fmax and other Issues
55048: 03/04/25: Re: WANTED ALTERA CYCLONE PCI BOARD
55162: 03/04/29: Re: clock i/o`s Altera Cyclone
55181: 03/04/29: Re: DSP/FPGA board
55365: 03/05/06: Re: LPM_ROM problem with Altera EP1K50 parts
55903: 03/05/23: Re: New version,Low Speed
56016: 03/05/27: Re: Can I implement a NIOS cpu in EP1C6
56181: 03/05/30: Re: FPGA's an Flash
56228: 03/05/31: Re: FPGA's an Flash
56239: 03/06/01: Re: New version,Low Speed
56505: 03/06/07: Re: Zero for replication multiplier --Quartus Bug?
56506: 03/06/07: Re: Zero for replication multiplier --Quartus Bug?
57042: 03/06/21: Re: Quartus / Leonardo frustration
57063: 03/06/23: Re: Implementing standard DDR module with Cyclone 1C6 (240PQFP)
57078: 03/06/23: Re: Implementing standard DDR module with Cyclone 1C6 (240PQFP)
57117: 03/06/24: Re: Quartus bug or wrong VHDL?
57118: 03/06/24: Re: Implementing standard DDR module with Cyclone 1C6 (240PQFP)
57167: 03/06/24: Re: Quartus II for Linux
57316: 03/06/27: Re: I need a commercial PCI FPGA board, please help
57318: 03/06/27: Re: Eighty layers of metal!
57348: 03/06/28: Re: why so many problems Xilinx ?
57364: 03/06/28: Re: why so many problems Xilinx ?
57374: 03/06/29: Re: why so many problems Xilinx ?
57383: 03/06/29: Re: why so many problems Xilinx ?
57543: 03/07/02: Re: why so many problems Xilinx ?
57598: 03/07/02: Re: Cyclone vs Spartan-3
57689: 03/07/03: Re: Cyclone vs Spartan-3
58206: 03/07/17: Re: PROM size for spartan
58225: 03/07/17: Re: Combinational logic and gate delays - Help
58408: 03/07/22: Re: Internal Error again in Quartus II 3.0
58565: 03/07/26: Re: Simple circuit / good design?
58572: 03/07/27: Re: VHDL Book Recommendations Please
58610: 03/07/29: Re: VHDL Book Recommendations Please
58687: 03/07/30: Re: Pricing question....
58697: 03/07/31: Re: binary to BCD assistance
58749: 03/08/01: Re: VHDL Book Recommendations Please
58814: 03/08/01: Re: Speed Grade...
58907: 03/08/04: Re: Size does matter
59129: 03/08/09: Re: speeding up quartus
59131: 03/08/09: Re: Xilinx Webpack ISE and Verilog-2001?
59165: 03/08/11: Re: Upgrading OS or WebPack
59298: 03/08/14: Re: LogicLock flow
60671: 03/09/19: Re: Xilinx
61182: 03/09/30: Re: Memory Handling in Altera Cyclone devices
61183: 03/09/30: Re: spam poll
61185: 03/09/30: Re: Reducing Clock Speed
61186: 03/09/30: Re: Strange synthesis behavior from Quartus II 2.2
61189: 03/09/30: Re: USB 1.1/2.0 Implementation
61190: 03/09/30: Re: Regulator for Spartan 2
61191: 03/09/30: Re: FPGA implementation in (V)HDL
61195: 03/09/30: Re: USB 1.1/2.0 Implementation
61197: 03/09/30: Re: Anybody have any experience with Altera Stratix 840 Mbps LVDS?
61198: 03/09/30: Re: Bit error rate
61276: 03/10/01: Re: Memory Handling in Altera Cyclone devices
61450: 03/10/04: Re: Interesting article about FPGAs
61475: 03/10/05: Re: Interesting article about FPGAs
61490: 03/10/06: Re: Interesting article about FPGAs
61518: 03/10/06: Re: Should I worry about metastability
61565: 03/10/07: Re: Memory Handling in Altera Cyclone devices
61650: 03/10/08: Re: Implementing a fast cache in Altera Cyclone
61654: 03/10/08: Re: Implementing a fast cache in Altera Cyclone
77117: 04/12/23: Re: making an fpga hot
78534: 05/02/02: Re: See Peter's High-Wire Act next Tuesday
78536: 05/02/02: Re: See Peter's High-Wire Act next Tuesday
78590: 05/02/03: Re: See Peter's High-Wire Act next Tuesday
79118: 05/02/14: Updated Stratix II Power Specs & Explanation
79119: 05/02/14: Re: See the next high-wire act, this time on power consumption
79177: 05/02/15: Re: Updated Stratix II Power Specs & Explanation [And a Junction Temperature Tutorial]
79180: 05/02/15: Re: See the next high-wire act, this time on power consumption
79183: 05/02/15: Re: See the next high-wire act, this time on power consumption
79184: 05/02/15: Re: See the next high-wire act, this time on power consumption
79207: 05/02/15: Re: Updated Stratix II Power Specs & Explanation [And a Junction Temperature Tutorial]
79214: 05/02/15: Re: See the next high-wire act, this time on power consumption
79224: 05/02/15: Re: See the next high-wire act, this time on power consumption
79239: 05/02/15: Re: See the next high-wire act, this time on power consumption
79241: 05/02/15: Re: Updated Stratix II Power Specs & Explanation
79242: 05/02/15: Re: Updated Stratix II Power Specs & Explanation
79249: 05/02/15: Re: Updated Stratix II Power Specs & Explanation
80522: 05/03/07: Re: Surge in S2? ~3 amperes at cold for a millisecond
80574: 05/03/08: Re: Surge in S2? ~3 amperes at cold for a millisecond
80585: 05/03/08: Re: Surge in S2? ~3 amperes at cold for a millisecond
80648: 05/03/09: Re: Xilinx vs Altera high-end solutions
80655: 05/03/09: Re: Xilinx vs Altera high-end solutions
80668: 05/03/09: Re: Xilinx vs Altera high-end solutions
81086: 05/03/17: Re: Quartus II and DSE
81177: 05/03/18: Re: Spartan 3E vs. Cyclone2
81476: 05/03/24: Re: Xilinx ISE 7.1 - Can this get any worse?
83093: 05/04/23: Re: Spartan 3E slower that Spartan 3?
83265: 05/04/26: Re: Virtex 4 Power consumption
84345: 05/05/17: Re: V4 vs. Stratix-II...
84348: 05/05/17: Re: V4 vs. Stratix-II...
84349: 05/05/17: Re: "Mine is bigger than yours..."
84350: 05/05/17: Re: "Mine is bigger than yours..."
84422: 05/05/18: Re: Virtex4 running at 360Mhz DDR
87405: 05/07/22: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87518: 05/07/25: Re: July 20th Altera Net Seminar: Stratix II Logic Density
98426: 06/03/09: Re: for all those who believe in ASICs....
98429: 06/03/09: Re: Altera PowerPlay Analyser
98430: 06/03/09: Re: for all those who believe in ASICs....
98431: 06/03/09: Re: for all those who believe in ASICs....
98672: 06/03/14: Re: About Altera FPGA Board
99525: 06/03/25: Re: Nios II - Branch Prediction
99615: 06/03/27: Re: Lattice FPGA
99616: 06/03/27: Re: Memory leaks with ISE 8.1
100185: 06/04/04: Re: about the low power design
100186: 06/04/04: Re: about the low power design
100188: 06/04/04: Re: Altera Stratix II GX LVDS max speed
100240: 06/04/05: Re: Altera Stratix II GX LVDS max speed
102198: 06/05/11: Re: Altera Equiv.
102498: 06/05/16: Re: Xilinx or Altera...
102600: 06/05/17: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
102602: 06/05/17: Re: Cyclone II PCI & Pin Swapping
102633: 06/05/18: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
102650: 06/05/18: Re: Virtex 5 announced and sampling: apologia for FX woes on V4
103205: 06/05/28: Re: Report for routing resource usage?
103752: 06/06/09: Re: Good free or paid merge software that edits two similar files?
111664: 06/11/07: Re: Should I use an external synthesis tool?
111722: 06/11/08: Re: New Quartus 6.1 is multi-threaded
111724: 06/11/08: Re: Non deterministic behaviour in quartus II ?
111759: 06/11/09: Re: Non deterministic behaviour in quartus II ?
111769: 06/11/09: Re: Non deterministic behaviour in quartus II ?
111822: 06/11/10: Re: Non deterministic behaviour in quartus II ?
111838: 06/11/10: Re: using FPGAs for synthesizing?
111848: 06/11/11: Re: Stratix-III announced
117019: 07/03/21: Re: Austin the Altera Mole
117020: 07/03/21: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117021: 07/03/21: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117062: 07/03/22: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117063: 07/03/22: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117068: 07/03/22: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117072: 07/03/22: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117073: 07/03/22: Re: Xilinx ISE support for dual/quad core CPUs?
117077: 07/03/22: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117095: 07/03/22: Re: Altera introduces Cyclone III devices, 'ships' 65nm
117192: 07/03/26: Re: Austin the Altera Mole
117195: 07/03/26: Re: Small memories in Cyclone
117296: 07/03/27: Re: What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L
119194: 07/05/14: Re: Power Consumption Estimation for PCI card, any advice?
119195: 07/05/14: Re: Power Consumption Estimation for PCI card, any advice?
119240: 07/05/15: Re: Power Consumption Estimation for PCI card, any advice?
119267: 07/05/15: Re: Power Consumption near Timing Failure Point
119359: 07/05/17: Re: Power Consumption near Timing Failure Point
119361: 07/05/17: Re: Power Consumption near Timing Failure Point
119391: 07/05/17: Re: Power Consumption near Timing Failure Point
119402: 07/05/17: Re: Power Consumption near Timing Failure Point
119404: 07/05/17: Re: Power Consumption near Timing Failure Point
119730: 07/05/25: Re: Dual Core or Quad Core when running Quartus 7.1
119731: 07/05/25: Re: Dual Core or Quad Core when running Quartus 7.1
119957: 07/05/30: Re: what is register packing?
120627: 07/06/12: Re: Unused clock pins tied inactive?
120628: 07/06/12: Re: Pin Capacitance Quartus 6.0
122637: 07/08/02: Re: Best CPU platform(s) for FPGA synthesis
122638: 07/08/02: Re: Best CPU platform(s) for FPGA synthesis
122639: 07/08/02: Re: Best CPU platform(s) for FPGA synthesis
122640: 07/08/02: Re: Static Timing Analysis Using Primetime for FPGAs
122641: 07/08/02: Re: Altera Cyclone II and Cyclone III "distributed" RAM?
122642: 07/08/02: Re: Altera or Xilinx
122644: 07/08/02: Re: Static Timing Analysis Using Primetime for FPGAs
123297: 07/08/23: Re: Spartan-3A DSP vs. Cyclone III Power-wise
123298: 07/08/23: Re: Power Reduction Strategy
123444: 07/08/28: Re: PLL Power and m/n ratio
123722: 07/09/03: Re: Low-level FPGA programming?
130432: 08/03/23: Re: ISE 10.0 finally with multi-threading and SV support ?
130494: 08/03/25: Re: ISE 10.0 finally with multi-threading and SV support ?
Paul Leventis at home:
68692: 04/04/14: Re: Apples to Apples? Stratix II <> Virtex-II Pro
74155: 04/10/04: Re: JOP on Spartan-3 Starter Kit
Paul Leventis (at home):
52742: 03/02/20: Re: Gate boosting
52769: 03/02/21: Re: Gate boosting
54045: 03/04/01: Re: Spartan vs. Cyclone for arithmetic functions
54048: 03/04/01: Re: Spartan vs. Cyclone for arithmetic functions
54049: 03/04/01: Re: Spartan vs. Cyclone for arithmetic functions
54050: 03/04/01: Re: What would it take?
54174: 03/04/04: Re: Matrix multiply in FPGA
54216: 03/04/05: Re: Matrix multiply in FPGA
54239: 03/04/05: Re: Matrix multiply in FPGA
64834: 04/01/15: Re: Faster than a speeding bullet...
64898: 04/01/16: Re: yo, Mr. FPGA Engineer
64961: 04/01/16: Re: Impact of voltage variations on timings for an FPGA
64962: 04/01/16: Re: mapper optimization
65199: 04/01/22: Re: xilinx 70% tracking rule
65202: 04/01/22: Re: BIST FPGA testing - Applying a test vector
65261: 04/01/23: Re: Why is router software not multi-threaded?
65308: 04/01/24: Re: Quartus doesn't work with Pentium Hypertheading!
65331: 04/01/25: Re: xilinx 70% tracking rule
65381: 04/01/27: Re: Timing model for MultiTrack interconnects in Stratix?
65411: 04/01/28: Re: Timing model for MultiTrack interconnects in Stratix?
65645: 04/02/04: Re: Tools for developing high-speed interfaces
65695: 04/02/05: Re: CycloneII, NiosII, StratixII more info please....
65909: 04/02/10: Re: Quartus II taking forever to compile
65911: 04/02/10: Re: Is nobody using c++ and/or plugs-lib? was Re: nios c++ and ethernet [may by ot?]
65941: 04/02/10: Re: Is nobody using c++ and/or plugs-lib? was Re: nios c++ and ethernet [may by ot?]
65943: 04/02/10: Re: Synchronization of signals
65944: 04/02/10: Re: Synchronization of signals
65947: 04/02/10: Re: Quartus II taking forever to compile
65952: 04/02/10: [OT] Re: Quartus II taking forever to compile
65953: 04/02/10: Re: Synchronization of signals
66917: 04/03/01: Re: Stratix 2 ALUT architecture patented ?
66918: 04/03/01: Re: Stratix 2 ALUT architecture patented ?
66920: 04/03/01: Re: Stratix 2 ALUT architecture patented ?
66932: 04/03/01: Re: Stratix 2 ALUT architecture patented ?
66993: 04/03/03: Re: Need to speed up Stratix compiles.
66994: 04/03/03: Re: Need to speed up Stratix compiles.
67003: 04/03/03: Re: Need to speed up Stratix compiles.
67028: 04/03/04: Re: Need to speed up Stratix compiles.
67029: 04/03/04: Re: Need to speed up Stratix compiles.
67084: 04/03/05: Re: Spec VPR Results for various processors...
67766: 04/03/18: Re: Quartus II 4.0 Web Edition Software & Documentation - Available for download
67795: 04/03/19: Re: Strange FPGA design - part working with divided clock frequency - time constraints problem
67981: 04/03/24: Re: Quartus with AMD64 processors?
67982: 04/03/24: Re: Quartus with AMD64 processors?
68029: 04/03/24: Re: Quartus with AMD64 processors?
68359: 04/04/02: Re: Best price per I/O
68658: 04/04/13: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
68708: 04/04/15: Re: Apples to Apples? Stratix II <> Virtex-II Pro
70501: 04/06/18: Re: compressing Xilinx bitstreams
71161: 04/07/10: Re: Info on FPGA routing algorithms?
71209: 04/07/12: Re: Info on FPGA routing algorithms?
71977: 04/08/05: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
71978: 04/08/05: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
72006: 04/08/05: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
72057: 04/08/06: Re: Acceleration
72152: 04/08/10: Re: Now I am really confused!
72189: 04/08/11: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
72278: 04/08/13: Re: Altera winner?
73822: 04/09/29: Re: DISCLOSURE : NV on-chip memory?
73825: 04/09/29: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
73930: 04/10/01: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
73931: 04/10/01: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
73932: 04/10/01: Re: NV on-chip memory?
73977: 04/10/01: Re: FPGA vs ASIC area
73979: 04/10/01: Re: Quartus II annoyance
73980: 04/10/01: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
73986: 04/10/01: Re: JOP on Spartan-3 Starter Kit
73990: 04/10/01: Re: FPGA vs ASIC area
73371: 04/09/20: Re: Altera Max II
73385: 04/09/21: Re: altera quartus II handbook is wrong??
73443: 04/09/22: Re: Stratix II vs. Virtex 4 - availability & fab partnership
73445: 04/09/22: Re: Stratix II vs. Virtex 4 - power
74963: 04/10/22: Re: Altera Cubic Cyclonium
74964: 04/10/22: Re: which xilinx CPLD to select?
74966: 04/10/22: Re: add/sub 2:1 mux and ena in a single LE (Cyclone)
75235: 04/10/30: Re: which xilinx CPLD to select?
75236: 04/10/30: Re: Feeding PLL
74325: 04/10/08: Re: add/sub 2:1 mux and ena in a single LE (Cyclone)
74504: 04/10/12: Re: EP1C12 or XC3S400?
74573: 04/10/14: Re: Routing PLL output
74604: 04/10/15: Re: add/sub 2:1 mux and ena in a single LE (Cyclone)
74620: 04/10/15: Re: Routing PLL output
74678: 04/10/15: Re: How many Altera LE's to Xilinx Slices????
74680: 04/10/16: Re: which xilinx CPLD to select?
74693: 04/10/16: Re: How many Altera LE's to Xilinx Slices????
76110: 04/11/25: Re: Choice of FPGA device
76111: 04/11/25: Re: Choice of FPGA device -- my view on benchmarks
76148: 04/11/25: Re: Choice of FPGA device
76149: 04/11/25: Re: Choice of FPGA device
76169: 04/11/27: Re: Choice of FPGA device -- my view on benchmarks
76373: 04/12/01: Re: CMOS capacitive loads, transition probabilities and FPGAs
76647: 04/12/07: Re: making an fpga hot
76687: 04/12/08: Re: making an fpga hot
76688: 04/12/08: Re: making an fpga hot
76689: 04/12/08: Re: Performance claims
76690: 04/12/08: Re: Performance claims
77087: 04/12/21: Re: making an fpga hot
77954: 05/01/20: Re: Altera HardCopy and SEUs
78037: 05/01/23: Re: Altera HardCopy and SEUs
78684: 05/02/05: Re: Altera's NIOS2 examples...
78685: 05/02/05: Re: See Peter's High-Wire Act next Tuesday
78697: 05/02/06: Re: See Peter's High-Wire Act next Tuesday
78701: 05/02/06: Re: See Peter's High-Wire Act next Tuesday
78702: 05/02/06: Re: See Peter's High-Wire Act next Tuesday
78705: 05/02/06: Re: How to fix this synthese warnings?
78726: 05/02/06: Re: See Peter's High-Wire Act next Tuesday
78727: 05/02/06: Re: See Peter's High-Wire Act next Tuesday
78783: 05/02/07: Re: See Peter's High-Wire Act next Tuesday
78784: 05/02/08: Re: See Peter's High-Wire Act next Tuesday
78785: 05/02/08: Re: See Peter's High-Wire Act next Tuesday
78789: 05/02/08: Re: See Peter's High-Wire Act next Tuesday
78905: 05/02/09: Re: See Peter's High-Wire Act next Tuesday
79444: 05/02/19: Re: Updated Stratix II Power Specs & Explanation
79449: 05/02/19: Re: Updated Stratix II Power Specs & Explanation
80532: 05/03/07: Re: Surge in S2? ~3 amperes at cold for a millisecond-- on ES material, fix available end of month for 2S60 ....
80706: 05/03/10: Re: Global Reset paths
80707: 05/03/10: Re: Surge in S2? ~3 amperes at cold for a millisecond-- on ES material, fix available end of month for 2S60 ....
80747: 05/03/10: Re: Xilinx vs Altera high-end solutions
80748: 05/03/10: Re: cyclone's pll
80786: 05/03/11: Re: Global Reset paths
80787: 05/03/11: Re: Xilinx vs Altera high-end solutions
81235: 05/03/19: Re: XC3S50 or EPM1270?
81236: 05/03/19: Re: Spartan 3E vs. Cyclone2
81293: 05/03/21: Re: Xilinx ISE 7.1 - Can this get any worse?
81652: 05/03/29: Re: Initializing Altera MEGARAMs in simulation
83227: 05/04/26: Re: Virtex 4 Power consumption
83512: 05/05/01: Re: Virtex4 and ISE reality check?
83849: 05/05/07: Re: Which chip should I use?
84286: 05/05/16: Re: Virtex4 running at 360Mhz DDR
84300: 05/05/17: Re: "Mine is bigger than yours..."
84301: 05/05/17: Re: wide ROM
84302: 05/05/17: Re: true dual port memory v/s simple dual port memory
84303: 05/05/17: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
84304: 05/05/17: Re: Virtex4 running at 360Mhz DDR
84306: 05/05/17: Re: V4 vs. Stratix-II...
84308: 05/05/17: Re: V4 vs. Stratix-II...
84310: 05/05/17: Re: Stupid Question on the Urination Contest... Re: V4 vs. Stratix-II...
84311: 05/05/17: Re: "Mine is bigger than yours..."
84454: 05/05/19: Re: How many logic cells are there in one slice
84513: 05/05/20: Re: Bullshit Achieves Literary Status
84852: 05/05/30: Re: Nios speed down
84854: 05/05/30: Re: Virtex4 running at 360Mhz DDR
86104: 05/06/22: Re: Lattice LFEC
86334: 05/06/25: Re: Lattice LFEC
86762: 05/07/06: Re: fastest FPGA speed grade?
86763: 05/07/06: Re: VPR fundaes
86829: 05/07/07: Re: VHDL Clock Domains
86877: 05/07/07: Re: fastest FPGA speed grade? Not the only measure, but ...
87203: 05/07/19: July 20th Altera Net Seminar: Stratix II Logic Density
87242: 05/07/20: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87307: 05/07/21: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87308: 05/07/21: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87309: 05/07/21: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87310: 05/07/21: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87551: 05/07/25: Re: verilog to blif(lut)
87553: 05/07/25: Re: July 20th Altera Net Seminar: Stratix II Logic Density
88446: 05/08/18: Re: Problem with quartus 5.0 sp1
89132: 05/09/06: ANN: Altera Power Net Seminar #2
89144: 05/09/06: Re: Strange behaviour while trying to program MAX II CPLD's
89145: 05/09/06: Re: Low Power RTL Design
89147: 05/09/06: Re: Altera Power Net Seminar #2
Paul M. Lynch:
15903: 99/04/20: Synopsys & Xilinx 6200
Paul Maddox:
25576: 00/09/14: Guide to useing Atmel FPGA (at40k)
25605: 00/09/15: Re: Guide to useing Atmel FPGA (at40k)
Paul Marciano:
69708: 04/05/18: How to select an FPGA size (beginner)
69784: 04/05/19: Re: How to select an FPGA size (beginner)
69959: 04/05/25: How to generate a 320x200 VGA signal?
81237: 05/03/19: Is the Xilinx EDK free?
81271: 05/03/20: Re: Is the Xilinx EDK free?
81301: 05/03/21: Re: Is the Xilinx EDK free?
81304: 05/03/21: Re: Is the Xilinx EDK free?
81307: 05/03/21: Re: Is the Xilinx EDK free?
81309: 05/03/21: Re: Is the Xilinx EDK free?
88109: 05/08/09: Re: can use bram for VGA
88655: 05/08/24: Re: how to reduce vga memory????????
88656: 05/08/24: Re: how to reduce vga memory????????
88658: 05/08/24: Re: how to reduce vga memory????????
88714: 05/08/25: Re: Ones Count 64 bit on Xilinx in VHDL
88869: 05/08/30: Quick Xilinx KCPSM3 with verilog question.
89866: 05/09/28: Re: Version Control Software
90154: 05/10/05: Re: Avoiding meta stability?
90216: 05/10/06: Re: Avoiding meta stability? No where in this thread...
90219: 05/10/06: Re: Avoiding meta stability?
90345: 05/10/10: What is a "full custom" design?
90676: 05/10/18: Re: Newbie question: XC3S400 Gate Count
91042: 05/10/27: Re: Cost to go from FPGA to ASIC
91091: 05/10/28: RLOC Map error! Help!
93788: 05/12/30: How do I instantiate an ADSU8 in ISE7.1i?
95720: 06/01/25: Re: help:dual-edge flip-flop possible using Verilog?
95759: 06/01/25: Re: Spartan-3 Starter Board
95844: 06/01/26: Re: Spartan-3 Starter Board
96195: 06/01/31: Xilinx owns the bitstream
96320: 06/02/01: Mixing and matching related clocks question.
96443: 06/02/03: Looking for literature on microprogrammed machines
96456: 06/02/03: Re: Looking for literature on microprogrammed machines
96458: 06/02/03: Re: Looking for literature on microprogrammed machines
96554: 06/02/06: Re: Mixing and matching related clocks question.
104555: 06/06/29: How to evaluate the space efficiency of a historic design.
104556: 06/06/29: Re: How to evaluate the space efficiency of a historic design.
Paul Martek:
52167: 03/02/03: Altera Stratix terminator technology
Paul McCallion:
34780: 01/09/07: Actel FPGA glitches
34820: 01/09/10: Re: Actel FPGA glitches
34822: 01/09/10: Re: Actel FPGA glitches
Paul McCanny:
31145: 01/05/13: VirtexblockRAM bug
Paul McGaugh:
200: 94/09/19: Re: Lattice ISP software: really bad or just different?
219: 94/09/26: Re: Lattice ISP software: really good
Paul Micheletti:
3979: 96/08/28: Re: INDUSTRY GADFLY: EDA Goes OJ
Paul Miseldine:
71994: 04/08/05: Using ISE flow in EPS
Paul Mondello:
18094: 99/09/29: Need help programming Spartan FPGA with Atmel serial EEPROM
20365: 00/02/07: FLASH-based reconfigurability
Paul Muller:
83294: 05/04/27: Re: *RANT* Ridiculous EDA software "user license agreements"?
Paul N.:
72730: 04/08/30: FPGA Floating Point Multiplier Design
Paul Oh:
11220: 98/07/27: [Q] motor control onto an FPGA
18857: 99/11/19: [Q] End-goal: porting ISA design to PCI. Which PLD to learn?
Paul Pham:
143829: 09/10/28: Re: Ideas for a pulse programmer needed
Paul Price:
128149: 08/01/16: Documentation on Insight VIRTEX-E Reference Board
Paul R:
91784: 05/11/13: Viretx4 FX chip availability
91835: 05/11/15: Re: Viretx4 FX chip availability
Paul Ranger:
149064: 10/09/27: Adding PLB Module to AMBA
149073: 10/09/28: Re: Adding PLB Module to AMBA
Paul Rubin:
23397: 00/06/24: Re: CHES 2000 accepted papers
101306: 06/04/28: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
101323: 06/04/28: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
155312: 13/06/23: Re: New soft processor core paper publisher?
155419: 13/06/26: Re: New soft processor core paper publisher?
155421: 13/06/26: Re: New soft processor core paper publisher?
155936: 13/10/17: Re: Zynq devices, boards and suppliers
155949: 13/10/19: Re: Zynq devices, boards and suppliers
156029: 13/11/11: Re: Zynq devices, boards and suppliers
Paul Russell:
67483: 04/03/12: Re: ANN: new Pulsonix version 3 PCB software released
Paul S Secinaro:
848: 95/03/13: Re: FPGA multi-chip modules ?
1790: 95/09/01: Re: Altera flex10k
2294: 95/11/17: Re: 2nd Global Clocks in ALTERA MAX7000E ? Help !!!
2448: 95/12/06: Re: Xilinx vs Altera with Verilog/VHDL
2486: 95/12/15: Re: Gated Clock Problem in Xilinx FPGA Implementation
4441: 96/10/29: Re: Altera Configuration EPROM Equivalents
5113: 97/01/24: Re: Altera Max Plus 2 Software bug
5499: 97/02/20: Re: Xilinx or Altera?
6358: 97/05/18: Re: xilinx xblox with capture ver 7.00
6467: 97/05/27: Re: Fine Pitch PQFP : anyone any hassles?
13294: 98/11/24: Integer divide algorithms
Paul S. Graham:
22122: 00/04/25: Running the Xilinx Alliance Tools under Linux
Paul S. Martin:
24607: 00/08/14: Re: Non-disclosures in job interviews
Paul Schreiber:
110119: 06/10/11: Re: Release Status of Spartan3E
111622: 06/11/06: Re: I2C Master in Verilog
Paul Sereno:
52161: 03/02/03: 3.3 Volt tolerance in Virtex II Pro...
58759: 03/07/31: Re: 5 volt tolerant Xilinx parts
59403: 03/08/18: Re: Anyone familiar with ispXPLD?
59426: 03/08/18: Re: Anyone familiar with ispXPLD?
59445: 03/08/19: Re: Anyone familiar with ispXPLD?
70958: 04/07/02: new Lattice FPGAs vs Cyclone and SpartanIII
71044: 04/07/06: Re: new Lattice FPGAs vs Cyclone and SpartanIII
71115: 04/07/08: Re: new Lattice FPGAs vs Cyclone and SpartanIII
Paul Smart:
24188: 00/07/28: For Sale: XC17128 serial proms
24412: 00/08/07: Re: Abel from dataIO?
32262: 01/06/21: ATPG tools for FPGA
32306: 01/06/22: Re: ATPG tools for FPGA
32511: 01/06/28: Re: Source of old Altera EPX780s
33408: 01/07/25: Re: EDN
33472: 01/07/27: Xilinx/Altera "behavioral" verilog
33554: 01/07/30: Re: Xilinx/Altera "behavioral" verilog
33561: 01/07/30: Re: Xilinx/Altera "behavioral" verilog
33615: 01/07/31: Re: Xilinx/Altera "behavioral" verilog
33834: 01/08/06: Re: Xilinx/Altera "behavioral" verilog
33838: 01/08/06: Choosing a verilog synthesis tool (Altera/Xilinx)
Paul Smith:
1525: 95/07/07: Re: aynchronous ripple counter
5482: 97/02/19: Re: Installation Problem with ACTEL Designer 3.1 on SunSolaris
23880: 00/07/13: Dual Port RAM
23905: 00/07/14: Re: Dual Port RAM
23912: 00/07/14: Re: Dual Port RAM
23987: 00/07/19: Re: Dual Port RAM
24683: 00/08/16: Xilinx design flow with Mentor
24685: 00/08/16: Xilinx Spartan II block RAM
24744: 00/08/17: Re: Xilinx Spartan II block RAM
25253: 00/09/01: Xilinx block Ram Verilog model
25842: 00/09/22: Re: Alliance 3.1i CAE Libs install hangs under Solaris
26505: 00/10/18: Spartan II ?
26829: 00/10/31: Re: Spartan II ?
29328: 01/02/14: Spartan II power
29449: 01/02/21: Re: Spartan II power
42975: 02/05/08: PCI bus software for Xilinx PCI core
43049: 02/05/10: Re: PCI bus software for Xilinx PCI core
45874: 02/08/08: Xilinx XC2VP4 price/availability ?
45903: 02/08/09: Re: Xilinx XC2VP4 price/availability ?
45993: 02/08/13: Re: unloading a fast ADC
51773: 03/01/21: Re: Lecroy Research Systems - what happened?
63438: 03/11/21: Re: 400 Mb/s ADC
75930: 04/11/19: RocketIO success?
81171: 05/03/18: XC4VFX12 price/delivery ?
81303: 05/03/21: Re: XC4VFX12 price/delivery ?
85299: 05/06/07: faster Spartan III adder
85424: 05/06/09: Re: faster Spartan III adder
85448: 05/06/09: Re: faster Spartan III adder
85452: 05/06/09: Re: faster Spartan III adder
85460: 05/06/09: Re: faster Spartan III adder
85515: 05/06/10: Re: faster Spartan III adder
Paul Solomon:
86938: 05/07/10: Quartus Timing Issues
86942: 05/07/11: Re: Quartus Timing Issues
86976: 05/07/12: Testbenching and verification
86979: 05/07/12: Unrolled Pipeline Implementation
87060: 05/07/14: Modulo division in Verilog
87063: 05/07/14: Re: Modulo division in Verilog
87091: 05/07/15: Re: Modulo division in Verilog
87097: 05/07/15: Re: Modulo division in Verilog
87618: 05/07/27: Re: QuartusII 4.2 problem
87932: 05/08/04: Quartus II 4.2 Incremental Systhesis
87937: 05/08/04: Auto generation of memory files
87940: 05/08/04: Re: Auto generation of memory files
87950: 05/08/04: Re: Auto generation of memory files
87955: 05/08/04: Re: Auto generation of memory files
87994: 05/08/05: Re: Auto generation of memory files
88673: 05/08/25: ADC Clock on Stratix II DSP Dev Board
Paul Somogyi:
24542: 00/08/12: Re: Yes but I want graphics.
25110: 00/08/26: Re: Accessing internal signals and ports for writing to a file using testbench
Paul Spencer:
784: 95/03/02: Re: Real-time fractal gen in h/w
Paul Staley:
Paul Surma:
5951: 97/03/29: Re: viewoffice <--> viewoffice compatibility
Paul Sutton:
22846: 00/05/27: AVNET Virtex Board
Paul Szczesny:
54683: 03/04/16: spartan 3 pin compatible with 2E?
Paul T. Shultz:
1572: 95/07/19: Re: ACTEL PLACE AND ROUTE
1695: 95/08/17: Re: FPGAs with embedded RAM
4797: 96/12/16: FPGA ATM VHDL Megafunctions/Libraries
10654: 98/06/09: Re: Multipliers on FPGA's
13404: 98/12/01: Re: Logical Devices ALLPRO diagnostics
15084: 99/03/05: Re: Can multiple FPGA share same SPROM for configuration?
22808: 00/05/25: Re: Coregen generated FIFO not working
Paul Taddonio:
80556: 05/03/08: Good, affordable verilog simulator
80575: 05/03/08: Re: Good, affordable verilog simulator
80580: 05/03/08: Re: Good, affordable verilog simulator
Paul Taylor:
5746: 97/03/12: Re: Fatal exception under Win95 & XACT v6.0.1
8781: 98/01/26: Re: High Voltage on xilinx FPGA/CPLD pins
10925: 98/07/01: Re: Power consumption question
12615: 98/10/20: Re: gray code counter in a Xilinx fpga???
18786: 99/11/16: Re: WHERE can I find xc9536_v2.bsd??!
27776: 00/12/07: XC9500/9500XL CPLD Clocks
28213: 00/12/31: Re: XC9500 and unused inputs
28228: 01/01/02: Re: XC9500 and unused inputs
28693: 01/01/21: Re: xc95108 funny behaviour
30241: 01/03/29: XC9500XL max, typ, min propagation delay values?
31498: 01/05/28: Re: Xilinx Coolrunner 100% routable - but the tools aren't
32583: 01/07/01: Closest Xilinx equivalent to Altera EPF10KE?
32637: 01/07/03: Re: Closest Xilinx equivalent to Altera EPF10KE?
39592: 02/02/14: SpartanXL & VHDL -- free software?
39623: 02/02/14: Re: SpartanXL & VHDL -- free software?
39637: 02/02/15: Re: SpartanXL & VHDL -- free software?
39690: 02/02/16: Re: SpartanXL & VHDL -- free software?
40276: 02/03/04: Re: student F2.1i printing problem
40352: 02/03/05: Re: Hardware FPGA questions
40626: 02/03/12: Re: First steps with clock enable constraining
50339: 02/12/09: Re: FPGA/PCI on low budget
118889: 07/05/06: Re: Atom HDL
118890: 07/05/06: Re: Atom HDL
119133: 07/05/12: Re: how to choose the perfect fpga support
126253: 07/11/18: Re: VHDL language is out of date! Why? I will explain.
126423: 07/11/21: Re: VHDL language is out of date! Why? I will explain.
126478: 07/11/24: Re: VHDL language is out of date! Why? I will explain.
134126: 08/07/26: Re: Creating new operators
134186: 08/07/29: Re: Creating new operators
134204: 08/07/30: Re: Creating new operators
134206: 08/07/30: Re: Creating new operators
134210: 08/07/30: Re: Creating new operators
134234: 08/07/31: Re: Creating new operators
134235: 08/07/31: Re: Creating new operators
134236: 08/07/31: Re: Creating new operators
134665: 08/08/25: Re: Analog Imager interface to FPGA
Paul Teagle:
8472: 97/12/18: VME Interface on 10k family
10319: 98/05/12: availability of EPC1LI20
11135: 98/07/21: Re: Hierachical signal/port trace in Maxplus2 s
11351: 98/08/06: Re: PCI Core In FPGA
30596: 01/04/18: looking for comment on implementation
30616: 01/04/19: Re: looking for comment on implementation
30664: 01/04/23: CIC interpolate by 3 & filter
30727: 01/04/26: manufacturer's of FIR chips
33397: 01/07/25: Windows ME and Foundation ISE?
33436: 01/07/26: Re: Windows ME and Foundation ISE?
33787: 01/08/05: Re: May I connect two pins to the same net?
33824: 01/08/06: Re: May I connect two pins to the same net?
34099: 01/08/14: Re: WinMe installation
35746: 01/10/16: Programming interface reference designs
35772: 01/10/17: Phase noise of Xilinx/Altera DLL/PLL
36136: 01/10/31: Re: Phase noise of Xilinx/Altera DLL/PLL
Paul Tiseo:
25010: 00/08/23: Re: Non-disclosures in job interviews, Round Two
25024: 00/08/24: Re: Non-disclosures in job interviews, Round Two
Paul Uiterlinden:
74297: 04/10/07: Re: modelsim crashs with large ram simulation model
79257: 05/02/16: Re: ISE:ERROR:Xst:829: Constant Value expected for Generic 'U'?
129344: 08/02/21: Re: TCL testcase in Modelsim.
Paul Urbanus:
2098: 95/10/14: Re: Help - Searching an PLD/FPGA Selection Software
9246: 98/03/04: Viewlogic file format for schematic symbols
19964: 00/01/20: Re: looping FIFO?
20553: 00/02/14: Post-synthesis simulation in Foundation Express
20686: 00/02/17: Re: Xilinx hold time problems...
30506: 01/04/11: Changing Xilinx ROM contents without recompiling
56991: 03/06/20: PALs, GALs and ABEL
57245: 03/06/26: Free PAL synth tools (ABEL, PALASM, VHDL, etc.)?
57260: 03/06/26: Re: Free PAL synth tools (ABEL, PALASM, VHDL, etc.)?
64106: 03/12/16: Multi-FPGA PCI board recommendations???
77549: 05/01/10: How to secure distributed IP for Xilinx FPGAs?
82007: 05/04/05: Re: Is the Xilinx EDK free?
82010: 05/04/05: Re: PAL problems (again)
88340: 05/08/16: XC5200 tool help needed
89429: 05/09/15: IP Protection of code block in Xilinx FPGA?
89456: 05/09/15: Re: IP Protection of code block in Xilinx FPGA?
105628: 06/07/27: Wanted: CPU config register code generator
120935: 07/06/20: MIG 7.12 DDR2 bank availibility
129492: 08/02/26: Re: Picoblaze enhencement and assembler
130035: 08/03/13: Re: Problem with Spartan 3 StarterKit
130043: 08/03/13: Re: Problem with Spartan 3 StarterKit
130044: 08/03/13: Re: Problem with Spartan 3 StarterKit
130495: 08/03/25: Re: Timing constraints in ucf
130505: 08/03/25: Re: Timing constraints in ucf
133501: 08/07/01: Re: Nintendo DS Screenshots / Video Capture
134110: 08/07/26: Re: Quartus2 pin assignment
134138: 08/07/27: Cyclone III passive serial config issue
134906: 08/09/06: Altera library sim question
135028: 08/09/11: Re: Altera library sim question
136413: 08/11/14: Re: Number of GCLKs: 9 out of 8 112% (OVERMAPPED)
136414: 08/11/14: Re: Using the FF @ Port pin
138558: 09/02/27: Re: Converting state machine encoding to std_logic_vector
138993: 09/03/18: Re: Zero operand CPUs
139002: 09/03/18: Re: Zero operand CPUs
154798: 13/01/11: Re: MIG help (Virtex-6)
155029: 13/04/01: ISIM issue with 'last_value attribute in functions
155031: 13/04/01: Re: Xilinx tools for XC3020???
160547: 18/03/22: Re: the FPGA one-shot
160554: 18/04/06: Re: the FPGA one-shot
Paul van der Linden:
98587: 06/03/13: Soldering SMT/BGA
98600: 06/03/13: Re: Soldering SMT/BGA
Paul van Haren:
11444: 98/08/14: Re: FFT-Speed
Paul Venginickal:
15845: 99/04/16: Altera 10K and High Density FLASH Memory
Paul Walker:
1246: 95/05/22: Re: Is anybody using FPGA's to do PCI interfaces?
1247: 95/05/22: Re: FLEXlogic opinions?
1266: 95/05/24: Re: Is anybody using FPGA's to do PCI interfaces?
1275: 95/05/25: Re: Flex780 programming errors
1277: 95/05/25: Re: Altera Contacts ...
1301: 95/05/30: Re: Help on Programming FPGAs
4948: 97/01/03: EPX880 & 8160 to Become Obsolete
6300: 97/05/12: RS232 in PLD
7348: 97/08/29: Flexible tools and FIFOs
8181: 97/11/25: Re: xilinx xc4kE and PCI LogiCORE
8476: 97/12/19: Experience with Atmel 40k?
9555: 98/03/23: Re: Dual port
9572: 98/03/24: Re: Dual port
9670: 98/03/30: Re: Dual port
10944: 98/07/06: Xilinx Foundation Frustartions
10975: 98/07/08: Re: question on combinational logic synthesis for FPGA
10976: 98/07/08: Re: Xilinx Foundation Frustartions
10977: 98/07/08: Re: Xilinx Foundation Frustartions
12634: 98/10/21: Re: How many ASIC per port for Switches?
12850: 98/11/02: Re: FPGA Decouple Capacitor values
12869: 98/11/03: Re: Q: fifo flags
12942: 98/11/06: Re: Q: fifo flags
15245: 99/03/16: Re: Xilinx routing issue
16277: 99/05/13: Re: Spartan Metastability parameters
17020: 99/06/25: Re: Read/Writes to memories/register files for PIC core
19789: 00/01/12: Re: Assignment of pins for thousand+ pin packages
19939: 00/01/19: Patent licences for circuits in FPGA
21860: 00/04/04: Re: Virtex DLL Spread-spectrum clock sensitivity
22236: 00/05/02: Re: Why are there no "cheap" FPGAs?
24890: 00/08/21: Re: Further FPGA metastability questions
Paul Wallich:
17186: 99/07/07: Re: Alto in an FPGA (was CPU's directly executing HLL's)
Paul Wheeler:
11963: 98/09/21: Xilinx tools
Paul Wiercienski:
28622: 01/01/18: fpga-cpu-subscribe @egroups.com
<paul.leventis@gmail.com>:
96688: 06/02/08: Re: Protected power calculation spread sheets
<paul.sc@gmail.com>:
157883: 15/05/10: Re: Open source Verilog BCH encoder/decoder
157885: 15/05/10: Re: Open source Verilog BCH encoder/decoder
157893: 15/05/11: Re: Open source Verilog BCH encoder/decoder
<paul_golik@hotmail.com>:
<paulcullen@purewebsites.co.uk>:
113381: 06/12/12: . What is the sign-and-magnitude of the following 4's complement number? (Leave answer in base 4).
PaulHam:
149054: 10/09/27: question when using asmi_parallel ip core
149198: 10/10/07: question when using asmi_parallel ip core
149200: 10/10/07: Re: question when using asmi_parallel ip core
149230: 10/10/10: i don't have any idea to select write mode at ASMI_PARALLEL
149269: 10/10/13: Re: i don't have any idea to select write mode at ASMI_PARALLEL
149341: 10/10/17: Re: i don't have any idea to select write mode at ASMI_PARALLEL
149375: 10/10/20: Re: i don't have any idea to select write mode at ASMI_PARALLEL
Pauli =?iso-8859-1?Q?Per=E4l=E4?=:
141029: 09/06/02: Re: VHDL synthesis difference bwetween tools
<pauljbennett@gmail.com>:
105474: 06/07/24: Xilinx Corgen & Synplicity... Anyone? Help?
PaulK:
125351: 07/10/23: Nios II, ThreadX, NetX
125352: 07/10/23: Nios II, ThreadX, NetX Anyone?
125353: 07/10/23: Nios II, ThreadX, NetX anyone?
125354: 07/10/23: Nios II, ThreadX, NetX
125355: 07/10/23: Nios II, ThreadX, NetX anyone?
125359: 07/10/23: Re: Nios II, ThreadX, NetX Anyone?
paulleventis-public@yahoo.ca:
98425: 06/03/09: Re: for all those who believe in ASICs....
Paulo Dutra:
5323: 97/02/06: Re: Xilinx Xact Step Software
5630: 97/03/03: Re: Place and Route on Pentium Pro Benchmark?
16009: 99/04/27: Re: Xilinx Virtex GCLKs
17167: 99/07/06: Re: Using Block SelectRAM+ in Virtex
17638: 99/08/17: Re: Constant port map in component instantiation
18127: 99/10/01: Re: reset in xilinx
18167: 99/10/04: Re: reset in xilinx
18195: 99/10/06: Re: Xilinx post route simulation
19371: 99/12/16: Re: Synopsys backannotation
21682: 00/03/28: Re: RTL vs. gate level simulation
27668: 00/12/01: Re: glbl
29333: 01/02/14: Re: Xilinx XCell is not on-line?
38682: 02/01/21: Re: simprims_ver/xilinxcorelib_ver /unisims_ver
42542: 02/04/26: Re: Freeware EDIF viewer
51146: 03/01/03: Re: How suppress Xilinx XCT complier warnings: WARNING:HDLCompilers?
53177: 03/03/05: Re: Problems with Xilinx EDK and Spartan2e devices
53180: 03/03/05: Re: conditional `include
53186: 03/03/05: Re: conditional `include
53867: 03/03/25: Re: Microblaze:Timing constraints
64039: 03/12/12: Re: EDK, reset module, interrupts
64490: 04/01/05: Re: connecting tristates
65184: 04/01/21: Re: Tristate buffer
66345: 04/02/17: Re: Xilinx EDK and reference system opb_ssp1_v1_00_a
66435: 04/02/19: Re: Xilinx ISE 4.2 Unisim Block RAM bug?
67220: 04/03/08: Re: Delay on Virtex-II IOB input FF
67222: 04/03/08: Re: Can Verilog codes be synthesized with XIlinx XST?
67273: 04/03/09: Re: Can Verilog codes be synthesized with XIlinx XST?
67930: 04/03/22: Re: EDK 6.1 and MGT UCF Inst Parameters
67931: 04/03/22: Re: opb, plb routing resources? (fwd)
67965: 04/03/23: Re: EDK 6.1 and MGT UCF Inst Parameters
68061: 04/03/25: Re: opb arbitrer
68190: 04/03/29: Re: Help with Xilinx Ram16X1S example VHDL code
68552: 04/04/07: Re: XST -read_cores YES doesn't merge the NGC into the compiled file...
68600: 04/04/08: Re: Problem using EDK tutorial for Memec board with Synplicity.
68652: 04/04/12: Re: using MicroBlaze SoC with OPB_DDR in ISE flow
68829: 04/04/19: Re: Microblaze Sub-Module Adventure
68870: 04/04/20: Re: Microblaze Sub-Module Adventure
68988: 04/04/23: Re: Xilinx XST problems packing signals into IOB registers...
69261: 04/05/03: Re: EDK 3.2
70597: 04/06/21: Re: IOBs in NGC - problem with OBUFT
70601: 04/06/21: Re: Interface Bidir IO datalines to dualport RAM within FPGA - URGENT
70660: 04/06/22: Re: EDK 6.2 ISE verilog toplevel possible ?
71971: 04/08/04: Re: Virtex 2 Pro OCM question
72731: 04/08/30: Re: EDK core wrapping and include files
72769: 04/08/31: Re: MGT
74870: 04/10/20: Re: Question for XST expert
79918: 05/02/25: Re: dealing with NGO files
79919: 05/02/25: Re: Using XBERT(XAPP661) with EDK6.3SP1
79921: 05/02/25: Re: EDK6.3i Memory conflict.....
79923: 05/02/25: Re: EDK, XST & inouts
84957: 05/06/01: Re: Quick way to synthesize pcores in EDK
85087: 05/06/03: Re: edk 6.3 : INTERNEL_ERROR
85089: 05/06/03: Re: Share one BRAM block between user logic and microblaze (Spartan3)
85090: 05/06/03: Re: Share one BRAM block between user logic and microblaze (Spartan3)
85317: 05/06/07: Re: ISE/EDK 6.3 vs 7.1...
85447: 05/06/09: Re: Memory management : microblaze system
89206: 05/09/07: Re: Signed addition
97058: 06/02/15: Re: Xilinx EDK BRAM confusion
97059: 06/02/15: Re: Xilinx EDK BRAM confusion
97063: 06/02/15: Re: EDK: OPB Question
97064: 06/02/15: Re: Xilinx EDK BRAM confusion
98464: 06/03/10: Re: EDK8.1: Is adding IP core parameters stiil possible?
98474: 06/03/10: Re: EDK8.1: Is adding IP core parameters stiil possible?
103159: 06/05/26: Re: Xilinx IP wizard help
104772: 06/07/05: Re: Incorporating CoreGen files in EDK 8.1 peripheral
115892: 07/02/23: Re: Not power of two BRAM size problem
119551: 07/05/22: Re: EDK 8.1i to EDK 9.1i UCF file errors
119552: 07/05/22: Re: "black_box"-ing of components in toplevel
119553: 07/05/22: Re: Problems to simulate (behavioural) in XPS
119554: 07/05/22: Re: Error in NGDBuild
119566: 07/05/22: Re: "black_box"-ing of components in toplevel
123771: 07/09/04: Re: ERROR:NgdBuild:604 with user ipcore
123837: 07/09/05: Re: BlockRAM connection error
Paulo Oliveira:
2796: 96/02/09: 8274 Inside FPGA?
Paulo Ricardo Pabst:
155870: 13/10/09: Book recommendation
155872: 13/10/09: Re: Book recommendation
155879: 13/10/10: Re: Book recommendation
Paulo Valentim:
34868: 01/09/12: LeonardoSpectrum Timing reports
38550: 02/01/17: Re: ASIC 2002 Call For Papers
42278: 02/04/19: Simulating Unisim
42406: 02/04/23: Re: Simulating Unisim
51954: 03/01/27: Virtex-II and LVDS clocks.
56083: 03/05/28: Altera hold violation errors
70386: 04/06/15: Altera CLKLK_FB use when OPERATION_MODE=NORMAL
70425: 04/06/16: Re: Altera CLKLK_FB use when OPERATION_MODE=NORMAL
paulojfonseca:
79640: 05/02/22: XilKernel Problem on Spartan3 Board
<pault.eg@googlemail.com>:
161596: 20/01/05: Re: Optimizations, How Much and When?
161605: 20/01/06: Re: Optimizations, How Much and When?
161615: 20/01/10: Re: Displays - Apple Mac vs. IBM PC
161617: 20/01/12: Re: Displays - Apple Mac vs. IBM PC
161687: 20/04/15: Re: No more gate-level simulation. for Cyclone V !!!
<pault888@my-dejanews.com>:
15385: 99/03/22: MIL-STD-1553 implementation
PaulTB:
19666: 00/01/07: Re: hobbyist friendly pld?
20583: 00/02/15: Re: Advice please
<paulw@mmail.ath.cx>:
81583: 05/03/28: using (verilog) reg as memory
Paulwb007:
16796: 99/06/09: Re: ALtera 20KE LVDS IO
Pauric Hennessy:
26104: 00/10/04: Category : virtex e I/O bank contention
Pav...:
8516: 98/01/02: help: megafunctions
paval:
12976: 98/11/09: HELP MAX PLUS v9.01
pavan:
97474: 06/02/23: query!! need help!!
pavan kumar:
112644: 06/11/26: I2C Controller
112645: 06/11/26: I2C Controller implementation
Pavel Semyonov:
76304: 04/11/30: Re: lowest-cost FPGA
76576: 04/12/06: Re: PLCC84
76846: 04/12/14: Re: Need help with CUPL
138427: 09/02/22: Where to find source code for Xilinx ML507 board demos?
Pavel Zivny:
16493: 99/05/25: Re: How can I get a ISA/PCI BUS model?
16495: 99/05/25: Re: Is schmitt trigger possible with Xilinx 9536?
<pavel.de.pavel@gmail.com>:
156555: 14/04/28: Re: How do you do an incdir in Vivado
pavel.m:
154757: 13/01/04: Constraints learning materials
154758: 13/01/04: Re: Constraints learning materials
154767: 13/01/05: Re: Constraints learning materials
154797: 13/01/11: FPGA board with SD card slot (code test)
154803: 13/01/13: Re: FPGA board with SD card slot (code test)
154816: 13/01/15: Data output constraint
154831: 13/01/16: Re: Data output constraint
154832: 13/01/16: Re: Data output constraint
154839: 13/01/17: Re: Data output constraint
Pavel.Schukin@gmail.com:
127696: 08/01/05: Spartan 3E Sarter Kit Ethernet
pavithra gowda:
144098: 09/11/11: about create or import pheripheral in EDk
<pavithra.eswaran@gmail.com>:
101214: 06/04/27: LED Driver
Pawan:
67621: 04/03/15: Re: xilinx jtag problems
67623: 04/03/15: Chipscope
67628: 04/03/15: Re: Chipscope
Pawel:
28652: 01/01/19: info about FPGA market?
28673: 01/01/20: Re: FPGAs with a partial reconfiguration
Pawel Chodowiec:
21361: 00/03/19: How to eliminate high fan-out in Xilinx FPGA's?
Pawel E. Tomaszewicz:
11060: 98/07/16: Partial reprogramming
Pawel Kolodziej:
59863: 03/08/30: Re: Free FPGA samples anywhere?
67291: 04/03/09: ACEX: max current per pin
Pawel Michocki:
14100: 99/01/13: Orcad Express Plus vs Foundation Express
14119: 99/01/14: Re: Orcad Express Plus vs Foundation Express
17104: 99/06/30: Re: uLaw and ALaw conversion in an FPGA
Pawel Piotr Czapski, SP5EPD:
115986: 07/02/27: Xilinx and archive of Teaching Materials
115987: 07/02/27: Handel-C, multiple clock domains, and PAL library
<pawel5732@my-deja.com>:
28648: 01/01/19: FPGAs with a partial reconfiguration
<pawel5732@my-dejanews.com>:
12170: 98/10/02: Re: Maxplus2 Timing Analyzer
12167: 98/10/02: ISP Synario - need a help!
12169: 98/10/02: ISP Synario - Installation help!
pawelm:
14106: 99/01/13: Re: Orcad Express Plus vs Foundation Express
14197: 99/01/19: Re: Q:Hardware debugging with Xilinx M1.4
PawelT:
55819: 03/05/20: fir distributed arithmetic
55908: 03/05/23: Re: fir distributed arithmetic
55917: 03/05/23: Re: fir distributed arithmetic
63545: 03/11/25: programmable fir and simulation
63706: 03/12/01: Re: programmable fir and simulation
67188: 04/03/08: fpga+ftdi245BM and C++builder
Pawe³ J. Rajda:
16965: 99/06/21: Re: Virtex Boards
Pawi:
79243: 05/02/15: .rbt file question
paxl13:
144407: 09/12/04: Picoblaze bit file block ram remplacement
144411: 09/12/04: Re: Picoblaze bit file block ram remplacement
<pbdelete@spamnuke.ludd.luthdelete.se.invalid>:
63897: 03/12/08: Re: clock recovery from HDB3 data
97122: 06/02/16: opencores.org ?
98739: 06/03/15: Re: Why does Xilinx hate version control?
98769: 06/03/16: Re: Where are FPGA heading?
99305: 06/03/22: Re: this JTAG thing is a joke
99549: 06/03/26: Re: this JTAG thing is a joke
99604: 06/03/27: Re: Altera web site inaccessible
99934: 06/03/31: Re: USB phy in dev board
100356: 06/04/07: Re: C H S in a Compact flash
100713: 06/04/17: Re: ARM Emulator
100786: 06/04/18: FPGA + MAC board?
100807: 06/04/18: FPGA availability & distribution options.
101145: 06/04/26: Re: Async FPGA ~2GHz
101389: 06/04/30: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101502: 06/05/02: Re: Quartus and source control
101525: 06/05/02: Re: windrvr for Linux broken in 2.6.16
101584: 06/05/03: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
101622: 06/05/04: Re: Xilinx 3s8000?
101652: 06/05/04: CPU resource type
101667: 06/05/04: Re: CPU resource type
101719: 06/05/05: Re: detailed description on the archetecture of FPGA's/CPLD's
101732: 06/05/05: Re: New To FPGA, Program question
101765: 06/05/05: Re: Opteron HT coprocessors
101883: 06/05/08: Re: Funky experiment on a Spartan II FPGA
101977: 06/05/09: Re: Funky experiment on a Spartan II FPGA
101983: 06/05/09: Re: UK source for Digilent S3 board?
101988: 06/05/09: Re: FPGA-based hardware accelerator for PC
102078: 06/05/10: Re: Quartus II 6.0 available
102085: 06/05/10: Re: CoolRunner XPLA3 getting axed?
102298: 06/05/14: Re: Spartan 3E
102430: 06/05/16: Re: USB2 camera to Xilinx ML40x boards
102457: 06/05/16: Re: USB2 camera to Xilinx ML40x boards
102534: 06/05/17: Re: ADC implementation on FPGA ?
102553: 06/05/17: Re: "disappointing" performance
102667: 06/05/18: Re: Spartan 3 Readback
102722: 06/05/19: Xilinx-ise, invert input?
102723: 06/05/19: Re: Processing DVI signals with an FPGA
102729: 06/05/19: Re: Xilinx-ise, invert input?
103015: 06/05/24: Re: PCI 64/66 fpga eval boards
103174: 06/05/27: Re: tft and uClinux
103183: 06/05/27: Re: Potential of the CELL Processor for Scientific Computing
103184: 06/05/27: Re: tft and uClinux
103185: 06/05/27: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
103195: 06/05/27: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
103204: 06/05/28: Re: ISE sends sensitive information to Xilinx site!------ Only if you say 'yes'
103313: 06/05/31: Re: Running Xilinx and Altera Tools on Fedora Core 5
103338: 06/05/31: Price history?
103408: 06/06/01: Re: Ethernet Snooping in the FPGA
103420: 06/06/01: Re: Ethernet Snooping in the FPGA
103437: 06/06/02: Re: Building custom ASIC solutions
103473: 06/06/03: Re: WebPack on Linux
103484: 06/06/03: Documentation miss? (sp3/xilinx)
103535: 06/06/05: Re: Webpack larger than CDs
103544: 06/06/05: Re: Webpack larger than CDs
103582: 06/06/06: Re: Webpack larger than CDs
103690: 06/06/08: Re: Space invaders on Spartan3e starter board
103702: 06/06/08: Re: stable, tested 6502 core
103921: 06/06/15: Re: Time for a new "Largest FPGA with free tool support"?
103982: 06/06/16: Re: Current from FPGA pins to ADC
103985: 06/06/16: Re: bga routing
103992: 06/06/16: Re: bga routing
103995: 06/06/16: Re: Floppy to FPGA?
104043: 06/06/17: Re: Floppy to FPGA?
104044: 06/06/17: Re: Time for a new "Largest FPGA with free tool support"?
104368: 06/06/26: Re: VHDL model for Micron SDRAM simulation ?
104589: 06/06/30: Re: Missing ISE HTML online help (pdf sucks!)
104626: 06/07/02: Re: Pointers for sending data using ethernet connection from V2Pro
105522: 06/07/25: Re: version control of ISE+EDK projects with CVS and/or SVN
106559: 06/08/15: Re: Maximum Current Draw of FPGA
108625: 06/09/14: Re: Spartan3E availability
109222: 06/09/22: Re: Dell Laptop for Embedded Work
109459: 06/09/27: Re: PUBLISHABLE PAPER RELATED TO FPGA!
109587: 06/09/29: Re: Migration from Spartan-2E to Spartan-3E
109588: 06/09/29: Re: Really slow programming time
109613: 06/10/01: Re: Migration from Spartan-2E to Spartan-3E
109923: 06/10/08: Re: Spartan3A - internal flash configuration or not?
109983: 06/10/09: Re: ISE/EDK computer selection
110018: 06/10/09: Re: Xilinx-Modelsim on Linux
110328: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
110403: 06/10/15: Re: Xilinx FPGAs in battery-powered scenarios
110455: 06/10/16: Re: Nand Flash programming times
110498: 06/10/16: Re: WebPack on Linux
110514: 06/10/17: Re: FPGA + GSM cores
110557: 06/10/17: Re: ANNC: Open Source, Free 32-bit soft processor webcast
110643: 06/10/19: Re: ANNC: Open Source, Free 32-bit soft processor webcast
110808: 06/10/23: Re: Spartan 3 Configuration Questions
111146: 06/10/30: Re: PC configuration for best Xilinx ISE performance
111452: 06/11/03: Re: Scientific Computing on FPGA
111475: 06/11/03: Re: Fastest ISE Compile PC?
112294: 06/11/19: Re: board - T562.jpg
112295: 06/11/19: Re: board - T562.jpg
112431: 06/11/22: Re: board - T562.jpg
112798: 06/11/29: Re: FPGA workstation - should I wait for Window Vista?
112862: 06/11/30: Re: FPGA workstation - should I wait for Window Vista?
112864: 06/11/30: Re: ISE on a cluster?
114579: 07/01/19: NetBSD on Xilinx fpga (ported to ML403)
<pbFJKD@ludd.invalid>:
114718: 07/01/23: Re: First Picture of Craignell Modules
114719: 07/01/23: Re: FPGA workstation - should I wait for Window Vista?
114739: 07/01/23: Re: Surface mount ic's
114774: 07/01/24: Re: Surface mount ic's
114782: 07/01/24: Re: FPGA damage from bad bitstream
114793: 07/01/24: Re: Good hardware design code re-use strategies, reference book
114949: 07/01/27: Re: Xilinx USB download cable
115063: 07/01/30: Re: USB 2.0 Streaming using FPGAs
115107: 07/01/31: Re: 1 Gbps - state of the art?: PCIe is 2.5Gb/s, and PCIe V2.x will be 5.0 Gb/s!
115133: 07/01/31: Re: DDR FPGA Design
115155: 07/02/01: Re: USB 2.0 Streaming using FPGAs
115255: 07/02/05: Re: Graphics demo using FPGA?
115727: 07/02/17: Re: Where to start???
116215: 07/03/05: Re: Sources (products) for Cannibalizing FPGAs, PLDs, etc.
119143: 07/05/13: Re: An Open-Source suggestion for Xilinx
121315: 07/07/02: Xilinx ISE + Multi CPU setup?
121317: 07/07/02: Re: Xilinx ISE + Multi CPU setup?
121351: 07/07/03: Re: Xilinx ISE + Multi CPU setup?
121352: 07/07/03: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121353: 07/07/03: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121515: 07/07/06: Re: Xilinx ISE, EDK and some ground roules in software development
121525: 07/07/06: Re: Xilinx ISE, EDK and some ground roules in software development
121547: 07/07/07: Re: Xilinx ISE, EDK and some ground roules in software development
122322: 07/07/25: Re: tiny Spartan 3 module?
122324: 07/07/25: Re: Altera or Xilinx
122427: 07/07/27: Xilinx XC3S400-4PQ208C pin name files?
122430: 07/07/27: Re: Xilinx XC3S400-4PQ208C pin name files?
125286: 07/10/19: Re: Fast Sampling of digital signals
125289: 07/10/19: Re: FPGA input level conversion
<pbFJqKD@ludd.invalid>:
125285: 07/10/19: FPGA input level conversion
<pbfrtl@NO.MAIL>:
17389: 99/07/23: EVERYTHING YOU WANT !!!! 7306
<pbgbbrsh@ludd.invalid>:
114667: 07/01/22: Re: Xilinx doing a re-entry in non-volatile FPGA arena!!!
114673: 07/01/22: Re: Considerations for FPGA Based Acceleration in Bio medical simulations/computational biology
114708: 07/01/23: Re: First Picture of Craignell Modules
114717: 07/01/23: Re: Surface mount ic's
<pbgibbrish@ludd.invalid>:
114625: 07/01/21: Re: suggest me the right fpga
pbljung:
141195: 09/06/10: Re: Doubt about a Microblaze Based Multiprocessor SoC
141214: 09/06/11: Re: Doubt about a Microblaze Based Multiprocessor SoC
141226: 09/06/11: Re: Doubt about a Microblaze Based Multiprocessor SoC
141818: 09/07/10: Re: more than one core of microblaze on EDK and ISE
147278: 10/04/21: Re: Tutorial for C based bit-accurate hardware modeling ?
148051: 10/06/16: Re: Expand TEMAC fifo?
<pbmueller@my-deja.com>:
27674: 00/12/01: Re: Synplify Benchmarks
<pboonen@my-deja.com>:
17612: 99/08/13: Re: Philips Semiconductors (NL) seeks digital designers
pborut:
72969: 04/09/09: Re: Need StateCAD 4.11!
pbpc:
47359: 02/09/24: xilinx demo board
47831: 02/10/04: Re: xilinx demo board
PC:
57586: 03/07/02: VHDL & OV6620 CMOS camera
57603: 03/07/03: Re: VHDL & OV6620 CMOS camera
100701: 06/04/16: Re: Petition about the xilinx online store ?
100740: 06/04/17: FLASH memory VHDL controller
100808: 06/04/18: Re: Petition about the xilinx online store ?
pc:
55528: 03/05/12: QuartusII issue
55568: 03/05/13: Re: QuartusII issue
121002: 07/06/21: Re: Virtex 5 Rocketio
pc88:
8720: 98/01/22: Share modem, ISDN and cable modem 12029
<pc>:
10898: 98/06/29: Brand New 200MHZ PC's for less than $600. Includes Monitor.
pcad user:
3473: 96/06/05: FPGA error
<pcalvert@radiancetech.com>:
77118: 04/12/23: Re: Newbie: Read from Compact Flash using System ACE
pcie-rat:
143936: 09/11/04: Re: Searching for cost effective PCI express x1 core..
<pcplanet@gmx.de>:
120996: 07/06/21: Virtex 5 Rocketio
<pcvijay30@gmail.com>:
115150: 07/01/31: Xc2v6000 package for ise
PD:
59283: 03/08/13: Proto-Board with VirtexII and multiple DDR SDRAM banks?
PDemos:
44476: 02/06/21: design cycle metrics
<pdorsey@gmail.com>:
130955: 08/04/06: Re: Conterfeit parts guidance
PDP11 Hacker .....:
67: 94/08/08: Re: How pricey is FPGA development?
68: 94/08/08: Re: How pricey is FPGA development?
75: 94/08/10: Re: Proprietary Configuration Data
76: 94/08/10: Re: How pricey is FPGA development?
102: 94/08/15: Re: FPGA Hobbyist and their software/programmer/hardware
126: 94/08/18: Re: Proprietary Configuration Data
pdq:
79676: 05/02/23: re:Debugging error in VHDL
79679: 05/02/23: re:Synchronizing multibit bus
79680: 05/02/23: re:How to handle clock skew?
79681: 05/02/23: re:Source of reset for synchronous reset can lead to metastabil
79852: 05/02/25: re:generic
<pdstroud@gmail.com>:
76999: 04/12/19: Re: PCI doubt
77133: 04/12/24: Re: PCI doubt
pdudley1@comcast.net:
125315: 07/10/20: Re: Starting FPGA
125322: 07/10/21: Re: Need suggestion on FPGA kit
126798: 07/12/02: Re: Fedora 8 and ISE 9.2
127699: 08/01/05: Re: question on AND
131162: 08/04/13: HiTech Global Eval boards?
132017: 08/05/09: Re: 5 V oscillator output to GCLK
<pdw96@casper.cs.virginia.edu>:
3021: 96/03/15: PDW'96 Advance Program
3053: 96/03/22: PDW'96 hotel reservation deadline is near
<pdw96@cobra.cs.virginia.edu>:
2982: 96/03/08: PDW'96 Advance Program
peace:
8521: 98/01/04: Design with EPM7128S
Pearl Heintz:
Pears772:
67095: 04/03/05: use of attributes
PeckPeck2:
31160: 01/05/13: 8051 microcontroller
Pedro:
87815: 05/08/01: Re: ISE webpack doesnt support Spartan xcs10, solution??
117719: 07/04/08: How do I use the Xilinx USB download cable for testing?
117723: 07/04/08: Re: How do I use the Xilinx USB download cable for testing?
117962: 07/04/14: ML506 Platform Flash
Pedro Alexandre:
36202: 01/11/01: XC6000
PEDRO C. GUILLEM VALENTIN:
20884: 00/02/25: DISTRIBUIDOR
Pedro Claro:
58140: 03/07/15: Re: free downloadable VLSI softwares
59406: 03/08/18: Re: Which software from Xilinx
Pedro Diniz:
30979: 01/05/07: Xilinx Virtex Libraries for Synopsys Behav. Compil
Pedro J. Rodríguez:
Pedro Lazaro:
156640: 14/05/18: How to reduce "Core static thermal dissipation" from fpga design in Quartus
Pedro Merino Gonzalez:
3370: 96/05/22: Which FPGA is better for PCI?
6647: 97/06/09: XC6200 Gate Count
8907: 98/02/06: Looking for XC6200 Sw
[Pedro Silva]:
30445: 01/04/08: Alternative to Xilink Foundation schematic editor
pedro uno:
78022: 05/01/22: Re: USB Host
81256: 05/03/20: Re: Creating own RPMs using Xilinx ISE
81257: 05/03/20: Re: FIR choice
82714: 05/04/16: Re: ISE 7.1 GUI (slightly OT)
Peekay Chan:
16389: 99/05/19: Internal visibility and EDIF/VHDL
peer:
88912: 05/08/31: chipscope commands?
Peet Badenhorst:
1617: 95/08/01: 16 bit computer on fpga's
Peet James peetj:
1098: 95/04/27: Re: Sunrise ???
Peeters:
5380: 97/02/12: PCI Prototyping board with a XC4013E or XC4013EX
Peggy:
72881: 04/09/07: How to purposely make pipelining in Handel-C?
pei@uwiep.com:
90439: 05/10/13: Data width change in opencores Ethernet MAC
<pei@uwiep.com>:
89553: 05/09/19: Testbench failures for Opencores Ethernet mac
peio:
152953: 11/11/04: Re: PCI core with expansion ROM support
Peixin Zhong:
6202: 97/04/25: Help needed on Viewlogic installation on NT
9636: 98/03/27: Q: Random number generator
9648: 98/03/27: Re: Q: Random number generator
pejdstran:
97513: 06/02/23: Re: EDK 7.1 XMD and platform USB cable
Pekka Jaaskelainen:
151459: 11/04/11: TTA-Based Co-design Environment (TCE) v1.4 released
153854: 12/06/07: TCE 1.6
154864: 13/01/21: TTA-based Co-design Environment (TCE) v1.7 released
Pelican:
6568: 97/06/03: test
pemiliv:
124611: 07/09/28: Re: Xilinx upgrade
135114: 08/09/16: security system password by voice recognition commands
Pendlebury Chumbleton:
155151: 13/05/01: Re: Low cost and/or small size CPU in an FPGA
Peng:
46275: 02/08/23: Re: X on bus
46339: 02/08/26: Re: sensing an oscillator
Peng Cong:
48622: 02/10/22: Beginner question
48993: 02/10/29: Modelsim help
49171: 02/11/04: Incremental design question
49612: 02/11/18: Re: Are block RAMs supported in simulation?
50126: 02/12/03: Re: block and distributed RAM
51754: 03/01/21: Re: Ram bits for Registers
51755: 03/01/21: FPGA new bie question
51840: 03/01/23: What's the reason?
53422: 03/03/13: The structure of the multiplier
55735: 03/05/18: Re: Xilinx Project Navigator in ISE 5.2i
55790: 03/05/20: Re: verilog question
56868: 03/06/18: Re: XCV 6000 data sheets
62080: 03/10/18: Re: Signed Multiplication in a Virtex-II Multiplier.
62110: 03/10/20: Re: Signed Multiplication in a Virtex-II Multiplier.
62316: 03/10/26: Re: Verilog Program With A Problem
63493: 03/11/24: Xilinx ISE 6.1i+SP2 And Modelsim 5.8
63534: 03/11/25: Re: Dual port RAM for Xilinx
63630: 03/11/27: Re: Xilinx ISE 6.1 external editor
66954: 04/03/02: Re: XST ff merging - how do I "preserve" flip flops
70134: 04/06/04: Re: where is ISE 6.2 SP#3 ?
78494: 05/02/02: Using FPGA Compiler2 with coreConultant?
PENG LIU:
9028: 98/02/16: the problem about counter.
penguin:
85093: 05/06/03: Re: how can i extend my code space to extern memory?
pengyun:
18444: 99/10/25: Synplify / LPM?
<pengyun@my-deja.com>:
19777: 00/01/12: Re: Altera Quartus 99.10
2Penny:
51363: 03/01/12: from ABEL/PLDs to VHDL&VeriLog/FPGAs
51397: 03/01/13: need pointers to FPGA software & download hardware
51594: 03/01/17: Re: need pointers to FPGA software & download hardware
62690: 03/11/05: device progamming hardware found; device programming software sought
PeopleSoft:
7471: 97/09/15: how generate xilinx 3020 EPROM?
pepeprisas:
79678: 05/02/23: reading from CF
Pepi:
118302: 07/04/23: Non-intrusive readback on FPGA configuration data
118397: 07/04/25: Re: Non-intrusive readback on FPGA configuration data
118643: 07/05/01: Re: Killed a Stratix-II Nios II Altera devkit, How to repair?
Pepito:
10145: 98/04/29: USB infos ( Hardware - Software - Driver ) at ...
11381: 98/08/08: Usb info here : hard and soft
Pepito Perez:
49705: 02/11/19: Free FPGA Development Board
49721: 02/11/19: Re: Free FPGA Development Board
49759: 02/11/20: Re: Free FPGA Development Board
53395: 03/03/12: Buying memory for FPGA...
53462: 03/03/13: Re: Buying memory for FPGA...
53522: 03/03/14: Re: Altera Sourcing
Peppe:
108397: 06/09/10: Functional and Post-Synthesis Simulation
Pepper Orlando:
73359: 04/09/20: How feasible is a SoC project?
73397: 04/09/21: ISE and BaseX for Linux?
Peppermint Pumpkin:
114194: 07/01/07: Re: Is there a simple complex magnitude algorithm in FPGA implementation?
Per:
136699: 08/12/02: Re: reading registers
136700: 08/12/02: Re: simulation results is correct but synthesis result is not correct
136870: 08/12/10: Re: Sampling a clock
161410: 19/07/14: Re: Field update
Per =?iso-8859-1?Q?Karlstr=F6m?=:
102465: 06/05/16: Re: Floating point reality check
Per Bjureus:
2249: 95/11/09: Re: X-Blox...The good, bad and ugly
3662: 96/07/10: Q:Veribest and Xilinx netlist.
4014: 96/09/03: Re: xilinx programing
Per Bjuréus:
6461: 97/05/26: Re: Best way to learn VHDL?
Per Fremrot:
10014: 98/04/22: Synopsys FPGA compiler
10037: 98/04/23: Re: Synopsys FPGA compiler
Per Jensen:
105303: 06/07/20: Combining Schematic and VHDL code in Webpack 8.1 ??
105410: 06/07/22: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
105419: 06/07/22: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
105434: 06/07/23: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
105435: 06/07/23: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
105440: 06/07/23: Re: Using BUS'es in ISE WebPACK 3.3WP8.1 ???
Per Zander:
12936: 98/11/05: FPGA on ASIC (Was: Re: New free FPGA CPU)
Perfect Queue:
97411: 06/02/21: Layer 2 (MAC) Research Project to Eliminate Routers
peri:
89907: 05/09/29: very urgent
perica:
89981: 05/09/30: re:Testbench using Modelsim/VHDL - simple signal generation pro
Pericles:
30526: 01/04/12: Re: fpga from linux/hc11
<perltcl@yahoo.com>:
81841: 05/04/01: fpga async design help me
Perry:
113197: 06/12/07: About partial reconfiguration in Virtex 4
114254: 07/01/09: crash of xilinx fpga_editor
114338: 07/01/11: user constraint file of slice based bus macro in virtex 4
115325: 07/02/07: Questions about pci transactions in my core
118225: 07/04/20: questions about pci conmmunications on a pcb board
121054: 07/06/24: What wrong with the DCM of Virtex4 in my project?
121083: 07/06/25: Re: What wrong with the DCM of Virtex4 in my project?
121107: 07/06/25: Re: Trouble using DCMs in EDK 8.2
121129: 07/06/26: Re: Trouble using DCMs in EDK 8.2
121158: 07/06/27: A strange error during PAR process in EDK, could anyone in xilinx help me?
121196: 07/06/27: Re: A strange error during PAR process in EDK, could anyone in xilinx help me?
121246: 07/06/28: How to snoop an inout signal in EDK?
personel:
113554: 06/12/15: Netlist Simulation for PPC (Virtex-4 FPGA)
pes:
127292: 07/12/17: Re: PCI Parallel port card for JTAG / programming?
145826: 10/02/25: Xilinx XPS crash on Linux
147513: 10/04/29: Spartan6 and 4GB RAM
147727: 10/05/19: spartan6 configuration
147934: 10/06/03: Spartan6 power consumption
148428: 10/07/22: Xilinx Plan Ahead question
150349: 11/01/11: deconvolution
150417: 11/01/19: Re: deconvolution
<pesc@telindus.be>:
10207: 98/05/04: How to make FIFO's in Altera FLEX8000 or FLEX6000
Pete:
1414: 95/06/19: Re: Any company for conversion FPGA to ASIC?
1415: 95/06/19: Re: altera mail adress ?
44345: 02/06/18: Re: new computer
57960: 03/07/10: Behavioral simulation problem using Modelsim
62065: 03/10/17: Anyone try the Gameboy FPGA system?
66031: 04/02/11: Xilinx Platform Flash Prom
66094: 04/02/12: Re: Xilinx Platform Flash Prom
70323: 04/06/12: Re: Cores into fpga
74538: 04/10/13: Xininx XC2V6000 Eval board for 1517 BGA Package
75368: 04/11/03: Need Virtex 2 Proto Board
80046: 05/02/28: virtex4 virtex-4 FX eval board
80997: 05/03/15: Annapolis WildCard for System Generator hardware-in-the-loop - Extreme DSP
83634: 05/05/04: embedded linux for v2pro PPC?
90761: 05/10/20: EDK on Virtex4 FX using embedded ethernet MAC
131071: 08/04/09: Xilinx FFT C-sim model
133654: 08/07/08: 2 BUFIOs in the same clock-capable pair?
133900: 08/07/18: Virtex-5, DDR2 SRAM, and ISERDES
134606: 08/08/20: Workaround for installing EDK on Vista x64?
134607: 08/08/20: VHDL models for DDR2 SDRAM?
134622: 08/08/21: Re: Workaround for installing EDK on Vista x64?
pete:
124723: 07/10/01: Re: memory in spartan 3 fpga
Pete Fraser:
7943: 97/11/01: Re: REMEMBER THE WATKINS MAN??
8243: 97/12/02: Whatever happened to PREP?
Pete Becker:
2293: 95/11/17: Re: NeoCAD and AT&T vs. Xilinx
2319: 95/11/20: Re: options for VHDL or Verilog simulation/synthesis < $10,000 ?
2322: 95/11/20: Looking for Low-$ Programmer
2328: 95/11/20: PC VHDL synth for FPGA?
2482: 95/12/15: Re: Gated Clock Problem in Xilinx FPGA Implementation
2678: 96/01/23: FPGAs for Newbie?
2920: 96/02/29: JEDEC Specification?
Pete Burch:
6925: 97/07/09: Altera FLEX10K initialization
Pete Danile:
18292: 99/10/12: Re: Mentor on a Laptop
pete dudley:
27818: 00/12/10: Re: Virtex II DLL at 311MHz on XCV300e-8ES
32344: 01/06/23: Re: Help needed: New user with Xilinx WebPack and XC9572 counter design - how to do basic things
32494: 01/06/27: Re: Alpha Particle
32588: 01/07/01: Re: Xilink WebPACK keeps removing a pin I want to keep.
32589: 01/07/01: Virtex II Block RAM's - Is the second port free?
34012: 01/08/10: Quicklogic and Actel floorplanning?
34013: 01/08/10: Re: Anyone using Xilinx System Generator yet???
34662: 01/09/02: DSP in OTP
34679: 01/09/03: Re: DSP in OTP
34838: 01/09/10: Xilinx Virtex II Embedded Multiplier - Pipeline Register?
34888: 01/09/12: Re: Xilinx Foundation Base(DS-ISE-XB2). Exactly what do you get?
34916: 01/09/13: Re: Innoveda and ISE Alliance 4.1i ?
34950: 01/09/14: Re: Xilinx Virtex II Embedded Multiplier - Pipeline Register?
36488: 01/11/09: Re: Virtex 2 parts availability???
36490: 01/11/09: Re: Decoupling capacitors on Virtex II
37758: 01/12/19: Re: Spartan-IIE schematic symbol?
76349: 04/11/30: CIC - Hogenauer glitch
76413: 04/12/01: Re: How to subscribe to the newsgroup comp.arch.fpga
Pete Dudley:
19243: 99/12/08: Re: JTAG on PCI slot
22084: 00/04/20: PLD Timing, Tco?
22090: 00/04/20: Re: PLD Timing, Tco?
22091: 00/04/20: Answer Found, thank you.
22550: 00/05/11: simulation of Xilinx Coregen modules in schematic environment
23546: 00/06/29: Re: Maximum Speed on obtainable on FPGAs?
23564: 00/06/30: Re: Buying Xilinx Chips online?
23569: 00/06/30: Viewlogic schematic from Synplify edif output?
23691: 00/07/05: Thanks for the tip
23730: 00/07/06: Re: Using LUTs in Virtex with ViewDraw and ViewSim
26707: 00/10/25: Re: 155Mhz DDR in a programmable logic
27562: 00/11/28: Virtex II DLL at 311MHz on XCV300e-8ES
28949: 01/01/30: lvds and lvpecl differential I/O input termination on Virtex II - Whats Best?
30054: 01/03/21: reduced precision floating point
31223: 01/05/15: Re: BUFG in Virtex_E
31657: 01/06/01: simulation of Viewdraw schematics containing VirtexII flip flops.
31724: 01/06/04: Re: XtremeDSP Ready for prime time?
34850: 01/09/11: Innoveda and ISE Alliance 4.1i ?
37675: 01/12/18: Re: Spartan-IIE schematic symbol?
37797: 01/12/20: Re: You take the low road and I'll ......
40900: 02/03/18: Re: Difference between Virtex-II(E) und Virtex-E
40901: 02/03/18: Re: High speed clock routing
41492: 02/03/30: Re: FPGA config without boot PROM???
43340: 02/05/19: Rounding Accumulator
47036: 02/09/16: Re: EDIF and JHDL information
47037: 02/09/16: ieee.math_real for presynthesis table calculation in vhdl
47148: 02/09/19: Re: ieee.math_real for presynthesis table calculation in vhdl
50306: 02/12/08: virtex 2 temperture sensing with max1617a on DXN and DXP
50307: 02/12/08: Re: Hold time violation
50314: 02/12/08: Re: FPGA Actual Power Measurement
52020: 03/01/28: analog in analog out DSP development board for Xilinx
55612: 03/05/13: Re: "Primitives" in XST?
61053: 03/09/26: Xilinx ISE 6.1 Clocking Wizard - no hdl generated?
61055: 03/09/26: Re: Xilinx ISE 6.1 Clocking Wizard - no hdl generated?
62545: 03/10/31: Re: pullup on inputs
62546: 03/10/31: Re: Picoblaze development tool
78332: 05/01/29: Re: Platform Cable USB on WinXP with SP2
Pete Fenelon:
53705: 03/03/20: Re: Help understanding 7408 and gate chip
109080: 06/09/20: Re: MicroFpga = program an FPGA as it would be a MCU !
Pete Fraser:
30796: 01/04/29: Re: manufacturer's of FIR chips
33160: 01/07/18: Xilinx Multiply generator Core V3.1
33162: 01/07/18: Athlon 1.4 vs Pentium 4 1.7 for Foundation ISE/ModelSim?
33210: 01/07/19: Re: Taking 4MSB a problem in 2's complement?
36299: 01/11/05: Heatsink for Xilinx FF896 package?
36376: 01/11/07: Re: FPGA Wish list
40769: 02/03/14: Re: Difference between Virtex-II(E) und Virtex-E
40852: 02/03/16: Re: just bought...
40885: 02/03/17: Re: just bought...
40893: 02/03/17: Re: just bought...
47922: 02/10/07: Xilinx Parallel Cable III with port replicator?
50479: 02/12/11: Re: question about fft vs. cross corelation in fpga
55852: 03/05/21: Re: FPGA design: firmware or hardware?
56102: 03/05/28: Re: FIFO Controller
58018: 03/07/11: Re: Cyclone vs Spartan-3
58595: 03/07/28: Re: VHDL Book Recommendations Please
58682: 03/07/30: Re: Altera-to-Xilinx IO 3.3V -> 1.8V
58717: 03/07/31: Re: Altera-to-Xilinx IO 3.3V -> 1.8V
59487: 03/08/20: Re: Legacy 4005 series and current Xilinx ISE offerings?
59790: 03/08/28: Re: How to listen to music through an FPGA pin?
60341: 03/09/10: Re: Original (5V) Xilinx Spartan ?
60375: 03/09/11: Paging Peter Alfke (3S1000 pricing)
62357: 03/10/27: Re: What's a good book on FPGA CPU design?
62539: 03/10/31: Re: Shannon Entropy for Black Holes
62715: 03/11/05: Re: Video Scan Conversion Rate - Camera Input to DVI Display Output
63011: 03/11/12: VHDL code for an mj2 parser.
64382: 03/12/31: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
66863: 04/02/27: Need to speed up Stratix compiles.
67009: 04/03/03: Re: Need to speed up Stratix compiles.
67977: 04/03/23: Re: Quartus with AMD64 processors?
68752: 04/04/16: Re: Osborne [Was: Apples to Apples? Stratix II <> Virtex-II Pro]
72017: 04/08/05: Re: Comparing Quality of Results of FPGA CAD Tools
72044: 04/08/06: Re: Comparing Quality of Results of FPGA CAD Tools
73436: 04/09/21: Re: Mr. Greenfield, spare us the propaganda !
73481: 04/09/22: Re: Mr. Greenfield, spare us the propaganda !
74983: 04/10/22: Hello Xilinx folks -- please answer
75009: 04/10/24: Re: Hello Xilinx folks -- please answer
74882: 04/10/20: When will the ML401 source be released?
75706: 04/11/12: Re: digital analog conversion
75791: 04/11/15: Re: video camera interface to FPGA
75793: 04/11/15: Re: Digital LP filter in multiplier free FPGA
77006: 04/12/19: Help with file read please
77884: 05/01/19: Re: video decoder for altera dev. board
78724: 05/02/06: Quality of Xilinx ML401 video output?
79081: 05/02/13: Re: Fast counting
79712: 05/02/23: Re: SD Card and FPGA
80269: 05/03/02: Re: Genlock
80309: 05/03/03: Re: Genlock
80402: 05/03/04: Re: Genlock
80441: 05/03/05: Re: PLL code
80478: 05/03/06: Re: DCT in FPGA
80562: 05/03/08: Re: Genlock
80607: 05/03/08: Re: Asynchronous processor !?!
80639: 05/03/09: O.T. Clock current (was Re: Asynchronous processor !?!)
80807: 05/03/11: Re: Xilinx vs Altera high-end solutions
81103: 05/03/17: Re: Bit-Rounding Algorithm
81861: 05/04/02: Re: Achieving required speed in Virtex-II Pro FPGA
81968: 05/04/05: Re: Reverse engineering ASIC into FPGA
82200: 05/04/08: Re: DCT
83931: 05/05/09: Re: DDR speed of the XUPV2P Board from Digilent
87188: 05/07/18: EDK 7.1 with ML401 (paging Antti)
87846: 05/08/02: ML401 JTAG configuration problem
87935: 05/08/03: Re: ML401 JTAG configuration problem
88467: 05/08/18: Re: Antti's last comp.arch.fpga posting
89233: 05/09/08: digilent web site?
89526: 05/09/17: Insight / Xilinx Spartan II Demo Board files?
89959: 05/09/30: Xilinx dev board with high quality video?
89997: 05/10/01: Re: Xilinx dev board with high quality video?
89998: 05/10/01: Re: Xilinx dev board with high quality video?
90002: 05/10/01: Re: Xilinx dev board with high quality video?
90138: 05/10/05: Re: Xilinx dev board with high quality video?
93340: 05/12/20: Re: real-time compression algorithms on fpga
93350: 05/12/20: Re: real-time compression algorithms on fpga
93352: 05/12/20: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93353: 05/12/20: Re: real-time compression algorithms on fpga
94754: 06/01/17: Re: xilinx free Sample Pack info now also on Xilinx own webpages
96497: 06/02/04: Re: advanced vhdl lerning
105158: 06/07/14: Data Logging / FPGA Dev board
114163: 07/01/05: Xilinx 2-D DCT core (Where?).
114870: 07/01/25: Re: video buffering scheme, nonsequential access (no spatial locality)
114873: 07/01/25: Re: video buffering scheme, nonsequential access (no spatial locality)
114890: 07/01/25: Re: video buffering scheme, nonsequential access (no spatial locality)
114897: 07/01/25: Re: video buffering scheme, nonsequential access (no spatial locality)
115488: 07/02/12: Re: substracting a whole array of values at once
115540: 07/02/13: Re: substracting a whole array of values at once
115594: 07/02/14: Re: substracting a whole array of values at once
115785: 07/02/20: Re: Do you like Virtex-5 ?
117270: 07/03/27: Help with Xilinx Parallel Cable IV.
117278: 07/03/27: Re: Help with Xilinx Parallel Cable IV.
117641: 07/04/05: Re: OT Re: Gray code in asynchronous FIFO design
117701: 07/04/07: Re: can anyone give me a reference price of the following Xilinx boards?
120694: 07/06/13: ISE write permissions?
120696: 07/06/13: Re: ISE write permissions?
120925: 07/06/20: Re: Suggestions for Xilinx based evaluation board for image processing
120998: 07/06/21: Agilent Dynamic Probe?
121892: 07/07/14: Re: Image Resolution Rescaling
122029: 07/07/17: Generating video noise.
122153: 07/07/20: Re: Generating video noise.
124790: 07/10/04: Re: JPEG-LS hardware implementation
133126: 08/06/18: Re: Xilinx Webpack
133129: 08/06/18: Re: Xilinx Webpack
133631: 08/07/07: Re: ANNOUNCE: TimingAnalyzer version beta 0.86
134390: 08/08/08: Development board with SD card.
134404: 08/08/08: Re: Development board with SD card.
134484: 08/08/12: Re: PCI Express with FPGA Webcast Tomorrow
135492: 08/10/04: Re: Xilinx PCIE problem
135536: 08/10/06: Re: Xilinx cores with license
135787: 08/10/15: Re: Simulation
136101: 08/10/31: GDDR3
136652: 08/11/28: Re: Dithering video signals
136664: 08/11/29: Re: Dithering video signals
139826: 09/04/15: Re: S3A starterkit weird behaviou (mini quiz)
140823: 09/05/26: Core 2 Duo E8500 vs. Core i7 920?
141250: 09/06/12: Re: NTSC/PAL Encoder using FPGA and DAC
142218: 09/07/29: Re: cool chart
142225: 09/07/29: Re: cool chart
142423: 09/08/10: Re: Spartan-6 Boards - Your Wish List
145597: 10/02/15: Re: How relevant is the Residue Number System (RNS)?
146001: 10/03/03: Modelsim PE vs. Aldec Active-HDL (PE)
146003: 10/03/03: Laptop for FPGA design?
146017: 10/03/03: Re: Laptop for FPGA design?
146198: 10/03/08: Some Active-HDL questions
146211: 10/03/08: Re: Some Active-HDL questions
146503: 10/03/20: Re: Active-HDL Strange Waveform Display
146562: 10/03/22: Writing Hex values to file in VHDL?
146583: 10/03/23: Re: Writing Hex values to file in VHDL?
146585: 10/03/23: Re: Writing Hex values to file in VHDL?
146586: 10/03/23: Re: Writing Hex values to file in VHDL?
146587: 10/03/23: Re: Writing Hex values to file in VHDL?
146593: 10/03/23: Re: Writing Hex values to file in VHDL?
146937: 10/04/02: ISE block RAM inference
147141: 10/04/15: Re: MPEG Reading material
147412: 10/04/26: Re: Inferring mutipliers
147430: 10/04/27: Re: Inferring mutipliers
147443: 10/04/27: Re: Inferring mutipliers
147444: 10/04/27: Re: Craignell2-48 - 48 Pin FPGA DIL Module
147486: 10/04/28: Re: xilinx arm finally announced
147624: 10/05/08: Re: I'd rather switch than fight!
148485: 10/07/27: LPM_MULT issues
148522: 10/07/29: Data-path accuracy in IIR filters?
148808: 10/08/27: Plotting sampled data in Matlab
148810: 10/08/27: Re: Plotting sampled data in Matlab
148818: 10/08/28: Re: Plotting sampled data in Matlab
148819: 10/08/28: Re: Plotting sampled data in Matlab
148820: 10/08/28: Re: Plotting sampled data in Matlab
149499: 10/10/31: [O.T.] Audio DAC as AWG (test source)?
149501: 10/10/31: Re: [O.T.] Audio DAC as AWG (test source)?
149536: 10/11/02: Re: [O.T.] Audio DAC as AWG (test source)?
150211: 10/12/31: Re: I Give Up!
150698: 11/02/04: Re: Trivia: Where are you on the HDL Map?
151267: 11/03/19: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of
151583: 11/04/21: Xilinx ML605 Demo Qusstion
151590: 11/04/22: Re: Xilinx ML605 Demo Qusstion
151594: 11/04/22: Re: Xilinx ML605 Demo Qusstion
151599: 11/04/25: Re: Xilinx ML605 Demo Qusstion
151601: 11/04/25: Re: Xilinx ML605 Demo Qusstion
151784: 11/05/18: Re: Counter clocks on both edges sometimes, but not when different
152336: 11/08/10: Re: image storing into BRAM
Pete H.:
47034: 02/09/15: Custom plug-in for HDL Designer
Pete Harrison:
71294: 04/07/14: WinCUPL state machine for 16V8
71302: 04/07/14: Re: WinCUPL state machine for 16V8
Pete Hudson:
95943: 06/01/27: C to FPGA Tools (Impulse C and others) and necessary trig IP
Pete Koziar:
42077: 02/04/15: Xilinx BSCAN_SPARTAN2 component
42079: 02/04/15: Re: FPGA config without boot PROM???
42080: 02/04/15: Re: new to fpga's need insight
42086: 02/04/15: Re: JTAG cable and iMPACT
42110: 02/04/16: Re: Xilinx BSCAN_SPARTAN2 component
42111: 02/04/16: Reconfiguring Spartan II after boot-up
42113: 02/04/16: Command-line utility for loading Xilinx XC9572XL and Spartan II via JTAG
42166: 02/04/17: Re: Reconfiguring Spartan II after boot-up
42167: 02/04/17: Re: Command-line utility for loading Xilinx XC9572XL and Spartan II via JTAG
42669: 02/04/30: Re: Problems creating a tristated data bus on Spartan-II
Pete Little:
20381: 00/02/08: Re: FPGA express: No clockbuf for rst
20389: 00/02/08: Re: FPGA express: No clockbuf for rst
pete o.:
111877: 06/11/12: Pad to Setup, Clock to Pad
111878: 06/11/12: Pad to Setup, Clock to Pad
114431: 07/01/15: Verifying a Bidirectional Data Bus
115433: 07/02/10: ModelSim - Do Files
Pete Ormsby:
45640: 02/07/30: Re: secure FPGA
45977: 02/08/13: Re: unloading a fast ADC
46211: 02/08/21: Re: What's wrong with clearLogic?
46643: 02/09/05: Re: QUARTUS II V2.1 LINUX (C) ALTERA
47547: 02/09/28: Re: Altera Cyclone low-cost FPGA chips?
50453: 02/12/11: Re: FPGA/PCI on low budget
53776: 03/03/22: Re: Altera FLEX10K100E voltage?
Pete Peterson:
3768: 96/07/29: Re: ### 7 Quick Multiple Choice Questions ###
Pete Robinson:
96966: 06/02/14: Which SelectIO for FPGA <-> FPGA buses?
Pete Sedcole:
74368: 04/10/08: Re: Daft modelsim question
87081: 05/07/14: Re: Xilinx MAP problem (>1 External Macro Output Pin on single net)
Pete Smoot:
28275: 01/01/04: Re: Nondeterministic FSMs in hardware?
Pete Zaitcev:
16157: 99/05/06: PCI slave in FPGA?
<pete@coho.org>:
130112: 08/03/14: Re: Xilinx Tristate Registration
PeteD:
27852: 00/12/12: Re: Xilinx CPLD capable of driving LEDs
28798: 01/01/24: Re: Could I use IOPAD twince in the design?
30040: 01/03/21: Re: Trouble with assigning output pins on Xilinx (foundation)
30117: 01/03/23: Re: what to do with I/O pins during powerup or during jtag programming
<petem2712@my-dejanews.com>:
15706: 99/04/09: Lattice PDS Software
peter:
26485: 00/10/18: scripting with xilinx tools (foundation) ????
98220: 06/03/07: Xilinx ISE8.1 & MIG1.5 crash
119062: 07/05/10: ISE9.1: ERROR:Place:911
119067: 07/05/10: Re: ISE9.1: ERROR:Place:911
119078: 07/05/10: Re: ISE9.1: ERROR:Place:911
Peter:
3255: 96/05/03: Re: Simple Xilinx board
3278: 96/05/08: Re: Implementation of a ROM
3303: 96/05/11: Re: Looking for free FPGA softw./Xilinx
3308: 96/05/12: Re: Anyone use Orcad PLD tools ?
3318: 96/05/13: Re: Looking for free FPGA softw./Xilinx
3327: 96/05/13: Re: Xilinx 4013 80% utilized but won't route
3337: 96/05/15: Re: Looking for free FPGA softw./Xilinx
3365: 96/05/21: Re: Xilinx and Viewlogic
3401: 96/05/24: Re: socket wanted for xilinx or other way to
3400: 96/05/24: Re: Xilinx and Viewlogic
3402: 96/05/24: WEIRD NOISE PROBLEM WITH XILINX XC3064 - can anyone help?
3410: 96/05/25: Re: OTP FPGAs was WEIRD NOISE PROB
3439: 96/05/30: Re: WEIRD NOISE PROBLEM WITH XILINX XC3064 - can anyone help?
3470: 96/06/04: Re: WEIRD NOISE PROBLEM WITH XILINX XC3064 - can anyone help?
3471: 96/06/04: Re: RS422 Connections and Pin-outs
3407: 96/05/25: Re: WEIRD NOISE PROBLEM WITH XILINX XC3064 - can anyone help?
3488: 96/06/08: Re: FPGA Companies
3499: 96/06/11: Re: UART for Actel FPGA
3539: 96/06/17: Re: UART for Actel FPGA
3570: 96/06/26: Re: Atmel AT17C65/128/256 Serial EEPROM Memories.
3609: 96/07/03: Re: INDUSTRY GADFLY "Why I Hate Wally"
3610: 96/07/03: Re: LCA to Schematic
3611: 96/07/03: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
3628: 96/07/05: Re: LCA to Schematic
3638: 96/07/06: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
3663: 96/07/10: Re: ANNOUNCE: New Model of the Month - 16 bit ADC
3683: 96/07/12: Re: wireless loader for (Xilinx) FPGAs ?
3695: 96/07/17: Re: XC3195 serial-EEPROM dissassembler ?
3706: 96/07/18: Re: Hardware sort?
3726: 96/07/22: Re: Hardware sort?
3785: 96/07/31: Re: Question: FPGA versus ASIC design.
3798: 96/08/03: Re: Xilinx/FPGA Timing Problems
3812: 96/08/06: Re: Xilinx/FPGA Timing Problems
3839: 96/08/08: Re: Xilinx/FPGA Timing Problems
3853: 96/08/09: Re: Xilinx/FPGA Timing Problems
3864: 96/08/10: Re: Shareware XILINX Synthesis Tool???
3880: 96/08/14: Re: Monostable multivibrator
3881: 96/08/14: Re: Xilinx/FPGA Timing Problems
3885: 96/08/14: Xilinx XC3090 intermittent place/route problem
3893: 96/08/15: Re: Xilinx XC3090 intermittent place/route problem
3943: 96/08/23: Re: CHEAP XILINX FPGA ROUTING SOFTWARE ?
3956: 96/08/24: Re: CHEAP XILINX FPGA ROUTING SOFTWARE ?
3961: 96/08/25: Anyone know about Viewlogic v4 with QEMM?
3984: 96/08/29: Re: Anyone know about Viewlogic v4 with QEMM?
3985: 96/08/29: Re: DES in Xilinx
4069: 96/09/07: Re: ORCA and Viewlogic - any good?
4090: 96/09/09: Re: ORCA and Viewlogic - any good?
4110: 96/09/11: Re: ORCA and Viewlogic - any good?
4137: 96/09/17: Re: Good Starting points to learn FPGA for hobbyist?
4138: 96/09/17: Re: manchester clock recovery
4180: 96/09/22: Re: manchester clock recovery
4216: 96/09/29: Re: Source for 8259 PIC
4219: 96/10/01: Viewlogic 4.1 (DOS) mouse alternatives?
4225: 96/10/02: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4499: 96/11/06: Re: XACT under WinNT is very slow
4500: 96/11/06: Re: XACT under WinNT is very slow
4501: 96/11/06: Re: UART FOR FPGAS
4510: 96/11/07: Re: XACT under WinNT is very slow
4511: 96/11/07: Re: UART FOR FPGAS
4533: 96/11/10: Re: Xilinx and cost of tools
4545: 96/11/12: Re: UART FOR FPGAS
4550: 96/11/13: Re: UART FOR FPGAS
4551: 96/11/13: Re: Xilinx and cost of tools
4552: 96/11/13: Re: Digital PLL or Sample Rate Multiplier
5085: 97/01/22: Re: GAL programming timing
5129: 97/01/25: Re: GAL programming timing
5139: 97/01/26: Re: Altera support better than Xilinx
5177: 97/01/29: Re: Safety Critical Apps -> Xilinx Checker.
5176: 97/01/29: Re: Altera support better than Xilinx
5183: 97/01/29: Re: Safety Critical Apps -> Xilinx Checker.
5189: 97/01/29: Re: Altera support better than Xilinx
5204: 97/01/30: Re: Altera support better than Xilinx
5240: 97/02/01: Re: Altera support better than Xilinx
5268: 97/02/03: Re: FPGA power dissipation
5315: 97/02/06: Re: Duplicate PLD?
5330: 97/02/07: Re: FPGA power dissipation
5346: 97/02/09: Re: Serial Communication Controller Design
5369: 97/02/11: Re: Serial Communication Controller Design
5401: 97/02/13: Re: [Q].FIFO in FPGA XILINX
5402: 97/02/13: Re: Serial Communication Controller Design
5430: 97/02/15: Re: Serial Communication Controller Design
5440: 97/02/16: Re: FPGA power dissipation
5530: 97/02/22: Re: Reverse Engineering FPGAs
5584: 97/02/26: Re: Reverse Engineering FPGAs
5600: 97/02/27: Is XACT 6 annual maintenance worthwhile?
5661: 97/03/05: Re: viewlogic ...
5696: 97/03/07: Re: viewlogic ...
5774: 97/03/13: Re: Reverse Engineering FPGAs
5775: 97/03/13: Re: Fatal exception under Win95 & XACT v6.0.1
5804: 97/03/16: Re: A viewlogic story
5845: 97/03/20: Re: Multiple clocks in Xilinx
5880: 97/03/22: Re: Multiple clocks in Xilinx
5886: 97/03/23: Re: Sole source
5906: 97/03/25: Re: Sole source
5945: 97/03/28: Re: Sole source
5963: 97/03/31: Re: Sole source
5977: 97/04/01: Re: 8051 core for XC40xx
6403: 97/05/21: Re: Cheap way to develop for FPGAs?
6463: 97/05/26: Re: Fine Pitch PQFP : anyone any hassles?
6493: 97/05/28: Re: Glitches in timing simulation of Xilinx FPGAs with Synopsys
6502: 97/05/29: Re: Glitches in timing simulation of Xilinx FPGAs with Synopsys
6531: 97/05/31: Re: In circuit programming of flash with Xilinx devices??
6626: 97/06/06: Re: Fine Pitch PQFP : anyone any hassles?
6667: 97/06/11: Re: Fine Pitch PQFP : anyone any hassles?
6797: 97/06/28: Re: Any designs to avoid in FPGAs
6807: 97/06/29: Re: Any designs to avoid in FPGAs
6834: 97/07/01: Re: Any designs to avoid in FPGAs
6688: 97/06/14: Re: Power consumption (Xilinx FPGA) questions
6794: 97/06/28: Programming Xilinx 3k/4k in C ?
6943: 97/07/12: Re: Xilinx Prom Generation Problem
6962: 97/07/16: Re: Xilinx Prom Generation Problem
7007: 97/07/22: Re: PCI burst transfers
7017: 97/07/23: Re: PCI burst transfers
7019: 97/07/23: Should Xiling have more local clock nets?
7042: 97/07/26: Re: Should Xiling have more local clock nets?
7056: 97/07/28: Re: PCI burst transfers
7057: 97/07/28: Re: Should Xiling have more local clock nets?
7085: 97/07/30: Re: Should Xiling have more local clock nets?
7084: 97/07/30: Re: Should Xiling have more local clock nets?
7103: 97/07/31: Re: PCI burst transfers
7117: 97/08/01: Re: PCI burst transfers
7131: 97/08/04: Re: PCI burst transfers
7152: 97/08/07: Re: Price of Serial EEPROM is Outrageous
7384: 97/09/05: Re: A fpga DMA design ?
7496: 97/09/17: Re: AMD PAL design change
7667: 97/10/01: Re: Xilinx license idiocy
7668: 97/10/01: Re: Xilinx licensie idiocy
7693: 97/10/03: Re: Hacking bitstream formats
7704: 97/10/05: Re: Xilinx license idiocy
7705: 97/10/05: Re: Xilinx license idiocy
7700: 97/10/04: Re: bidirectional bus problem
7761: 97/10/12: Re: Looking for CUPL, PALASM, etc. source
7792: 97/10/16: Can I use M1.3 with Protel Schematic 3.2 ?
7933: 97/10/31: Anyone using Protel Schematic 3 for XILINX?
7991: 97/11/05: Re: Anyone using Protel Schematic 3 for XILINX?
8032: 97/11/10: Re: Anyone using Protel Schematic 3 for XILINX?
8005: 97/11/06: Re: Small FIFO in CPLD
8006: 97/11/06: Re: I'm interested in FPGAs. How do I start ?
8116: 97/11/19: Re: ? State Machine Design
8161: 97/11/22: Re: XACT 5.0 problem under DOS
8211: 97/11/28: Xilinx P&R - how does M1 compare to XACT6?
8215: 97/11/29: Re: FPGAs for hobbyist, HELP
8299: 97/12/06: Re: Xilinx P&R - how does M1 compare to XACT6?
8300: 97/12/06: Re: what is metastability time of a flip_flop
8306: 97/12/07: Re: what is metastability time of a flip_flop
8307: 97/12/07: Re: Xilinx P&R - how does M1 compare to XACT6?
8311: 97/12/07: Re: what is metastability time of a flip_flop
8308: 97/12/07: Re: A suggestion for Xilinx
8351: 97/12/10: Re: A suggestion for Xilinx
8422: 97/12/13: Re: dynamic power in Xilinx designs
8421: 97/12/13: Re: Z80 in FPGA: clockspeed?
8443: 97/12/15: Re: Xilinx Configuration Problem
8510: 97/12/29: Re: Xilinx XACT 2.10 memory error
8519: 98/01/03: Re: Xilinx Stock
8579: 98/01/10: Re: Xilinx Stock
8580: 98/01/10: Re: Xilinx Configuration Problem
8594: 98/01/12: Re: Xilinx Stock
8620: 98/01/14: Re: Asynchronous square root.
8657: 98/01/17: Re: Xilinx software for less than 70 bucks
8667: 98/01/19: Xilinx X3000: Does XACT6 accept the "L" or "SC=n" attribs?
8689: 98/01/20: Re: UART Spec
8765: 98/01/24: Re: Xilinx M1.4 and Viewlogic
8766: 98/01/24: Re: UART Spec
8773: 98/01/25: Xilinx X3000: Does XACT6 accept the "L" or "SC=n" attribs?
8772: 98/01/25: Re: UART Spec
8795: 98/01/27: Re: comparing asic gates with gates in FPGA's
8843: 98/02/01: Re: VHDL vs schematics
8855: 98/02/02: Re: VHDL vs schematics
8864: 98/02/02: Re: VHDL vs schematics, I vote for VHDL and this is why...
8905: 98/02/06: Re: VHDL vs schematics, I vote for VHDL and this is why...
8960: 98/02/09: Xilinx X3000: Does XACT6 accept the "L" or "SC=n" attribs?
9133: 98/02/23: Xilinx X3000: Does XACT6 accept the "L" or "SC=n" attribs?
9179: 98/02/27: Re: Xilinx Info.
9256: 98/03/05: Re: Xilinx X3000: Does XACT6 accept the "L" or "SC=n" attribs?
8876: 98/02/04: Re: FPGA/ASIC - same difference?
8886: 98/02/05: Can XACT6 run in a NT4 DOS box?
8933: 98/02/07: Re: Can XACT6 run in a NT4 DOS box?
8934: 98/02/07: Re: Asic to FPGA
8943: 98/02/08: Re: Free FPGA tools???
8944: 98/02/08: Re: Can XACT6 run in a NT4 DOS box?
8949: 98/02/08: Re: Can XACT6 run in a NT4 DOS box?
9016: 98/02/13: Re: Philips P5Z22V10 wanted
9017: 98/02/13: Re: Philips P5Z22V10 wanted
9091: 98/02/19: Re: Free FPGA tools???
9098: 98/02/20: Re: System Gates and Logic Cells...
9114: 98/02/21: Re: System Gates and Logic Cells...
9115: 98/02/21: Re: XACT6 & ORCAD IV
9169: 98/02/27: Re: DES: beginner FPGA questions.
9178: 98/02/27: Re: PLL design with Xilinx 4kseries
9180: 98/02/28: Any problems in using Pro-Series Unified Libraries in Viewlogic 4?
9265: 98/03/05: Re: The case for free operating systems and EDA
9274: 98/03/05: Re: The case for free operating systems and EDA
9312: 98/03/06: Re: The case for free operating systems and EDA
9292: 98/03/05: Re: The case for free operating systems and EDA
9313: 98/03/06: Re: The case for free operating systems and EDA
9326: 98/03/06: Re: The case for free operating systems and EDA
9239: 98/03/04: Re: Debugging question.
9240: 98/03/04: Re: Version Control for schematics?
9257: 98/03/05: Re: Help with ViewLogic 4
9264: 98/03/05: Re: Viewlogic file format for schematic symbols
9273: 98/03/05: Re: Announce - Stuart jumps ship
9372: 98/03/07: Re: Die Size Comparison of competing FPGAs
9392: 98/03/09: Re: Viewlogic file format for schematic symbols
9454: 98/03/14: Re: Strange Xilinx question?
9467: 98/03/16: Re: Xilinx XACT 6.01 crack
9471: 98/03/16: Re: Xilinx could gaurd its secrets better (Re: Strange Xilinx question?)
9543: 98/03/22: Re: Xilinx XACT 6.01 crack
9551: 98/03/23: Re: Dual port
9553: 98/03/23: USB bus interface (12 mbit/sec) in an FPGA - how difficult?
9567: 98/03/24: Re: USB bus interface (12 mbit/sec) in an FPGA - how difficult?
9580: 98/03/24: Re: Lowest POWER FPGAs???
9635: 98/03/27: Re: XactStep6 - The cure for a dongle
9647: 98/03/27: Re: XactStep6 - The cure for a dongle
9676: 98/03/30: Re: XactStep6 - The cure for a dongle
9707: 98/04/01: Re: Digital PLL's or Manual Synching?
9710: 98/04/01: Re: XactStep6 - The cure for a dongle
9728: 98/04/02: Re: XactStep6 - The cure for a dongle
9736: 98/04/02: Re: XactStep6 - The cure for a dongle
9759: 98/04/03: Re: XactStep6 - The cure for a dongle
9785: 98/04/05: Re: XactStep6 - The cure for a dongle
9800: 98/04/06: Re: XactStep6 - The cure for a dongle
9811: 98/04/07: Re: XactStep6 - The cure for a dongle
9818: 98/04/07: Re: XactStep6 - The cure for a dongle
9834: 98/04/08: Re: XactStep6 - The cure for a dongle
9893: 98/04/11: Re: XactStep6 - The cure for a dongle
9760: 98/04/03: Re: Smoking Crater in a Xilinx 3k FPGA
9784: 98/04/05: Re: Smoking Crater in a Xilinx 3k FPGA
9894: 98/04/11: Re: Smoking Crater in a Xilinx 3k FPGA
9895: 98/04/11: Re: Event counting?
9961: 98/04/17: Re: XactStep6 - The cure for a dongle
9969: 98/04/18: Re: Question about DRAM market forcasts
10023: 98/04/22: Re: Xilinx Serial Proms
10069: 98/04/25: Re: Xilinx Serial Proms
10080: 98/04/26: Re: Make a delay in Xilinx FPGAs (Help)?
10098: 98/04/27: Re: Make a delay in Xilinx FPGAs (Help)?
10116: 98/04/28: Re: Xilinx Serial Proms
10137: 98/04/29: Re: Xilinx Serial Proms
10138: 98/04/29: Re: FPGA input data rate limitations?
10175: 98/05/01: Re: Q: XILINX Foundation
10183: 98/05/02: TMS9902ANL UART in FPGA - anyone wants to do this?
10195: 98/05/03: Re: TMS9902ANL UART in FPGA - anyone wants to do this?
10196: 98/05/03: Re: Xilinx Foundation and Linux
10249: 98/05/07: Re: Xilinx Foundation and Linux
10299: 98/05/10: Re: Xilinx Foundation and Linux
10300: 98/05/10: Re: Xilinx Configuration Problem
10308: 98/05/11: Re: Low power FPGA design
10325: 98/05/12: Re: Low power FPGA design
10389: 98/05/15: Re: Minimal ALU instruction set.
10446: 98/05/19: Re: Minimal ALU instruction set.
10466: 98/05/20: Re: FPGA-based CPUs (was Re: Minimal ALU instruction set)
10585: 98/06/03: Re: Xilinx 5200 - XACT 6.0.1 vs. M1.4
10592: 98/06/03: Re: Example of 8051 codes to configure Xilinx fpga
10617: 98/06/06: Re: Example of 8051 codes to configure Xilinx fpga
10634: 98/06/08: Re: ViewDraw Info
10648: 98/06/09: Re: FPGA Conversion
10669: 98/06/10: Re: BREAKTHROUGH ASIC PRODUCT---Beta customers needed
10732: 98/06/13: Re: old PLDShell software wanted
10955: 98/07/07: Re: Configure with BIT file
10954: 98/07/07: Re: Xilinx Foundation Frustartions
10979: 98/07/08: Re: Xilinx Foundation Frustartions
11002: 98/07/09: Re: Configure with BIT file
11003: 98/07/09: Re: question on combinational logic synthesis for FPGA
11013: 98/07/10: Re: Configure with BIT file
11025: 98/07/11: Re: I need footprints for PCI & ISA (for Protel PCB)
11250: 98/07/30: Re: low power FPGAs
11404: 98/08/11: Re: Security
11528: 98/08/21: Re: Data I/O Chiplab and NT
11672: 98/08/30: Re: CPLD/FPGA software
11684: 98/08/31: Re: Digital PLL
11730: 98/09/04: Re: Digital PLL
11743: 98/09/06: Re: 22V10 programming
11834: 98/09/12: Re: Design Security Question
11984: 98/09/23: FPGA information
12045: 98/09/25: Re: Xilinx 3000 family
12046: 98/09/25: Re: Which FPGA tool is better
12186: 98/10/03: Re: Design Security Question
12191: 98/10/03: Re: FIR Filter Design
12192: 98/10/03: Re: Orcad Capture error DSM0006 and DBO3203
12349: 98/10/09: Re: Design security again - the Actel solution
12483: 98/10/13: Re: Xilinx may not support schematics for Virtex?????
12482: 98/10/13: Re: Design security again - the Actel solution
12484: 98/10/13: Re: Digital Sine Generator
12519: 98/10/14: Re: Digital Sine Generator
12743: 98/10/27: Re: New free FPGA CPU
12843: 98/11/01: Re: New free FPGA CPU
12902: 98/11/04: Re: New free FPGA CPU
13139: 98/11/17: Re: DES in VHDL
12907: 98/11/04: Re: Q: 3.3 V regulators suitable for XILINX - ?
12908: 98/11/04: Re: XILINX NODELAY Attribute
12941: 98/11/06: Re: Q: 3.3 V regulators suitable for XILINX - ?
12978: 98/11/09: Re: Q: 3.3 V regulators suitable for XILINX - ?
13137: 98/11/17: Re: Xilinx 4k programming
13138: 98/11/17: Re: Modifying Disk serial number in boot sector....anyone have any problems with it?
13140: 98/11/17: Re: newbie question about timing
13365: 98/11/30: Re: Will XILINX survive?
13366: 98/11/30: Re: Will XILINX survive?
13454: 98/12/03: Re: Will XILINX survive?
13485: 98/12/05: Re: Which parts are fastest for 3-state enables?
13486: 98/12/05: Re: Will XILINX survive?
13577: 98/12/10: Re: A short digression...
13542: 98/12/08: Re: HELP, Tool selection
13587: 98/12/10: Re: HELP, Tool selection
13607: 98/12/11: Re: HELP, Tool selection
13597: 98/12/11: Re: HELP, Tool selection
13526: 98/12/08: Re: New FPGA Brd: FPGA+PowerPC+Ethernet+TCP/IP
13543: 98/12/08: Re: The best PLD?
13640: 98/12/15: Re: Parallel Port Pass Through Specs?
13674: 98/12/17: Re: HELP, Tool selection
13675: 98/12/17: Re: Fast *Industrial* 22V10?
13723: 98/12/21: Re: Fast *Industrial* 22V10?
13740: 98/12/21: Re: Fast *Industrial* 22V10?
13741: 98/12/21: Re: Fast *Industrial* 22V10?
13761: 98/12/22: Re: Xilinx/CAST 16550 core
13784: 98/12/27: 22V10 Metastability - help please
13791: 98/12/28: Re: 22V10 Metastability - help please
13792: 98/12/28: Re: 22V10 Metastability - help please
13793: 98/12/28: Re: 22V10 Metastability - help please
13795: 98/12/28: Re: 22V10 Metastability - help please
13802: 98/12/28: Re: 22V10 Metastability - help please
13803: 98/12/28: Re: 22V10 Metastability - help please
13807: 98/12/28: Re: 22V10 Metastability - help please
13811: 98/12/28: Re: 22V10 Metastability - help please
13814: 98/12/28: Re: 22V10 Metastability - help please
13834: 98/12/29: Re: 22V10 Metastability - help please
13851: 98/12/29: Re: 22V10 Metastability - help please
13871: 98/12/30: Re: 22V10 Metastability - help please
13872: 98/12/30: Re: 22V10 Metastability - help please
13879: 98/12/31: Re: 22V10 Metastability - help please
13880: 98/12/31: Re: 22V10 Metastability - help please
13881: 98/12/31: Re: program flow chart to state machine ?
13906: 99/01/01: Re: Can a cross coupled latch "oscillate"? was Re: ..........
13913: 99/01/02: Re: Can a cross coupled latch "oscillate"? was Re: ..........
13923: 99/01/02: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
13968: 99/01/05: Re: 22V10 Metastability - my 2c
13969: 99/01/05: Re: 22V10 Metastability - help please
13970: 99/01/05: Re: 22V10 Metastability - my 2c
13985: 99/01/06: Re: 22V10 Metastability - my 2c
13986: 99/01/06: Re: 22V10 Metastability - my 2c
14010: 99/01/07: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14046: 99/01/09: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14050: 99/01/09: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14054: 99/01/10: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14208: 99/01/20: Re: I don't trust Orcad
14329: 99/01/26: Re: Hysteresis on PLD Clock Inputs
14378: 99/01/27: Re: Hysteresis on PLD Clock Inputs
14464: 99/01/30: Re: Off topic DRAM/SIMM question....
14480: 99/02/01: Re: Off topic DRAM/SIMM question....
14511: 99/02/02: Re: PLL in FPGA
14512: 99/02/02: Re: Off topic DRAM/SIMM question....
14513: 99/02/02: Re: Off topic DRAM/SIMM question....
14551: 99/02/04: Re: Off topic DRAM/SIMM question....
14690: 99/02/11: Re: Xilinx de-compiler
15366: 99/03/20: Re: Xilinx Makefile?
15055: 99/03/04: Re: Asynchronous resets: How tricky?
15138: 99/03/09: Re: Jedec programming standard?
15278: 99/03/17: Re: Power Estimiation
15439: 99/03/24: Re: Free Xilinx Vendor Tools ... NOT :-(
15523: 99/03/29: Re: Info about FPGA/PLD
15635: 99/04/05: Re: Help: Xilinx FPGA demonstration board and parallel cable iii doesn't work
15865: 99/04/17: Re: Zero power gals won't wake up on slow input transitions?
16477: 99/05/25: Re: Xilinx M1.5 Crash
17039: 99/06/27: Re: Request for information on discontinued Xilinx XC4000-series variants
17218: 99/07/09: Re: FW: Xilinx Acquisition of CoolRunners
17615: 99/08/14: Xilinx purchase of Philips CoolRunner PLDs - good or bad, any views?
17947: 99/09/18: Re: Lowest power FPGA
18434: 99/10/24: Re: Static power consumption
18653: 99/11/05: Re: Xlinx FPGA
18832: 99/11/18: Re: How many bits in an FPGA bitstream?
19077: 99/11/27: Re: implementing TCP/IP on PLD
20730: 00/02/19: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20744: 00/02/20: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20917: 00/02/28: Re: Foundation 2.1i device support?
20977: 00/03/01: Re: Philips LA PM3585 disassembler software wanted
20995: 00/03/02: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
21317: 00/03/16: Xilinx configuration current
21339: 00/03/17: Re: Xilinx configuration current
21576: 00/03/25: Re: Clock disabling
21577: 00/03/25: Anyone using Philips (now Xilinx) Coolrunner PLDs?
21600: 00/03/26: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
21732: 00/03/30: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
22182: 00/04/29: Why are there no "cheap" FPGAs?
22375: 00/05/06: Re: Why are there no "cheap" FPGAs?
22608: 00/05/13: Re: Future of FPGAs?
22685: 00/05/17: Re: SMT 7 segment display ??
22849: 00/05/27: Re: 8087 in FPGA?
23926: 00/07/15: Re: XC2018 development system xact5 or xact6 sale?
25679: 00/09/17: Re: hardware compatibility and patent infringement
25801: 00/09/20: Re: Freelance Designer Needed: Protel & FPGA
25865: 00/09/23: Re: Reassurance on Xilinx Sought
26206: 00/10/08: Re: Xilinx XC2018 Design tools
26409: 00/10/15: Re: Xilinx and CD databooks (rant)
26410: 00/10/15: Re: palasm
26595: 00/10/21: Re: CoolRunner news :(
26596: 00/10/21: Re: CoolRunner news :(
26692: 00/10/25: Re: CoolRunner news :(
26693: 00/10/25: Re: RS422 interfacing to a FPGA ?
26737: 00/10/26: Re: Fpga vs. ASIC
26762: 00/10/27: Re: Fpga vs. ASIC
26776: 00/10/28: Re: CoolRunner news :(
26795: 00/10/29: Re: CoolRunner news :(
27693: 00/12/03: Re: Xilinx Coolrunner going on last time buy?
27980: 00/12/18: Re: Is it necessary to synchronize the reset signal in an FPGA ?
28923: 01/01/29: Re: Encryption is supported in new Virtex II but.....
29045: 01/02/03: Re: Encryption is supported in new Virtex II but.....
30959: 01/05/04: Re: C++ To Gates
30960: 01/05/04: Re: Serial UART
31463: 01/05/25: Re: Xilinx Coolrunner 100% routable - but the tools aren't
35655: 01/10/12: Re: future Xilinx products wish list ...
35902: 01/10/23: Are there any Coolrunner P5Z22V10 (PLCC) devices left anywhere?
35916: 01/10/23: P5Z22V10 - any left anywhere?
36094: 01/10/29: Re: Are there any Coolrunner P5Z22V10 (PLCC) devices left anywhere?
36194: 01/11/01: Help with a 1996 XC3064 design!!
36266: 01/11/04: Re: Help with a 1996 XC3064 design!!
43413: 02/05/21: Altera FPGA (EPM7256AETC100-5) programming
46533: 02/09/02: Re: Hardware Code Morphing?
48212: 02/10/14: A nice one-off project for a competent UK based FPGA designer :)
48255: 02/10/15: Re: A nice one-off project for a competent UK based FPGA designer :)
61819: 03/10/13: Please Help: Looking for XC3064 PLCC-84...
76816: 04/12/13: Re: PLLs on biphase mark signals
76862: 04/12/14: Re: Xilinx speed grading
76864: 04/12/14: Re: Cylone Problem with Large Shift Register
76867: 04/12/14: Re: altera cyclone and fifo synchronisation
76899: 04/12/15: Re: Cylone Problem with Large Shift Register
76916: 04/12/15: Re: Digital clock synthesis
76918: 04/12/15: Re: Xilinx FIFO
76919: 04/12/15: Re: Xilinx speed grading
76925: 04/12/15: Re: Xilinx FIFO
76958: 04/12/16: Re: Xilinx FIFO
77032: 04/12/20: Re: altera cyclone and fifo synchronisation
77065: 04/12/21: Re: Clock Synchronization
77084: 04/12/22: Protel/Nexar DXP 2004 SP2 Released with TSK3000A 32-bit RISC Processor
77911: 05/01/20: Re: C programmer, what does this syntax mean?
77975: 05/01/21: Re: C programmer, what does this syntax mean?
83143: 05/04/24: Executing program from external memory
94963: 06/01/19: V4 not packing registers into IOBs
95449: 06/01/23: Re: V4 not packing registers into IOBs
104929: 06/07/10: Any *really old* Viewlogic / Xilinx users around here? :)
130271: 08/03/19: Re: Optimizing an inferred counter
137955: 09/02/03: Re: Dangling blockram output - how to remove warning?
140915: 09/05/29: Urgent help with a Simple AND simulation
140939: 09/05/30: Re: Urgent help with a Simple AND simulation
140940: 09/05/30: Re: Urgent help with a Simple AND simulation
146504: 10/03/21: Finally, selling my old Xilinx/Viewlogic software package
146519: 10/03/21: Re: Finally, selling my old Xilinx/Viewlogic software package
146533: 10/03/22: Re: Finally, selling my old Xilinx/Viewlogic software package
146536: 10/03/22: Re: Finally, selling my old Xilinx/Viewlogic software package
146546: 10/03/22: Re: Finally, selling my old Xilinx/Viewlogic software package
146565: 10/03/23: Re: Finally, selling my old Xilinx/Viewlogic software package
146594: 10/03/23: Re: Finally, selling my old Xilinx/Viewlogic software package
146620: 10/03/24: Re: Finally, selling my old Xilinx/Viewlogic software package
146623: 10/03/24: Re: Finally, selling my old Xilinx/Viewlogic software package
146634: 10/03/24: Re: Finally, selling my old Xilinx/Viewlogic software package
146691: 10/03/26: Re: USB 3.0 implementation on FPGA
146765: 10/03/28: Re: Finally, selling my old Xilinx/Viewlogic software package
146940: 10/04/03: Re: Finally, selling my old Xilinx/Viewlogic software package
147203: 10/04/18: Finally, selling my old Xilinx/Viewlogic software package
Peter (Peter):
18536: 99/10/29: Re: FPGA Timing Problem
Peter - one extra v to stop junk mail:
4474: 96/11/03: Re: VHDL for Xilinx designs?
4475: 96/11/03: Re: XACT under WinNT is very slow
Peter =?iso-8859-1?Q?S=F8rensen?=:
16229: 99/05/11: Re: Counters
16373: 99/05/19: Re: flex10k 1 gate change
16398: 99/05/20: Re: flex10k 1 gate change
16371: 99/05/19: Re: Dual Port mem
16375: 99/05/19: Re: DSP in FPGA
16374: 99/05/19: Re: Fpga gates, PLD gates ASIC gates: Help us please.
16376: 99/05/19: Re: FPGA, PLD, EPLD, CPLD differences
16377: 99/05/19: Re: Is schmitt trigger possible with Xilinx 9536?
16397: 99/05/20: Re: Is schmitt trigger possible with Xilinx 9536?
16396: 99/05/20: Re: Is schmitt trigger possible with Xilinx 9536?
16881: 99/06/16: Re: Digital filters in VHDL
16891: 99/06/16: Re: Altera EPC1 replacement?
16892: 99/06/16: Re: newbie -- What's the best way to get started?
16893: 99/06/16: Re: Altera/Synplicity TIMESTAMP?
Peter A Dudley:
15553: 99/03/30: Re: FPGAs with ECL-compatible I/Os
19366: 99/12/16: Virtex Configuration Trouble
19370: 99/12/16: Re: Virtex Configuration Trouble
19649: 00/01/06: Re: BGA sockets and Virtex
Peter Alfke:
1917: 95/09/19: Re: Fast FPGA's? (No XILINX PREP data)
1991: 95/09/29: Re: Xilinx Flash FPGA ??
2032: 95/10/04: Re: Generic use of Serial Configuration EPROMs
2214: 95/11/02: Re: Xilinx XSI FPGA User Guide
2253: 95/11/10: Re: Can X30xx Reset itself?
2488: 95/12/16: Re: Gated Clock Problem in Xilinx FPGA Implementation
2702: 96/01/25: Re: HowTo access a SRAM with a XC4000
2819: 96/02/12: Re: Help: Xilinx behavior if Power down
2852: 96/02/16: Re: Xilinx is NOT specified MINIMUM delay -
2863: 96/02/19: Re: Xilinx is NOT specified MINIMUM delay -
2866: 96/02/20: Re: Lowest power FPGA or PLD
2874: 96/02/21: Re: Xilinx is NOT specified MINIMUM delay -
2907: 96/02/27: Re: Xilinx is NOT specified MINIMUM delay -
2930: 96/03/01: Re: Comp.Arch.FPGA
2931: 96/03/01: Re: ORCA and 3.3V logic
2946: 96/03/04: Re: Xilinx is NOT specified MINIMUM delay -
2947: 96/03/05: Re: ORCA and 3.3V logic
2962: 96/03/05: Re: [NEWBIE] FPGA Project?
2973: 96/03/07: Re: [NEWBIE] FPGA Project?
2992: 96/03/09: Re: actel act2 ta161 library element
3114: 96/04/04: Re: XACT5.2 bit file length count changes
3117: 96/04/05: Re: XACT5.2 bit file length count changes
3167: 96/04/17: Re: What's the lowest-priced FPGA?
3179: 96/04/19: Re: ECL, PECL gate arrays or FPGA's
3197: 96/04/23: Re: The problem with ECL (was Re: ECL, PECL gate arrays or FPGA's)
3210: 96/04/26: Re: run time reconfiguration
3226: 96/04/29: Re: FPGA leaders - Who are they? Xilinx, Altera, Actel?
3247: 96/05/03: Re: How to use the notplace constrain in Xilinx chip?
3276: 96/05/08: Re: Is XC7336 the least expensive CPLD?
3279: 96/05/08: Re: Implementation of a ROM
3280: 96/05/08: Re: Is XC7336 the least expensive CPLD?
3301: 96/05/10: Re: Is XC7336 the least expensive CPLD?
3322: 96/05/13: Re: Looking for free FPGA softw./Xilinx
3338: 96/05/15: Re: Looking for free FPGA softw./Xilinx
3388: 96/05/23: Re: Xilinx and Viewlogic
3399: 96/05/24: Re: Evolvable HW
3423: 96/05/28: Re: WEIRD NOISE PROBLEM WITH XILINX XC3064 - can anyone help?
3433: 96/05/30: Re: WEIRD NOISE PROBLEM WITH XILINX XC3064 - can anyone help?
3461: 96/06/03: Re: Xilinxs FPGAs (newbies)
3463: 96/06/03: Re: WEIRD NOISE PROBLEM WITH XILINX XC3064 - can anyone help?
3475: 96/06/05: Re: FPGA Companies
3506: 96/06/11: Re: UART for Actel FPGA
3513: 96/06/12: Re: Xtal Osc. at XC31xxA
3533: 96/06/16: Re: UART for Actel FPGA
3567: 96/06/25: Re: Atmel AT17C65/128/256 Serial EEPROM Memories.
3573: 96/06/27: Re: XC3100A Tristates
3742: 96/07/23: Re: Designing Dual Port RAM with 4000 series.
3746: 96/07/24: Re: Hardware sort?
3780: 96/07/30: Re: Question: FPGA versus ASIC design.
3799: 96/08/03: Re: Question about books for FPGA
3816: 96/08/06: Re: Question about books for FPGA
3845: 96/08/08: Re: Xilinx clock doubler?
3830: 96/08/07: Re: "Xilinx nixes its antifuse arrays"
3914: 96/08/19: Re: Xilinx: question about bitstream and parallel download
3917: 96/08/19: Re: Xilinx Product Strategy
3929: 96/08/21: Re: XC6200 FPGAs
3942: 96/08/23: Re: xilinx programing
3969: 96/08/26: Re: XC4010E en downloading bitstream
4020: 96/09/03: Re: *** FREE INTERNET! *** Forever!
4071: 96/09/07: 256K EEPROM
4087: 96/09/09: Re: FPGA design project
4099: 96/09/10: Re: ..people NOT using Xilinx
4142: 96/09/17: Re: manchester clock recovery
4148: 96/09/18: Re: Inaccrate Xilinx simulations ???
4155: 96/09/19: Re: manchester clock recovery
4165: 96/09/20: Re: manchester clock recovery
4184: 96/09/23: Re: manchester clock recovery
4201: 96/09/25: Re: How to Begin with FPGA design?
4207: 96/09/26: Re: XilinX XC5200 address pointer based FIFO
4209: 96/09/26: Re: 4800 baud serial input to xc4000
4298: 96/10/11: Serial EEPROM problem
4384: 96/10/22: Re: What are I/O's doing prior to configuration?
4471: 96/11/01: Re: What is the fastest fpga for ...
4478: 96/11/03: Re: What is the fastest fpga for ...
4493: 96/11/05: Re: UART FOR FPGAS
4507: 96/11/06: Re: Info on FPGA Internal Architecture/ Programming
4525: 96/11/08: Re: Info on FPGA Internal Architecture/ Programming
4528: 96/11/08: Re: Info on FPGA Internal Architecture/ Programming
4637: 96/11/24: Re: Digital PLL or Sample Rate Multiplier
4643: 96/11/25: Re: FPGA Gate Counts: No Truth in Advertising
4755: 96/12/11: Re: Xilinx configuration PROM
4765: 96/12/12: Re: XC4010E configuration problem.
4766: 96/12/12: Re: Fpga, Epld, cpld....
4819: 96/12/17: Re: FPGA market overview
4898: 96/12/26: Re: Proper target for design
4899: 96/12/26: Re: Integer divide IC
4986: 97/01/08: Re: Oscillator with PLD's or FPGA's
5122: 97/01/24: Re: Question: XC4013E configuration in async. periph. mode
5137: 97/01/26: Re: Processorless FPGA computer help
5169: 97/01/28: Re: FPGA power dissipation
5184: 97/01/29: Re: Synthesizing fast counter (carry look ahead adder)
5202: 97/01/30: Re: Reconfigurable Logic Query
5318: 97/02/06: Re: Embedded SRAM in FPGAs
5372: 97/02/11: Re: Random Number Generators with Xilinx FPGA xc4000 series
5399: 97/02/13: Re: Inversion 1/T with registers
5442: 97/02/16: Re: HELP: XC4000 download cable
5455: 97/02/17: Re: [Q].FIFO in FPGA XILINX
5457: 97/02/17: Re: HELP: XC4000 download cable
5465: 97/02/18: Re: Implementing Phase Comparator in XC7354
5466: 97/02/18: Re: Xilinx or Altera?
5471: 97/02/18: Re: Xilinx or Altera?
5484: 97/02/19: Re: What kind of functions mostly implemented using FPGAs?
5500: 97/02/20: Re: 2nd try: What kind of functions mostly implemented using FPGAs?
5519: 97/02/21: Re: Reverse Engineering FPGAs
5540: 97/02/23: Re: 2nd try: What kind of functions mostly implemented using FPGAs?
5566: 97/02/24: Re: Xilinx or Altera?
5587: 97/02/26: Re: Slew-rate control feature in XC4000E
5610: 97/02/28: Re: Cypress says good-bye to Anti-Fuse
5611: 97/02/28: Re: Xilinx or Altera?
5680: 97/03/06: Re: What is the different between FPGA and CPLD?
5725: 97/03/10: Re: Xilinx FPGA & SIMMs
5745: 97/03/11: Re: Xil FPGA: Usage of Multi-purpose pins as I/O
5752: 97/03/12: Re: FPGA Reliability
5789: 97/03/14: Re: Xilinx 4002 RAM Question
5802: 97/03/16: Re: ACTEL RAM BASED FPGAs
5811: 97/03/17: Re: pld 74hc195 equiv
5833: 97/03/19: Re: FCCM'97 Preliminary Program
5835: 97/03/19: Re: FCCM'97 Preliminary Program
5836: 97/03/19: Re: Multiple clocks in Xilinx
5837: 97/03/19: Re: Sole source
5857: 97/03/20: Re: Is this really possible?
5877: 97/03/21: Re: FIFOs
5878: 97/03/21: Re: Sole source
5891: 97/03/23: Re: FIFOs
5892: 97/03/23: Re: problem: my xc4003 don't work !!!!
5898: 97/03/24: Re: Sole source
5918: 97/03/26: Re: Xilinx 4013 cannot configuration
5934: 97/03/27: Re: Xilinx 4013 cannot configuration
5960: 97/03/31: Re: fast resampling
5961: 97/03/31: Re: Sole source
6009: 97/04/04: Re: Sole source
5998: 97/04/03: Re: XC2018
6022: 97/04/05: Re: Vendors (Xilinx, Cypress) leaving antifuse market
6073: 97/04/09: Re: prep benchmarks for FPGAs
6074: 97/04/09: Re: fpga technologies and Iddq testing
6083: 97/04/10: Re: Chip Temperature (was:Re: Sole source)
6128: 97/04/14: Re: PCI Bus Problems
6203: 97/04/25: Re: prep benchmarks for FPGAs
6213: 97/04/28: Re: XC52xx and Hardware Debugger
6224: 97/04/29: Re: 1 or 2 flip-flops to synchronise an async.
6229: 97/04/30: XC6200 plentifully available
6101: 97/04/11: Re: prep benchmarks for FPGAs
6344: 97/05/16: Re: Low power PLD?
6251: 97/05/02: Re: Schmitt trigger inputs?
6273: 97/05/07: Re: [Help] Buggy LFSR in Xilinx Application notes???
6314: 97/05/14: Re: Anyone using Actel software?
6332: 97/05/15: Re: Wide edged decoders in Xilinx XC4000 series!
6346: 97/05/16: Xilinx Seminar Series
6355: 97/05/17: Re: Fast comparator
6776: 97/06/26: Re: Asynchronous Peripheral Download Mode, Probs
6787: 97/06/27: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
6818: 97/06/30: Re: Asynchronous Peripheral Download Mode, Probs
6860: 97/07/02: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
6981: 97/07/18: Re: Generating Sine/Cosine digitally
7022: 97/07/23: Re: Why fast message delete in this group?
7029: 97/07/24: Re: Xilinx Prom Generation Problem
7052: 97/07/27: Re: FPGA die photograph
7159: 97/08/07: Re: Incremental changes of FPGA's possibel ?
7225: 97/08/15: Re: FPGA power consumption
7230: 97/08/16: Re: Price of Serial EEPROM is Outrageous
7241: 97/08/18: Re: Price of Serial EEPROM is Outrageous
7261: 97/08/19: Re: Xilinx & Altera using same configuration lines?
7369: 97/09/03: Re: Flexible tools and FIFOs
7350: 97/08/29: Re: Flexible tools and FIFOs
7406: 97/09/07: Re: Which FPGA ?
7407: 97/09/07: Re: University FPGA Project
7415: 97/09/08: Re: HELP: FIFO's on an FPGA
7422: 97/09/09: Re: HELP: FIFO's on an FPGA
7470: 97/09/15: Re: Large FPGA
7475: 97/09/15: Re: HELP: FIFO's on an FPGA
7495: 97/09/17: Re: Can 3.3v Xilinx drive CMOS?
7529: 97/09/19: Re: Atmel 17256 serial config EEPROMs
7627: 97/09/29: Re: AMD TAXI
7644: 97/09/30: Re: Problem using FAST config mode with X4kE part?
7664: 97/10/01: Re: Problem using FAST config mode with X4kE part?
7698: 97/10/03: Re: bidirectional bus problem
7710: 97/10/06: Re: bidirectional bus problem
7735: 97/10/08: Re: bidirectional bus problem
7893: 97/10/27: Re: Counter Problem
7894: 97/10/27: Re: XILINX pin compatible replacements
7959: 97/11/03: Re: Pin compatible
7954: 97/11/02: Re: 'compatible' fpgas
8103: 97/11/17: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
8104: 97/11/17: Re: What is the difference between CPLD and FPGA ?
8110: 97/11/18: Re: Register Intensive Designs and Dynamically Reconfigurable FPGAs
8139: 97/11/20: Re: Study guide for metastability
8240: 97/12/02: Re: what is metastability time of a flip_flop
8275: 97/12/04: Re: what is metastability time of a flip_flop
8406: 97/12/12: Re: what is metastability time of a flip_flop
8259: 97/12/03: Re: Whatever happened to PREP?
8289: 97/12/05: Re: A suggestion for Xilinx
8304: 97/12/06: Re: A suggestion for Xilinx
8344: 97/12/09: Re: I looked up Altera in an Italian dictionary.....
8431: 97/12/14: Re: combinational multipliers
8433: 97/12/14: Re: Xilinx Configuration Problem
8434: 97/12/14: Re: dynamic power in Xilinx designs
8445: 97/12/15: Re: parallel counters: which device is suitable?
8477: 97/12/19: Re: md5 in a FPGA?
8489: 97/12/22: Re: Schmitt Trigger on ISP
8577: 98/01/10: Re: Xilinx Configuration Problem
8524: 98/01/04: Re: Interfacing 3.3V FPGA with ISA bus
8534: 98/01/06: Re: Newbe to fpga
8553: 98/01/08: Re: seeking example for PWM using PLDs
8555: 98/01/08: Re: simple FPGA project for somebody...
8568: 98/01/09: Re: serial conf. PROMS
8628: 98/01/14: Re: Xilinx 4000E Series Ram Problem
8650: 98/01/16: Xilinx software for less than 70 bucks
8743: 98/01/23: Re: DSP vs FPGA
8779: 98/01/26: Re: High Voltage on xilinx FPGA/CPLD pins
8807: 98/01/27: Re: Opinions wanted on PLD selection
8808: 98/01/27: Re: Divide by N counter with Altera:7064/7096
8860: 98/02/02: Re: FPGA/ASIC - same difference?
8909: 98/02/06: Re: Asic to FPGA
8913: 98/02/06: Re: Power consumption
9010: 98/02/13: Re: Why altera CPLDS are slow to power-up?
9015: 98/02/13: Re: Why altera CPLDS are slow to power-up?
9049: 98/02/17: Re: Why altera CPLDS are slow to power-up?
9050: 98/02/17: Re: Xilinx download cable ??????
9082: 98/02/18: Re: Free FPGA tools???
9083: 98/02/18: Re: Why altera CPLDS are slow to power-up?
9086: 98/02/18: Re: System Gates and Logic Cells...
9094: 98/02/19: Re: Atmel SPROMs for Xilinx
9105: 98/02/20: Re: System Gates and Logic Cells...
9130: 98/02/23: Re: Atmel SPROMs for Xilinx
9155: 98/02/25: Re: PLL design with Xilinx 4kseries
9229: 98/03/03: Re: Die Size Comparison of competing FPGAs
9474: 98/03/16: Re: Strange Xilinx question?
9484: 98/03/17: Re: Strange Xilinx question?
9507: 98/03/19: Re: Strange Xilinx question?
9508: 98/03/19: Re: Strange Xilinx question?
9547: 98/03/22: Re: Dual port
9436: 98/03/13: Re: Strange Xilinx question?
9739: 98/04/02: Re: fifo
9742: 98/04/02: Re: One time programmables
9756: 98/04/03: Re: Choosing the right tools and company....
9790: 98/04/05: Re: One time programmables
9791: 98/04/05: Re: Counter problem ?
9822: 98/04/07: Re: Xilinx routing optimization?
9836: 98/04/08: Re: FLEX 10K : FPGA or CPLD
9879: 98/04/10: Re: Xilinx XC9500 series -- software?
9881: 98/04/10: Re: Xilinx XC9500 series -- software?
9904: 98/04/12: Re: Xilinx routing optimization?
9905: 98/04/12: Re: Event counting?
9966: 98/04/17: Verilog to VHDL or VHDL to Verilog
9992: 98/04/21: Re: Xilinx FPGAs: Usable Pins on XS Boards (Help)
9993: 98/04/21: Re: Could you help me save CLB's?
10053: 98/04/24: Re: XC4000XL and Ground Bouncing
10062: 98/04/24: Re: How low can they go?
10127: 98/04/28: Re: FPGA input data rate limitations?
10229: 98/05/05: Re: 3.3V design conversion
10255: 98/05/07: Re: Low power FPGA design
10283: 98/05/09: Re: Low power FPGA design
10296: 98/05/10: Re: Xilinx Configuration Problem
10474: 98/05/20: Re: Building signal delays inside an FPGA
10475: 98/05/20: Re: Building signal delays inside an FPGA
10480: 98/05/21: Re: Xilinx FPGA Configuration Problem
10528: 98/05/27: Re: Xilinx BootProm ignores everything
10627: 98/06/06: Re: Evolutionary FPGAs
10572: 98/06/01: Xilinx BootProm does not ignore everything
10658: 98/06/09: Re: Multipliers on FPGA's
10726: 98/06/12: Re: Xilinx 4000/Spartan: Maximum pin pullup
10745: 98/06/15: Re: Fastest and biggest FPGA fast and big enough?
10794: 98/06/19: Re: 62.5MHz 128x17Bit Dualport-Fifo in Xilinx
10816: 98/06/22: Re: Getting into using FPGAs
10840: 98/06/24: Re: How to Double Clk Freq in the FPGA design
10873: 98/06/26: Re: Xilinx Foundation simulator problem?
10885: 98/06/27: Re: How to Double Clk Freq in the FPGA design
10924: 98/07/01: Re: Power consumption question
11377: 98/08/07: Re: Delay Element for async design.
11392: 98/08/09: Re: Gray code counter in ABEL HDL?
11399: 98/08/10: Re: Gray code counter in ABEL HDL?
11400: 98/08/10: Re: Security
11502: 98/08/19: Re: Manchester decoding
11664: 98/08/29: Re: FPGA Manufacturer's gate counts
13413: 98/12/01: Re: Will XILINX survive?
13457: 98/12/03: Re: Will XILINX survive?
13461: 98/12/03: Re: Will XILINX survive?
13464: 98/12/03: Re: Which parts are fastest for 3-state enables?
13522: 98/12/07: Re: HELP, Tool selection
13428: 98/12/02: Re: XILINX FPGA reaches GHz speeds
13431: 98/12/02: Re: Minimum clock freq reqd
13503: 98/12/06: Re: CPLD with extended temperature (almost mil temp range)
13651: 98/12/16: Re: Fast *Industrial* 22V10?
13657: 98/12/16: Re: Samples of Xilinx Virtex XVC300+?
13661: 98/12/16: Re: Fast *Industrial* 22V10?
13676: 98/12/17: Re: Fast *Industrial* 22V10?
13678: 98/12/17: Re: Fast *Industrial* 22V10?
13697: 98/12/18: Re: Fast *Industrial* 22V10?
13704: 98/12/18: Re: Async Fifo Core or Macro for Xilinx FPGA
13733: 98/12/21: Re: Fast *Industrial* 22V10?
13734: 98/12/21: Re: Async Fifo Core or Macro for Xilinx FPGA
13812: 98/12/28: Re: 22V10 Metastability - help please
13817: 98/12/28: Re: 22V10 Metastability - help please
13821: 98/12/28: Re: 22V10 Metastability - help please
13822: 98/12/28: Re: 22V10 Metastability - help please
13842: 98/12/29: Re: 22V10 Metastability - help please
13845: 98/12/29: Re: 22V10 Metastability - help please
13846: 98/12/29: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
13856: 98/12/29: Re: 22V10 Metastability - help please
13894: 98/12/31: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
13895: 98/12/31: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
13963: 99/01/05: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
13967: 99/01/05: Re: 22V10 Metastability - help please
14058: 99/01/10: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14071: 99/01/11: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10
14072: 99/01/11: Re: Glitchless Logic, hazards, and Metastability - Was Re: 22V10 Metastability - help please
14216: 99/01/20: Re: PLL in FPGAs?
13994: 99/01/06: Re: which FPGA to choose ?
14041: 99/01/08: Re: Field Applications Engineers: ASIC/Field Programable Gate Arrays
14069: 99/01/11: Re: Non-standard use of I/O blocks
14187: 99/01/18: Re: Xilinx Bitstream
14250: 99/01/21: Re: Q: Counting GHz pulses - ?
14303: 99/01/24: Re: PLL in FPGA
14315: 99/01/25: Re: Xilinx flip flops hold time
14347: 99/01/26: Re: Hysteresis on PLD Clock Inputs
14351: 99/01/26: Re: Xilinx - Questions on clock & Async delays.
14374: 99/01/27: Re: Hysteresis on PLD Clock Inputs
14446: 99/01/29: Re: Help for the scientifically-challenged
14475: 99/01/31: Re: Worst service in India by Xilinx
14516: 99/02/02: Re: PLL in FPGA
14637: 99/02/07: Re: dual port RAM on XC4000
14650: 99/02/08: Re: dual port RAM on XC4000
14662: 99/02/09: Re: dual port RAM on XC4000
14724: 99/02/12: Re: Very Long Write Enable in Xilinx Dual Port RAMs
14797: 99/02/17: Re: Digital PLL
14925: 99/02/25: Re: Where do I connect my reset pins to?
15024: 99/03/03: Re: experience with Xilinx 4K series I/Os
15025: 99/03/03: Re: Clock divider
15027: 99/03/03: Re: Asynchronous resets: How tricky?
15035: 99/03/03: Re: Clock divider: 100MHz->40MHz
15037: 99/03/03: Re: Clock divider: 100MHz->40MHz
15044: 99/03/03: Re: Asynchronous resets: How tricky?
15062: 99/03/04: Re: Clock divider: 100MHz->40MHz
15091: 99/03/05: Re: Can multiple FPGA share same SPROM for configuration?
15123: 99/03/08: Re: Manchester Decoder VHDL Model
15142: 99/03/09: Re: Spartan Configuration
15143: 99/03/09: Re: Startup issues with 24c04 eeprom and I2C interface
15146: 99/03/09: Re: Function generator in Xilinx
15164: 99/03/10: Re: LUT
15168: 99/03/10: Infidels Invited, Heathens Highly Welcome !
15187: 99/03/11: Re: Infidels Invited, Heathens Highly Welcome !
15195: 99/03/12: Re: Infidels Invited, Heathens Highly Welcome !
15198: 99/03/12: Re: Function generator in Xilinx
15197: 99/03/12: Re: Function generator in Xilinx
15196: 99/03/12: Re: Function generator in Xilinx
15200: 99/03/12: Re: Spartan, delaying a clock.
15201: 99/03/12: Re: Spartan, delaying a clock.
15226: 99/03/15: Re: Possible problem with die shrink of xc4010
15257: 99/03/16: Re: Power Estimiation
15262: 99/03/16: Re: Power Estimiation
15297: 99/03/17: Re: Power Estimiation
15296: 99/03/17: Re: Xilinx Spartan configuration troubles
15456: 99/03/24: Re: Info about FPGA/PLD
15479: 99/03/25: Re: Free Xilinx Vendor Tools ... NOT :-(
15534: 99/03/29: Re: virtex partial reconfiguration
15536: 99/03/29: Re: Info about FPGA/PLD
15537: 99/03/29: Re: Free Xilinx Vendor Tools ... NOT :-(
15552: 99/03/30: Re: virtex partial reconfiguration
15564: 99/03/30: Re: Info about FPGA/PLD
15655: 99/04/06: Re: FIFO
15654: 99/04/06: Re: FIFO
15679: 99/04/07: Re: Help: FPGA for voltage working range 3...6 V
15711: 99/04/09: Re: Levels of logic
15718: 99/04/09: Re: Illegal States in 1 Hot State Machines
15712: 99/04/09: Re: Illegal States in 1 Hot State Machines
15756: 99/04/12: Re: Does any one want to talk about Dynamic Configuration?
15754: 99/04/12: Re: Programming a long daisy-chain Xilinx 4000
15791: 99/04/14: Re: Obsolete Xilinx series - how to use them?
16213: 99/05/10: Re: Spartan Metastability parameters
16214: 99/05/10: Re: Spartan Metastability parameters
16266: 99/05/12: Re: Spartan Metastability parameters
16238: 99/05/11: Re: Synchronizer design?
16242: 99/05/11: Re: Synchronizer design?
16246: 99/05/11: Re: Synchronizer design?
16285: 99/05/13: Re: Synchronizer design?
16308: 99/05/14: Re: Who do you know? Motorola FPGA
16309: 99/05/14: Re: Who do you know? Motorola FPGA
16340: 99/05/17: Re: Synchronizer design?
16383: 99/05/19: Re: Is schmitt trigger possible with Xilinx 9536?
16780: 99/06/08: Re: Q: Spartan XL pull-ups
16782: 99/06/08: Re: LINE DELAYS USING RAMS
16792: 99/06/08: Re: LINE DELAYS USING RAMS
16806: 99/06/09: Re: Q: Spartan XL pull-ups
16814: 99/06/10: Re: Q: Spartan XL pull-ups
16871: 99/06/15: Re: Problems programming Xilinx FPGAs
16981: 99/06/21: Re: Request for information on discontinued Xilinx XC4000-series
17051: 99/06/28: Re: Request for information on discontinued Xilinx XC4000-series
17075: 99/06/29: Re: Read/Writes to memories/register files for PIC core
17105: 99/06/30: Re: FW: Xilinx Acquisition of CoolRunners
17124: 99/07/01: Re: FW: Xilinx Acquisition of CoolRunners
17141: 99/07/02: Re: FW: Xilinx Acquisition of CoolRunners
17183: 99/07/07: Re: Floating point on fpga, Counters?
17294: 99/07/19: Re: Frequency multiplier in XC4000
17301: 99/07/19: Re: Frequency multiplier in XC4000
17313: 99/07/20: Re: Frequency multiplier in XC4000
17419: 99/07/26: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
17431: 99/07/27: Re: NRZ Deserializing in Virtex
17450: 99/07/28: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
17462: 99/07/29: Re: Xilinx Virtex Block Select RAM, is is reg or flow thru output
17501: 99/08/02: Re: Xilinx Readback Problems
17532: 99/08/06: Re: carry logic for implementing wide logic functions
17599: 99/08/12: Re: looking for info on programing XILINX 4000 series
17587: 99/08/11: Re: Clock multiplexing
17588: 99/08/11: Re: Clock multiplexing
17981: 99/09/20: Re: Programming Spartan XL
18124: 99/10/01: Re: Implementing a LFSH in Xilinx XC9500 series
18148: 99/10/03: Re: Reconfigurable FPGAs-- A query on this..
18206: 99/10/07: Re: Virtex and PCI 5V?
18475: 99/10/26: Re: Xilinx BGA pinout issue.....
18598: 99/11/02: Re: Input metastability
18641: 99/11/04: Re: High Speed Enough!?
18749: 99/11/11: Re: fast programmable divider using xilinx xc4002xl
18773: 99/11/13: Re: How many bits in an FPGA bitstream?
19165: 99/12/02: Re: Tristate bidirectional pads with Xilinx
19255: 99/12/08: Re: TIme Delay 1us-100ms
19358: 99/12/15: Re: Speed grade
19384: 99/12/17: Re: Speed grade
19567: 99/12/31: Re: Design security
19619: 00/01/04: Re: M1 timings
19683: 00/01/07: Re: Disable clockbuffer for only a single flip-flop
19739: 00/01/10: Re: On chip Oscillator
19741: 00/01/10: Re: Virtex Temperature Sensing diode pins DXP, DXN
19799: 00/01/12: Re: 100 MHz counters
19800: 00/01/12: Re: Design security
19807: 00/01/12: Re: Xilinx Spartan2
19841: 00/01/13: Re: Reliability of programming SRAM FPGAs
19870: 00/01/14: Re: Xilinx Spartan2
19873: 00/01/14: Re: Xilinx Spartan2
19975: 00/01/20: Re: looping FIFO?
20014: 00/01/24: Re: Biphase mark decoder
20032: 00/01/24: Re: Xilinx vs. other FPGAs manufactrers
20053: 00/01/25: Re: Atmel config PROMs
20122: 00/01/27: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20127: 00/01/27: Re: ADC to DSP... FIFO?
20132: 00/01/28: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20151: 00/01/28: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20157: 00/01/28: Re: ADC to DSP... FIFO?
20205: 00/01/31: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20254: 00/02/02: Re: Count 1's algorithm...
20266: 00/02/03: Re: Count 1's algorithm...
20155: 00/01/28: Re: ADC to DSP... FIFO?
20395: 00/02/08: Re: Spartan II availability and pricing
20400: 00/02/08: Re: Spartan II availability and pricing
20443: 00/02/10: Re: Spartan and timing analyzer: clock nets using non-dedicated
20450: 00/02/10: Re: Spartan and timing analyzer: clock nets using non-dedicated
20499: 00/02/11: Re: Master/Serial mode for Virtex
20515: 00/02/13: Re: xilinx
20530: 00/02/14: Re: xilinx
20598: 00/02/15: Re: Virtex size: Row,Col or Col,Row ?
20630: 00/02/16: Re: Xilinx Virtex Reset
20648: 00/02/16: Re: Xilinx hold time problems...
20647: 00/02/16: Re: Choosing the correct size FPGA
20721: 00/02/18: Re: Predictable Delays of Altera's Fast Interconnect for DLL/PLL
20725: 00/02/19: Re: Xilinx 9500 CPLD
20726: 00/02/19: Re: Generating a Higher Frequency Clock from a Lower One in FPGA
20743: 00/02/20: Re: x18 FIFO's in Virtex
20753: 00/02/20: Re: Viewlogic 4 and XACT6.1 - any good for XC4k ??
20804: 00/02/23: Re: Help!!!
20805: 00/02/23: Re: Bit Serial Arithmetic De-mystified
20877: 00/02/24: Re: Design security
20924: 00/02/28: Re: atmel fpga starter kit
20942: 00/02/29: Re: Delay Lines using FPGA ??
20980: 00/03/02: Re: Virtex loading question
20996: 00/03/02: Re: ORCA 3T - input/output delay reduction?
21007: 00/03/02: Re: New name: DLLs, PLLs and videotape...
21082: 00/03/06: Re: New name: DLLs, PLLs and videotape...
21111: 00/03/07: Re: New name: DLLs, PLLs and videotape...
21134: 00/03/07: Re: setup and hold times for data during configuration (Xilinx Virtex
21154: 00/03/08: Re: antifuse fpga's replacing xilinx
21163: 00/03/08: Re: antifuse fpga's replacing xilinx
21194: 00/03/09: Re: SpartanXL route and place
21196: 00/03/09: Re: SpartanXL route & place, Corrected
21261: 00/03/14: Re: Virtex IOB T register
21262: 00/03/14: Re: Virtex IOB T register
21270: 00/03/14: Re: Programming FPGAs via backplane (Xilinx)
21275: 00/03/14: Re: Atmel censors web access
21298: 00/03/15: Re: Difference between FPGA, PLD, CPLD ?
21303: 00/03/16: Re: Difference between FPGA, PLD, CPLD ?
21307: 00/03/16: Re: Difference between FPGA, PLD, CPLD ?
21308: 00/03/16: Re: Xilinx 6200 devices?
21321: 00/03/16: Re: Difference between FPGA, PLD, CPLD ?
21329: 00/03/16: Re: Xilinx configuration current
21328: 00/03/16: Re: Difference between FPGA, PLD, CPLD ?
21393: 00/03/21: Re: Clock disabling
21404: 00/03/22: Re: Virtex DLL inoperability
21450: 00/03/22: Re: FPGA openness
21581: 00/03/25: Re: DLL
21603: 00/03/26: Re: FPGA openness
21604: 00/03/26: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
21605: 00/03/26: Re: FPGA openness
21642: 00/03/27: Re: Anyone using Philips (now Xilinx) Coolrunner PLDs?
21716: 00/03/29: Re: I/O characteristics of Xilinx 1804 PROM
21720: 00/03/29: Re: Global clock nets. Can I use it for signal other than clock.
21748: 00/03/30: Re: Global clock nets. Can I use it for signal other than clock.
21751: 00/03/30: Re: What's so good about antifuse???
21752: 00/03/30: Re: What's so good about antifuse???
21268: 00/03/14: Atmel censors web access
21347: 00/03/17: Re: SV: Atmel censors web access
21558: 00/03/24: Re: FPGA openness
21811: 00/04/01: Re: FPGA openness
21805: 00/04/01: Re: FPGA price vs Size
21966: 00/04/10: Re: Distributed Arithmetic
21965: 00/04/10: Re: Virtex Trivia
21967: 00/04/10: Re: Virtex Trivia
21992: 00/04/11: Re: Virtex E Pads Output Impedance
21994: 00/04/11: Re: LUT
22048: 00/04/15: Re: synchronous FIFO
22157: 00/04/27: Re: Xilinx "length count" question
22204: 00/05/01: Re: Why are there no "cheap" FPGAs?
22514: 00/05/10: Re: SpartanXL driving 5V CMOS input
22548: 00/05/11: Re: SpartanXL driving 5V CMOS input
22633: 00/05/15: Re: HELP - what to choose?
22856: 00/05/28: Re: Buying FPGAs in Germany
22902: 00/05/31: Re: Design of Phase-Locked Loop (PLL) - 2 alternatives
22956: 00/06/06: Re: 3.3V I/O TO 5V LOGIC?
22957: 00/06/06: Re: 3.3V I/O TO 5V LOGIC?
22970: 00/06/06: Re: 3.3V I/O TO 5V LOGIC?
23004: 00/06/08: Re: XCV vs. XCV-E ?
23006: 00/06/08: Re: XCV vs. XCV-E ?
23069: 00/06/12: Re: Please,give me solution for "serious pad to pad delay" in Xilinx.
23113: 00/06/14: Re: Question: Xilinx FPGA PROGRAM pin
23127: 00/06/15: Re: FIFO design
23146: 00/06/15: Re: Altera Output Timing Question
23173: 00/06/16: Re: XC4005XL OTP?
23192: 00/06/16: Re: spartan and virtex on the same board ?
23226: 00/06/18: Re: Problem copying text from the Spartan II data sheet
23227: 00/06/18: Re: Problem copying text from the Spartan II data sheet
23228: 00/06/18: Re: Problem copying text from the Spartan II data sheet
23232: 00/06/18: Re: Problem copying text from the Spartan II data sheet
23244: 00/06/19: Re: How to cut the power disipation down ?
23260: 00/06/19: Re: How to cut the power disipation down ?
23266: 00/06/20: Re: Problem copying text from the Spartan II data sheet
23284: 00/06/21: Re: How to cut the power disipation down ?
23303: 00/06/21: Re: 500 million transistor FPGA's
23324: 00/06/22: Re: How to cut the power disipation down ?
23327: 00/06/22: Re: Looking for 'FREE' FPGA software
23340: 00/06/22: Re: VHDL - ripple carry counter
23342: 00/06/22: Re: VHDL - ripple carry counter
23348: 00/06/22: Re: Looking for 'FREE' FPGA software
23357: 00/06/23: Re: 500 million transistor FPGA's
23387: 00/06/23: Re: Xilinx xc4000
23390: 00/06/23: Re: Xilinx xc4000
23394: 00/06/23: Re: a lot of basic questions - where's the FAQ?
23465: 00/06/26: Re: serial 2's C add/substractor msb first
23467: 00/06/26: Re: FPGA and ASIC
23468: 00/06/26: Re: Dual Port BlockRAM Timing (Write-Read)
23478: 00/06/27: Re: Different ?
23521: 00/06/28: Re: I cant stand it any more.
22958: 00/06/06: Re: 3.3V I/O TO 5V LOGIC?
22976: 00/06/07: Re: 3.3V I/O TO 5V LOGIC?
23278: 00/06/20: Re: Problem copying text from the Spartan II data sheet
23520: 00/06/28: Re: digital phase lock loop
23584: 00/07/01: Re: Maximum Speed on obtainable on FPGAs?
23597: 00/07/02: Remedies after the Fathers' Day Massacre
23606: 00/07/02: Re: BIST in FPGAs?
23615: 00/07/02: Re: BIST in FPGAs?
23616: 00/07/02: Re: Remedies after the Fathers' Day Massacre
23635: 00/07/04: Re: How to augment the output of a Xilinx lfsr in verilog??
23636: 00/07/04: Re: How to augment the output of a Xilinx lfsr in verilog??
23665: 00/07/04: Re: Serial Number embedded in PROM.
23683: 00/07/05: Re: BIST in FPGAs?
24209: 00/07/29: Re: Spartan-II / Virtex-E / DC linear regulators
24217: 00/07/30: Re: LFSR as a divider
24218: 00/07/30: Re: Which one is good coding style?
24370: 00/08/05: Clock quadrupling
24371: 00/08/05: Look-up tables in Altera
24372: 00/08/05: Virtex DLL and external clocks
24373: 00/08/05: Which one is good coding style?
24374: 00/08/05: VirtexE FF set/reset
24402: 00/08/07: Re: FPGA selection
24403: 00/08/07: Re: FPGA selection
24448: 00/08/09: Re: Help!! Virtex system gate count.
24491: 00/08/11: Re: Further FPGA metastability questions
24492: 00/08/11: Re: 3-state busses on Virtex?
24493: 00/08/11: Re: Further FPGA metastability questions
24530: 00/08/12: Re: Comparing Xilinx FPGAs
24544: 00/08/13: Re: Virtex 2.5V part with 5V IO problems
24562: 00/08/14: Re: state encoding in Synplify!!!
24423: 00/08/07: Re: Help!! Virtex system gate count.
24489: 00/08/10: Re: Help with Xilinx
24610: 00/08/15: Re: clock skew problem please help!!
24611: 00/08/15: Re: what does 0.35 micron mean
24612: 00/08/15: Re: Non-disclosures in job interviews
24660: 00/08/16: Re: fifo;s
24698: 00/08/17: Re: Xilinx Spartan II block RAM
24701: 00/08/17: Re: When will SpartanII be in ditribution
24587: 00/08/14: Re: clock skew problem please help!!
24635: 00/08/15: Re: what does 0.35 micron mean
24557: 00/08/13: Re: state encoding in Synplify!!!
24585: 00/08/14: Re: Crossing Clock Domains.
24682: 00/08/16: Re: Permanently programming FPGAs
24525: 00/08/11: Re: Xilinx chip not programming correctly
24588: 00/08/14: Re: what does 0.35 micron mean
24668: 00/08/16: Re: Non-disclosures in job interviews
24690: 00/08/16: Re: Xilinx Spartan II block RAM
24692: 00/08/16: Re: Permanently programming FPGAs
24738: 00/08/17: Re: When will SpartanII be in ditribution
24826: 00/08/20: Re: Further FPGA metastability questions
24827: 00/08/20: Re: Further FPGA metastability questions
24842: 00/08/20: Re: Metastability and antifuze
24844: 00/08/20: Re: Metastability measurement
24850: 00/08/20: Re: Metastability and antifuze
24851: 00/08/20: Re: Arg! 8051 - 6502 and friends
24853: 00/08/20: Re: Non-disclosures in job interviews, Round One
24857: 00/08/20: Re: Metastability measurement
24858: 00/08/20: Re: Metastability and antifuze
24864: 00/08/21: Re: Further FPGA metastability questions
24925: 00/08/22: Re: Some notes on metastability
24938: 00/08/22: Re: Permanently programming FPGAs
24986: 00/08/23: Re: Some notes on metastability
24987: 00/08/23: Re: Metastability and antifuze
25016: 00/08/24: Re: Non-disclosures in job interviews, Round Two
25025: 00/08/24: Re: Permanently programming FPGAs
25026: 00/08/24: Re: Virtex partial reconfiguration feature (?)
25036: 00/08/24: Re: availability of Spartan II
25043: 00/08/24: Re: largest fpga in the industry
25049: 00/08/24: Re: largest fpga in the industry
25051: 00/08/24: Re: largest fpga in the industry
25052: 00/08/24: Re: create a RAM in a Virtex
25079: 00/08/25: Re: create a RAM in a Virtex
25082: 00/08/25: Re: largest fpga in the industry
25093: 00/08/25: Re: largest fpga in the industry
25102: 00/08/25: Re: Why Aren't Anti-Fuse FPGAs The Biggest FPGAs In The World?
25108: 00/08/25: Re: Is there any way to configure the Virtex BRAM outputs as direct,
24321: 00/08/04: Who needs all those printed ac parameters?
24369: 00/08/05: 8251 USART
24461: 00/08/09: Re: Crossing Clock Domains.
24468: 00/08/10: Re: Crossing Clock Domains.
24829: 00/08/20: Re: Permanently programming FPGAs
24915: 00/08/22: Re: Looks like Xilinx is at it again!
25672: 00/09/17: Re: Adders in FPGA?
25768: 00/09/19: Re: virtex shape
25847: 00/09/22: Re: memory interface trouble...
25871: 00/09/24: Re: memory interface trouble...
25880: 00/09/24: Re: MAPLD
25881: 00/09/24: Re: memory interface trouble...
26145: 00/10/05: Re: Xilinx Licensing.
26377: 00/10/13: Re: const coeff multiplier w/ LUTs
26470: 00/10/17: Re: ordered list
26618: 00/10/22: Re: CoolRunner news :(
26769: 00/10/27: Re: How safe is the algorithm implemented with FPGA?
26770: 00/10/27: Re: CoolRunner news :(
26893: 00/11/02: Re: Need a PCB speaker driven by XCV100
27124: 00/11/11: Re: PLL vs DLL
27127: 00/11/11: Re: CRC, LFSR and scramblers
27168: 00/11/13: Re: PLL vs DLL
27211: 00/11/15: Re: CRC, LFSR and scramblers
27272: 00/11/16: Re: Can FPGA perform float point calculation?
27317: 00/11/17: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
27711: 00/12/04: Re: Issues with Spartan II
27813: 00/12/09: Re: Linear Regulator troubles
27834: 00/12/11: Re: VHDL technique for synchronizer ?
27854: 00/12/12: Re: Xilinx CPLD capable of driving LEDs
27882: 00/12/13: Re: Setup violation
27896: 00/12/13: Re: really fast counter in SpartanXL?
27957: 00/12/17: Re: questions regarding external setup & hold time considerations
27958: 00/12/17: Re: async interface
27975: 00/12/18: Re: dual port ram for altera
27978: 00/12/18: Re: Virtex and metastability
27979: 00/12/18: Re: Setup violation
27985: 00/12/18: Re: Setup violation
27994: 00/12/18: Re: Setup violation
27995: 00/12/18: Re: dual port ram for altera
28023: 00/12/19: Re: Setup violation
28024: 00/12/19: Re: 3V -> 5V clock signal level conversion
28025: 00/12/19: Re: Spartan2 and industrial temperatures
28026: 00/12/19: Re: Setup violation
28036: 00/12/19: Re: Hold time constraints in virtex?
28038: 00/12/19: Re: 3V -> 5V clock signal level conversion
28044: 00/12/19: Re: dual port ram for altera
28075: 00/12/20: Re: dual port ram for altera
28076: 00/12/20: Re: really fast counter in SpartanXL?
28077: 00/12/20: Re: Spartan2 and industrial temperatures
28080: 00/12/20: Re: Virtex and metastability
28082: 00/12/20: Re: Reverse-engineering FPGA's
28084: 00/12/20: Re: dual port ram for altera
28085: 00/12/20: Re: really fast counter in SpartanXL?
28086: 00/12/20: Re: 3V -> 5V clock signal level conversion
28095: 00/12/20: Re: 3V -> 5V clock signal level conversion
28114: 00/12/21: Re: Metastability rant (was Re: dual port ram for altera)
28117: 00/12/21: Re: Metastability rant (was Re: dual port ram for altera)
28167: 00/12/23: Re: Question about programming xcv100
28170: 00/12/23: Re: really fast counter in SpartanXL?
28191: 00/12/27: Re: really fast counter in SpartanXL?
28194: 00/12/27: Re: Newbie question on clock timing generation
28201: 00/12/28: Re: really fast counter in SpartanXL?
27814: 00/12/09: Re: Linear Regulator troubles
27815: 00/12/09: Re: Linear Regulator troubles
28838: 01/01/25: Re: really fast counter in SpartanXL?
28866: 01/01/26: Re: really fast counter in SpartanXL?
28271: 01/01/04: Re: Nondeterministic FSMs in hardware?
28364: 01/01/10: Re: Alliance for Linux
28366: 01/01/10: Re: grey code counters
28369: 01/01/10: Re: grey code counters
28371: 01/01/10: Re: grey code counters
28375: 01/01/10: Re: grey code counters
28381: 01/01/10: Re: Alliance for Linux
28385: 01/01/11: Re: grey code counters
28409: 01/01/11: Re: grey code counters
28410: 01/01/11: Re: address of ram using the clk net
28412: 01/01/11: Re: grey code counters
28417: 01/01/11: Re: CRC - from long division to XOR, how?
28426: 01/01/12: Re: address of ram using the clk net
28442: 01/01/12: Re: SRAM fpga cell
28461: 01/01/14: Re: grey code counters
28497: 01/01/15: Re: grey code counters
28498: 01/01/15: Re: Virtex-II officially launched
28510: 01/01/15: Re: Virtex-II officially launched
28513: 01/01/16: Re: grey code counters
28542: 01/01/16: Re: Oscillator for FPGA - low cost
28551: 01/01/16: Re: FPGA driving clock line
28552: 01/01/16: Re: FPGA driving clock line
28579: 01/01/17: Re: Virtex counter speed
28582: 01/01/17: Re: Virtex-II officially launched
28592: 01/01/17: Re: CMOS or TTL
28598: 01/01/17: Re: spartanII chip availability
28621: 01/01/18: Re: Virtex-II officially launched
28636: 01/01/18: Re: Best design for asyn. interface DSP <-> FPGA?
28638: 01/01/18: Re: CMOS or TTL
28656: 01/01/19: Re: FSM encoding
28660: 01/01/19: Re: Best design for asyn. interface DSP <-> FPGA?
28683: 01/01/20: Re: Virtex-II officially launched
28698: 01/01/21: Re: Virtex-II officially launched
28699: 01/01/21: Re: Designing fractional counters?
28700: 01/01/21: Re: Firewire bus driven/received by Xilinx using LVDS
28702: 01/01/21: Re: CMOS or TTL
28757: 01/01/23: Re: Xilinx XCell is not on-line?
28771: 01/01/24: Re: Virtex counter speed
28803: 01/01/24: Re: Encryption is supported in new Virtex II but.....
28881: 01/01/26: Re: RAM reset question - Xilinx Virtex
28884: 01/01/27: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
28886: 01/01/27: Re: XtremeDSP seminar comments -- Virtex-II 4xPowerPC chip
28907: 01/01/29: Re: Is it a timing constraint problem?
28928: 01/01/30: Re: Encryption is supported in new Virtex II but.....
28938: 01/01/30: Re: Clocking system with CPLD? - timing.JPG (0/1)
28971: 01/01/31: Re: Xilinx fast carry counter question
28986: 01/02/01: Re: 64-bit counter @ 200 MHz on FPGA?
29004: 01/02/01: Re: 64-bit counter @ 200 MHz on FPGA?
29015: 01/02/01: Re: Spartan 2 DLL
29016: 01/02/02: Re: 64b/66b gearbox in an FPGA
29018: 01/02/02: Re: Encryption is supported in new Virtex II but.....
29039: 01/02/03: Re: Encryption is supported in new Virtex II but.....
29054: 01/02/04: Re: Encryption is supported in new Virtex II but.....
29061: 01/02/04: Re: help need to make a clock multiplier
29066: 01/02/04: Re: Encryption is supported in new Virtex II but.....
29111: 01/02/06: Re: Xilinx XC4010
29122: 01/02/06: Re: Switching matrix, FPGA or CPLD? - smatrix.JPG (0/1)
29161: 01/02/08: Re: Xilinx vs Altera
29204: 01/02/09: Re: Xilinx vs Altera
29214: 01/02/09: Re: Can a Virtex control its own reconfiguration?
29224: 01/02/10: Re: what exactly is the dff between fpga and cpld?
29225: 01/02/10: Re: Help for a novice. Where to begin?
29226: 01/02/10: Re: double precision floating point arithmetic
29227: 01/02/10: Re: DLL jitter "bake-off" vs. PLL
29239: 01/02/10: Re: does a disabled FDC consume power ?
29240: 01/02/10: Re: any idea ?
29251: 01/02/11: Re: any idea ?
29252: 01/02/11: Re: OT: IEEE & Floating point
29253: 01/02/11: Re: any idea ?
29380: 01/02/17: Re: Design of a divide by 6.5 counter ?
29404: 01/02/19: Re: Fine Phase Shift in VirtexII
29442: 01/02/21: Re: clock divider by 1.5
29468: 01/02/22: Re: Virtex E:Sample price
29475: 01/02/22: Re: Virtex E:Sample price
29529: 01/02/25: Re: Is anybody using Quicklogic PCI/FPGA devices?
29534: 01/02/25: Re: Is anybody using Quicklogic PCI/FPGA devices?
29536: 01/02/26: Re: Spartan II power
29546: 01/02/26: Re: Metastability data for Spartan2, Virtex and VirtexE?
29550: 01/02/26: Re: Virtex II availability
29612: 01/03/01: Re: SRAM vs. FLASH?
29623: 01/03/01: Re: What about speed-grade?
29624: 01/03/01: Re: Virtex DLLs
29641: 01/03/03: Re: Bad Xilinx bitstream=big bang?
29650: 01/03/03: Re: Bad Xilinx bitstream=big bang?
29652: 01/03/03: Re: Bad Xilinx bitstream=big bang?
29659: 01/03/04: Re: Bad Xilinx bitstream=big bang?
29672: 01/03/05: Re: Metastability, Asynchronous Signals, & Asynchronous design
29680: 01/03/05: Re: Metastability, Asynchronous Signals, & Asynchronous design
29681: 01/03/05: Re: Metastability, Asynchronous Signals, & Asynchronous design
29683: 01/03/05: Re: Metastability, Asynchronous Signals, & Asynchronous design
29684: 01/03/05: Re: Bad Xilinx bitstream=big bang?
29810: 01/03/12: Re: SRAM fpga cell
29824: 01/03/12: Re: order Xilinx FPGA`s in Benelux
29832: 01/03/13: Re: VirtexE LVPECL I/O Ports? experience?
29844: 01/03/13: Re: 64 simultan A/D Converters in an SPARTAN-II
29847: 01/03/13: Re: 64 simultan A/D Converters in an SPARTAN-II
29848: 01/03/13: Re: 64 simultan A/D Converters in an SPARTAN-II
29856: 01/03/14: Re: 64 simultan A/D Converters in an SPARTAN-II
29905: 01/03/16: Re: RAM-based Shift Register
29923: 01/03/17: Re: about core generator
29926: 01/03/18: Re: FFT in FPGAs
29933: 01/03/19: Re: FFT in FPGAs
29963: 01/03/19: Re: FFT in FPGAs
30011: 01/03/20: Re: TOA measurement
30042: 01/03/21: Re: Do I need to tie unused CPLD pins to GND?
30052: 01/03/21: Re: Yet Another Newbie Question
30056: 01/03/22: Re: reduced precision floating point
30081: 01/03/22: Re: Is the carry logic for Virtex included in PAR timing report/check?
30093: 01/03/23: Re: Is the carry logic for Virtex included in PAR timing report/check?
30126: 01/03/24: Re: Accumulator - Core in XC4K
30129: 01/03/24: Re: config FPGA OK but nothing running !?
30134: 01/03/24: Re: config FPGA OK but nothing running !?
30147: 01/03/26: Re: No inputs on XC9536XL
30165: 01/03/26: Re: RAM read?
30176: 01/03/27: Re: Alternatives for Xilinx Spartan-II configuration PROM
30246: 01/03/29: Re: Encryption Bitstrems
30261: 01/03/29: Re: Programmble Logic Sequencer
30274: 01/03/30: Re: VIRTEX BLOCK RAM
30313: 01/04/02: Re: xapp258 question
30341: 01/04/03: Re: xapp258 question
30347: 01/04/03: Re: pseudo random numbers
30352: 01/04/04: Re: Combined Multiplier-Divider in Virtex-E
30395: 01/04/06: Re: High Speed PLA/FPGA
30406: 01/04/06: Re: High Speed PLA/FPGA
30407: 01/04/06: Re: x4000 series reset
30462: 01/04/09: Re: Spartan-II DLL question
30492: 01/04/11: Re: High Speed PLA/FPGA
30566: 01/04/17: Re: XCV1000BG560: onchip ram
30577: 01/04/17: Re: Clean Frequency Division
30582: 01/04/18: Re: Clean Frequency Division
30584: 01/04/18: Re: XC9500XL Internal Noise Immunity
30604: 01/04/19: Re: clocking on both edges
30623: 01/04/19: Re: clocking on both edges
30624: 01/04/19: Re: clocking on both edges
30625: 01/04/19: Re: looking for comment on implementation
30629: 01/04/19: Re: clocking on both edges
30630: 01/04/19: Re: some general questions about FPGA design
30649: 01/04/20: Re: What is a FPGA ?
30667: 01/04/23: Re: Something about the counter
30905: 01/05/02: Re: Serial UART
30971: 01/05/06: Re: VirtexE LVPECL I/O Ports? experience?
31097: 01/05/11: Re: Asynchronous Compare
31108: 01/05/12: Re: Clock Waveform
31200: 01/05/14: Re: SRAM fpga cell
31250: 01/05/16: Re: SRAM fpga cell
31252: 01/05/16: Re: PROGRAMMABLE LOGIC SEQUENCER CORRECTIONS
31273: 01/05/16: Re: Xilinx Service Pack 8 Now Available
31296: 01/05/17: Plenty of technical info is available...
31395: 01/05/22: Re: LFSR Taps for 64 bit registers?
31421: 01/05/23: Re: fast divider
31464: 01/05/25: Re: Xilinx Coolrunner 100% routable - but the tools aren't
31465: 01/05/25: Re: Xilinx Coolrunner 100% routable - but the tools aren't
31471: 01/05/27: Re: Xilinx XC4010E Problem
31472: 01/05/27: Re: Internal tri states
31474: 01/05/27: Re: Xilinx XC4010E Problem
31475: 01/05/27: New Xilinx data book Frisbee
31481: 01/05/27: Re: Internal tri states
31482: 01/05/27: Re: Fragen zu PCI und FPGA
31491: 01/05/27: Re: Internal tri states
31501: 01/05/28: Re: New Xilinx data book Frisbee
31508: 01/05/29: Re: Fun with DLLs.
31509: 01/05/29: Re: Xilinx Reset
31511: 01/05/29: Re: xilinx webpack warning !!
31536: 01/05/29: Re: xilinx webpack warning !!
31537: 01/05/29: Re: Fun with DLLs.
31539: 01/05/29: Re: xilinx webpack warning !!
31555: 01/05/30: Re: Fun with DLLs.
31617: 01/05/31: Re: [Q]setup-time violation
31618: 01/05/31: Re: Help: RAM clear in one clock cycle
31619: 01/05/31: Re: Barrel shifter in Xilinx Virtex-E
31663: 01/06/01: Re: Help on Xilinx 6200
31707: 01/06/03: Re: one state machine
31720: 01/06/04: Re: one state machine
31721: 01/06/04: Re: XtremeDSP Ready for prime time?
31726: 01/06/04: Re: Xilinx XC4010E Problem
31729: 01/06/04: Re: Xilinx Coolrunner 100% routable - but the tools aren't
31730: 01/06/04: Re: Xilinx Coolrunner 100% routable - but the tools aren't
31743: 01/06/05: Re: Xilinx Coolrunner 100% routable - but the tools aren't
31744: 01/06/05: Re: Help in FIFO design
31768: 01/06/05: Re: on-chip vs off-chip ram
31779: 01/06/05: Re: Help in FIFO design
31784: 01/06/05: Re: Help in FIFO design
31811: 01/06/06: Re: Help in FIFO design
31824: 01/06/06: Re: one state machine
31830: 01/06/06: Re: Xilinx Configuration Bitstream
31833: 01/06/06: Re: Help in FIFO design
31842: 01/06/06: Re: one state machine
31875: 01/06/07: Re: Help in FIFO design
31885: 01/06/07: Re: Help in FIFO design
31907: 01/06/08: Re: system clock speed
31908: 01/06/08: Re: XC4005XL is it a modern chip?
31960: 01/06/09: Re: Async FIFO in maxplus2
31976: 01/06/10: Re: Async FIFO in maxplus2
32034: 01/06/11: Re: On the prices of the FPGA and how to buy it
32050: 01/06/12: Re: Gray Code Guard bits (was Re: Help in FIFO design)
32124: 01/06/14: Re: FPGA comparsion
32126: 01/06/14: Re: Xilinx Virtex 2: Configurations problems
32168: 01/06/18: Re: Xilinx web site ?
32238: 01/06/20: Re: Gray counter STRUCTURAL (VHDL)
32318: 01/06/22: Re: Clock Derivation
32356: 01/06/24: Re: Clock Derivation
32365: 01/06/25: Re: Register balancing in FPGA Express
32377: 01/06/25: Re: Date Code Problem?
32396: 01/06/25: Re: XPower
32426: 01/06/26: Re: Xilinx Configuration Bitstream
32430: 01/06/26: Re: Stupid Xilinx Patent
32436: 01/06/26: Re: Stupid Xilinx Patent
32467: 01/06/27: Re: Xilinx Patent
32484: 01/06/27: Re: Cheap ECL-TTL translator
32512: 01/06/28: Re: clock speed in XC95288XL
32513: 01/06/28: Re: clock speed in XC95288XL
32514: 01/06/28: Re: Xc4K still alive?
32516: 01/06/28: Re: Clock muxes
32520: 01/06/28: Re: clock speed in XC95288XL
32522: 01/06/28: Re: Is the Grass Greener for an Engineer in the USA?
32573: 01/06/30: Re: XC9500 drive capability
32596: 01/07/02: Re: Virtex II Block RAM's - Is the second port free?
33402: 01/07/25: Re: In-Circuit Power Supply Verification of Xilinx Chips
33413: 01/07/25: Re: What chip!?
33471: 01/07/27: Re: Too low output voltage on Altera 7000S??
33539: 01/07/30: Re: finite defect statistics
33563: 01/07/30: Re: SRL16
33598: 01/07/31: Re: RAM... got it
33601: 01/07/31: Re: finite defect statistics
33648: 01/08/01: Re: May I connect two pins to the same net?
33700: 01/08/02: Re: Spartan II and asynchronous memory interface
33710: 01/08/02: Re: Spartan II and asynchronous memory interface
33720: 01/08/02: Re: Too low output voltage on Altera 7000S??
33896: 01/08/07: Re: URL for XILINX's free 314-page design and sythesis guide
33897: 01/08/07: Re: URL for XILINX's free 314-page design and sythesis guide
33981: 01/08/09: Re: Spartan-II serial configuration problem from ATMEL device
34002: 01/08/10: Re: Spartan-II serial configuration problem from ATMEL device
34007: 01/08/10: Re: Spartan-II serial configuration problem from ATMEL device
34106: 01/08/14: Re: virtex2 Block Ram: dual port ram with different da
34149: 01/08/15: Re: Internal clock skew when using DLL
34231: 01/08/16: Re: Internal clock skew when using DLL
34258: 01/08/17: Re: Internal clock skew when using DLL
34260: 01/08/17: Re: Internal clock skew when using DLL
34264: 01/08/17: Re: Xilinx DLL in VirtexE
34314: 01/08/20: Re: hardware damage to a Virtex or Spartan-II?
34315: 01/08/20: Re: connected "not connect" pins on Xilinx
34341: 01/08/21: Re: hardware damage to a Virtex or Spartan-II?
35085: 01/09/20: Re: Clockin on rising AND falling edge
35094: 01/09/20: Re: Maximum clock rate of various Xilinx families?
35144: 01/09/24: Re: Clockin on rising AND falling edge
35149: 01/09/24: Re: comp.arch.fpga : Unusual clock divider ckt
35150: 01/09/24: Re: comp.arch.fpga : Unusual clock divider ckt
35156: 01/09/24: Re: comp.arch.fpga : Unusual clock divider ckt
35161: 01/09/24: Re: comp.arch.fpga : Unusual clock divider ckt
35162: 01/09/24: Re: Registered outputs...
35165: 01/09/24: Re: comp.arch.fpga : Unusual clock divider ckt
35188: 01/09/25: Re: comp.arch.fpga : Unusual clock divider ckt
35190: 01/09/25: Re: FPGA with embedded Memory
35240: 01/09/26: Re: Spartan-IIE?
35243: 01/09/26: Re: Logical constraints of LUT
35244: 01/09/26: Re: Digital design/ASIC/FPGA/CAD engineer (MSEE) looking for a new
35274: 01/09/27: Re: Logical constraints of LUT
35336: 01/09/29: Re: Timing on output
35350: 01/09/30: Re: Xilinx Virtex-II reconfiguration
35375: 01/10/02: Re: barrel shifter in Xilinx Virtex-E
35384: 01/10/02: Re: barrel shifter in Xilinx Virtex-E
35394: 01/10/02: Re: Which Cable for the Xilinx 3064XL ?
35437: 01/10/04: Re: input signal frequency
35472: 01/10/06: Re: ROM based FSMs
35488: 01/10/08: Re: future Xilinx products wish list ...
35503: 01/10/08: Re: ROM based FSMs
35507: 01/10/09: Re: Call For Papers - Special Issue on Programmable Logic (ACM Trans. on
35531: 01/10/10: Re: Virtex-2 maximum clock speed
35532: 01/10/10: Re: FPGA reset
35561: 01/10/10: Re: FPGA reset
35573: 01/10/10: Re: 155MHz to DLL in Spartan II
35598: 01/10/11: Re: Dual Port Fifo for Virtex II
35622: 01/10/12: Re: Block RAMs
35623: 01/10/12: Re: Block RAMs
35675: 01/10/13: Re: future Xilinx products wish list ...
35728: 01/10/15: Re: PLLs & DLLs
35753: 01/10/16: Re: LUT Glitches
35763: 01/10/17: Re: PLLs & DLLs
35764: 01/10/17: Re: LUT Glitches
35842: 01/10/19: Re: Glitch Hunting, a true story ;-)
35895: 01/10/22: Re: What is a difference?
35896: 01/10/22: Re: Maser Serial Config Problem
35939: 01/10/24: Re: Are there any Coolrunner P5Z22V10 (PLCC) devices left anywhere?
35994: 01/10/25: Re: transferring data between related clocks
36073: 01/10/28: Re: How to make an implementable big counter?
36095: 01/10/29: Re: P5Z22V10 - any left anywhere?
36102: 01/10/30: Re: How can I design a bi-deriction bus buffer?
36119: 01/10/30: Re: How can I design a bi-deriction bus buffer?
36138: 01/10/31: Re: Field Programmable Logic in energy poor environments
36163: 01/10/31: Re: Field Programmable Logic in energy poor environments
36164: 01/10/31: Re: one SPROM for 2 XCS30XLs?
36192: 01/11/01: Re: Second Scenario: BRAM usage reduction in FIFO design
36193: 01/11/01: Re: Second Scenario: BRAM usage reduction in FIFO design
36199: 01/11/01: Re: Can anyone guide me in selecting an FPGA?
36204: 01/11/01: Re: Help with a 1996 XC3064 design!!
36205: 01/11/02: Re: Help with a 1996 XC3064 design!!
36206: 01/11/02: Re: XC6000
36253: 01/11/04: Re: spartan synthesis with synopsis
36269: 01/11/04: Re: Help with a 1996 XC3064 design!!
36368: 01/11/07: Re: FPGA Wish list
36415: 01/11/08: Re: How dense are FPGA/CPLD's
36442: 01/11/08: Re: How dense are FPGA/CPLD's
36449: 01/11/09: Re: Fifo books
36518: 01/11/10: Re: ZX81 production run, is there any interest?
36538: 01/11/12: Re: What is the optimal number of fanouts?
36573: 01/11/12: Re: Funny voltage levels
36688: 01/11/15: Re: CAM
36691: 01/11/15: Re: High Speed PWM?
36693: 01/11/15: Re: High Speed PWM?
36712: 01/11/16: Re: Spartan2 - 5 V tolerance question
36716: 01/11/17: Re: High Speed PWM?
36720: 01/11/17: Re: Virtex 2 parts availability???
36721: 01/11/17: Re: Clock Divider or Multiplier ???
36722: 01/11/17: Re: Xilinx and Multirate clock ??
36777: 01/11/19: Re: Xilinx and Multirate clock ??
36812: 01/11/20: Re: don't cares and X's in a case statement?
36815: 01/11/20: Re: don't cares and X's in a case statement?
36850: 01/11/22: Re: slew rate of virtex output buffers figures
36910: 01/11/25: Re: How to make an implementable big counter?
36913: 01/11/25: Re: ALTERA's Mercury CDR
36927: 01/11/26: Re: How to make an implementable big counter?
36930: 01/11/26: Re: ALTERA's Mercury CDR
36936: 01/11/26: Re: ALTERA's Mercury CDR -- my mistake, sorry!
36968: 01/11/27: Re: Creating a jitter free clock
36971: 01/11/27: Got enough mebibytes of RAM ?
36986: 01/11/27: Re: Which vendor to choose
36987: 01/11/27: Re: Creating a jitter free clock
36992: 01/11/28: Re: What does a 'Slice' refer to in a Xilinx MAP report?
37029: 01/11/28: Re: SpartanIIE
37072: 01/11/29: Re: palette LUT design(finding Virtex / Spartan II)
37091: 01/11/29: Re: SpartanIIE
37133: 01/11/30: Re: Is there a full open-source synthesis path for any FPGA?
37154: 01/12/02: Re: Is there a full open-source synthesis path for any FPGA?
37198: 01/12/03: Re: Is there a full open-source synthesis path for any FPGA?
37308: 01/12/06: Re: XC6200
37364: 01/12/08: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37378: 01/12/09: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37379: 01/12/09: Re: Xilinx multiplier and block ram error
37380: 01/12/09: Re: ALTERA's Mercury CDR
37381: 01/12/09: Re: aldec
37411: 01/12/10: Re: Michelangelo's Counter
37424: 01/12/10: Re: Michelangelo's Counter
37452: 01/12/11: Re: Michelangelo's Counter
37468: 01/12/11: Re: Crosstalk on clocks
37492: 01/12/12: Re: Initialization of RAM
37494: 01/12/12: Re: Michelangelo's Counter
37495: 01/12/12: Re: Crosstalk on clocks
37530: 01/12/13: Re: FPGA introduction
37534: 01/12/13: Re: FPGA introduction
37545: 01/12/14: Re: Dual-port ram templates
37565: 01/12/15: Re: Dual-port ram templates
37572: 01/12/16: Re: annoying problem
37607: 01/12/17: Re: division 64
37652: 01/12/18: Kindergarten Stuff
37654: 01/12/18: Re: FGPA express bidir pins Xilinx, FPGA-pmap-18
37659: 01/12/18: Re: Barrel shifter puts three 2->1 muxes / slice in Xilinx
37757: 01/12/19: Re: annoying problem and "simple and clever solution"
37792: 01/12/20: Re: Hardware FPGA questions
37793: 01/12/20: Re: Clock pins in Virtex-E
37795: 01/12/20: Re: Hardware FPGA questions
37811: 01/12/20: Re: Best-case timing?
37820: 01/12/20: Re: annoying problem and "simple and clever solution"
37831: 01/12/21: Re: Hardware FPGA questions
37832: 01/12/21: Re: Defauolt Should Be "Inputs and Outputs" For IOBs
37855: 01/12/21: Re: A ram wish
37857: 01/12/21: Re: CE on XILINX FFs and Metastability
37859: 01/12/21: Re: CE on XILINX FFs and Metastability
37860: 01/12/21: Re: How to make an implementable big counter?
37861: 01/12/21: Re: How to make an implementable big counter?
37862: 01/12/21: Re: A ram wish
37864: 01/12/21: Re: A ram wish
37904: 01/12/24: Re: availability of VirtexII production silicon
37905: 01/12/24: Re: Kindergarten Stuff
37906: 01/12/24: Re: Does the core or Xilinx Core Generator support timing-simlulation?
38070: 02/01/04: Re: A Fast counter in VHDL?
38072: 02/01/04: Re: asic vs. fpga
38098: 02/01/04: Re: help with older xilinx fpga's
38100: 02/01/04: Re: asic vs. fpga
38103: 02/01/04: Re: ASIC faster than VirtexII FPGA?
38134: 02/01/06: Re: 4 fpga configuration using 1 EPROM
38138: 02/01/07: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38185: 02/01/08: Re: latch vs. register
38204: 02/01/08: Re: latch vs. register
38205: 02/01/08: Re: Repost: Should clock skew be included for setup time analysis?
38209: 02/01/08: Re: latch vs. register
38228: 02/01/09: Re: distributed ram bits in XCVxxxx series
38253: 02/01/10: Re: Repost: Should clock skew be included for setup time analysis?
38286: 02/01/10: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38287: 02/01/10: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38342: 02/01/11: Re: latch vs. register
38446: 02/01/15: Re: CLKDLL cascade questions
38488: 02/01/15: Re: Repost: Should clock skew be included for setup time analysis?
38526: 02/01/16: Re: Audio time delay circuit
38527: 02/01/16: Re: Repost: Should clock skew be included for setup time analysis?
38569: 02/01/17: Re: Audio time delay circuit
38574: 02/01/18: Re: Audio time delay circuit
38651: 02/01/20: Re: SPARTAN 2-DLL USAGE
38670: 02/01/21: Re: Atmel FPGA configuration memory?!
38675: 02/01/21: Re: Signal processing using FPGAs
38681: 02/01/21: Re: Signal processing using FPGAs
38713: 02/01/22: Re: input source to feed 20 filters! how to decrease the load
38735: 02/01/23: Re: IDT7204 Using CoreGen
38777: 02/01/24: Re: Dynamic Reconfiguration of single Xilinx FPGA
38782: 02/01/24: Re: Audio time delay circuit
38864: 02/01/27: Re: tri-state vs. Mux
38865: 02/01/27: Re: Xilinx webpack
38882: 02/01/27: Re: Xilinx webpack
38884: 02/01/27: Re: Xilinx webpack
38886: 02/01/27: Re: fpga device utilization
38896: 02/01/28: Re: Simple shift register not working (update)
38897: 02/01/28: Re: Xilinx webpack
38924: 02/01/28: Re: Xilinx webpack
38930: 02/01/28: Re: Peaks in smaller PLDs
38932: 02/01/28: Re: Simple shift register not working (update)
38951: 02/01/28: Re: Peaks in smaller PLDs
38970: 02/01/29: Re: glitchless clock enable/disable in spartanII
38998: 02/01/29: Re: Memory Question on Virtex
39003: 02/01/29: Re: glitchless clock enable/disable in spartanII
39007: 02/01/29: Re: The LUT puzzle, Iam on the way
39056: 02/01/30: Re: Dynamic Reconfiguration of single Xilinx FPGA
39063: 02/01/30: Re: glitchless clock enable/disable in spartanII
39064: 02/01/30: Re: The LUT puzzle, Iam on the way
39067: 02/01/30: Re: glitchless clock enable/disable in spartanII
39101: 02/01/31: Re: glitchless clock enable/disable in spartanII
39102: 02/01/31: Re: Xilinx XC3020-70
39103: 02/01/31: Re: FPGA or Micro-controller in Lowpower designs?
39108: 02/01/31: Re: skew between gated clks in Virtex2?
39120: 02/01/31: Re: glitchless clock enable/disable in spartanII
39143: 02/02/01: Re: Dual ported RAM in SpartanII, output = ?????
39179: 02/02/03: Re: DCM relationship question
39191: 02/02/04: Re: can comparisons glitch?
39216: 02/02/04: Re: RAM question
39235: 02/02/04: Re: RAM question
39247: 02/02/04: Re: Dual ported RAM in SpartanII, output = ?????
39768: 02/02/19: Re: Virtex-E BRAM timing
39860: 02/02/21: Re: CLKDLL x4 problem
39863: 02/02/21: Re: Here is an argument and can anyone help me out
39889: 02/02/21: Re: Problems : INOUT not allowed, alternatives
39900: 02/02/21: Re: INIT on XC2S30
39968: 02/02/22: Re: How can I disable clock buffer (BUFG) insertion in Xilinx Foundation
39971: 02/02/22: Re: cross clock domain signals
40032: 02/02/25: Re: RAM question
40035: 02/02/25: Re: RAM question
40068: 02/02/26: Re: RAM question
40070: 02/02/26: Re: RAM question
40083: 02/02/27: Re: RAM question
40123: 02/02/28: Re: RAM question
40141: 02/02/28: Re: Rising and falling edge of a clk
40156: 02/02/28: Re: Altera FPGAs
40206: 02/03/01: Re: Rising and falling edge of a clk
40208: 02/03/01: Re: stuck in state in Spartan-II!
40245: 02/03/03: Re: Rising and falling edge of a clk
40251: 02/03/03: Re: Rising and falling edge of a clk
40283: 02/03/04: Re: Asynchronous boundaries in FPGA
40407: 02/03/06: Re: FPGA wich supports LVDS
40408: 02/03/06: Re: QPRO Virtex
40409: 02/03/06: Re: FPGA or DSP in a power supply?
40418: 02/03/06: Re: Fast transmission
40425: 02/03/07: Re: Using a battery instead of Config device
40452: 02/03/07: Re: FPGA or DSP in a power supply?
40487: 02/03/07: Re: CLKDLL in Virtex
40514: 02/03/08: Re: FPGA or DSP in a power supply?
40518: 02/03/08: Re: GATE ARRAY PROJECT
40525: 02/03/08: Re: FPGA or DSP in a power supply?
40537: 02/03/09: Re: BlockRam
40578: 02/03/11: Re: Spartan II E output voltage characteristics
40583: 02/03/11: Re: First steps with clock enable constraining
40589: 02/03/11: Re: FPGA wich supports LVDS
40606: 02/03/11: Re: Spartan II E output voltage characteristics
40660: 02/03/12: Re: powerpc in virtex2pro
40989: 02/03/19: Re: FIFO general question
41008: 02/03/19: Re: Unused I/Os + External Clock on Virtex II
41065: 02/03/20: Re: FIFO general question
41066: 02/03/20: Re: FPGA or Micro-controller in Lowpower designs?
41087: 02/03/20: Re: FIFO general question
41148: 02/03/21: Re: XPOWER accuracy? Commendations
41205: 02/03/22: Re: Clock termination affecting JTAG interface
41206: 02/03/22: Re: XPOWER accuracy? Commendations
41237: 02/03/22: Re: GREAT availability on Coolrunner!!! (was: Poor availability problems
41314: 02/03/25: Re: question on LFSR
41353: 02/03/26: Re: clock source
41361: 02/03/26: Re: failure rate of Xilinx chips
41372: 02/03/26: Re: question on LFSR
41415: 02/03/27: Re: FPGA config without boot PROM???
41428: 02/03/27: Re: FPGA config without boot PROM???
41442: 02/03/28: Re: PLLs included in Altera Stratix Devices
41444: 02/03/28: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41453: 02/03/28: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41455: 02/03/28: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41491: 02/03/30: Re: powerpc in virtex2pro
41493: 02/03/30: Re: PCI Compliance..
41504: 02/03/31: Re: VirtexII : Any limitation on using LVDS?
41505: 02/03/31: Re: Memory design for processor
41506: 02/03/31: Re: Compiler library ...
41525: 02/04/01: Re: powerpc in virtex2pro
41560: 02/04/02: Re: pricing and gate count info
41624: 02/04/03: Re: Pullup of Spartan-2
41630: 02/04/03: Re: powerpc in virtex2pro
41652: 02/04/04: Re: Signals pollution.
41663: 02/04/04: Re: powerpc in virtex2pro
41669: 02/04/04: Re: hand placement
41676: 02/04/04: Re: powerpc in virtex2pro
41709: 02/04/05: Re: DPLL
41747: 02/04/06: Re: Distributed ram
41757: 02/04/06: Re: Distributed ram
41758: 02/04/06: Re: strange RAM timing problem (VirtexE)
41771: 02/04/07: Re: signal delay in altera 20KE
41775: 02/04/08: Re: signal delay in altera 20KE
41834: 02/04/08: Re: 32 bit accumulator/comparator PWM?
41880: 02/04/09: Re: virtexe pin problem
42016: 02/04/12: Re: Price List ?
42048: 02/04/13: Re: new to fpga's need insight
42087: 02/04/15: Re: FPGA parameters
42114: 02/04/16: Re: Power supply pins
42120: 02/04/16: Re: Need Help to Implement Div Operation
42178: 02/04/17: Re: Reconfiguring Spartan II after boot-up
42218: 02/04/18: Re: 1000 I/O Pins -- What is cheapest FPGA?
42220: 02/04/18: Re: Understanding clock routing (or not)
42255: 02/04/18: Re: Xilinx Programmable World 2002 - Review
42349: 02/04/21: Re: Programming Spartan2 and external clock
42391: 02/04/22: Re: XC9500XL problem
42544: 02/04/26: Re: 4005XL and 4010XL compatibility
42572: 02/04/28: Re: SpartanII design considerations...
42574: 02/04/28: Re: SpartanII design considerations...
42579: 02/04/28: Re: SpartanII design considerations...
42580: 02/04/28: Re: static logic vs LUT
42590: 02/04/28: Re: Xilinx
42594: 02/04/28: Re: SpartanII design considerations...
42623: 02/04/29: Re: Does Vertex II PRO Really work?
42628: 02/04/29: Re: 4005XL and 4010XL compatibility
42632: 02/04/29: Re: SpartanII design considerations...
42636: 02/04/29: Tristate and Output Enable
42639: 02/04/29: Re: Does Vertex II PRO Really work?
42666: 02/04/30: Re: SpartanIIE hold timing
42691: 02/04/30: Virtex Evolution ( Deltas )
42722: 02/05/01: Re: Spartan outputs to 3.3V DRAMs...
42726: 02/05/01: Re: Availability of XC2S150E-6FG456I
42737: 02/05/01: Re: Availability of XC2S150E-6FG456I
42741: 02/05/01: Re: SpartanII design considerations...
42748: 02/05/02: Re: Availability of XC2S150E-6FG456I
42780: 02/05/02: Re: Availability of XC2S150E-6FG456I
42791: 02/05/02: Re: simultaneous switching of LVPECL outputs
42792: 02/05/02: Re: SpartanII design considerations...
42826: 02/05/03: Re: Frequency synthesiser
42871: 02/05/06: Re: SelectRAM and DCM
42872: 02/05/06: Re: Xilinx IOBUF?
42874: 02/05/06: Re: Xilinx IOBUF?
42891: 02/05/06: Re: Xilinx IOBUF?
42982: 02/05/08: Re: Timing of XC2S200E-6FG456C compared to XC2S200E-6FG456I
42983: 02/05/08: Re: Timing of XC2S200E-6FG456C compared to XC2S200E-6FG456I
42989: 02/05/08: Re: Timing of XC2S200E-6FG456C compared to XC2S200E-6FG456I
42990: 02/05/08: Re: Transistor Counts for Xilinx FPGAs
43019: 02/05/09: Re: JTAG 5V tollerance...?
43066: 02/05/11: Re: dual port fifo
43084: 02/05/13: Re: Neverending ISA bus interface drama, Spartan-II
43092: 02/05/13: Re: Architecture for high-level reconfigurable computing
43103: 02/05/14: Re: Architecture for high-level reconfigurable computing
43105: 02/05/14: Re: Neverending ISA bus interface drama, Spartan-II
43124: 02/05/14: Re: 50 mA sink
43125: 02/05/14: Re: Architecture for high-level reconfigurable computing
43126: 02/05/14: Re: Driving high speed external devices from an FPGA
43132: 02/05/14: Re: Architecture for high-level reconfigurable computing
43257: 02/05/17: Re: What properties has FPGA?
43258: 02/05/17: Re: Architecture for high-level reconfigurable computing
43266: 02/05/17: Re: virtex 2 block rams
43312: 02/05/18: Re: Signal Fan-out
43384: 02/05/20: Re: Xilinx 4000XLA-8: is 4 stages of logic ok?
43405: 02/05/21: Re: Addressable shift register
43426: 02/05/21: Re: Synchronous Single Clock Designs
43438: 02/05/21: Re: button & 3 LED's
43443: 02/05/21: Re: Shift register or state machine
43464: 02/05/21: Re: What properties has FPGA?
43516: 02/05/22: Re: Xilinx configuration times
43518: 02/05/22: Re: Routing in a 6200-like sea of gates
44078: 02/06/11: Re: burning a design
44079: 02/06/11: Re: Asynchronous Perhiperal Mode
44084: 02/06/11: Re: fpga and ultra highspeed counters
44091: 02/06/11: Re: Problems initialising an FPGA - SPARTAN II
44098: 02/06/11: Re: fpga and ultra highspeed counters
44099: 02/06/11: Re: 20,000 gates?
44150: 02/06/12: Re: 20,000 gates?
44165: 02/06/13: Re: clock gating by any other name...
44210: 02/06/13: Re: must signals to ram come from a register?
44215: 02/06/14: Re: new to fpga.
44220: 02/06/14: Re: 20,000 gates?
44267: 02/06/15: Re: TTL library in Xilinx?
44278: 02/06/16: Re: fpga and ultra highspeed counters
44292: 02/06/16: Re: Which is greater?
44326: 02/06/18: Re: Internal oscillator in CPLD?
44356: 02/06/18: Re: what's the use of BlockRAM
44411: 02/06/19: Re: what's the use of BlockRAM
44532: 02/06/22: Re: Xilinx's 4.1i's Lastest webpack
44623: 02/06/25: Re: too hot fpga device
44656: 02/06/26: Re: too hot fpga device
44701: 02/06/27: Re: 5V tolerance
44712: 02/06/27: Re: VIRTEX II DCM Question
44722: 02/06/28: Re: Who near London UK can burn a Xilinx SPROM ?
44727: 02/06/28: Re: VIRTEX II DCM Question
44733: 02/06/28: Re: VIRTEX II DCM Question
44742: 02/06/28: Re: Problem: Designing for older FPGAs
44744: 02/06/28: Re: State machine and syncronous inputs
44753: 02/06/29: Re: XC9572 VCCIO change
44769: 02/06/30: Re: 5V tolerance
44770: 02/06/30: Re: virtex2 : 180 deg. phase clocks
44797: 02/07/01: Re: Xpower accuracy (is there anybody from Xilinx out there ?)
44807: 02/07/01: Re: VIRTEX II DCM Question
44809: 02/07/02: Re: Converting Altera Block Ram to Xilinx Block Ram
44814: 02/07/02: Re: Xilinx's 4.1i's Lastest webpack
44835: 02/07/02: Re: Virtex II - Assigning Pins before routing?
44840: 02/07/02: Re: Virtex II - Assigning Pins before routing?
44848: 02/07/02: Re: Converting to Altera Quartus
44883: 02/07/03: Re: Converting to Altera Quartus
44971: 02/07/08: Re: Are these design guideline safe ?
44978: 02/07/08: Re: SpartanXL,2E: How many flipflops on one clock-net?
45019: 02/07/10: Re: 32 bit multiplier (1 cycle)
45041: 02/07/10: Re: LUT and Xilinx Distributed SelectRam
45082: 02/07/11: Re: Virtex II - What to do with unused banks?
45112: 02/07/12: Re: Actel 3.3v to 5v
45116: 02/07/12: Re: Accurate Oscillator
45122: 02/07/12: Re: 5V input to CLOCK on Xilinx Spartan 2
45123: 02/07/12: Re: 5V input to CLOCK on Xilinx Spartan 2
45155: 02/07/14: Re: What proportion of an FPGA's configuration data is used for routing?
45157: 02/07/14: Re: serial configuration in parallel? Xilinx Spartan-II
45167: 02/07/14: Re: What proportion of an FPGA's configuration data is used for routing?
45201: 02/07/15: Re: Which is best method for register with settable and clearable bits
45218: 02/07/16: Re: problem porting sync write, async read RAM to Xilinx...
45270: 02/07/17: Re: problem with configuration of spartan2e
45280: 02/07/17: Re: Commercial FPGA Architectures
45337: 02/07/19: Re: Counter Metrics
46115: 02/08/19: Re: rising_edge detector?
46119: 02/08/19: Re: rising_edge detector?
46243: 02/08/22: Re: onboard reconfiguration of Xilinx FPGA
46249: 02/08/22: Re: Downloading bit streams in Xilinx
46254: 02/08/22: Re: Downloading bit streams in Xilinx
46303: 02/08/25: Re: Can I directly connect XTAL to SpartanXL ?
46310: 02/08/25: Re: sensing an oscillator
46338: 02/08/26: Re: need cheap and dirty time delay for spartan2e
46358: 02/08/27: Re: FPGA speed level
46376: 02/08/27: Re: Any FSM optimizer?
46387: 02/08/28: Re: Any FSM optimizer?
46404: 02/08/28: Re: Any FSM optimizer?
46412: 02/08/28: Re: Any FSM optimizer?
46427: 02/08/29: Re: My SpartanII thinks it's a Virtex??
46438: 02/08/29: Re: gate the main FPGA clk
46470: 02/08/30: Re: gate the main FPGA clk
46471: 02/08/30: The Prodigal Son
46474: 02/08/30: Re: Silicon lifetime
46497: 02/09/01: Re: Thermoelectric Controller by FPGAs
46506: 02/09/02: Re: In 2 clk domains. How to xfer data from 1 bus to the another ?
46590: 02/09/04: Re: choice of fpga
46694: 02/09/05: Re: question about quiescent current
46721: 02/09/06: Re: Performance degradation when put on an FPGA ?
46741: 02/09/06: Re: XCR3384XL availability
46745: 02/09/06: Metastability numbers
46760: 02/09/07: Re: Fault tolerant FPGA design
46761: 02/09/07: Re: Metastability numbers, even better!
46773: 02/09/08: Re: Metastability numbers, even better!
46785: 02/09/09: Re: minimalist FPGA system
46787: 02/09/09: Re: Metastability numbers
46807: 02/09/09: Re: XCR3384XL availability
46816: 02/09/09: Re: Metastability numbers
46818: 02/09/09: Re: Metastability numbers
46822: 02/09/09: Re: Metastability numbers
46824: 02/09/09: Re: Metastability numbers
46839: 02/09/10: Re: XCR3384XL availability
46872: 02/09/10: Re: XCR3384XL availability
46884: 02/09/10: Re: XCR3384XL availability
46888: 02/09/10: Re: XCR3384XL availability
46943: 02/09/12: Re: Xilinx LogicCore Pipelined Divider at 4 Clocks/Division
46976: 02/09/13: Re: exploiting metastability
47016: 02/09/14: Re: Clcok divison : Rational clock divider
47083: 02/09/16: Re: Multiple divide by 10
47124: 02/09/18: Re: Multiple divide by 10
47135: 02/09/18: Re: using CPLD's inverter in oscillator circuit
47136: 02/09/18: Re: State of FPGA I/O pins before programming
47141: 02/09/18: Re: Xilinx Spartan II PIN Status?
47175: 02/09/19: Re: Overheat with XCV-600E
47181: 02/09/20: Re: Multiple divide by 10
47214: 02/09/20: Re: Question on Spartan2E maximum toggle frequency
47228: 02/09/20: Re: Multiple divide by 10
47236: 02/09/20: Re: pulldown resistor value for Xilinx CPLD
47257: 02/09/21: Re: Can a fpga replace external inverters in a crystal osc ?
47320: 02/09/23: Re: MTBF
47330: 02/09/24: Re: MTBF
47351: 02/09/24: Re: fpga comparisons???
47356: 02/09/24: Re: FPGA fail when Electrostatic discharge Occurs
47372: 02/09/24: Re: Spartan II JTAG reconfiguration bug - workaround
47376: 02/09/24: Re: Altera Cyclone low-cost FPGA chips?
47390: 02/09/25: Re: MTBF
47391: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
47392: 02/09/25: Re: Where can I get XC6200 series FPGAs
47435: 02/09/25: Re: pulldown resistor value for Xilinx CPLD
47443: 02/09/25: Re: Virtex2 Block Multiplier: Faster, Faster
47505: 02/09/27: Re: Altera Cyclone 'FPGA'
47506: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47524: 02/09/27: Re: Is it possible to build a Ring Oscillator in an FPGA chip?
47571: 02/09/29: Re: design multiplier
47612: 02/09/30: Re: design multiplier
47713: 02/10/02: Re: AMD9513 Timer Chip
47715: 02/10/02: Re: Block Ram Timing Issues
47718: 02/10/02: Re: Moving average filter
47720: 02/10/02: Re: virtex 2 -5i vs -6
47721: 02/10/02: Re: Block Ram Timing Issues
47856: 02/10/05: Re: DDS in PLD?
47925: 02/10/07: Re: .13 micron - what does it indicate
48091: 02/10/10: Re: Sync Reset without clocks
48226: 02/10/14: Re: A nice one-off project for a competent UK based FPGA designer :)
48227: 02/10/14: Re: Spartan II: CLKDLL
48273: 02/10/15: Re: Sync Reset without clocks
48356: 02/10/16: Re: Delay elements using the schematic editor (Xilinx)
48430: 02/10/17: Re: multiple clocks
48441: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48451: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48455: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48461: 02/10/17: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
48660: 02/10/22: Re: slow slew rate signal...
48674: 02/10/22: Re: clock divider
48692: 02/10/22: Re: clock divider
48695: 02/10/22: Re: 6502 core available
48738: 02/10/23: Re: slow slew rate signal...
48739: 02/10/23: Re: slow slew rate signal...
48754: 02/10/23: Re: clock divider
48807: 02/10/24: Re: Xilinx POS Power On Surge Current
48873: 02/10/25: Re: What speed grade do I have?
48915: 02/10/26: Re: Crystal oscillator question
48916: 02/10/26: Re: FPGA XC4005E
48917: 02/10/26: Re: for what do you use fpga's
49053: 02/10/30: Re: Concepts: What is "Clock Edge"?
49086: 02/10/31: Re: Concepts: What is "Clock Edge"?
49089: 02/10/31: Re: Concepts: What is "Clock Edge"?
49091: 02/10/31: Re: BLOCK RAM : FIFO implementation
49101: 02/10/31: Re: Simple question on Xilinx CPLD 9500
49102: 02/10/31: Re: Concepts: What is "Clock Edge"?
49103: 02/10/31: Metastability results are finally posted
49142: 02/11/01: Re: BLOCK RAM : FIFO implementation
49143: 02/11/01: Re: Asynchronous clock enable with stable data
49160: 02/11/03: Re: Asynchronous clock enable with stable data
49183: 02/11/04: Re: Excessive heating on Xilinx XC9500XL
49201: 02/11/04: Re: Excessive heating on Xilinx XC9500XL
49278: 02/11/07: Re: LUT Consumption in Virtex-2
49279: 02/11/07: Re: Instruction sets to implement instruction sets
49307: 02/11/08: Re: functional test for Xilinx virtex II Pro
49309: 02/11/08: Re: functional test for Xilinx virtex II Pro
50111: 02/12/02: Re: MetaStability Issue on BRAMs
50150: 02/12/03: Re: block and distributed RAM
50222: 02/12/05: Re: clock difference between DLL input and output?
50232: 02/12/05: Re: series termination question
50250: 02/12/06: Re: meaning of system gates vs. logic gates?
50476: 02/12/11: Re: partial Bitstream Size in Virtex-II
50498: 02/12/11: Re: Power consumption question
50515: 02/12/11: Re: Power consumption question
50555: 02/12/12: Re: MTBF Calculation
50603: 02/12/13: Re: MTBF Calculation
50667: 02/12/16: Re: Matrics Memory controller
50674: 02/12/16: Re: Matrics Memory controller
50740: 02/12/18: Re: How to asynchronously reset a flip-flop?
50741: 02/12/18: Re: A/D converter in FPGA
50747: 02/12/18: Re: How to asynchronously reset a flip-flop?
50750: 02/12/18: Re: How to asynchronously reset a flip-flop?
50799: 02/12/19: Re: Async RAM on an FPGA board
50804: 02/12/19: Re: What voltage level is considered as "floating"?
50805: 02/12/19: Re: Hi xilinx
50834: 02/12/20: Re: 16-bit LFSR
50845: 02/12/20: Re: How to handle Fautly Interconnection in Virtex ?
50856: 02/12/20: Re: thermal issues on FPGA
50857: 02/12/20: Re: Virtex2Pro question
50939: 02/12/23: Re: How to generate a clock signal for CPLD?
50949: 02/12/23: Re: thermal issues on FPGA
51037: 02/12/27: Re: sram cells
51055: 02/12/28: Re: Virtex architecture newbie question
51093: 02/12/31: Re: Unused FPGA I/O Pins?
51105: 03/01/01: Re: Unused FPGA I/O Pins?
51127: 03/01/02: Re: Running 2 inter related programs on the FPGA
51128: 03/01/02: Re: interface DRAM to FPGA
51140: 03/01/03: Re: Alternative to theXilinx XC4005E
51142: 03/01/03: Re: interface DRAM to FPGA
51144: 03/01/03: Re: interface DRAM to FPGA
51148: 03/01/03: Re: Running 2 inter related programs on the FPGA
51169: 03/01/04: Re: interface DRAM to FPGA
51170: 03/01/04: Re: Dynamic Reconfiguration
51198: 03/01/06: Re: asynchronous inputs
51258: 03/01/08: Re: 4-bit excess-3 counter with parallel load
51281: 03/01/09: Re: Power usage of CLOCK in FPGA
51283: 03/01/09: Re: Virtex-II Pro misfire?
51319: 03/01/10: Re: Virtex-II Pro misfire?
51321: 03/01/10: Re: Power usage of CLOCK in FPGA
51330: 03/01/10: Re: shift register implementation
51331: 03/01/10: Re: Virtex-II Pro misfire?
51334: 03/01/10: Re: Virtex-II Pro misfire?
51423: 03/01/13: Re: Virtex-II Pro misfire?
51443: 03/01/13: Re: Open FPGA please!
51485: 03/01/14: Re: Open FPGA please!
51526: 03/01/15: Re: Short FIFO in Verilog / Spartan IIE
51527: 03/01/15: Re: Short FIFO in Verilog / Spartan IIE
51654: 03/01/17: Re: Booting Spartan IIE from SPI
51728: 03/01/20: Re: frequency matching of ring oscillators
51771: 03/01/21: Re: Ram bits for Registers
51958: 03/01/27: Re: What's the difference between LUT and RAM?
51959: 03/01/27: Re: New to FPGA world...need guidline/help
51996: 03/01/28: Re: Carry Logic propagation delay
52000: 03/01/28: Re: XC3020 .nph
52009: 03/01/28: Re: Random number generator
52019: 03/01/28: Re: XC3020 .nph
52045: 03/01/29: Re: Xilinx memory size
52050: 03/01/29: Re: Reconfigure only some elements
52054: 03/01/29: Re: Reconfigure only some elements
52232: 03/02/04: Re: Clock Enables
52281: 03/02/05: Re: Clock Enables
52312: 03/02/06: Re: Clock Enables
52328: 03/02/06: Re: debounce circuit
52378: 03/02/07: Re: Divide clock frequency by 1.5: output duty cycle is not 50%
52527: 03/02/12: Re: Fractional Divide
52561: 03/02/13: Easy links to Xilinx documentation
52669: 03/02/18: Re: Xilinx Virtex-IIP multipliers
52693: 03/02/19: Re: Should I choose Xilink or Altera for a small project
52700: 03/02/19: Re: PCB Design for a Xilinx Spartan-II FPGA
52752: 03/02/20: Re: Should I choose Xilink or Altera for a small project
52758: 03/02/20: Re: Should I choose Xilink or Altera for a small project
52785: 03/02/21: Re: Gate boosting
52859: 03/02/24: Re: FPGA's at High Temperatures
52862: 03/02/24: Re: help me figure out this problem?
52900: 03/02/25: Re: Delay element in Virtex2
52907: 03/02/25: Re: Unprogrammed XC9536XL is driving the databus high
52947: 03/02/26: Re: Spartan II PCB, I/O pins consederations
52948: 03/02/26: Re: FPGA arch.
53011: 03/02/28: Re: 10 MHz Clock out of 30 MHz
53013: 03/02/28: Re: How to maintain pipeline delays
53016: 03/02/28: Re: IBUF : Pullup Resistors
53022: 03/02/28: Re: 10 MHz Clock out of 30 MHz
53026: 03/02/28: Re: IBUF : Pullup Resistors
53032: 03/02/28: Re: 10 MHz Clock out of 30 MHz
53034: 03/02/28: Re: FPGA programming question.
53037: 03/02/28: Re: FPGA programming question.
53039: 03/02/28: Re: FPGA programming question.
53146: 03/03/04: Re: How to select the chip before using FPGA?
53150: 03/03/04: Re: Implementation of latch in FPGA
53222: 03/03/06: Re: Implementation of latch in FPGA
53247: 03/03/07: Re: Implementation of latch in FPGA
53248: 03/03/07: Re: Current Consumption/Limitation Upon Output
53300: 03/03/10: Re: Cyclone power up problem
53301: 03/03/10: Re: Implementation of latch in FPGA
53303: 03/03/10: Re: comp.arch.fpga : VCC shorted to GND within FPGA???
53309: 03/03/10: Re: Using divided clock
53320: 03/03/10: Re: Are there any FPGA magazines/journals?
53351: 03/03/11: Re: Can you recommend a text on...?
53380: 03/03/12: Re: RESET --- Synchronous Vs Asynchronous
53446: 03/03/13: Re: Adding delay to a signal?
53447: 03/03/13: Re: RESET --- Synchronous Vs Asynchronous
53453: 03/03/13: Re: Cyclone power up problem
53461: 03/03/13: Re: RESET --- Synchronous Vs Asynchronous
53467: 03/03/13: Re: Using divided clock
53478: 03/03/13: Re: Adding delay to a signal?
53505: 03/03/14: Re: Using divided clock
53631: 03/03/18: Re: Low Power CPLD suggestion request...
53638: 03/03/18: Re: RESET --- Synchronous Vs Asynchronous
53641: 03/03/18: Re: Conversion of Xilinx bit file
53716: 03/03/20: Re: FPGA programming question.
53722: 03/03/20: Re: FPGA choice (UK)
53806: 03/03/24: Re: Difference between static and active partial reconfiguration of
53808: 03/03/24: Re: Xilinx FPGAs available?
53822: 03/03/24: Re: Xilinx FPGAs available?
53893: 03/03/26: Re: FPGA specs
53925: 03/03/27: Re: Tristate pins + Inputs => External Pullup ?
54211: 03/04/04: Re: Xilinx announces 90nm sampling today!
54221: 03/04/04: Re: Xilinx announces 90nm sampling today!
54308: 03/04/07: Re: Spartan-3 in docsan Webpack release notes... a joke???
54312: 03/04/07: Re: Spartan-3 in docsan Webpack release notes... a joke???
54344: 03/04/08: Re: OK, where does an FPGA newbie start?
54502: 03/04/11: Re: Double Edge FlipFlop
54578: 03/04/14: Re: request for simple UART
54581: 03/04/14: Re: Tristate-Bus-Termination; fast pullup req'd
54598: 03/04/14: Re: error correcting codes
54605: 03/04/14: Re: Xilinx has released SpartanIII
54610: 03/04/14: Re: Xilinx has released SpartanIII
54775: 03/04/17: Re: SpartanIII Partial Reconfiguration
54784: 03/04/17: Re: Permanent Local Damage to FPGA
54814: 03/04/18: Re: LFSR MAXIMUM LENGTH
55025: 03/04/24: Re: bidirectional bus
55089: 03/04/25: Re: max BlockRam speed
55112: 03/04/27: Re: visualising a shift register using an LUT
55137: 03/04/28: Re: 4 bit Multiplier and Divider
55179: 03/04/29: Re: Xilinx XAct
55184: 03/04/29: Re: Virtex-II DCM frequency synthesizer
55260: 03/05/01: Re: Schmitt Trigger an a Virtex
55261: 03/05/01: Re: programmable oscillators
55262: 03/05/01: Re: Schmitt Trigger an a Virtex
55263: 03/05/01: Re: Schmitt Trigger an a Virtex
55291: 03/05/02: Re: Thermal Data for Logic Devices
55295: 03/05/02: Re: Thermal Data for Logic Devices
55296: 03/05/02: Re: Schmitt Trigger an a Virtex
55301: 03/05/02: Re: I want a 800 k gates FPGA in 40 pin DIL
55354: 03/05/05: Re: Output switching time
55429: 03/05/07: Re: Xilinx configuration flash/proms
55455: 03/05/08: Re: Xilinx configuration flash/proms
55490: 03/05/09: Re: help on FPGA-programming tutorial for students
55491: 03/05/09: Re: Encrypted bitstream - battery lifetime problem
55600: 03/05/13: Re: OK I am pissed off with Xilinx webpack.
55670: 03/05/15: Re: Low power, high temperature CPLD
55672: 03/05/15: Re: Low power, high temperature CPLD
55680: 03/05/15: Re: Large Fifos
55681: 03/05/15: Re: Low power, high temperature CPLD
55687: 03/05/15: Re: Low power, high temperature CPLD
55715: 03/05/16: Re: smallest embedded cpu.
55720: 03/05/16: Re: Output switching time
55767: 03/05/19: Re: FPGA: Feasibility of Memory testing
55768: 03/05/19: Re: smallest embedded cpu....and the most pain?
55782: 03/05/19: Re: FPGA: Feasibility of Memory testing
55895: 03/05/22: Re: Nois generator - project
55921: 03/05/23: Re: Nois generator - project
55927: 03/05/23: Re: Nois generator - project
55938: 03/05/23: Re: Nois generator - project
55941: 03/05/23: Re: Can I implement frequency multiplier using FPGA/CPLD?
56029: 03/05/27: Re: High-Speed Clock & Data Recovery
56088: 03/05/28: Re: FIFO Controller
56095: 03/05/28: Re: FIFO Controller
56097: 03/05/28: Re: Nois generator - project
56154: 03/05/29: Re: FIFO Controller
56155: 03/05/29: Re: FIFO Controller
56158: 03/05/29: Re: FIFO Controller
56162: 03/05/29: Re: Antifuse and SRAM FPGA
56168: 03/05/29: Re: FPGA's an Flash
56174: 03/05/29: Re: smallest embedded cpu....and the most pain?
56178: 03/05/29: Re: Antifuse and SRAM FPGA
56182: 03/05/29: Re: Antifuse and SRAM FPGA
56214: 03/05/30: Re: FPGA's an Flash
56289: 03/06/02: Re: FPGA's an Flash
56290: 03/06/02: Re: FPGA's an Flash
56292: 03/06/02: Re: DES-encrypt, Spartan3, was Re: FPGA's an Flash
56294: 03/06/02: Re: power consumption in CMOS..
56342: 03/06/03: Re: size of SRAM, antifuses and EPROM elements
56346: 03/06/03: Re: DES-encrypt, Spartan3, was Re: FPGA's an Flash
56354: 03/06/03: Re: FPGA's an Flash
56357: 03/06/03: Re: FPGA's an Flash
56406: 03/06/04: Re: DES-encrypt, Spartan3, was Re: FPGA's an Flash
56420: 03/06/04: Re: FPGA's an Flash
56422: 03/06/04: Re: Clk between multiple boards
56452: 03/06/05: Re: Xilinx Block RAM
56466: 03/06/05: Re: Clk between multiple boards
56489: 03/06/06: using USB
56490: 03/06/06: Re: using USB
56562: 03/06/09: Re: Controlling FPGA speed with VCCINT
56619: 03/06/10: Re: Pseudo random shift register - > DAC
56623: 03/06/10: Re: What's in a bitstream?
56633: 03/06/10: Re: Pseudo random shift register - > DAC
56639: 03/06/10: Re: Shift registers
56645: 03/06/10: Re: Shift registers
56685: 03/06/11: Re: Pseudo random shift register - > DAC
56687: 03/06/11: Re: DVI with a Virtex-II - summary
56688: 03/06/11: Re: Drive Capabilities of the FPGA
56704: 03/06/11: Re: DVI with a Virtex-II - summary
56706: 03/06/11: Re: Virtex 2 evaluation board
56707: 03/06/11: Re: DVI with a Virtex-II - summary
56723: 03/06/12: Re: DVI with a Virtex-II
56732: 03/06/12: Re: DVI with a Virtex-II
56735: 03/06/12: Re: Analog signals connected to xilinx spartan2
56736: 03/06/12: Re: Analog signals connected to xilinx spartan2
56759: 03/06/13: Re: Power consumed in a non configured FPGA?
56805: 03/06/16: Re: Power consumed in a non configured FPGA?
56807: 03/06/16: Re: spartan 2e dll locking
56813: 03/06/16: Re: DVI with a Virtex-II
56815: 03/06/16: Re: DVI with a Virtex-II
56827: 03/06/16: Re: Power consumed in a non configured FPGA?
56899: 03/06/18: Re: XCV 6000 data sheets
56901: 03/06/18: Re: XCV 6000 data sheets
56907: 03/06/18: Re: Cyclone vs. Acex consumption?
56917: 03/06/18: Re: Power consumed in a non configured FPGA?
56919: 03/06/18: Re: Power consumed in a non configured FPGA?
56971: 03/06/19: Re: Dr. Leaky responds
57008: 03/06/20: Re: Multiple clock generation and maybe FIFO
57110: 03/06/23: Re: Programmable Delay (not clock driven)
57145: 03/06/24: Re: How to get 27MHz from 10 MHz in FPGA???
57146: 03/06/24: Re: Transfer between clock domains at 350 MHz
57152: 03/06/24: Re: How to get 27MHz from 10 MHz in FPGA???
57194: 03/06/25: Re: Interfacing IDE
57208: 03/06/25: Re: Max Allowable Clock Skew on local Clocks - Spartan-II -5
57210: 03/06/25: Re: Xilinx XC3430A
57259: 03/06/26: Re: Low-power FPGA
57275: 03/06/26: Re: why so many problems Xilinx ?
57281: 03/06/26: Re: Low-power FPGA
57396: 03/06/29: Re: why so many problems Xilinx ?
57431: 03/06/30: Re: Asynchronous RESET?
57442: 03/06/30: Re: Asynchronous RESET?
57445: 03/06/30: Re: 48bit adder won't fit
57486: 03/07/01: Re: why so many problems Xilinx ?
57489: 03/07/01: Re: Cyclone vs Spartan-3
57491: 03/07/01: Re: Asynchronous RESET?
57493: 03/07/01: Re: Cyclone vs Spartan-3
57500: 03/07/01: Re: Cyclone vs Spartan-3
57510: 03/07/01: Re: Cyclone vs Spartan-3
57512: 03/07/01: Re: SPARTAN-3 vs. VIRTEX-II
57428: 03/06/30: Re: Asynchronous RESET?
57566: 03/07/02: Re: How to get 27MHz from 10 MHz in FPGA???
57569: 03/07/02: Re: why so many problems Xilinx ?
57571: 03/07/02: Re: why so many problems Xilinx ?
57581: 03/07/02: Re: Fixed point signed multiplication algorithm
57591: 03/07/02: Re: How to get 27MHz from 10 MHz in FPGA???
57607: 03/07/02: Re: UART -- Process variable setup times and propogations
57653: 03/07/03: Re: Spartan-3 availability
57660: 03/07/03: Re: Xilinx ISE drops support for more parts
57677: 03/07/03: Re: Cyclone vs Spartan-3
57688: 03/07/03: Re: Xilinx ISE drops support for more parts
57791: 03/07/07: Re: DCM usage question
57793: 03/07/07: Re: information required
57819: 03/07/07: Re: XPLA3 vs. MAX3000A
57820: 03/07/07: Re: Pulse stretching
57849: 03/07/08: Re: phase noise in NCO
57923: 03/07/09: Re: division
57948: 03/07/10: Re: Xilinx Spartan-3 samples, how to get?
57956: 03/07/10: Re: okay what am I missing??? Please
58057: 03/07/13: Re: Missing something...
58058: 03/07/13: Re: Combinational logic and gate delays - Help
58091: 03/07/14: Re: Combinational logic and gate delays - Help
58092: 03/07/14: Re: Combinational logic and gate delays - Help
58135: 03/07/15: Re: PROM size for spartan
58231: 03/07/17: Re: Digital Design with just one clock at one edge
58303: 03/07/19: Re: Phase / frequency detector types
58346: 03/07/21: Re: Phase / frequency detector types
58356: 03/07/21: Re: asynchronous FIFO
58367: 03/07/21: Re: Distributed RAM
58368: 03/07/21: Re: asynchronous FIFO
58389: 03/07/22: Re: asynchronous FIFO
58391: 03/07/22: Re: Distributed RAM
58395: 03/07/22: Re: Phase / frequency detector types
58396: 03/07/22: Re: asynchronous FIFO
58433: 03/07/23: Re: asynchronous FIFO
58434: 03/07/23: Re: asynchronous FIFO
58439: 03/07/23: Re: asynchronous FIFO
58449: 03/07/23: Re: Pricing question....
58478: 03/07/24: Re: Pricing question....
58500: 03/07/24: Re: Active Probe
58539: 03/07/25: Re: Reseting the whole thing
58596: 03/07/28: Re: xilinx programing interface
58720: 03/07/31: Re: DDS question. How to generate a square from a sine wave?
58725: 03/07/31: Re: Altera-to-Xilinx IO 3.3V -> 1.8V
58727: 03/07/31: Re: DDS question. How to generate a square from a sine wave?
58734: 03/07/31: Re: DDS question. How to generate a square from a sine wave?
58737: 03/07/31: Re: binary to BCD assistance
58741: 03/07/31: Re: Question: String matching with CAM?
58742: 03/07/31: Re: DDS question. How to generate a square from a sine wave?
58793: 03/08/01: Re: PLL / DPLL phase question
58795: 03/08/01: Re: Speed Grade...
58805: 03/08/01: Re: DDS question. How to generate a square from a sine wave?
58821: 03/08/01: Re: DDS question. How to generate a square from a sine wave?
58984: 03/08/05: Re: Block ram simulation
58985: 03/08/05: Re: model sim block ram sim
58991: 03/08/05: Re: model sim block ram sim
59017: 03/08/06: Re: Gates Counting?
59035: 03/08/06: Re: FPGAs: basic question: two-level AND-OR vs. two-level OR-AND
59062: 03/08/07: Re: Spartan-IIE LVDS?
59114: 03/08/08: Re: Virtex-E power trace
59116: 03/08/08: Re: Clocking in a virtex 2 without using the clock trees : questions
59123: 03/08/08: Re: reconfiguration time
59177: 03/08/11: Re: Pad-to-pad hold time
59178: 03/08/11: Re: Q: async flip-flop reset by a signal from a different clock domain
59182: 03/08/11: Re: Virtex "Virtual VCC"
59184: 03/08/11: Re: async flip-flop reset by a signal from a different clock domain
59217: 03/08/12: Re: Virtex "Virtual VCC"
59218: 03/08/12: Re: Non volatile implementation of Xc2s100
59225: 03/08/12: Re: Datasheet for National PAL20L10
59307: 03/08/14: Re: Old Xilinx FPGAs
59320: 03/08/14: Re: Old Xilinx FPGAs
59397: 03/08/18: Re: Old Xilinx FPGAs
59409: 03/08/18: Re: DDFS question
59441: 03/08/19: Re: DDFS question
59452: 03/08/19: Re: DDFS question
59481: 03/08/20: Re: Xilinx XC3000 with Xilinx ISE student edition 4.2i
59501: 03/08/20: Re: Xilinx FPGA pin locking/assignment
59513: 03/08/20: Re: Xilinx XC3000 with Xilinx ISE student edition 4.2i
59518: 03/08/20: Re: DCM vs state machine
59521: 03/08/20: Re: DCM vs state machine
59549: 03/08/21: Re: DCM vs state machine
59554: 03/08/21: Re: DCM vs state machine
59567: 03/08/21: Re: DCM vs state machine
59636: 03/08/25: Re: What is the context switching time
59640: 03/08/25: Re: Thinking out loud about metastability
59644: 03/08/25: Re: Thinking out loud about metastability
59659: 03/08/25: Re: Thinking out loud about metastability
59663: 03/08/25: Re: Two near-identicial clocks?
59703: 03/08/26: Re: FPGA minimum operating frequencies
59706: 03/08/26: Re: Thinking out loud about metastability
59708: 03/08/26: Re: Free FPGA samples anywhere?
59715: 03/08/26: Re: What is the context switching time
59744: 03/08/27: Re: Thinking out loud about metastability
59745: 03/08/27: Re: Asynchronous clock switching circuits vs. BUFGMUX
59746: 03/08/27: Re: Thinking out loud about metastability
59756: 03/08/27: Re: Thinking out loud about metastability
59786: 03/08/28: Re: Thinking out loud about metastability
59787: 03/08/28: Re: pricing, cyclone or spartan
59788: 03/08/28: Re: Is Platform Flash PROM an electrically erasable??
59814: 03/08/28: Re: Selecting between two clock signals
59815: 03/08/28: Re: Thinking out loud about metastability
59816: 03/08/28: Re: Selecting between two clock signals
59858: 03/08/29: Re: pricing, cyclone or spartan
59859: 03/08/29: Re: Selecting between two clock signals
60230: 03/09/08: Re: Original (5V) Xilinx Spartan ?
60278: 03/09/09: Re: Original (5V) Xilinx Spartan ?
60286: 03/09/09: Re: Power-on slope :Spartan IIE
60289: 03/09/09: Re: opinions are OK
60314: 03/09/10: Re: Original (5V) Xilinx Spartan ?
60316: 03/09/10: Re: Crystal Input to FPGA
60337: 03/09/10: Re: Original (5V) Xilinx Spartan ?
60339: 03/09/10: Re: Crystal Input to FPGA
60364: 03/09/11: Re: Metatstable Modeling
60372: 03/09/11: Re: Metatstable Modeling
60377: 03/09/11: Re: Paging Peter Alfke (3S1000 pricing)
60382: 03/09/11: Re: Metatstable Modeling
60436: 03/09/12: Re: Xilinx S3 I/O robustness question
60440: 03/09/12: Re: Xilinx S3 I/O robustness question
60510: 03/09/15: Re: Paging Peter Alfke (3S1000 pricing)
60552: 03/09/16: Re: Original (5V) Xilinx Spartan ?
60608: 03/09/17: Re: Xilinx
60609: 03/09/17: Re: Xilinx
60617: 03/09/17: Re: Xilinx
60630: 03/09/17: Re: Xilinx
60642: 03/09/18: Re: Using LUTs for array of coefficients
60643: 03/09/18: Re: Xilinx
60663: 03/09/18: Re: divide by on spartan3?
60695: 03/09/19: Re: Xilinx
60696: 03/09/19: Re: Some question about using FPGA
60697: 03/09/19: Re: divide by on spartan3?
60711: 03/09/19: Re: Questions about XPower
60713: 03/09/19: Re: ORCA fpga?
60723: 03/09/19: Re: Transistor count
60774: 03/09/22: Re: Transistor count
60776: 03/09/22: Re: show-ahead FIFOs
60777: 03/09/22: Re: Configuration Options:
60779: 03/09/22: Re: Regarding XC6216
60780: 03/09/22: Re: Moderator of comp.arch.fpga
60782: 03/09/22: Re: Synchronous counter enable pulse length
60799: 03/09/22: Re: Synchronous counter enable pulse length
60800: 03/09/22: Re: Synchronous counter enable pulse length
60832: 03/09/23: Re: Regarding XC6216
60834: 03/09/23: Re: Synchronous counter enable pulse length
60835: 03/09/23: Re: Synchronous counter enable pulse length
60840: 03/09/23: Re: New to VHDL for Xilinx
60858: 03/09/23: Re: Regarding XC6216
60859: 03/09/23: Re: FPGA implementation in (V)HDL
60886: 03/09/24: Re: Regulator for Spartan 2
60887: 03/09/24: Re: FPGA implementation in (V)HDL
60913: 03/09/24: Re: Regulator for Spartan 2
60947: 03/09/25: Re: Synchronous Binary counter question.
60958: 03/09/25: Re: Regulator for Spartan 2
60964: 03/09/25: Nanometers, Gigahertz, and Femtoseconds
60966: 03/09/25: Re: Reducing Clock Speed
61056: 03/09/26: Re: Synchronous Binary counter question.
61157: 03/09/29: Re: Spartan 2e implementation
61226: 03/09/30: Re: Counting ones
61538: 03/10/06: Re: Should I worry about metastability
61602: 03/10/07: Re: Xilinx courses
61775: 03/10/10: Re: Counting ones
61788: 03/10/10: Re: Counting ones
61818: 03/10/13: Re: How to select a FPGA
61824: 03/10/13: Re: Please Help: Looking for XC3064 PLCC-84...
61863: 03/10/14: Re: How to program an XC5210
61865: 03/10/14: Re: Xilinx Logic Handbook
61869: 03/10/14: Re: SpartanXL
61871: 03/10/14: Re: Electronic Dice ( 3 die ) In VHDL
61881: 03/10/14: Re: Electronic Dice ( 3 die ) In VHDL
61896: 03/10/14: Re: How to program an XC5210
61951: 03/10/15: To our future engineers, smart and otherwise...
62007: 03/10/16: Re: SpartanXL
62060: 03/10/17: Re: Should I worry about metastability
62302: 03/10/24: Re: Are clock and divided clock synchronous?
62343: 03/10/27: Re: Are clock and divided clock synchronous?
62394: 03/10/28: Re: Are clock and divided clock synchronous?
62422: 03/10/29: Re: How to protect fpga based design against cloning?
62426: 03/10/29: Re: Virtex-II DCM frequency synthesizer
62432: 03/10/29: Re: Are clock and divided clock synchronous?
62434: 03/10/29: Re: Xilinx Spartan3: Price
62438: 03/10/29: Re: Xilinx Spartan3: Price
62447: 03/10/29: Re: How to protect fpga based design against cloning?
62483: 03/10/30: Re: Xilinx Spartan3: Price
62484: 03/10/30: Re: How to protect fpga based design against cloning?
62488: 03/10/30: Re: How to protect fpga based design against cloning?
62493: 03/10/30: Re: DDFS technique problem in generating a few clocks
62515: 03/10/31: Re: Essential hazards in CPLD's?
62532: 03/10/31: Re: Floating Point support
62536: 03/10/31: Re: Electronic News Article on 90 nm soft error FUD
62633: 03/11/03: Re: Using the Virtex Block Select RAM+ Features
62670: 03/11/04: Re: Xilinx - Multi Volt Interfacing
62674: 03/11/04: Re: I/O on current FPGAs - deserialise first ??
62757: 03/11/06: Re: Arithmetics with carry
62811: 03/11/07: Re: Arithmetics with carry
62895: 03/11/10: Re: Implementing a very fast counterin VirtexII
62901: 03/11/10: Re: Implementing a very fast counterin VirtexII
62943: 03/11/11: Re: Transforming vector position to binary value
62945: 03/11/11: Re: Implementing a very fast counterin VirtexII
62961: 03/11/11: Re: Implementing a very fast counterin VirtexII
62964: 03/11/11: Re: Home grown CPU core legal?
62975: 03/11/11: Re: Implementing a very fast counterin VirtexII
62976: 03/11/11: Re: Home grown CPU core legal?
63008: 03/11/12: Re: Implementing a very fast counterin VirtexII
63009: 03/11/12: Re: Transforming vector position to binary value
63020: 03/11/12: Re: Frequency Doubler - VHDL/Verilog
63025: 03/11/12: Re: Frequency Doubler - VHDL/Verilog
63052: 03/11/13: Re: Xilinx Virtex2 tristate support
63055: 03/11/13: Re: Frequency Doubler - VHDL/Verilog
63058: 03/11/13: Re: Transforming vector position to binary value
63071: 03/11/13: Re: Frequency Doubler - VHDL/Verilog
63072: 03/11/13: Re: Transforming vector position to binary value
63074: 03/11/13: Re: Writing Blockrams in VHDL
63075: 03/11/13: Re: Xilinx UART Macro ERROR???
63173: 03/11/17: Re: SRL16 as synchronizer
63232: 03/11/18: Re: SRL16 as synchronizer
63308: 03/11/19: Re: Transforming vector position to binary value
63312: 03/11/19: Re: regarding clock routing
63319: 03/11/19: Re: State Machines....
63338: 03/11/19: Re: State Machines....
63383: 03/11/20: Re: regarding clock routing
63387: 03/11/20: Re: Xilinx legacy situation
63458: 03/11/21: Re: Differential terminations in Virtex2 Pro.
63510: 03/11/24: Re: Xilinx legacy situation
63575: 03/11/25: Re: Slightly unmatched UART frequencies
63616: 03/11/26: Re: 5V I/O with 1.8V Core
63625: 03/11/26: Re: 5V I/O with 1.8V Core
63688: 03/11/29: Re: Digilent Inc.
63714: 03/12/01: Re: Quote from Xilinx re: XPLA3
63735: 03/12/02: Re: Exact Timing Constraints vs. Over-Constraining
63736: 03/12/02: Re: Exact Timing Constraints vs. Over-Constraining
63740: 03/12/02: Re: Exact Timing Constraints vs. Over-Constraining
63765: 03/12/03: Re: DPRAM - DIN, DOUT
63810: 03/12/04: Re: DPRAM - DIN, DOUT
63843: 03/12/05: Re: Dual-port and single-port BlockRAM instantiation
63853: 03/12/05: Re: Dual-port and single-port BlockRAM instantiation
63939: 03/12/09: Re: FIFO design
63941: 03/12/09: Re: FIFO design
63950: 03/12/09: Re: ASMBL - hmmm ---- hmmmm -- Wow?
63966: 03/12/10: Re: ASMBL - hmmm ---- hmmmm -- Wow?
63972: 03/12/10: Re: Manufacturing Tests
63979: 03/12/10: Re: Easypath question (was "Hard-tocopy" rant)
63984: 03/12/10: Re: ASMBL - hmmm ---- hmmmm -- Wow?
64000: 03/12/11: Re: FIFO design
64004: 03/12/11: Re: FIFO design
64073: 03/12/15: Re: datasheet needed!
64127: 03/12/17: Re: What is this ASMBL thing from Xilinx?
64200: 03/12/19: Re: Spartan3 availability
64298: 03/12/25: Re: How to get first bit '0' position in certain register?
64303: 03/12/26: Re: FPGA SRAM
64314: 03/12/27: Re: [Spartan-IIE] Exeeding max. input rise/fall time of signals ??
64315: 03/12/27: Re: predictable timing for xilinx cpld?
64323: 03/12/28: Re: [Spartan-IIE] Exeeding max. input rise/fall time of signals ??
64345: 03/12/29: Re: [Spartan-IIE] Exeeding max. input rise/fall time of signals ??
64351: 03/12/29: Re: predictable timing for xilinx cpld?
64353: 03/12/29: Re: predictable timing for xilinx cpld?
64379: 03/12/31: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
64380: 03/12/31: Re: SOS : 4-bit binary divider circuit PLEASE!!!!!!!
64530: 04/01/06: Re: Where i can get the programming sequence of CoolRunner?
64555: 04/01/07: Re: Virtex and Spartan
64566: 04/01/07: Re: newbie question: speed grade + area constraint
64597: 04/01/08: Re: min propagation delay in xilinx cpld
64598: 04/01/08: Re: min propagation delay in xilinx cpld
64613: 04/01/08: Re: Large/Fast static RAM
64639: 04/01/09: Re: min propagation delay in xilinx cpld
64727: 04/01/12: Re: min propagation delay in xilinx cpld
64729: 04/01/12: Re: How to generate a CSA tree?
64784: 04/01/13: Re: using signal as clk source
64819: 04/01/14: Re: Altera Cyclone data is incomplete or messy
64830: 04/01/14: Re: Altera Cyclone data is incomplete or messy
64831: 04/01/14: Re: Altera Cyclone data is incomplete or messy
64859: 04/01/15: Re: Generating clock delays
64861: 04/01/15: Re: 1.8v SpartanIIE
64874: 04/01/15: Re: yo, Mr. FPGA Engineer
64954: 04/01/16: Re: Generating clock delays
65038: 04/01/19: Re: Deriving 36MHz from a 40MHz crystal using DCM?
65041: 04/01/19: Re: WTD: info on AMD palce22v10
65066: 04/01/19: Re: QUES: Where can I find Xilinx M1 tools
65069: 04/01/19: Re: Deriving 36MHz from a 40MHz crystal using DCM?
65097: 04/01/20: Re: SDRAM Controller timing problem
65106: 04/01/20: Re: BIST FPGA testing - Applying a test vector
65118: 04/01/20: Re: changing values in a fifo
65120: 04/01/20: Re: Tristate buffer
65124: 04/01/20: Re: BIST FPGA testing - Applying a test vector
65164: 04/01/21: Re: BIST FPGA testing - Applying a test vector
65165: 04/01/21: Re: spartan3 power supply
65168: 04/01/21: Re: BIST FPGA testing - Applying a test vector
65179: 04/01/21: Re: Tristate buffer
65180: 04/01/21: Re: WTD: info on AMD palce22v10
65188: 04/01/21: Re: Soft failures (?) 9536XL
65238: 04/01/22: Re: xilinx 70% tracking rule
65239: 04/01/22: Re: Random data generator...
65267: 04/01/22: Re: xilinx 70% tracking rule
65268: 04/01/22: Re: WTD: info on AMD palce22v10
65269: 04/01/22: Re: asic vs fpga comparison issues
65309: 04/01/23: Re: Spirit on Mars, upsets on Earth -- does your vendor know? How?
65449: 04/01/29: Re: Is FPGA fully static?
65488: 04/01/30: Re: Is FPGA fully static?
65682: 04/02/04: Re: Soft failures (?) 9536XL
65688: 04/02/04: Re: Dual clock FIFO with Atmel FPGA ??
65740: 04/02/05: Re: Do Xilinx Fix Their Prices?
65795: 04/02/06: Re: Help with BUFGMUX in Xilinx Virtex2 and Timing constraints ?
65796: 04/02/06: Re: Do Xilinx Fix Their Prices?
65806: 04/02/06: Re: Virtex-3 PRO
65814: 04/02/06: Re: Differences between Xilinx ISE and Altera Quartus software
65897: 04/02/09: Re: Pricing, 101
65963: 04/02/10: Re: negative hold time
65966: 04/02/10: Re: Pricing, 101
66019: 04/02/11: Re: negative hold time
66035: 04/02/11: Re: negative hold time
66036: 04/02/11: Re: Pricing, 101
66053: 04/02/11: Re: negative hold time (Typ/max)
66056: 04/02/11: Re: Xilinx Platform Flash Prom
66106: 04/02/12: Re: negative hold time
66109: 04/02/12: Re: Programmable clock, FPGA PLLs, and Actel PLL Core
66110: 04/02/12: Re: clock
66114: 04/02/12: Re: Programmable clock, FPGA PLLs, and Actel PLL Core
66121: 04/02/12: Re: negative hold time
66122: 04/02/12: Re: Peter's 1Hz-640MHz Synth project
66130: 04/02/12: Re: Peter's 1Hz-640MHz Synth project
66132: 04/02/12: Re: Programmable clock, FPGA PLLs, and Actel PLL Core
66137: 04/02/12: Re: Peter's 1Hz-640MHz Synth project
66284: 04/02/16: Re: confused DCM clkin_period vs true input clock
66285: 04/02/16: Re: 74ls193 in coolrunner
66286: 04/02/16: Re: PREP benchmark
66288: 04/02/16: Re: Plea for help - 29PL141
66293: 04/02/16: Re: Configuring Multiple V2Pros with Same Bitstream
66311: 04/02/16: Re: Configuring Multiple V2Pros with Same Bitstream
66396: 04/02/18: Re: regarding synchronization
66654: 04/02/24: Re: FPGA vendors and their patents
66772: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
66780: 04/02/26: Re: one more inquiry....fpga architecture
66808: 04/02/26: Re: Stratix 2 ALUT architecture patented ?
66811: 04/02/26: Re: DPRAM design issue
66862: 04/02/27: Re: Stratix 2 ALUT architecture patented ?
66977: 04/03/02: Re: CASCADING DCM
67065: 04/03/04: Re: Global reset question?
67076: 04/03/04: Re: Global reset question?
67107: 04/03/05: Re: A newbie question
67123: 04/03/05: Re: FPGA hangs
67126: 04/03/05: Re: Global reset question?
67127: 04/03/05: Re: CASCADING DCM
67219: 04/03/08: Re: Release asynchrounous resets synchronously
67267: 04/03/09: Re: Release asynchrounous resets synchronously
67270: 04/03/09: Re: Reg..How to use BUFGMUX in Spartan 2 family
67275: 04/03/09: Re: Release asynchrounous resets synchronously
67289: 04/03/09: Re: Using ALTPLL
67296: 04/03/09: Re: lattice metastable info
67595: 04/03/15: Re: low power Oscillator for Xilinx CoolrunnerII
67602: 04/03/15: Re: low power Oscillator for Xilinx CoolrunnerII
67603: 04/03/15: Re: low power Oscillator for Xilinx CoolrunnerII
67605: 04/03/15: Re: Programmed ground pins v physical grounding (Xilinx CPLD)
67684: 04/03/17: Re: clock rising edge alignment
67712: 04/03/17: Re: newbie question about fpga internals
67763: 04/03/18: Re: Xilinx ISE 6.2 and Virtex-II
67805: 04/03/19: Re: LVTTL Spartan-3 pin input current...
67817: 04/03/19: Re: LVTTL Spartan-3 pin input current...
67827: 04/03/19: Re: Virtex-E IOB programmable delay
67900: 04/03/22: Re: Synchronization of data
67903: 04/03/22: Re: zener power supply to XC95144XL?
67913: 04/03/22: Re: Virtex-E IOB programmable delay
67951: 04/03/23: Re: How many times can I burn an FPGA?
68031: 04/03/24: Re: Time measurement with Xilinx Spartan-3 - Help
68057: 04/03/25: Re: Clock divider preserving duty-cycle ?
68189: 04/03/29: Re: CLB usage: Xilinx XCS20 and Foundation 3.1
68237: 04/03/30: Re: speed vs. temperature
68287: 04/03/31: Re: Metastablility
68289: 04/03/31: Re: Metastablility
68392: 04/04/02: Re: vertex II vs Stratix
68396: 04/04/02: Re: Logic required for multiplication
68459: 04/04/05: Re: Can I use the Done signal in FPGA to reset my design
68580: 04/04/08: Re: Xilinx XC9500 CPLD Wired-OR; Wired-ND
68581: 04/04/08: Re: Xilinx XC9500 CPLD Wired-OR; Wired-ND
68707: 04/04/14: Re: DDS-Based PLL
68814: 04/04/19: Re: PLL and DLL
68824: 04/04/19: Re: Clock Enables and Power
68849: 04/04/20: Re: What does a "background check" mean? ...
68871: 04/04/20: Re: Issues on Shift Register in a Clockless UART
68872: 04/04/20: Re: calculate the number of logic gate in FPGA
68900: 04/04/21: Re: Issues on Shift Register in a Clockless UART
68901: 04/04/21: Re: calculate the number of logic gate in FPGA
68906: 04/04/21: Re: calculate the number of logic gate in FPGA
68935: 04/04/22: Re: PLL and DLL
68947: 04/04/22: Re: PLL and DLL
68952: 04/04/22: Re: What is MPGA?
68955: 04/04/22: Re: Time domain/Delay line UARTs - high speeds
68975: 04/04/23: Re: Time domain/Delay line UARTs - high speeds
68987: 04/04/23: Re: PLL and DLL
68989: 04/04/23: Re: OT - Generating a 20MHz clock that can be adjusted by +- 2%
68996: 04/04/23: Re: What is MPGA?
69075: 04/04/26: Re: transport applications
69110: 04/04/27: Re: transport applications
69259: 04/05/03: Re: frequency multiplication
69268: 04/05/03: Re: frequency multiplication
69271: 04/05/03: Re: Connecting a crystal to a Cyclone or Max PLD
69281: 04/05/04: Re: Connecting a crystal to a Cyclone or Max PLD
69304: 04/05/05: Re: Connecting a crystal to a Cyclone or Max PLD
69311: 04/05/05: Re: V2p block ram clock -> Q delay help
69351: 04/05/07: Re: Virtex2 (500) DCM Frequency Synthesize
69813: 04/05/20: Re: shift register by block RAM
69953: 04/05/25: Re: What can I do if my chip can't meet timing?
69955: 04/05/25: Re: Driving fpga pin out over long cable
70001: 04/05/26: Re: What can I do if my chip can't meet timing?
70027: 04/05/27: Re: Driving fpga pin out over long cable
70168: 04/06/07: Re: Variable Frequency and Voltage Supply
70223: 04/06/09: Re: Digital Clock Manager (DCM) Question
70228: 04/06/09: Re: Digital Clock Manager (DCM) Question
70254: 04/06/10: Re: Virtex4: I don't understand their thinking....
70305: 04/06/11: Re: tri-state in altera and xilinx
70364: 04/06/14: Re: FPGA serial programming troubles. (Virtex II)
70368: 04/06/14: Re: RAM in Altera EABs and Xilinx Block Rams
70370: 04/06/14: Re: RAM in Altera EABs and Xilinx Block Rams
70401: 04/06/15: Re: FPGA serial programming troubles. (Virtex II)
70469: 04/06/17: Re: RAM in Altera EABs and Xilinx Block Rams
70588: 04/06/21: Re: Frequency synthesizer.
70589: 04/06/21: Re: Is the Xilinix XC3020 atill supported?
70591: 04/06/21: Re: XST: Inferring dual-port RAM from VHDL with BlockRAM
70632: 04/06/22: Re: RAM in Altera EABs and Xilinx Block Rams
70646: 04/06/22: Re: RAM in Altera EABs and Xilinx Block Rams
70746: 04/06/25: Re: Using a BlockRam in an async FIFO for bus width conversion ?
70791: 04/06/28: Re: Using a BlockRam in an async FIFO for bus width conversion ?
70796: 04/06/28: Re: Battle of the Vapours
70801: 04/06/28: Re: Battle of the Vapours
70859: 04/06/30: Re: FPGA with fully asynchronous RAM
70912: 04/07/01: Re: FPGA with fully asynchronous RAM
71122: 04/07/08: Re: How to constrain a divide by 3 clock?
71145: 04/07/09: Re: Spartan 3 termination question (DCI)
71223: 04/07/12: Re: Is the Xilinix XC3020 atill supported?
71224: 04/07/12: Re: Spartan 3 termination question (DCI)
71287: 04/07/13: Re: FSM in illegal state (conclusion)
71293: 04/07/13: Re: Xilinx Virtex 4
71326: 04/07/14: Re: FSM in illegal state (conclusion)
71499: 04/07/20: Re: Spartan 3 termination question (DCI)
71507: 04/07/20: Re: Spartan 3 termination question (DCI)
71512: 04/07/20: Re: Low Power Applications - enumerate
71545: 04/07/21: Re: Spartan 3 termination question (DCI)
71556: 04/07/21: Re: FPGA Selection--
71573: 04/07/22: Re: Converting High Rise Time clock to Low Rise time clock -
71648: 04/07/26: Re: 1GHz FPGA counters
71649: 04/07/26: Re: 1GHz FPGA counters
71682: 04/07/27: Re: 1GHz FPGA counters
71803: 04/07/30: Re: On-Chip Oscillator
71807: 04/07/30: Re: On-Chip Oscillator
71852: 04/08/02: Re: SPARTANII pinout table mysteries ???
71857: 04/08/02: Re: 1GHz FPGA counters
71860: 04/08/02: Re: Compact FPGA Board?
71891: 04/08/03: Re: 1GHz FPGA counters
71913: 04/08/03: Re: clock synthesis with RocketIO
71917: 04/08/03: Re: Can I use RocketIO to generate pulse edge with very high
71950: 04/08/04: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
71953: 04/08/04: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
71966: 04/08/04: Re: Choosing FPGAs: Xilinx vs Altera vs Actel vs Lattice
72055: 04/08/06: Re: Comparing Quality of Results of FPGA CAD Tools
72114: 04/08/09: Re: Comparing Quality of Results of FPGA CAD Tools
72122: 04/08/09: Re: Now I am really confused!
72129: 04/08/09: Re: Now I am really confused!
72175: 04/08/10: Re: Now I am really confused!
72353: 04/08/16: Re: let me have logic design for traffic light
72462: 04/08/19: Re: Regarding BIST in FPGA
72537: 04/08/23: Re: SSO and decoupling relationship
72585: 04/08/25: Re: ring oscillator calibration
72626: 04/08/26: Re: 6.1 vs. 6.2
73717: 04/09/28: Re: Xilinx Read First Write First
73718: 04/09/28: Re: Xilinx Read First Write First
73803: 04/09/29: Re: High speed counters on Xilinx CoolRunner-II
73898: 04/09/30: Re: FPGA vs ASIC area
73914: 04/09/30: Re: FPGA vs ASIC area
73915: 04/09/30: Re: FPGA vs ASIC area
73970: 04/10/01: Re: NV on-chip memory?
73410: 04/09/21: Mr. Greenfield, spare us the propaganda !
73429: 04/09/21: Re: Mr. Greenfield, spare us the propaganda !
73512: 04/09/22: Re: Stratix II vs. Virtex 4 - features and performance
73587: 04/09/24: Virtex-4 vs Virtex-II
74935: 04/10/21: Re: Async reset
75215: 04/10/29: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
74130: 04/10/04: Re: FPGA vs ASIC area
74135: 04/10/04: Re: Asynchronous reset timing problem
74247: 04/10/06: Re: DCM and CLKFX - is this allowed?
74303: 04/10/07: Re: FPGA vs ASIC area -- the crucial issue is power consumption
74315: 04/10/07: Re: Xilinx lead free parts hidden fact
74317: 04/10/07: Re: DCM and CLKFX - is this allowed?
74440: 04/10/11: Re: multiplexing clocks
74441: 04/10/11: Re: Temperature considerations of inactive logic blocks
74452: 04/10/11: Re: multiplexing clocks
74454: 04/10/11: Re: Temperature considerations of inactive logic blocks
74499: 04/10/12: Re: multiplexing clocks
74916: 04/10/21: Re: Async reset
74923: 04/10/21: Re: Async reset
74930: 04/10/21: Re: Async reset
77185: 04/12/28: Re: Google is turning usenet into crap - was Primers for Handel-C
77267: 05/01/02: Re: Verilog /DIP Switch Question....
77270: 05/01/02: Re: Verilog /DIP Switch Question....
77322: 05/01/04: Whither common courtesy ?
77345: 05/01/04: Re: Whither common courtesy ?
77396: 05/01/05: Re: Utilisation of Xilinx FPGAs
77437: 05/01/06: Re: Utilisation of Xilinx FPGAs
77539: 05/01/10: Re: Editing bitstream
77554: 05/01/10: Re: How protection diodes 'wear out'.
77585: 05/01/11: Re: Editing bitstream
77593: 05/01/11: Re: Clock Domains with PLL
77632: 05/01/12: Re: General Question - Which FPGAs can support partial run-tim reconfiguration?
77633: 05/01/12: Re: Programming and copyright
77672: 05/01/13: Re: Programming and copyright
77734: 05/01/15: Re: No respect of exernal pins [xilinx]
77735: 05/01/15: Re: maximum DDS clocking frequency on an Xilinx FPGA
77741: 05/01/15: Re: No respect of exernal pins [xilinx]
78020: 05/01/22: Re: Power Analisys with MicroBlaze
78110: 05/01/24: Re: 60Hz clock on XC9572
78150: 05/01/25: Re: 60Hz clock on XC9572
78153: 05/01/25: Re: Xilinx Engineering Samples [JTAG issues]
78156: 05/01/25: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
78177: 05/01/25: Re: Xilinx Engineering Samples [JTAG issues]
78183: 05/01/25: Re: 60Hz clock on XC9572
78280: 05/01/27: See Peter's High-Wire Act next Tuesday
78403: 05/01/31: Re: See Peter's High-Wire Act next Tuesday
78431: 05/01/31: Re: Metastability MTBF in Cyclone
78458: 05/02/01: Re: Metastability MTBF in Cyclone
78468: 05/02/01: Re: Synchronizing multibit bus
78472: 05/02/01: Re: Oscillator for Digilent Spartan 3 Starter Kit
78488: 05/02/01: Re: Oscillator for Digilent Spartan 3 Starter Kit
78499: 05/02/01: Re: See Peter's High-Wire Act next Tuesday
78592: 05/02/03: Re: See Peter's High-Wire Act next Tuesday
78602: 05/02/03: Re: See Peter's High-Wire Act next Tuesday
78606: 05/02/03: Re: See Peter's High-Wire Act next Tuesday
78629: 05/02/04: Re: Xilinx Virtex4 / Spartan3 High Speed Designs
78633: 05/02/04: Re: Xilinx Virtex4 / Spartan3 High Speed Designs
78638: 05/02/04: Re: Benchmarks or not.
78641: 05/02/04: Re: Xilinx Virtex4 / Spartan3 High Speed Designs
78656: 05/02/04: Re: Benchmarks or not.
78688: 05/02/05: Re: See Peter's High-Wire Act next Tuesday
78706: 05/02/06: Re: See Peter's High-Wire Act next Tuesday
78717: 05/02/06: Re: See Peter's High-Wire Act next Tuesday
78720: 05/02/06: Re: GND and VCC pins
78723: 05/02/06: Re: GND and VCC pins
78850: 05/02/08: Re: virtex4 distributed RAM
78908: 05/02/09: See the next high-wire act, this time on power consumption
78992: 05/02/10: Re: Variable phase shift on Spartan3 DCMs. Does it work?
79050: 05/02/11: Re: second flop in asyn reset distribution
79054: 05/02/11: Re: second flop in asyn reset distribution
79067: 05/02/13: Re: Fast counting in Spartan 3
79077: 05/02/13: Re: second flop in asyn reset distribution
79078: 05/02/13: Re: See the next high-wire act, this time on power consumption
79141: 05/02/14: Re: See the next high-wire act, this time on power consumption
79143: 05/02/14: Re: clock division / multiplication in xilinx cpld
79187: 05/02/15: Re: Xilinx Post Place and Route FIFO problems
79191: 05/02/15: Re: Updated Stratix II Power Specs & Explanation [And a Junction Temperature Tutorial]
79218: 05/02/15: Re: See the next high-wire act, this time on power consumption
79230: 05/02/15: Re: See the next high-wire act, this time on power consumption
79240: 05/02/15: Re: Updated Stratix II Power Specs & Explanation
79293: 05/02/16: Re: clock split approach for 270MHz design in Spartan2E
79346: 05/02/17: Re: Updated Stratix II Power Specs & Explanation
79363: 05/02/17: Re: Virtex4: Usign OSERDES + LVDS Deserializers
79364: 05/02/17: Re: Virtex4: Usign OSERDES + LVDS Deserializers
79448: 05/02/18: Re: Updated Stratix II Power Specs & Explanation
79479: 05/02/19: Re: why to use FIFO on FPGA?
79534: 05/02/20: Re: difficult to build counter, some help please : (
79549: 05/02/20: Re: difficult to build counter, some help please : (
79554: 05/02/20: Re: difficult to build counter, some help please : (
79631: 05/02/22: Re: virtex II register file
79659: 05/02/22: Re: Hardcopy Vs ASIC
79668: 05/02/22: Re: Is Altera Cyclone a good choice ?
79751: 05/02/23: Re: Hardcopy Vs ASIC
79764: 05/02/23: Re: The real performance leader: V4
79801: 05/02/24: Re: Prescalable counter
79887: 05/02/25: Re: IP unnecessarily using Spartan-3 DCM?
79917: 05/02/25: Re: Maximum Current utilized by Spartan-3
79925: 05/02/25: Re: Maximum Current utilized by Spartan-3
79946: 05/02/26: Re: spartan 3 vs virtex 2
79947: 05/02/26: Re: setup-hold time problems
79959: 05/02/26: The third high-wire act: Signal Integrity or "It's the inductance, stupid".
79974: 05/02/27: Re: Prescalable counter
79975: 05/02/27: Re: maximum freq of operation of a circuit
79978: 05/02/27: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
79979: 05/02/27: Re: Prescalable counter
79989: 05/02/27: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
80015: 05/02/28: Re: spartan 3 vs virtex 2
80016: 05/02/28: Re: Prescalable counter
80043: 05/02/28: Re: FPGA interface to an asynchronous microcontroller memory bus
80053: 05/02/28: Re: FPGA interface to an asynchronous microcontroller memory bus
80058: 05/02/28: Signal Integrity, ground bounce, crosstalk, SSOs, BGA pin-outs, parasitic inductance...
80062: 05/02/28: Re: Resource (FMAPs) use when using block RAMs
80127: 05/03/01: Re: Resetting Virtex II BlockRAM
80130: 05/03/01: Re: Signal Integrity, ground bounce, crosstalk, SSOs, BGA pin-outs, parasitic inductance...
80198: 05/03/02: Re: Signal Integrity, ground bounce, crosstalk, SSOs, BGA pin-outs, parasitic inductance...
80204: 05/03/02: Re: spartan3E price
80223: 05/03/02: Re: Signal Integrity, ground bounce, crosstalk, SSOs, BGA pin-outs, parasitic inductance...
80307: 05/03/03: Re: How to get 1.8432 MHz out of 24 MHz with Sparten-3?
80310: 05/03/03: Re: making an fpga hot - addendum
80326: 05/03/03: Re: making an fpga hot - addendum
80369: 05/03/04: Re: Newby Getting started with FPGA
80396: 05/03/04: Re: SR latches in Xilinx devices?
80432: 05/03/05: Re: reading data from register and writing to ram
80445: 05/03/05: Re: Spartan 3 - insurge current
80503: 05/03/07: Re: state encoding in FSM for simple cases ?
80516: 05/03/07: Re: Surge in S2? ~3 amperes at cold for a millisecond
80588: 05/03/08: Re: Async FIFO problem...
80601: 05/03/08: Re: Async FIFO problem...
80603: 05/03/08: Re: Async FIFO problem...
81477: 05/03/24: Re: XC3000 non-recoverable lockup problem
81502: 05/03/25: Re: Onchip SRAM Vs Registers
81556: 05/03/27: Re: Multi-FPGA PCB data aggregation?
81560: 05/03/27: Re: Multi-FPGA PCB data aggregation?
81571: 05/03/27: Re: Block RAM in Xilinx Spartan 3
81596: 05/03/28: Re: What type of IO to use
81780: 05/03/31: Re: XC3000 non-recoverable lockup problem
82077: 05/04/06: Re: Single Event Functional Interrupts (SEFI) in Virtex
82144: 05/04/07: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
82160: 05/04/07: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
82248: 05/04/09: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
82260: 05/04/09: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
82452: 05/04/12: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
82484: 05/04/13: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
82487: 05/04/13: Re: LUT in fpga
82548: 05/04/13: Re: Neural Networks in FPGA
82749: 05/04/17: Re: Spartan 3E slower that Spartan 3?
82759: 05/04/17: Re: Spartan 3E slower that Spartan 3?
82804: 05/04/18: Re: Spartan 3E slower that Spartan 3?
82898: 05/04/19: Re: Odd Oversampling
82925: 05/04/19: Re: Slow rising strobe used to clock IOB's, can it cause trouble?
83116: 05/04/23: Re: CAM for FPGA ...
83251: 05/04/26: Re: Sync + FIFO
83264: 05/04/26: Re: Virtex 4 Power consumption
83274: 05/04/26: Re: Sync + FIFO
83343: 05/04/27: Re: XC4k parts obsolete ?
83347: 05/04/27: Re: Sync + FIFO
83390: 05/04/28: Re: Sync + FIFO
83420: 05/04/29: Re: Sync + FIFO
83430: 05/04/29: Re: Sync + FIFO
83438: 05/04/29: Re: Patent issues in implementing embedded fpgas
83447: 05/04/29: Re: Sync + FIFO
83474: 05/04/30: Re: VGA sync signals
83483: 05/04/30: Re: Sync + FIFO
83497: 05/05/01: Re: Xilinx input path: Why does the optional delay element with inputFF help me?
83498: 05/05/01: Re: Xilinx input path: Why does the optional delay element with inputFF help me?
83510: 05/05/01: Re: cross clock timing constraints
83513: 05/05/01: Re: Virtex4 and ISE reality check?
83533: 05/05/02: Re: Virtex4 and ISE reality check?
83579: 05/05/03: Re: Xilinx input path: Why does the optional delay element with inputFF help me?
83604: 05/05/03: Re: Xilinx input path: Why does the optional delay element with inputFF help me?
83641: 05/05/04: Re: Multiply Accumulate FPGA/DSP
83657: 05/05/04: Re: Multiply Accumulate FPGA/DSP
83659: 05/05/04: Re: Availability of the Xilinx ML481 Development Board
83664: 05/05/04: Re: Availability of the Xilinx ML481 Development Board
83666: 05/05/04: Re: Does this group allow JobPostings?
83700: 05/05/05: Re: Availability of the Xilinx ML481 Development Board
83715: 05/05/05: Re: Clock Gating
83735: 05/05/05: Re: Multiply Accumulate FPGA/DSP
83788: 05/05/06: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83804: 05/05/06: Re: Metastability / MUX question
83816: 05/05/06: Re: Metastability / MUX question
83844: 05/05/07: Re: Clock delay vs. clock skew
83868: 05/05/08: Re: Metastability / MUX question
83891: 05/05/09: Re: true dual port memory v/s simple dual port memory
83896: 05/05/09: Re: dcm's for increasing clock speed
83911: 05/05/09: Re: Clock delay vs. clock skew
83930: 05/05/09: Re: true dual port memory v/s simple dual port memory
83957: 05/05/10: Re: true dual port memory v/s simple dual port memory
83960: 05/05/10: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
83964: 05/05/10: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
83975: 05/05/10: Re: Multiple Virtex 2 Pro's, DCM and CLKIN_DIVIDE_BY_2
83979: 05/05/10: Re: Virtex4 running at 360Mhz DDR
83980: 05/05/10: Re: dividing the clcok by 2.5
84034: 05/05/11: Re: Analog to Digital Converted (ADC) & Spartan 3
84052: 05/05/11: Re: Slice Virtex II = Equivalent gates ??
84101: 05/05/12: "Mine is bigger than yours..."
84108: 05/05/12: Re: Slice Virtex II = Equivalent gates ??
84163: 05/05/13: Re: V4 vs. Stratix-II...fabric only thread...LUT details...
84194: 05/05/13: Re: initializing fifo pointers to simulate overflow
84241: 05/05/15: Re: wide ROM
84274: 05/05/16: Bullshit Achieves Literary Status
84275: 05/05/16: Re: Bullshit Achieves Literary Status
84280: 05/05/16: Re: Is a gated oscillator using NAND okay within a Cyclone FPGA?
84285: 05/05/16: Re: Is a gated oscillator using NAND okay within a Cyclone FPGA?
84477: 05/05/19: Re: Xilinx V2Pro DCM config and settling time questions
84483: 05/05/19: Re: Spartan 3 CPI
84496: 05/05/19: Re: Bullshit Achieves Literary Status
84497: 05/05/19: Re: Newbie: Falling edge, what is the threshold? (Xilinx XC9572XL)
84500: 05/05/19: Re: Bullshit Achieves Literary Status
84510: 05/05/19: Re: Bullshit Achieves Literary Status
84547: 05/05/20: Re: Bullshit Achieves Literary Status
84589: 05/05/22: Re: How to make a 1.44MHz clock?
84594: 05/05/22: Re: How to make a 1.44MHz clock?
84601: 05/05/22: Re: simple delays
84629: 05/05/23: Re: VHDL vs. Schematic Capture
84642: 05/05/23: Re: System Reset / GSR with Virtex 2 & Virtex 4
84746: 05/05/25: Re: warning place and route ise7.1?
84811: 05/05/27: Re: Accessing BRAM as a SRAM
84812: 05/05/27: Re: VHDL vs. Schematic Capture
84909: 05/05/31: Re: Implementing sin function in fpga
84933: 05/06/01: Re: Implementing sin function in fpga
85022: 05/06/02: Re: Clock Generation : FPGA
85029: 05/06/02: Re: keypad scanner
85030: 05/06/02: Re: Clock Generation : FPGA
85077: 05/06/03: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
85079: 05/06/03: Re: Share one BRAM block between user logic and microblaze (Spartan3)
85081: 05/06/03: Re: Share one BRAM block between user logic and microblaze (Spartan3)
85092: 05/06/03: Re: not clear about doing power estimation using xpower
85094: 05/06/03: Re: keypad scanner
85119: 05/06/05: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
85207: 05/06/06: Re: Pissed off with Xilinx - Spartan 3
85208: 05/06/06: Re: Clock Generation : FPGA
85280: 05/06/07: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
85322: 05/06/07: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
85325: 05/06/07: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
85328: 05/06/07: Re: FPGA I/O pin current sink
85337: 05/06/07: Re: Great Tutorial on Signal Integrity, SSOs, Ground Bounce etc
85338: 05/06/07: Re: faster Spartan III adder
85401: 05/06/08: Re: Can I use a 18k ram as 2 single-port ram?
85402: 05/06/08: Re: searching spartan-3
85423: 05/06/09: Re: Can I use a 18k ram as 2 single-port ram?
85434: 05/06/09: Re: Can I use a 18k ram as 2 single-port ram?
85450: 05/06/09: Re: faster Spartan III adder
85656: 05/06/13: Re: RAM State Machine Examples
85718: 05/06/14: Re: Gated clock question
85773: 05/06/15: Re: Availability of Spartan3
85776: 05/06/15: Re: Availability of Spartan3
85783: 05/06/15: Re: Availability of Spartan3
85785: 05/06/15: Re: Pissed off with Xilinx - Spartan 3 [The Rest of the Story]
85900: 05/06/17: Re: Xlinix configuration: DONE pin too early?
85914: 05/06/17: Re: Xlinix configuration: DONE pin too early?
85926: 05/06/18: Re: Interesting question on CPLD
85935: 05/06/18: Re: CPLD fusemap data - why the secrecy?
85942: 05/06/18: Re: CPLD fusemap data - why the secrecy?
85945: 05/06/18: Re: circuit optimization - a feedbackless machine
85946: 05/06/18: Re: LUT, how to?
85950: 05/06/18: Re: CPLD fusemap data - why the secrecy?
85976: 05/06/19: Re: damage Atmel AT40k/AT94k with wrong bitstream?
85981: 05/06/19: Re: Interesting question on CPLD
86031: 05/06/20: Re: 5 Volt tolerance - Altera
86055: 05/06/21: Re: Xilinx MacFir5.0 - Block Ram requirenments
86074: 05/06/21: Re: circuit optimization - a feedbackless machine
86077: 05/06/21: Re: Spartan 3 availability
86084: 05/06/21: Re: dru files for eagle ?
86087: 05/06/21: Re: [V2PRO]IOB tristate pins.
86102: 05/06/21: Re: comp.arch.fpga.<mfr>
86176: 05/06/22: Re: 5 Volt tolerance - Altera
86189: 05/06/22: Re: Frequency divisors
86201: 05/06/22: Re: FYI: Spartan-3 XC3S50 through XC3S1500 Back on Xilinx Online Store (www.xilinx.com/store)
86204: 05/06/22: Re: Commercial Z180 / 64180 core
86253: 05/06/23: Re: Xilinx webshop
86264: 05/06/23: Re: Good FPGA introduction book ?
86270: 05/06/23: Re: Good FPGA introduction book ?
86274: 05/06/23: Re: Need help for Xilinx FPGA
86366: 05/06/26: Re: Xilinx webshop
86367: 05/06/26: Re: Xilinx Spartan 3 CLB Slice Options - more detail than in datasheet available?
86534: 05/06/29: Re: ADPLL for NRZ
86535: 05/06/29: Re: Xilinx Virtex 4 device technology
86549: 05/06/29: Re: Small FPGA
86556: 05/06/29: Re: Xilinx Virtex 4 device technology
86615: 05/06/30: Re: Direct audio output from FPGA pins
86620: 05/06/30: Re: Clock buffering in VirtexE FPGA
86642: 05/07/01: Re: Direct audio output from FPGA pins
86643: 05/07/01: Re: Clock buffering in VirtexE FPGA
86651: 05/07/01: Re: FPGA system RAM
86653: 05/07/01: Re: FPGA system RAM
86656: 05/07/01: Re: FPGA system RAM
86659: 05/07/02: Re: Problem for xilinx!!!
86664: 05/07/03: Re: Clock buffering in VirtexE FPGA
86666: 05/07/03: Re: Xilinx: XST synchronous FIFO using BRAMs
86670: 05/07/03: Re: Xilinx: XST synchronous FIFO using BRAMs
86673: 05/07/03: Re: Xilinx: XST synchronous FIFO using BRAMs
86704: 05/07/04: Re: Xilinx: XST synchronous FIFO using BRAMs
86709: 05/07/04: Re: Problem for xilinx!!!
86724: 05/07/05: Re: Xilinx: XST synchronous FIFO using BRAMs
86740: 05/07/05: Re: Xilinx: XST synchronous FIFO using BRAMs
86782: 05/07/06: Re: fastest FPGA speed grade?
86809: 05/07/06: Re: Spartan-3e order of availability?
87051: 05/07/13: Re: Virtex 300: what could cause pin to short?
87084: 05/07/14: Re: Clock buffering in VirtexE FPGA
87176: 05/07/18: Re: pricing of Virtex-4
87186: 05/07/18: Re: Virtex-4 5V tolerance
87211: 05/07/19: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87230: 05/07/19: Re: Ones Count 64 bit on Xilinx in VHDL
87232: 05/07/19: Re: Ones Count 64 bit on Xilinx in VHDL
87254: 05/07/20: Re: Using unregistered inputs in FSM
87266: 05/07/20: Re: Design is too large for the device! xc3s400
87281: 05/07/20: Re: Ones Count 64 bit on Xilinx in VHDL
87283: 05/07/20: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87285: 05/07/20: Re: Design is too large for the device! xc3s400
87292: 05/07/20: Re: Design is too large for the device! xc3s400
87346: 05/07/21: Re: Creating Variable Delay for output signals in an XCV1000
87347: 05/07/21: Re: Ones Count 64 bit on Xilinx in VHDL
87348: 05/07/21: Re: Design is too large for the device! xc3s400
87434: 05/07/23: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87464: 05/07/24: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87517: 05/07/25: Re: Exact time-to-Failure data for FPGA devices
87555: 05/07/25: Re: Exact time-to-Failure data for FPGA devices
87562: 05/07/25: Re: Exact time-to-Failure data for FPGA devices
87665: 05/07/27: Re: Delay Generators in FPGAs
87666: 05/07/27: Re: Design is too large for the device! xc3s400
87844: 05/08/02: Re: Xilinx Multiple Spartan 3
87849: 05/08/02: Re: Programmable frequency synthesizer with Xilinx DCM
87856: 05/08/02: Re: Programmable frequency synthesizer with Xilinx DCM
87863: 05/08/02: Re: Programmable frequency synthesizer with Xilinx DCM
87928: 05/08/03: Re: Programmable frequency synthesizer with Xilinx DCM
87939: 05/08/03: Re: Where can i find GeneticFPGA toolkit
87960: 05/08/04: Re: Where can i find GeneticFPGA toolkit
87965: 05/08/04: Re: Programmable frequency synthesizer with Xilinx DCM
87966: 05/08/04: Re: Modulation Clock to set FPGA timing
87973: 05/08/04: Re: Where can i find GeneticFPGA toolkit
87975: 05/08/04: Re: Sparan S3E availability update
87988: 05/08/04: Re: Programmable frequency synthesizer with Xilinx DCM
87991: 05/08/04: Re: Programmable frequency synthesizer with Xilinx DCM
88085: 05/08/08: Re: can use bram for VGA
88165: 05/08/10: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
88169: 05/08/10: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
88189: 05/08/11: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
88201: 05/08/11: Re: Using an oscillator in a rugged environment
88242: 05/08/12: Re: Regarding clock muxing
88271: 05/08/13: Re: Peter Alfke's SPDT Switch Debouncer
88285: 05/08/14: Re: Glitches in Output of FSM
88337: 05/08/15: Re: Peter Alfke's SPDT Switch Debouncer
88347: 05/08/15: Re: Peter Alfke's SPDT Switch Debouncer
88385: 05/08/16: Re: Spartan-3 configuration -- peculiar problem
88388: 05/08/16: Re: Spartan-3 configuration -- peculiar problem
88423: 05/08/17: Re: super fast divide-by-N
89616: 05/09/20: Re: problem with Thold violation under quartus
89658: 05/09/21: Re: Count "1" bit in bit stream
89659: 05/09/21: Re: Xilinx Spartan-3
89729: 05/09/23: Re: Synchronizer Flip Flop / Metastability
89746: 05/09/23: Re: Question on Metastability
89752: 05/09/24: Re: Question on Metastability
89794: 05/09/26: Re: Question on Metastability
89806: 05/09/26: Re: Synchronizer Flip Flop / Metastability
89834: 05/09/27: Re: Synchronizer Flip Flop / Metastability
90011: 05/10/01: Re: I, Wish: I had an Spartan-3e NOW!
90090: 05/10/04: Re: Avoiding meta stability?
90114: 05/10/04: Re: Avoiding meta stability?
90141: 05/10/05: Re: Avoiding meta stability?
90159: 05/10/05: Re: Avoiding meta stability?
90284: 05/10/07: Re: Question about metastability that's been on my mind for a while - mine too, I lived it
90285: 05/10/07: Re: Avoiding meta stability?
90341: 05/10/10: Re: Eliminates meta stability (yes or no)?
90374: 05/10/11: Re: converting 12v signal to 3.3v
90375: 05/10/11: Re: LUT 4:1 VS FF
90419: 05/10/12: Re: Avoiding meta stability?
90453: 05/10/13: Re: Avoiding meta stability?
90458: 05/10/13: Re: LUT 4:1 VS FF
90468: 05/10/13: Re: Anyone remember the really early Xilinx FPGAs?
90469: 05/10/13: Re: Xilinx ML403 Board Beginner
90502: 05/10/14: Re: Anyone remember the really early Xilinx FPGAs?
90545: 05/10/16: Re: Best Async FIFO Implementation
90549: 05/10/16: Re: Best Async FIFO Implementation
90550: 05/10/16: Re: Anyone remember the really early Xilinx FPGAs?
90554: 05/10/16: Re: Best Async FIFO Implementation
90558: 05/10/16: Re: Best Async FIFO Implementation
90562: 05/10/16: Re: ADC implementation on fpga? Information and procudures wanted.
90585: 05/10/17: Re: Best Async FIFO Implementation
90601: 05/10/17: Re: Best Async FIFO Implementation
90602: 05/10/17: Re: Best Async FIFO Implementation
90605: 05/10/17: Re: Best Async FIFO Implementation
90607: 05/10/17: Re: clock timing
90658: 05/10/18: Re: Best Async FIFO Implementation
90730: 05/10/19: Re: which is Low power FPGA?
90733: 05/10/19: Re: MAC Architectures
90737: 05/10/19: Re: Best Async FIFO Implementation
90764: 05/10/20: Re: Best Async FIFO Implementation
90782: 05/10/20: Re: low power design and unused i/os
90783: 05/10/20: Re: Simple PWM Spartan 3
90805: 05/10/21: Re: Best Async FIFO Implementation
90902: 05/10/24: Re: Xilinx ISERDES
90926: 05/10/25: Re: Xilinx FIFO Generator: FIFO Length
90935: 05/10/25: Re: Xilinx FIFO Generator: FIFO Length
90948: 05/10/25: Re: Xilinx ISERDES
90983: 05/10/26: Re: state machine with 2 clock's
90985: 05/10/26: Re: state machine with 2 clock's
90992: 05/10/26: Re: state machine with 2 clock's
91002: 05/10/26: Re: Optimizing a State Machine
91003: 05/10/26: Re: crc on only data or including the address
91022: 05/10/27: Re: Cost to go from FPGA to ASIC
91035: 05/10/27: Re: Optimizing a State Machine
91051: 05/10/27: Re: 24 to 32 8-bit PWM outputs
91089: 05/10/28: Re: Virtex-4: SLICEM and SLICEL, why? (Peter Alfke?)
91102: 05/10/29: Re: Spartan-3E starter kit
91115: 05/10/29: Re: Spartan-3E starter kit
91153: 05/10/31: Re: Spartan-3E starter kit
91157: 05/10/31: Re: Virtex-4 DSP48 - special features (Peter Alfke?)
91163: 05/10/31: Re: Spartan-3E starter kit
91170: 05/10/31: Re: Spartan-3E starter kit
91273: 05/11/02: Re: clock detection
91278: 05/11/02: Re: Spartan-3E starter kit
91331: 05/11/03: Re: Spartan-3E starter kit
91352: 05/11/03: Re: I have received a job offer
91397: 05/11/04: Re: Spartan-3E starter kit
91488: 05/11/07: Re: Spartan-3E starter kit
91499: 05/11/07: Re: Spartan-3E starter kit
91602: 05/11/09: Re: Best Case Timing Parameters
91608: 05/11/09: Re: Best Case Timing Parameters
91613: 05/11/09: Re: old xilinx components
91623: 05/11/09: Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?
91647: 05/11/10: Re: fpga speed logic/density MIPS/FLOPS as compared to general purpose microprocessors
91867: 05/11/15: Re: Rise time/fall time for Spartan3 clock inputs
91901: 05/11/16: Re: Rise time/fall time for Spartan3 clock inputs
91904: 05/11/16: Re: XILINX BlockRAM setuphold violation (setup) problems HELP!
92182: 05/11/23: Re: FPGA and metastability once again
92206: 05/11/23: Re: XC2000
92214: 05/11/23: Re: XC2000
92215: 05/11/23: Re: Unconnected Ports
92245: 05/11/24: Re: XC2000
92255: 05/11/24: Re: XC2000
92323: 05/11/27: Re: Virtex 4 Tapped Delay Lines
92329: 05/11/27: Re: Virtex 4 Tapped Delay Lines
92330: 05/11/27: Re: hi
92368: 05/11/28: Re: async fifo design
92418: 05/11/29: Re: Slow FIFO using external SRAM
92432: 05/11/29: Re: Virtex 4 Tapped Delay Lines
92446: 05/11/29: Re: async fifo design
92522: 05/11/30: Re: Xilinx LUT behavior question
92523: 05/11/30: Re: Supplier of Xilinx XC2V1000 or 2V250?
92560: 05/12/01: Re: Supplier of Xilinx XC2V1000 or 2V250?
92582: 05/12/01: Re: Xilinx LUT behavior question
92594: 05/12/01: Re: Xilinx LUT behavior question
92653: 05/12/02: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92704: 05/12/05: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92719: 05/12/05: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
92729: 05/12/05: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92736: 05/12/05: Re: Xilinx Adder Subtracter Core (What's Wrong With Xilinx People??!)
92840: 05/12/07: Re: Embedded ppc405 w/o RAM?
92855: 05/12/07: Re: 2 clocks switching
92933: 05/12/09: Re: No, not FIFOs again...
92949: 05/12/09: Re: No, not FIFOs again...
92956: 05/12/09: Re: XC4VFX12 -- availability?
92985: 05/12/10: Re: No, not FIFOs again...
92986: 05/12/10: Re: Adding "super-LUTs" to FPGA, good idea ?
92999: 05/12/11: Re: Important BRAM safety tip ( was: Adding "super-LUTs" to FPGA, good idea ?)
93132: 05/12/14: Re: Mission critical & low core voltages
93138: 05/12/14: Re: Mission critical & low core voltages
93203: 05/12/15: Re: Xilinx DCM Shuts down at 75degree centigrade
93362: 05/12/20: Re: Place and Route Algorithms
93413: 05/12/21: Re: Place and Route Algorithms
93427: 05/12/21: Re: consensus theorem and power
93521: 05/12/23: Re: RTL for Z8000 series CPU?
93528: 05/12/23: Re: RTL for Z8000 series CPU?
93533: 05/12/23: Re: RTL for Z8000 series CPU?
93535: 05/12/23: Re: RTL for Z8000 series CPU?
93563: 05/12/24: Re: Spartan3e and ChipScope
93590: 05/12/25: Re: Spartan 3 power requirements
93593: 05/12/25: Re: Spartan 3 power requirements
93612: 05/12/26: Re: Spartan 3 power requirements
93614: 05/12/26: Re: Spartan 3 power requirements
93619: 05/12/26: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93623: 05/12/26: Re: Patents and (possible) Plagiarism, Anyone ever been in a similar situation?
93648: 05/12/27: Re: RTL for Z8000 series CPU?
93662: 05/12/27: Re: Virtex-4 CCLK termination
93667: 05/12/27: Re: Virtex-4 CCLK termination
93670: 05/12/27: Re: Virtex-4 CCLK termination
93718: 05/12/28: Re: Virtex-4 CCLK termination
93749: 05/12/29: Re: Power Optimization: can the routing and placement really save power?
93758: 05/12/29: Re: Power Optimization: can the routing and placement really save power?
93800: 05/12/30: Re: Power Optimization: can the routing and placement really save power?
93858: 06/01/02: Re: fx12
93873: 06/01/02: Re: optimization tips (badly) needed
93955: 06/01/03: Re: RTL for Z8000 series CPU?
94021: 06/01/04: Re: Xilinx Spartan3E Sample Pack: Real fun for all Ages!
94078: 06/01/05: Re: Xilinx Spartan3E Sample Pack: Real fun for all Ages!
94001: 06/01/04: Re: DCM spartan 3 variable frequency divider
94010: 06/01/04: Re: DCM spartan 3 variable frequency divider
94091: 06/01/05: Re: Virtex2 I/O state in configure phase
94234: 06/01/08: Re: CRC error correction
94283: 06/01/09: Re: CRC error correction
94238: 06/01/08: Re: CRC error correction
94351: 06/01/10: Re: tcam implemented in fpga
94514: 06/01/12: Re: FPGA Journal Article
94643: 06/01/15: Re: FPGA Journal Article
94648: 06/01/15: Re: FPGA Journal Article
94652: 06/01/15: Re: FPGA Journal Article
94699: 06/01/16: Re: FPGA Journal Article
94892: 06/01/18: Re: FPGA Journal Article
95114: 06/01/20: Re: FPGA Journal Article
94718: 06/01/16: Re: FPGA Journal Article
94650: 06/01/15: Re: what happens in SDR-SDRAM if i exceed tRAS(max)
94752: 06/01/17: Re: FIFO in SDRAM
94762: 06/01/17: Re: FIFO in SDRAM
94764: 06/01/17: Re: FIFO in SDRAM
94891: 06/01/18: Re: FIFO in SDRAM
94774: 06/01/17: Re: S3e slower than S3
94779: 06/01/17: Re: S3e slower than S3
94850: 06/01/18: Re: clock generation with DOPPLER shift
94896: 06/01/18: Re: clock generation with DOPPLER shift
94955: 06/01/19: Re: Xilinx padding LC numbers, how do you feel about it?
94984: 06/01/19: Re: Quadrature Encoder ::
95119: 06/01/20: Re: need for a group FAQ?
95544: 06/01/23: Re: Creating Multiple Configuration PROM File
95152: 06/01/20: Irrelevant, stupid, racist, and worse.
95593: 06/01/24: Re: Irrelevant, stupid, racist, and worse.
95345: 06/01/22: Re: Starting with LVDS
95619: 06/01/24: Re: help:dual-edge flip-flop possible using Verilog?
95640: 06/01/24: Re: help:dual-edge flip-flop possible using Verilog?
95778: 06/01/25: Re: help:dual-edge flip-flop possible using Verilog?
95638: 06/01/24: Re: How to handle the "gate count" issue?
95900: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source interface?
95853: 06/01/26: Re: Current to sink PROG_B low?
95865: 06/01/26: Re: Current to sink PROG_B low?
96151: 06/01/30: Re: power up reset question
96278: 06/02/01: Re: Die Area
96288: 06/02/01: Re: Die Area
96319: 06/02/01: Re: Die Area
96354: 06/02/02: Re: Die Area
96393: 06/02/02: Re: BGA central ground matrix
96353: 06/02/02: Re: high input to CPLD
94753: 06/01/17: Re: FIFO in SDRAM
94851: 06/01/18: Re: clock generation with DOPPLER shift
94956: 06/01/19: Re: Xilinx padding LC numbers, how do you feel about it?
95545: 06/01/23: Re: Creating Multiple Configuration PROM File
95641: 06/01/24: Re: help:dual-edge flip-flop possible using Verilog?
95901: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source interface?
96434: 06/02/03: Re: FPGA growth vs. ASIC growth
96449: 06/02/03: Re: FPGA growth vs. ASIC growth
96459: 06/02/03: Re: FPGA growth vs. ASIC growth
96465: 06/02/03: Re: FPGA growth vs. ASIC growth
96466: 06/02/03: Re: fpga hardware "breakpoint"
96575: 06/02/06: Re: Arbiter for several wires competing
96631: 06/02/07: Re: Arbiter for several wires competing
96697: 06/02/08: Re: BGA central ground matrix
96756: 06/02/09: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest possible speed?
96815: 06/02/10: Re: Spartan3 embedded synchronous multipliers
96835: 06/02/11: Re: Creating low freq. clock on Altera FPGA
96855: 06/02/11: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest possible speed?
96930: 06/02/13: Re: digital logic library by 74xxxx part number?
97007: 06/02/14: Re: digital logic library by 74xxxx part number?
97014: 06/02/14: Re: dynamic partial reconfiguration of Xilinx Virtex-4 FPGAs
97053: 06/02/15: Re: digital logic library by 74xxxx part number?
97055: 06/02/15: Re: EDK Woes and Worries
97107: 06/02/16: Re: Implementing a two-modulus PLL divider in Altera Stratix II
97115: 06/02/16: Re: Need some Advice, please
97164: 06/02/17: Re: Need some Advice, please
97249: 06/02/19: Re: Addressing BRAM in a V2 pro
97339: 06/02/20: Re: FPGA - software or hardware -2-
97570: 06/02/23: Re: Combinatorial Division?
97635: 06/02/24: Re: V4 FIFO16 and SRAM
97650: 06/02/25: Re: V4 FIFO16 and SRAM
97661: 06/02/25: Re: V4 FIFO16 and SRAM
97662: 06/02/25: Re: Combinatorial Division?
97668: 06/02/25: Re: fpga to 5v ttl logic
97673: 06/02/25: Re: Combinatorial Division?
97694: 06/02/26: Re: Combinatorial Division?
97695: 06/02/26: Re: fpga to 5v ttl logic
97696: 06/02/26: Re: Virtex 4 Multiplier RPM Constraints?
97698: 06/02/26: Re: FIFO design
97699: 06/02/26: Re: VHDL to create LUT based delay
97712: 06/02/26: Re: V4 FIFO16 and SRAM
97714: 06/02/26: Re: Virtex 4 Multiplier RPM Constraints?
97717: 06/02/26: Re: V4 FIFO16 and SRAM
97720: 06/02/26: Re: fpga to 5v ttl logic
97723: 06/02/26: Re: Combinatorial Division?
97734: 06/02/26: Re: V4 FIFO16 and SRAM
97805: 06/02/27: Re: VHDL to create LUT based delay
97840: 06/02/28: Re: How do I make dual-port RAM from single port RAM?
97866: 06/02/28: Re: How do I make dual-port RAM from single port RAM?
97900: 06/03/01: Re: fpga to 5v ttl logic
97911: 06/03/01: Re: Pulse Shape in a functional simulation
97921: 06/03/01: Re: Pulse Shape in a functional simulation
97922: 06/03/01: Re: Pulse Shape in a functional simulation
97928: 06/03/01: Re: Pulse Shape in a functional simulation
98057: 06/03/03: Re: why use an FPGA when a CPLD will do ??
98166: 06/03/06: Re: Pullup questions on Spartan3
98173: 06/03/06: Re: Pullup questions on Spartan3
98179: 06/03/06: Re: Asynchronous FIFO design question
98192: 06/03/06: Re: Asynchronous FIFO design question
98250: 06/03/07: Re: Asynchronous FIFO design question
98270: 06/03/07: Re: for all those who believe in ASICs....
98330: 06/03/08: Re: 5v Xilinx development board
98338: 06/03/08: Re: DCM question
98416: 06/03/09: Re: FIFO Simulation Oddities!
98479: 06/03/10: Re: (no subject)
98533: 06/03/12: Re: Combinatorial Division?
98547: 06/03/12: Re: Combinatorial Division?
98548: 06/03/12: Re: Question about multi write ports RAM in FPGA?
98754: 06/03/15: Re: fpga to 5v ttl logic
98818: 06/03/16: Re: for all those who believe in ASICs....
98820: 06/03/16: Re: Urgent Help Needed!!!!!
98833: 06/03/16: Re: Urgent Help Needed!!!!!
98838: 06/03/16: Re: for all those who believe in ASICs....
98874: 06/03/17: Re: for all those who believe in ASICs....
98901: 06/03/17: Re: for all those who have stopped listening, and are ranting now...
98906: 06/03/17: Re: for all those who believe in ASICs....and can't stop ranting
98943: 06/03/17: Re: Where are you heading?
98955: 06/03/17: Re: Support software for XC3042
98956: 06/03/17: Re: Where are FPGA heading?
98959: 06/03/17: Re: Support software for XC3042
98964: 06/03/17: Re: Support software for XC3042
98967: 06/03/17: Re: for all those who believe
99012: 06/03/18: Re: for all those who believe in ASICs....
99016: 06/03/18: Re: Urgent Help Needed!!!!!
99057: 06/03/19: Re: Debugging ideas.
99065: 06/03/19: Re: FPGA FIR advice
99067: 06/03/19: Re: Spartan-3E Sample Pack
99100: 06/03/20: Re: DDS
99254: 06/03/21: Re: need help on asynchronous buffer
99276: 06/03/22: Re: need help on asynchronous buffer
99281: 06/03/22: Re: Fixed vs Float ?
99285: 06/03/22: Re: Going from CLK1X to CLK2X.. really safe?
99288: 06/03/22: Re: need help on asynchronous buffer
99568: 06/03/26: Re: Clock multiplication without using the Xilinx DCM's
99580: 06/03/26: Re: Clock multiplication without using the Xilinx DCM's
99647: 06/03/27: Re: deglitching a clock
99655: 06/03/27: Re: deglitching a clock
99673: 06/03/27: Re: spartan FPGA with PLCC package
99760: 06/03/28: Re: spartan FPGA with PLCC package
100065: 06/04/02: Re: Configuration pins on Spartan-3
100070: 06/04/02: Re: Discrete
100429: 06/04/08: Re: asynchronous FIFO design
100499: 06/04/10: Re: asynchronous FIFO design
100500: 06/04/10: Re: Distributed Arithmetic
100678: 06/04/15: Re: Where is the xilinx online store gone?
100687: 06/04/15: Re: Where is the xilinx online store gone?
100704: 06/04/16: Re: what wrong of this counter ?
100711: 06/04/16: Re: Where is the xilinx online store gone?
100738: 06/04/17: Re: what wrong of this counter ?
100742: 06/04/17: Re: Which is the best way to measure low frequencies?
100762: 06/04/17: Re: Spartan 3 chips in power up
100828: 06/04/18: Re: How is the max clock rate of a device fixed?
100901: 06/04/20: Re: clock mux in spartan2e fpga
100975: 06/04/21: Re: Why Edge is required to read from Block RAM of V4
100999: 06/04/23: Re: Synthesizer is creating unwanted global resources
101114: 06/04/25: Re: clock multiplication
101161: 06/04/26: Re: Async FPGA ~2GHz
101175: 06/04/26: Re: What is the best way to clock data in on one clock edge and out on another?
101183: 06/04/26: Re: Async FPGA ~2GHz
101186: 06/04/26: Re: Async FPGA ~2GHz
101213: 06/04/27: Re: Xilinx: Prohibit propagation of timing constraint through a mux
101215: 06/04/27: Re: Async FPGA ~2GHz
101226: 06/04/27: Re: CLock Issue
101313: 06/04/28: Re: Pull up resistors on Spartan 3 mode pins
101349: 06/04/29: Re: URGENT: Xilinx site
101368: 06/04/29: Re: Pull up resistors on Spartan 3 mode pins
101369: 06/04/29: Re: Spartan 3 documentation confusing...
101371: 06/04/29: Re: Book Software for XC3190A?
101373: 06/04/29: Re: Pull up resistors on Spartan 3 mode pins
101375: 06/04/29: Re: Reset
101378: 06/04/29: Re: Pull up resistors on Spartan 3 mode pins
101400: 06/04/30: Re: design optimization
101419: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
101425: 06/04/30: Re: Spartan 3 documentation confusing...
101430: 06/04/30: Re: Pull up resistors on Spartan 3 mode pins
101455: 06/05/01: Re: Async FPGA ~2GHz
101471: 06/05/01: Re: Async FPGA ~2GHz
101514: 06/05/02: Re: Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler
101515: 06/05/02: Re: LED Driver
101592: 06/05/03: Re: Unreactive Output Pins on Xilinx Virtex-II
101607: 06/05/03: Re: Unreactive Output Pins on Xilinx Virtex-II
101629: 06/05/03: Re: Xilinx 3s8000?
101658: 06/05/04: Re: Phase alignment of DCMs on different boards/devices
101671: 06/05/04: Re: async. load line on shift register
101684: 06/05/04: Re: Xilinx 3s8000?
101741: 06/05/05: Re: Virtex 4 LX25
101753: 06/05/05: Re: Xilinx 3s8000?
101829: 06/05/07: Re: Xilinx 3s8000?
101832: 06/05/07: Re: Xilinx 3s8000?
101837: 06/05/07: Re: Funky experiment on a Spartan II FPGA
101842: 06/05/07: Re: Funky experiment on a Spartan II FPGA
101849: 06/05/07: Re: Xilinx 3s8000?
101858: 06/05/07: Re: Can an FPGA be operated reliably in a car wheel?
101918: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
101923: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
101938: 06/05/08: Re: Xilinx 3s8000?
101940: 06/05/08: Re: flashing a led
101941: 06/05/08: Re: Funky experiment on a Spartan II FPGA
101955: 06/05/08: Re: Xilinx 3s8000?
101965: 06/05/08: Re: Xilinx 3s8000?
101967: 06/05/08: Re: Xilinx 3s8000?
101968: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
101972: 06/05/08: Re: Can an FPGA be operated reliably in a car wheel?
101993: 06/05/09: Re: Funky experiment on a Spartan II FPGA
101996: 06/05/09: Re: Crossing clock domains
102036: 06/05/09: Re: Funky experiment on a Spartan II FPGA
102098: 06/05/10: Re: CoolRunner XPLA3 getting axed?
102107: 06/05/10: CoolRunner XPLA3 thriving for many years to come
102115: 06/05/10: Re: CoolRunner XPLA3 getting axed?
102135: 06/05/10: Re: CoolRunner XPLA3 thriving for many years to come
102137: 06/05/10: Re: Interrupt signal sampling (Level or edge?)
102138: 06/05/10: Re: Xilinx warning for DCM
102264: 06/05/12: Re: clock multiplier in spartan 2
102363: 06/05/15: Re: Make a signal free for glitches?
102384: 06/05/15: Re: Virtex 5 announced
102388: 06/05/15: Re: getting good deals on small qty?
102390: 06/05/15: Re: Virtex 5 announced and sampling
102409: 06/05/15: Re: Virtex 5 announced and sampling
102442: 06/05/16: Re: Make a signal free for glitches?
102454: 06/05/16: Re: Virtex 5 announced and sampling
102458: 06/05/16: Re: Virtex 5 announced and sampling
102463: 06/05/16: Re: Virtex 5 announced and sampling
102474: 06/05/16: Re: Virtex4 FX12 dynamic clock divider
102475: 06/05/16: Re: Xilinx or Altera...
102481: 06/05/16: Re: Spartan 3E
102486: 06/05/16: Re: Xilinx or Altera...
102487: 06/05/16: Re: getting good deals on small qty?
102494: 06/05/16: Re: Virtex4 FX12 dynamic clock divider
102550: 06/05/17: Re: "disappointing" performance
102551: 06/05/17: Re: getting good deals on small qty?
102576: 06/05/17: Re: Make a signal free for glitches?
102656: 06/05/18: Re: DCM and Clock
102664: 06/05/18: Re: V5 and carry lookahead
102762: 06/05/19: Re: "disappointing" performance
102788: 06/05/20: Re: Signal 2 clocks long but only one clock possible
102795: 06/05/20: Re: CPLD (CoolRunner failures)
102851: 06/05/22: Re: Independent clock FIFOs
102857: 06/05/22: Re: CPLD (CoolRunner failures)
102951: 06/05/23: Re: xilinx pricing discrepancy
102954: 06/05/23: Re: xilinx pricing discrepancy
102963: 06/05/23: Re: xilinx pricing discrepancy
103037: 06/05/24: Re: xilinx pricing discrepancy
103077: 06/05/25: Re: Metastability question (newbie)
103080: 06/05/25: Re: setting max fanout with xps flow
103098: 06/05/25: Re: setting max fanout with xps flow
103112: 06/05/25: Re: DSP48E, What are the internal implementations used?
103121: 06/05/25: Re: DSP48E, What are the internal implementations used?
103191: 06/05/27: Re: Independent clock FIFOs
103254: 06/05/29: Re: Fast Serial I/O on Virtex-5
103316: 06/05/30: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103369: 06/05/31: Re: How do I scale a 9-b signed 2's complement data by 17/sqrt(21)?
103377: 06/05/31: Re: clockless arbiters on fpgas?
103425: 06/06/01: Re: timings
103430: 06/06/01: Re: clockless arbiters on fpgas?
103433: 06/06/01: Re: clockless arbiters on fpgas?
103460: 06/06/02: Re: clockless arbiters on fpgas?
103477: 06/06/03: Re: Difference Logic Cells <=> Slices
103498: 06/06/04: Re: Asynchronous BRAM input ?
103526: 06/06/05: Re: Asynchronous BRAM input ?
103532: 06/06/05: Re: timings
103548: 06/06/05: Re: Asynchronous BRAM input ?
103554: 06/06/05: Re: Webpack larger than CDs
103557: 06/06/05: Re: Webpack larger than CDs
103601: 06/06/06: Re: Propagation delay sensitivity to temperature, voltage, and manufacturing
103642: 06/06/07: Re: FlipChip BGA Conformal Coating
103666: 06/06/07: Re: IOBDELAY's delay value
103673: 06/06/07: Re: STOP IT :)
103674: 06/06/07: Re: IOBDELAY's delay value
103684: 06/06/07: Re: Block Ram vs Distributed Ram
103694: 06/06/08: Re: Block Ram vs Distributed Ram
103729: 06/06/09: Re: Current from FPGA pins to ADC
103786: 06/06/11: Re: Anyone with Xilinx SP305-board ?
103830: 06/06/12: Re: Virtex4 DCM in DRP mode
103831: 06/06/12: Re: Virtex4 DCM in DRP mode
103857: 06/06/13: Re: IDELAY clock spec. in Xilinx V4
103868: 06/06/13: Re: IDELAY clock spec. in Xilinx V4
103955: 06/06/15: Re: clockless arbiters on fpgas?
103965: 06/06/15: Re: clockless arbiters on fpgas? [here's how it's done in ASICs]
104003: 06/06/16: Re: LVTTL or LVCMOS for PCI Signaling?
104034: 06/06/16: Re: Anyone get a Pictiva OLED to work?
104059: 06/06/17: Re: LVTTL or LVCMOS for PCI Signaling?
104060: 06/06/17: Re: Anyone with Xilinx SP305-board ?
104067: 06/06/18: Re: LVTTL or LVCMOS for PCI Signaling?
104068: 06/06/18: Re: High speed differential to single ended
104072: 06/06/18: Re: High speed differential to single ended
104078: 06/06/18: Re: High speed differential to single ended
104079: 06/06/18: Re: Newbie to FPGA
104082: 06/06/18: Re: Newbie to FPGA
104083: 06/06/18: Re: High speed differential to single ended
104189: 06/06/20: Re: comp.arch.fpga : Selection of Device
104236: 06/06/21: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
104253: 06/06/21: Re: SerDES with FPGA Rocket I/O, Aurora at 40 Gbits/sec???
104330: 06/06/23: Re: Spartan3 or 3E pins to GND
104331: 06/06/23: Re: Optimization of Multiplication in FPGA
104353: 06/06/25: Re: Test:PRBS
104382: 06/06/26: Re: PicoBlaze and DDR Ram
104407: 06/06/26: Re: keys to the Kingdom
104446: 06/06/27: Re: Xilinx ML461 memory board, whats the real story?
104450: 06/06/27: Re: keys to the Kingdom
104454: 06/06/27: Re: keys to the Kingdom
104566: 06/06/29: Re: Xilinx BUFGMUX Setup Time requirement clarification needed
104620: 06/07/01: Re: stable reset in fpga
104675: 06/07/03: Re: Chaos in FF metastability
104684: 06/07/03: Re: Chaos in FF metastability
104747: 06/07/05: Re: "Large" memory array in VHDL
104753: 06/07/05: Re: Chaos in FF metastability
104767: 06/07/05: Re: Chaos in FF metastability
104780: 06/07/05: Re: stable reset in fpga
104823: 06/07/06: Re: Chaos in FF metastability
104863: 06/07/07: Re: Chaos in FF metastability
104867: 06/07/07: Re: stable reset in fpga
104877: 06/07/07: Re: Chaos in FF metastability
104878: 06/07/07: Re: Chaos in FF metastability
104891: 06/07/08: Re: Chaos in FF metastability
104896: 06/07/08: Re: Can I use all 18bits of a BlockRAM?
104926: 06/07/09: Re: The FFs with synchronous reset perform worse?
104950: 06/07/10: Re: LUT4 INIT value to implement 2:1 MUX ?
104955: 06/07/10: Re: High-speed DAC/ADC with FPGA
106169: 06/08/08: Re: 100 Mbit manchester coded signal in FPGA
106178: 06/08/08: Re: 100 Mbit manchester coded signal in FPGA
106181: 06/08/08: Re: 100 Mbit manchester coded signal in FPGA
106186: 06/08/08: Re: 100 Mbit manchester coded signal in FPGA
106253: 06/08/09: Re: 100 Mbit manchester coded signal in FPGA
106278: 06/08/10: Re: Switching two (synchronous) clocks with variable phase difference, without glitching or period loss
106286: 06/08/10: Re: Switching two (synchronous) clocks with variable phase difference, without glitching or period loss
106339: 06/08/11: Re: 100 Mbit manchester coded signal in FPGA
106343: 06/08/11: Re: Clock domain crossing (again)
106414: 06/08/12: Re: Maximum Current Draw of FPGA
106416: 06/08/12: Re: Maximum Current Draw of FPGA
106444: 06/08/13: Re: Maximum Current Draw of FPGA
106519: 06/08/14: Re: Crystal input for FPGA
106529: 06/08/14: Re: Crystal input for FPGA
106579: 06/08/15: Re: Maximum Current Draw of FPGA
106640: 06/08/16: Re: FPGA Memory Power
106697: 06/08/17: Re: DCM and Maximum Frequency implied by XST
106819: 06/08/20: Re: CPU design
107010: 06/08/23: Re: fastest FPGA
107048: 06/08/23: Re: DCM vs. PLL
107082: 06/08/24: Re: Why No Process Shrink On Prior FPGA Devices ?
107085: 06/08/24: Re: Xilinx BRAMs question - help needed ..
107088: 06/08/24: Re: Global signal conservation
107129: 06/08/24: Re: Why No Process Shrink On Prior FPGA Devices ?
107138: 06/08/24: Re: Xilinx BRAMs question - help needed ..
107154: 06/08/24: Re: fastest FPGA
107158: 06/08/24: Re: fastest FPGA
107160: 06/08/24: Re: fastest FPGA
107164: 06/08/24: Re: Why No Process Shrink On Prior FPGA Devices ?
107198: 06/08/25: Re: Why No Process Shrink On Prior FPGA Devices ?
107272: 06/08/25: Re: fastest FPGA
107300: 06/08/26: Re: What is the truth about the Virtex5 ?
107306: 06/08/26: Re: fastest FPGA
108113: 06/09/05: Re: FPGA multiplier
108140: 06/09/05: Re: Serial I/O Question
108142: 06/09/05: Re: fastest FPGA
108177: 06/09/06: Re: NON-CLK pins failed to route using a CLK template
108228: 06/09/06: Re: fastest FPGA
108284: 06/09/07: Re: 2 FF synchronizer
108361: 06/09/08: Re: Why No Process Shrink On Prior FPGA Devices ?
108392: 06/09/10: Re: HOLD violations in Xilinx fpga
108511: 06/09/12: Re: FPGA timing
108513: 06/09/12: Re: Spartan-3: 5V -> 2.5V level shifting
108538: 06/09/12: Re: Spartan-3: 5V -> 2.5V level shifting
108596: 06/09/13: Re: Spartan-3: 5V -> 2.5V level shifting
108675: 06/09/14: Re: Spartan3 driving mosfets
108676: 06/09/14: Re: Spartan3 driving mosfets
108680: 06/09/14: Re: Unwanted clock on output pin....
108800: 06/09/16: Re: XIlinx Spartan 2E stuck in configuration mode
108803: 06/09/16: Re: XIlinx Spartan 2E stuck in configuration mode
108872: 06/09/18: Re: XPLA3 going obsolete?
108886: 06/09/18: Are you ready for Virtex-5? We are...
108890: 06/09/18: Re: regarding 4 bit multiplier
108891: 06/09/18: Re: Are you ready for Virtex-5? We are...
108932: 06/09/19: Re: Buffering the critical path.
108964: 06/09/19: Re: Buffering the critical path.
108992: 06/09/19: Re: Metastability resolution
108994: 06/09/19: Re: Metastability resolution
108999: 06/09/19: Re: Buffering the critical path.
109003: 06/09/19: Re: synchronous clocks
109109: 06/09/20: Re: Metastability resolution
109159: 06/09/21: Re: Are you ready for Virtex-5? We are...
109177: 06/09/21: Re: Are you ready for Virtex-5? We are...
109274: 06/09/22: Re: X4000 bad configuration
109312: 06/09/23: Re: X4000 bad configuration
109317: 06/09/23: Re: X4000 bad configuration
109325: 06/09/23: Re: X4000 bad configuration
109330: 06/09/24: Re: X4000 bad configuration
109375: 06/09/25: Re: state machine dead problem
109437: 06/09/26: Re: PUBLISHABLE PAPER RELATED TO FPGA!
109507: 06/09/27: Re: synchronous clocks
109523: 06/09/27: Re: PUBLISHABLE PAPER RELATED TO FPGA!
109555: 06/09/28: Re: Are you ready for Virtex-5? We are...
109617: 06/10/01: Re: Are you ready for Virtex-5? We are...
109624: 06/10/01: Re: Are you ready for Virtex-5? We are...
109734: 06/10/04: Re: Are you ready for Virtex-5? We are...
109771: 06/10/05: Re: Generate 16MHz from 75MHz using DCM
109775: 06/10/05: Re: Just a matter of time
109782: 06/10/05: Re: Virtex-5 FX when ?
109783: 06/10/05: Re: Generate 16MHz from 75MHz using DCM
109894: 06/10/06: Re: Just a matter of time
109912: 06/10/07: Re: VHDL count error when cascading
109915: 06/10/07: Re: Spartan 3 Starter Kit I/O ports
109945: 06/10/08: Re: An implementation of a clean reset signal
109948: 06/10/08: Re: Antifuse, lower cost?
109950: 06/10/08: Re: An implementation of a clean reset signal
109953: 06/10/08: Re: Antifuse, lower cost?
109984: 06/10/09: Re: Antifuse, lower cost?
109985: 06/10/09: Re: An implementation of a clean reset signal
110004: 06/10/09: Re: An implementation of a clean reset signal
110005: 06/10/09: Re: An implementation of a clean reset signal
110009: 06/10/09: Re: Antifuse, lower cost?
110028: 06/10/09: Re: Antifuse, lower cost?
110040: 06/10/09: Re: CPLD's and labels
110085: 06/10/10: Re: Xilinx coregen fifo
110095: 06/10/10: Re: Antifuse, lower cost?
110164: 06/10/11: Re: Antifuse, lower cost?
110234: 06/10/12: Re: Xilinx coregen fifo
110253: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110257: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110261: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110264: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110267: 06/10/12: Re: OT: Internships?
110270: 06/10/12: Re: Glitches in post-layout (PAR) simulation
110303: 06/10/13: Re: Are you ready for Virtex-5? We are...
110304: 06/10/13: Re: Virtex-5 LXT orderable?
110310: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
110329: 06/10/13: Re: Xilinx FPGAs in battery-powered scenarios
110381: 06/10/14: Re: Xilinx FPGAs in battery-powered scenarios
110393: 06/10/14: Re: Xilinx documentation typos
110394: 06/10/14: Re: Xilinx FPGAs in battery-powered scenarios
110396: 06/10/14: Re: Xilinx FPGAs in battery-powered scenarios
110419: 06/10/15: Re: how to change cclk frequency ?
110421: 06/10/15: Re: Xilinx FPGAs in battery-powered scenarios
110422: 06/10/15: Re: Xilinx documentation typos
110599: 06/10/18: Re: 64 bit division compensate NCO
110871: 06/10/24: Re: XC2V80005FF1517C
110918: 06/10/25: Re: Meta-stable problem with MAX-II ?
110936: 06/10/25: Re: Meta-stable problem with MAX-II ?
110939: 06/10/25: Re: Am I seeing meta-stable or what?
110942: 06/10/25: Re: Xilinx documentation typos
110960: 06/10/25: Re: Xilinx documentation typos
110981: 06/10/26: Re: xilinx sync fifo with first word fall-through
111046: 06/10/27: Re: Xilinx documentation typos
111047: 06/10/27: A spectre is haunting this newsgroup, the spectre of metastability
111048: 06/10/27: Re: Xilinx documentation typos
111049: 06/10/27: Re: Xilinx documentation typos
111053: 06/10/27: A spectre is haunting this newsgroup, the spectre of metastability
111059: 06/10/27: Re: A spectre is haunting this newsgroup, the spectre of metastability
111063: 06/10/27: Re: A pre-emptive strike against blaming the chip
111067: 06/10/27: Re: On the Futility of Documentation Webcases ( Was: Xilinx documentation typos )
111088: 06/10/28: Re: A pre-emptive strike against blaming the chip
111097: 06/10/28: Re: A pre-emptive strike against blaming the chip
111113: 06/10/29: Re: A pre-emptive strike against blaming the chip
111126: 06/10/29: Re: On the Futility of Documentation Webcases ( Was: Xilinx documentation typos )
111149: 06/10/30: Re: Jumps in FPGA implemented integrator
111160: 06/10/30: Re: On the Futility of Documentation Webcases ( Was: Xilinx documentation typos )
111182: 06/10/30: Re: How stable is the internal clock of a Xilinx CPLD?
111185: 06/10/30: Re: A pre-emptive strike against blaming the chip
111195: 06/10/30: Re: A pre-emptive strike against blaming the chip
111198: 06/10/30: Re: How stable is the internal clock of a Xilinx CPLD?
111247: 06/10/31: Re: Dual Port RAM
111254: 06/10/31: Re: Dual Port RAM
111256: 06/10/31: Re: Need just a few 5V Spartan
111257: 06/10/31: Re: A spectre is haunting this newsgroup, the spectre of metastability
111261: 06/10/31: Re: Question about bandwidth of scope?
111266: 06/10/31: Re: DSP48 carry logic for multi-precision addition
111277: 06/10/31: Re: Dual Port RAM
111279: 06/10/31: Re: Dual Port RAM
111314: 06/11/01: Re: A spectre is haunting this newsgroup, the spectre of metastability
111316: 06/11/01: Re: De-serializer using Xilinx DCM
111318: 06/11/01: Re: Spectre of Metastability Update
111327: 06/11/01: Re: De-serializer using Xilinx DCM
111330: 06/11/01: Re: Interface standards (was Re: Dual Port RAM)
111335: 06/11/01: Re: Interface standards (was Re: Dual Port RAM)
111341: 06/11/01: Re: De-serializer using Xilinx DCM
111342: 06/11/01: Re: Interface standards (was Re: Dual Port RAM)
111343: 06/11/01: Re: Spectre of Metastability Update
111353: 06/11/01: Re: De-serializer using Xilinx DCM
111364: 06/11/01: Re: Dual Port RAM
111365: 06/11/01: Re: Dual-port BlockRAM "write first" puzzler...
111406: 06/11/02: Re: Interface standards (was Re: Dual Port RAM)
111413: 06/11/02: Re: Interface standards (was Re: Dual Port RAM)
111479: 06/11/03: Re: Spectre of Metastability Update
111537: 06/11/04: Re: Interface standards (was Re: Dual Port RAM)
111552: 06/11/05: Re: Interface standards (was Re: Dual Port RAM)
111613: 06/11/06: Re: Global Clocks in Xilinx Virtex-4
111618: 06/11/06: Re: Global Clocks in Xilinx Virtex-4
112911: 06/11/30: Re: Old XCell journals gone?
112962: 06/12/02: Re: LUT input order
113007: 06/12/04: Re: LUT input order
113010: 06/12/04: Re: LUT input order
113055: 06/12/05: Re: Spartan-3A launched
113066: 06/12/05: Re: Free Anydivider, Divide clock by any number
113068: 06/12/05: Re: Timing constraings: min delay?
113069: 06/12/05: Re: How to check high impedance of a RAM with Logic Analyzer
113111: 06/12/06: Re: Free Anydivider, Divide clock by any number
113121: 06/12/06: Re: Clock phase shift
113135: 06/12/06: Re: How do I delay signal to pad?
113142: 06/12/06: Re: Free Anydivider, Divide clock by any number
113144: 06/12/06: Re: How to reduce jitter of 30-bit accumulator
113152: 06/12/06: Re: Spartan-3A launched
113180: 06/12/07: Re: Free Anydivider, Divide clock by any number
113346: 06/12/11: Re: spartan3E : which differential inputs level fits CAN2B bus level ?
113364: 06/12/11: Re: Give me job :)
113398: 06/12/12: Re: Virtex4 : cleaner signals?
113444: 06/12/13: Re: FPGA : Async FIFO, Programmable full
113484: 06/12/14: Re: FPGA : Async FIFO, Programmable full
113509: 06/12/14: Re: FPGA : Async FIFO, Programmable full
113576: 06/12/17: Re: FPGA : Async FIFO, Programmable full
113591: 06/12/17: Re: FPGA : Async FIFO, Programmable full
113596: 06/12/17: Re: FPGA : Async FIFO, Programmable full
113621: 06/12/18: Re: FPGA : Async FIFO, Programmable full
113625: 06/12/18: Re: Frequency divider?
113688: 06/12/19: Re: Frequency divider ?
113697: 06/12/19: Re: FPGA : Async FIFO, Programmable full
113976: 06/12/31: Re: xilinx xc9536?
113980: 07/01/01: Re: xilinx xc9536?
114023: 07/01/02: Re: xilinx xc9536?
114054: 07/01/03: Re: newbie needs help
114059: 07/01/03: Re: FPGA ROUTING
114149: 07/01/05: Re: Spartan3E minimum clock-to-output (hold time)
114152: 07/01/05: Re: Virtex 4 FIFO question
114252: 07/01/08: Re: Variable clock using Virtex 4?
114280: 07/01/10: Re: crossing clock domain ??
114290: 07/01/10: Re: crossing clock domain ??
114298: 07/01/10: Re: crossing clock domain ??
114387: 07/01/13: Re: IDELAY and whether pigs can fly...
114451: 07/01/16: Re: Digital Filter and external PLL (VCO)
114505: 07/01/17: Re: Generation of Divided-by-3 clock
114532: 07/01/18: Re: Generation of Divided-by-3 clock
114592: 07/01/19: Re: Phasse Detector
114615: 07/01/20: Re: suggest me the right fpga
114628: 07/01/21: Re: project help
114758: 07/01/23: Re: "Divide" a video line in two stripe
114833: 07/01/24: Re: Does xiling cpld's need a power supply bypass cap?
114840: 07/01/24: Re: Aligning data with clock
114874: 07/01/25: Re: On-chip randomness (V4FX)
114952: 07/01/27: Re: On-chip randomness (V4FX)
114960: 07/01/27: Re: Minimal design for xilinx?
114971: 07/01/28: Re: Minimal design for xilinx?
115124: 07/01/31: Re: cpld version?
115131: 07/01/31: Re: DDR FPGA Design
115139: 07/01/31: Re: DDR FPGA Design
115147: 07/01/31: Re: cpld version?
115216: 07/02/02: Re: Xilinx Interconnects/Routing
115227: 07/02/03: Re: Xilinx Interconnects/Routing
115230: 07/02/04: Re: Differential pairs per Bank
115237: 07/02/04: Re: Xilinx Interconnects/Routing
115238: 07/02/04: Re: Xilinx Interconnects/Routing
115239: 07/02/04: Re: Reconfiguration
115269: 07/02/05: Re: moving data from slower to faster clock domain
115270: 07/02/05: Re: DDR FPGA Design
115282: 07/02/05: Re: Is Digilent still in business ???
115371: 07/02/08: Re: Replacing/emulating an asynchronous FIFO
115393: 07/02/08: Re: Question Regarding Look-Up Tables and Access Time/Levels of Logic
115411: 07/02/09: Re: Question Regarding Look-Up Tables and Access Time/Levels of Logic
115414: 07/02/09: Re: Replacing/emulating an asynchronous FIFO
115448: 07/02/11: Re: CLOCK GENERATOR
115450: 07/02/11: Re: question about DCM in virtex5: fails the maximum period check
115484: 07/02/12: Re: substracting a whole array of values at once
115565: 07/02/13: Re: Typical clock frequencies of FPGA designs
115630: 07/02/15: Re: Need fair opinions on choosing either Altera or Xilinx as main FPGA source
115641: 07/02/15: Do you like Virtex-5 ?
115645: 07/02/15: Re: Do you like Virtex-5 ?
115743: 07/02/18: Re: best way to get 4xclk
115744: 07/02/18: Re: Testing FPGA
115795: 07/02/20: Re: Selecting device in Project Properties : no XC2V1000?
115834: 07/02/21: Re: Determine error in asynchronous signal
115859: 07/02/22: Re: Determine error in asynchronous signal
115922: 07/02/25: Re: Edge vs Level triggering
115937: 07/02/26: Re: Virtex 4, how do I generate 100khz clock
115957: 07/02/26: Re: Spartan-3AN
116126: 07/03/01: Virtex-5 are available from distribution
116159: 07/03/02: Re: Making a 32KB BRAM block, virtex-4
116200: 07/03/04: Re: Multiplication operation
116208: 07/03/04: Re: Multiplication operation
116292: 07/03/06: Re: Block RAM in VirtexE FPGA - 'Read-after-Write' and 'No-Read-on-Write' modes
116311: 07/03/06: Re: Block RAM in VirtexE FPGA - 'Read-after-Write' and 'No-Read-on-Write' modes
116337: 07/03/07: Re: VHDL and Latch
116350: 07/03/07: Re: Spartan3AN - Roadmap
116373: 07/03/07: Re: Introducing picosecond delay between two output signals
116412: 07/03/08: Re: VHDL and Latch
116467: 07/03/09: Re: Xilin X-Fest Lunacy
116473: 07/03/09: Re: Xilin X-Fest Lunacy
116479: 07/03/09: Re: Xilin X-Fest Lunacy
116483: 07/03/09: Re: Xilin X-Fest Lunacy
116487: 07/03/10: Re: Addressing scheme in Block RAM
116491: 07/03/10: Re: Xilin X-Fest Lunacy
116493: 07/03/10: Re: Addressing scheme in Block RAM
116540: 07/03/12: Re: Xilin X-Fest Lunacy
116551: 07/03/12: Re: PAL
116559: 07/03/12: Re: Xilin X-Fest Lunacy
116562: 07/03/12: Re: Dual edge detection
116589: 07/03/13: Re: Addressing scheme in Block RAM
116591: 07/03/13: Re: Dual edge detection
116610: 07/03/13: Re: Xilin X-Fest Lunacy
116662: 07/03/14: Re: Clearing fpga internal memory...
116664: 07/03/14: Welcome to X-Fest 2007
116710: 07/03/15: Re: Clearing fpga internal memory...
116778: 07/03/17: Re: Use of both positive reference and negative reference of the same signal for Xilinx chips would cause additional LUT delay?
116800: 07/03/18: Re: FPGA vs. GPP anyone?
116858: 07/03/19: Re: Sparten 3E clock generator
116919: 07/03/20: Re: Virtex-II block RAM problem
117156: 07/03/24: Re: shift register with distributed ram
117176: 07/03/25: Re: shift register with distributed ram
117208: 07/03/26: Re: how to read a sequence of video
117228: 07/03/26: Re: Variable delay line (was Re: shift register with distributed ram)
117293: 07/03/27: Re: What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L
117432: 07/03/30: Re: shift register with distributed ram
117444: 07/03/30: Re: What is the best application notes or patents filed by Xilinx to disclose Vertex-5 Slice L
117445: 07/03/30: Re: Help with a face recognition system
117453: 07/03/31: Re: Help with a face recognition system
117616: 07/04/04: Re: fifo occupancy bigger than fifo size?
117647: 07/04/05: Re: suitability of systolic architecture on FPGA
117759: 07/04/09: Re: Word sync in Cypress FX2 fifos /w 8 bit bus
117798: 07/04/10: Re: Ross Freeman - inventor of the FPGA
117800: 07/04/10: Re: Flip Flop problem (asynchronous or synchronous???? )
117904: 07/04/12: Re: SETUP & HOLD time confusion
118039: 07/04/16: Re: dual port memory from single port RAM.
118054: 07/04/16: Re: dual port memory from single port RAM.
118113: 07/04/17: Re: SETUP & HOLD time confusion
118119: 07/04/17: Re: Block RAM strange behavior, address off by one
118146: 07/04/18: Re: Block RAM strange behavior, address off by one
118156: 07/04/18: Re: Block RAM strange behavior, address off by one
118157: 07/04/18: Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
118173: 07/04/18: Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
118220: 07/04/19: Re: dual port memory from single port RAM.
118282: 07/04/21: Re: Ouputs during startup and Programming
118319: 07/04/23: Re: Ouputs during startup and Programming
118358: 07/04/24: Re: FPGA and DAC for wave generation
118457: 07/04/26: Re: physical chip size
118478: 07/04/27: Re: a question about DDFS
118481: 07/04/27: Re: Problem cascading 2 DCMs
118513: 07/04/28: Re: physical chip size
118522: 07/04/28: Re: driving Spartan-3 input from 74LS TTL
118529: 07/04/29: Re: physical chip size
118532: 07/04/29: Re: debounce state diagram FSM
118546: 07/04/29: Re: driving Spartan-3 input from 74LS TTL
118607: 07/04/30: Re: debounce state diagram FSM
118860: 07/05/04: Re: Select pullup, pulldown or none via embedded S/W
118892: 07/05/06: Re: V5 LVPECL Inputs
118928: 07/05/07: Re: FF setup and hold time.
118934: 07/05/07: Re: V5 LVPECL Inputs
119038: 07/05/09: Re: How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4
119069: 07/05/10: Re: How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4
119070: 07/05/10: Re: How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4
119075: 07/05/10: Re: How to get 240Mhz clock (8x) using 30Mhz clock input in Virtex4
119106: 07/05/11: =?iso-8859-1?q?Re:_power_consumption_of_integrated_circuit_in_0=2E13=B5m_CMOS_technology?=
119107: 07/05/11: Re: how to choose the perfect fpga support
119111: 07/05/11: Re: how to choose the perfect fpga support
119308: 07/05/16: Re: how to delay a signal in virtex FPGA
119309: 07/05/16: Re: clock wide pulse transfer b/w clock domains
119325: 07/05/16: Re: clock wide pulse transfer b/w clock domains
119331: 07/05/16: Re: CML output swing for V5
119340: 07/05/16: Re: CML output swing for V5
119342: 07/05/16: Re: CML output swing for V5
119370: 07/05/17: Re: clock wide pulse transfer b/w clock domains
119386: 07/05/17: Re: clock wide pulse transfer b/w clock domains
119426: 07/05/18: Re: Power Consumption near Timing Failure Point
119431: 07/05/18: Re: video soltion provider
119449: 07/05/19: Re: external clock frequency doubles
119494: 07/05/21: Re: external clock frequency doubles
119514: 07/05/21: Re: Timing not met but working on board
119574: 07/05/22: Re: LVCMOSS33 I/O sink current
119578: 07/05/22: Re: Design running on board but timing are not met
119595: 07/05/23: Re: LVCMOSS33 I/O sink current
119670: 07/05/24: Re: Use BRAM as ROM (Xilinx)
119712: 07/05/24: Re: Binary to BCD
119787: 07/05/25: Re: Use BRAM as ROM (Xilinx)
119821: 07/05/26: Re: Spartan3 LVCMOS33 Slew rate
119822: 07/05/26: Re: Spartan3 LVCMOS33 Slew rate
119826: 07/05/26: Re: Spartan3 LVCMOS33 Slew rate
119837: 07/05/27: Re: Best way of moving paralell bits of data from over clock domains?
119871: 07/05/28: Re: Rodney Smith, long term Altera CEO, dies in accident
119928: 07/05/29: Xilinx Seminars in Wiesbaden, Berlin, Hannover
119948: 07/05/29: Re: Use BRAM as ROM (Xilinx)
119990: 07/05/30: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
119992: 07/05/30: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
120003: 07/05/30: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
120041: 07/05/31: Re: Chain of LUTs is being removed during par
120056: 07/05/31: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
120061: 07/05/31: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
120077: 07/05/31: Re: Xilinx Seminars in Wiesbaden, Berlin, Hannover
120190: 07/06/02: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
120938: 07/06/20: Want to become part of Xilinx Applications Engineering ?
121027: 07/06/22: Re: How to deal with unavoidable setup time violation in CoolRunner II cpld?
121145: 07/06/26: Re: Can FPGAs inputs detect low currents?
121278: 07/06/29: Re: Xilinx FPGA to interface to special I/O
121344: 07/07/02: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121415: 07/07/03: Re: Hobbyist trying to decide which device to start with...
121569: 07/07/08: Re: Doubt in Asynchronus Circuit design
121695: 07/07/11: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121851: 07/07/13: Re: Counter ?
121877: 07/07/13: Re: Image Resolution Rescaling
121944: 07/07/15: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
122167: 07/07/21: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
122177: 07/07/22: Re: FIFO Full logix - V4
122244: 07/07/24: Re: 3 input adder in Spartan 3E
122245: 07/07/24: Re: 3 input adder in Spartan 3E
122268: 07/07/24: Re: 3 input adder in Spartan 3E
122333: 07/07/25: Re: Documentation/leds/simulation
122349: 07/07/25: Re: Altera or Xilinx
122357: 07/07/25: Re: Altera or Xilinx
122382: 07/07/26: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122389: 07/07/26: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122449: 07/07/27: Re: or1200 uses more than 100% of resources. how to reduce?
122461: 07/07/27: Re: or1200 uses more than 100% of resources. how to reduce?
122492: 07/07/28: Re: dual port ram
122645: 07/08/01: Re: Altera or Xilinx
122862: 07/08/08: Re: New Xilinx forum.
122894: 07/08/09: Re: New Xilinx forum.
122920: 07/08/10: Re: Amount of wire and logic
122926: 07/08/10: Re: Amount of wire and logic
122940: 07/08/11: Re: Amount of wire and logic
122948: 07/08/11: Re: Amount of wire and logic
122963: 07/08/12: Re: LUT distributed memory in FPGA devices
122964: 07/08/12: Re: Amount of wire and logic
122985: 07/08/13: Re: Xilinx 13th August opportunity
123029: 07/08/14: Re: Delaying a pulse train
123034: 07/08/14: Re: Delaying a pulse train
123041: 07/08/14: Re: Delaying a pulse train
123046: 07/08/14: Re: Delaying a pulse train
123071: 07/08/15: Re: Amount of wire and logic
123123: 07/08/16: Re: Delaying a pulse train
123166: 07/08/17: Re: FIFO16 on virtex4 error?
123182: 07/08/18: Re: DDR controller - best device to perform
123230: 07/08/20: Old issues of XCell magazine
123233: 07/08/20: Re: At what frequencies is it acceptable to generate a clock from a register?
123241: 07/08/20: Re: Amount of wire and logic
123263: 07/08/21: Re: Voltage translation question
123287: 07/08/22: Re: Power Reduction Strategy
123303: 07/08/22: Re: At what frequencies is it acceptable to generate a clock from a register?
123335: 07/08/23: Re: At what frequencies is it acceptable to generate a clock from a register?
123607: 07/08/30: Re: Die size, pitch size?
123658: 07/08/31: Re: Die size, pitch size?
123661: 07/08/31: Re: Die size, pitch size?
123795: 07/09/04: Re: Multiple CPLDs on a PCB.
123800: 07/09/04: Re: Multiple CPLDs on a PCB.
123882: 07/09/06: Re: Is it possible to perform gate level simulation on a design without a reset?
123913: 07/09/06: Re: Clock boundary crossing
123922: 07/09/06: Re: VCCAUX too high on a Spartan 3 design
123926: 07/09/06: Re: VCCAUX too high on a Spartan 3 design
123958: 07/09/07: Re: VCCAUX too high on a Spartan 3 design
124017: 07/09/10: Re: What is called carry chain structure in FPGA is called in IC?
124021: 07/09/10: Re: Uses of Gray code in digital design
124135: 07/09/12: Re: Uses of Gray code in digital design
124211: 07/09/14: Re: Physical Design Contribution to FPGA/CPLD success
124576: 07/09/26: Re: Gated Clock Problems
124645: 07/09/28: Re: 2 leg crystal on FPGA: Lattice vs Xilinx
124800: 07/10/04: Re: Optimized bitcounting on FPGA
124820: 07/10/05: Re: Optimized bitcounting on FPGA
125253: 07/10/18: Re: Fast Sampling of digital signals
125260: 07/10/18: Re: Fast Sampling of digital signals
125309: 07/10/19: Re: FPGA input level conversion
125367: 07/10/23: Re: Changing refresh rate for DRAM while in operation?
125391: 07/10/24: Re: Changing refresh rate for DRAM while in operation?
125467: 07/10/25: Re: Changing refresh rate for DRAM while in operation?
125572: 07/10/29: Re: FPGA Configuration
125586: 07/10/29: Re: FPGA Configuration
125675: 07/10/31: Re: Ping Jim: The PFD is dead!
125677: 07/10/31: Re: FPGA vs ASIC
125687: 07/10/31: Re: Ping Jim: The PFD is dead!
125688: 07/10/31: Re: FPGA vs ASIC
125704: 07/11/01: Re: can i use dual edge or two clocks?
125726: 07/11/01: Re: Another way to handle floating inputs.
125744: 07/11/02: Re: Another way to handle floating inputs.
125752: 07/11/02: Re: Another way to handle floating inputs.
125755: 07/11/02: Re: FPGA vs ASIC
125764: 07/11/03: Re: How do I meet this memory IO with least resources on FPGA?
125773: 07/11/04: Re: How do I meet this memory IO with least resources on FPGA?
125774: 07/11/04: Re: Another way to handle floating inputs.
125794: 07/11/05: Re: Another way to handle floating inputs.
125807: 07/11/05: Re: Audio Output from Spartan 3 Starter Kit
125950: 07/11/09: Re: ROM (altsyncram) corruption
125961: 07/11/09: Re: ROM (altsyncram) corruption
125962: 07/11/09: Re: ROM (altsyncram) corruption
125977: 07/11/10: Re: newbie to 16v8
125979: 07/11/10: Re: ROM (altsyncram) corruption
125991: 07/11/11: Re: newbie to 16v8
126030: 07/11/12: Re: Asynchronous FIFO Latency.
126106: 07/11/14: Re: Block-ram FIFO in Xilinx
126110: 07/11/14: Re: Block-ram FIFO in Xilinx
126118: 07/11/14: Re: Xilinx Virtex-II Newbie
126163: 07/11/15: Re: Block-ram FIFO in Xilinx
126197: 07/11/16: Re: Block-ram FIFO in Xilinx
126205: 07/11/16: Re: simulating xilinx block ram with modelsim
126219: 07/11/16: Re: Gate count calculation in xilinx.
126329: 07/11/19: Re: Coolrunner in system programming - XAPP0058 - viable?
126475: 07/11/23: Re: DCM with instable clock
126477: 07/11/23: Re: DCM with instable clock
126501: 07/11/25: Re: Measuring setup and hold time in Lab
126523: 07/11/26: Re: xilinx spartan 3 + 16 adc
126566: 07/11/27: Re: Xilinx IO leakage when not powered
126685: 07/11/29: Re: Asynchronous FIFO and almost empty - bug?
126696: 07/11/29: Re: Asynchronous FIFO and almost empty - bug?
126734: 07/11/30: Re: Asynchronous FIFO and almost empty - bug?
126736: 07/11/30: Re: Asynchronous FIFO and almost empty - bug?
126746: 07/11/30: Re: CPU design uses too many slices
126747: 07/11/30: Re: Asynchronous FIFO and almost empty - bug?
126802: 07/12/02: Re: Asynchronous FIFO and almost empty - bug?
127435: 07/12/24: Re: FPGA Project Support
127452: 07/12/26: Re: TechXclusives from Xilinx
127465: 07/12/27: Re: TechXclusives from Xilinx
127476: 07/12/27: Re: TechXclusives from Xilinx
127486: 07/12/28: Re: TechXclusives from Xilinx
127491: 07/12/28: Re: TechXclusives from Xilinx
127493: 07/12/28: Re: Spartan 3E 3.3V configuration reverse current situation
127526: 08/01/01: Where are the LCD or OLED bitmapped displays?
127533: 08/01/01: Re: Where are the LCD or OLED bitmapped displays?
127535: 08/01/01: Re: Where are the LCD or OLED bitmapped displays?
127536: 08/01/01: Re: Where are the LCD or OLED bitmapped displays?
127541: 08/01/01: Re: Where are the LCD or OLED bitmapped displays?
127543: 08/01/01: Re: Where are the LCD or OLED bitmapped displays?
127558: 08/01/02: Re: Where are the LCD or OLED bitmapped displays?
127800: 08/01/08: Re: Real examples of metastability causing bugs
127815: 08/01/08: Re: Real examples of metastability causing bugs
127863: 08/01/09: Re: Real examples of metastability causing bugs
127879: 08/01/09: Re: Real examples of metastability causing bugs
127891: 08/01/09: Re: Real examples of metastability causing bugs
127918: 08/01/10: Re: Synthesizing big RAMs
127932: 08/01/10: Re: Purchasing IC components at a good price
127934: 08/01/10: Re: Connecting different FPGAs using LVDS
127937: 08/01/10: Re: Real examples of metastability causing bugs
127985: 08/01/11: Re: Real examples of metastability causing bugs
127989: 08/01/11: Re: Real examples of metastability causing bugs
128017: 08/01/13: Re: Real examples of metastability causing bugs
128023: 08/01/13: Re: Real examples of metastability causing bugs
128079: 08/01/14: Re: Real examples of metastability causing bugs
128083: 08/01/14: Re: Real examples of metastability causing bugs
128234: 08/01/18: Re: How is FIFO implemented in FPGA and ASIC?
128237: 08/01/18: Re: How is FIFO implemented in FPGA and ASIC?
128240: 08/01/18: Source of accurate frequency
128250: 08/01/18: Re: Source of accurate frequency
128268: 08/01/19: Re: Source of accurate frequency
128332: 08/01/22: Re: Source of accurate frequency
128340: 08/01/22: Re: bi-phase decoding
128341: 08/01/22: Re: bi-phase decoding
128352: 08/01/22: Re: Source of accurate frequency
128711: 08/02/04: Re: 4-bit table look-up
128787: 08/02/06: Re: Simple Memory Read problem, help appreciated
128861: 08/02/07: Re: Weired Distributed Memory behaviour
129069: 08/02/13: Virtex-5 User Guide "Lite"
129077: 08/02/13: Re: setup time not met in Quartus
129123: 08/02/14: Re: Spartan 3 configuration download error
129145: 08/02/15: Re: Virtex 4 package layout
129177: 08/02/17: Antti needs a job
129182: 08/02/17: Re: Antti needs a job
129343: 08/02/21: Re: Software Defined Radio auf Xilinx Virtex 4
129390: 08/02/22: Re: Reconfiguration (on the fly) using SPARTAN 3A
129394: 08/02/22: Re: Reconfiguration (on the fly) using SPARTAN 3A
129701: 08/03/03: Re: clock distribution accross boards
129926: 08/03/10: Re: SiliconBlue enters the FPGA fray
129932: 08/03/10: Re: Virtex-4 VLX25 DCM problem
129933: 08/03/10: Re: Virtex-4 VLX25 DCM problem
129951: 08/03/11: Re: BRAM synthesis question
130004: 08/03/12: Re: SiliconBlue enters the FPGA fray
130027: 08/03/13: Re: microblaze to blockram - Byte-Writes
130127: 08/03/15: Re: SiliconBlue enters the FPGA fray
130209: 08/03/17: Re: dual clock fifo
130234: 08/03/18: Re: dual clock fifo
130244: 08/03/18: Re: dual clock fifo
130286: 08/03/19: Re: Optimizing an inferred counter
130291: 08/03/19: Re: Optimizing an inferred counter
130335: 08/03/20: Re: A Challenge for serialized processor design and implementation
130394: 08/03/21: Re: Spartan 3E intefacing for dummies
130446: 08/03/24: Re: counterfeit Xilinx ?
130448: 08/03/24: Re: Spartan 3E intefacing for dummies
130489: 08/03/25: Re: Xilinx PLEASE FIX YOUR servers (ISE 10.1)
130497: 08/03/25: Re: counterfeit Xilinx ?
130504: 08/03/25: Re: counterfeit Xilinx ?
130520: 08/03/26: Re: How to run a block with half the clockspeed on virtex 5
130583: 08/03/27: Re: Places to visit in Amsterdam and Brussells
130653: 08/03/29: Re: async clk input, clock glitches
130664: 08/03/29: Re: async clk input, clock glitches
130782: 08/04/01: Re: Antii, can you give us an update?
130784: 08/04/01: Re: now I can talk about it...
130790: 08/04/01: Re: now I can talk about it...
130825: 08/04/02: Re: counterfeit Xilinx ?
130829: 08/04/02: Re: async clk input, clock glitches
130831: 08/04/02: Re: async clk input, clock glitches
130935: 08/04/05: Re: Virtex-5 FXT coming soon?
130951: 08/04/06: Re: Xilinx inferred FIFOs
131046: 08/04/08: Re: 32 bit multiplier
131074: 08/04/09: Re: Serial Transmission w/o 8B/10B encoding
131078: 08/04/09: Re: Specifying strict setup constraint in ISE
131082: 08/04/09: Re: Serial Transmission w/o 8B/10B encoding
131083: 08/04/09: Re: Serial Transmission w/o 8B/10B encoding
131136: 08/04/11: Re: Xilinx tech Xclusive
131363: 08/04/20: Re: Problem writing quadrature decoder
131369: 08/04/20: Re: Problem writing quadrature decoder
131371: 08/04/20: Re: synchronous reset problems on FPGA
131378: 08/04/20: Re: Problem writing quadrature decoder
131379: 08/04/20: Re: synchronous reset problems on FPGA
131380: 08/04/20: Re: Problem writing quadrature decoder
131383: 08/04/20: Re: Problem writing quadrature decoder
131385: 08/04/20: Re: Problem writing quadrature decoder
131422: 08/04/21: Re: Problem writing quadrature decoder
131514: 08/04/23: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131579: 08/04/25: Re: Xilinx is cancelling the Virtex-E XCV1000E-FG860
131585: 08/04/25: Re: Spartan3 "commercial" temperature range
131597: 08/04/25: Re: Problem writing quadrature decoder
131620: 08/04/26: Re: Problem writing quadrature decoder
131628: 08/04/26: Re: Virtex-4 inrush power-on current
131629: 08/04/26: Re: Virtex-4 inrush power-on current
131631: 08/04/26: Re: Problem writing quadrature decoder
131640: 08/04/27: Re: Problem writing quadrature decoder
131678: 08/04/28: Re: Debounce in Verilog?
131763: 08/05/01: Re: Functional Simulation of Virtex-4 Block Memory
131866: 08/05/05: Re: Problem writing quadrature decoder
131933: 08/05/07: Re: Problem writing quadrature decoder
132008: 08/05/09: Re: 5 V oscillator output to GCLK
132012: 08/05/09: Re: 5 V oscillator output to GCLK
132014: 08/05/09: Re: 5 V oscillator output to GCLK
132016: 08/05/09: Re: 5 V oscillator output to GCLK
132036: 08/05/10: Re: Problem writing quadrature decoder
132037: 08/05/10: Re: 5 V oscillator output to GCLK
132044: 08/05/11: Re: Problem writing quadrature decoder
132046: 08/05/11: Re: Problem writing quadrature decoder
132075: 08/05/12: Re: Problem writing quadrature decoder
132095: 08/05/13: Re: Virtex XCV1000E-6FG860C
132100: 08/05/13: Re: Problem writing quadrature decoder
132108: 08/05/13: Re: Problem writing quadrature decoder
132109: 08/05/13: Re: Problem writing quadrature decoder
132192: 08/05/16: Re: Resetting FPGA Without watch dog timer
132246: 08/05/19: Re: Resetting FPGA Without watch dog timer
132264: 08/05/19: Re: HELP: a Funny asynchronous input design
132282: 08/05/20: Re: HELP: a Funny asynchronous input design
132299: 08/05/20: Re: Stratix IV Announced
132350: 08/05/22: Re: 1250gbps input on virtex-5
132373: 08/05/23: Re: 1250gbps input on virtex-5
132484: 08/05/28: Re: Sequentially syncrhronous
132521: 08/05/29: Re: Xilinx Clock Doubler
132522: 08/05/29: Re: Are FPGAs headed toward a coarse granularity?
132576: 08/06/01: Re: Combinatorial logic delay plus routing delay exceeds clock period
132594: 08/06/02: Re: Combinatorial logic delay plus routing delay exceeds clock period
132603: 08/06/02: Re: Combinatorial logic delay plus routing delay exceeds clock period
132618: 08/06/03: Re: Combinatorial logic delay plus routing delay exceeds clock period
132662: 08/06/04: Re: Xilinx cuts 250 jobs.
132692: 08/06/05: Re: Xilinx cuts 250 jobs.
132890: 08/06/09: Re: fpga reprogrammable?
132915: 08/06/10: Re: FSM running with unstable clock
132917: 08/06/10: Re: Whitepapers are taking over the lost TechXclusives
132930: 08/06/10: Re: Whitepapers are taking over the lost TechXclusives
132943: 08/06/10: Re: fpga reprogrammable?
132958: 08/06/11: Re: fpga reprogrammable?
133039: 08/06/14: Re: FPGA IO Pin Unwanted Coupling
133253: 08/06/22: Re: virtex-5: can't use DCM (too low input frequency)
133258: 08/06/22: Re: virtex-5: can't use DCM (too low input frequency)
133293: 08/06/23: Re: virtex-5: can't use DCM (too low input frequency)
133397: 08/06/26: Re: Beginner : Rotary switch (quad sw)
133440: 08/06/29: Re: Signal forwarding between FPGAs
133510: 08/07/01: Re: How do I program an fpga once it has been designed and layout is
133563: 08/07/03: Re: External Clock Generator
133636: 08/07/07: Re: Virtex 4 expected production end-of-life
133642: 08/07/07: Re: Virtex 4 expected production end-of-life
133805: 08/07/15: Re: Xilinx Virtex 4
133908: 08/07/18: Re: Which FPGA has most ram in a TQFP144 or smaller non-BGA?
133962: 08/07/20: Re: Change clock domain for FIFO ...
134166: 08/07/28: Re: vhdl code for debouncing push button
134187: 08/07/29: Re: Die sizes of FPGAs (approx)
134258: 08/08/01: Re: question about fifo
134422: 08/08/09: Re: Block Rams
134425: 08/08/09: Re: Block Rams
134449: 08/08/11: Re: Block Rams
134463: 08/08/11: Re: Block Rams
134464: 08/08/11: Re: Block Rams
134473: 08/08/12: Re: Block Rams
134485: 08/08/12: Re: Optimizing a LUT-based pow(val, 2.2)
134513: 08/08/15: Re: video timing with TFP410
134515: 08/08/15: Re: video timing with TFP410
134534: 08/08/16: Re: video timing with TFP410
134546: 08/08/17: Re: why does inferred RAM cause synthesis times to explode?
134585: 08/08/19: Re: why does inferred RAM cause synthesis times to explode?
134597: 08/08/20: Re: Xilinx extends Spartan 3A series
134711: 08/08/27: Re: Virtex 5 bitstream encryption
134763: 08/08/28: Re: How many mux input on a Xilinx V4 are pratical
135133: 08/09/17: Re: Random Mask Generation on FPGAs
135184: 08/09/19: Peter says Good Bye
135367: 08/09/28: Re: Low frequency clock generation - need help
135503: 08/10/05: Re: Do two clock system blocks with one clock running half of other's
135505: 08/10/05: Re: A question about the use of FPGA
135566: 08/10/08: Re: How to synthesize a delay of around 10 ns in FPGA?
135574: 08/10/08: Re: MUX Inference
135575: 08/10/08: Re: How to synthesize a delay of around 10 ns in FPGA?
135584: 08/10/08: Re: How to synthesize a delay of around 10 ns in FPGA?
135613: 08/10/09: Re: How to synthesize a delay of around 10 ns in FPGA?
135673: 08/10/11: Re: How to synthesize a delay of around 10 ns in FPGA?
135899: 08/10/20: Re: How to synthesize a delay of around 10 ns in FPGA?
136929: 08/12/14: Re: FIFO with External Memory
136934: 08/12/14: Re: FIFO with External Memory
136938: 08/12/14: Re: Duty Cycle change effects on Internal reg's
137430: 09/01/15: Re: Duty Cycle change effects on Internal reg's
137446: 09/01/16: Re: Duty Cycle change effects on Internal reg's
137480: 09/01/19: Re: Time to de-assert RAM for changing CLK
137700: 09/01/27: Re: XST Makes Odd Choice
137854: 09/01/31: Re: Heavily pipelined design
138182: 09/02/08: Re: How to divide clock frequency......
138753: 09/03/08: Re: Dual port RAM on Spartan
139036: 09/03/18: Re: Xilinx XAPP052 LFSR and its understanding
139141: 09/03/21: Re: Xilinx XAPP052 LFSR and its understanding
139168: 09/03/22: Re: Xilinx XAPP052 LFSR and its understanding
139177: 09/03/22: Re: Xilinx XAPP052 LFSR and its understanding
139879: 09/04/17: Re: Dual-frequency quartz oscillator with a FPGA ?
140284: 09/05/07: Re: Dual Port RAM Inference
140296: 09/05/07: Re: Dual Port RAM Inference
140330: 09/05/09: Re: Dual Port RAM Inference
140343: 09/05/09: Re: Dual Port RAM Inference
140352: 09/05/10: Re: implementing arbitrary combinational functions using block rams
140602: 09/05/19: Re: DCM Jitter
140758: 09/05/25: Re: Adders with multiple inputs?
140780: 09/05/25: Re: Adders with multiple inputs?
140872: 09/05/27: Re: phase locking a slow (2Mhz) signal.
140957: 09/05/31: Re: phase locking a slow (2Mhz) signal.
140961: 09/05/31: Re: Virtex4 LX DCM Minimum Input Frequency
140994: 09/06/01: Re: phase locking a slow (2Mhz) signal.
141581: 09/06/28: Re: STA Problem on Asynchronous FIFO
141822: 09/07/10: Re: How to implementa an FSM in block ram
141856: 09/07/13: Re: Adder size vs Register size
141891: 09/07/15: Re: How to implementa an FSM in block ram
141896: 09/07/15: Re: How to implementa an FSM in block ram
141898: 09/07/15: Re: How to implementa an FSM in block ram
141908: 09/07/16: Re: Generating a negated clock
141935: 09/07/17: Re: How to implementa an FSM in block ram
142035: 09/07/22: Re: gate capacity between old Virtex-II and newer Virtex-4
142079: 09/07/23: Almost everything about Virtex-6 in one location
142117: 09/07/25: Re: How to implementa an FSM in block ram
142120: 09/07/25: Re: How to implementa an FSM in block ram
142123: 09/07/25: Re: How to implementa an FSM in block ram
142124: 09/07/25: Re: Almost everything about Virtex-6 in one location
142136: 09/07/26: Re: How to implementa an FSM in block ram
142233: 09/07/29: Re: How to implementa an FSM in block ram
142238: 09/07/29: Re: How to implementa an FSM in block ram
142393: 09/08/08: Re: Peter Alfke
142596: 09/08/19: Re: Help with crystal oscillator (MG-7010SA replacement)?
143322: 09/10/01: Re: Up-counter with async load/clear and overflow detection (Verilog)
143513: 09/10/13: Re: How to get clocks from DCM that the duty cycle is not 1:1
143530: 09/10/14: Re: What is the basis on flip-flop replaced by a latch
143697: 09/10/21: Re: Can I use a crystal for the clock source for a Xilinx Spartan 3A
143752: 09/10/23: Re: Time stability of clock on FPGA board
143882: 09/10/31: Re: Almost Full signal a clk before Wfull signal
144393: 09/12/03: Re: Does Xilinx sync FIFO use dual port memory? Does this affect
144433: 09/12/07: Re: very wide counter (42-bit)
144505: 09/12/11: Re: very wide counter (42-bit)
144518: 09/12/12: Re: Does a 1-bit mux glitch if only one input is known to change at
144527: 09/12/13: Re: Does a 1-bit mux glitch if only one input is known to change at
144637: 09/12/21: Re: Please help, Xilinx FIFO problem!
144639: 09/12/21: Re: Please help, Xilinx FIFO problem!
144655: 09/12/21: Re: Please help, Xilinx FIFO problem!
144777: 10/01/01: Re: Xilinx and Multi-port memories
144856: 10/01/07: Re: Difference among Virtex Families, FPGA Books
144857: 10/01/07: Re: Difference among Virtex Families, FPGA Books
146100: 10/03/05: Re: FSM in BlockRAM
146116: 10/03/05: Re: FSM in BlockRAM
146135: 10/03/06: Re: FSM in BlockRAM
146272: 10/03/10: Re: Why doesn't this situation generate a latch?
146276: 10/03/10: Re: Why doesn't this situation generate a latch?
146280: 10/03/10: Re: Why doesn't this situation generate a latch?
146319: 10/03/11: Re: Tier Logic introduces the world's first 3D FPGA
146339: 10/03/12: Re: Tier Logic introduces the world's first 3D FPGA
146429: 10/03/17: Re: Xilinx Spartan6 Virtex6 Rollout
147750: 10/05/21: Re: Xilinx FIFO cannot be written
147926: 10/06/02: Re: Job experience? How?
148260: 10/07/02: Re: Xilinx xapp175, empty + full flag really synchronous?
148875: 10/09/05: Re: We need an administrator for the group to fight spam
148881: 10/09/06: Re: We need an administrator for the group to fight spam
149017: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
149018: 10/09/20: Re: Xilinx XST and a State Machine - A Mystery
149141: 10/10/04: Re: Actel bought by Microsemi
149148: 10/10/04: Re: Actel bought by Microsemi
149152: 10/10/04: Re: Actel bought by Microsemi
Peter April:
54962: 03/04/23: Re: Initial values for internal RAM
Peter Ashenden:
7661: 97/10/01: Re: book
7795: 97/10/16: Re: VHDL SRAM model for testbench?
7919: 97/10/30: VIUF Fall 1998 Call for Topics
8062: 97/11/13: VIUF Fall 1998 Call for Topics - repost
8216: 97/11/29: VIUF Fall 1998 Call for Topics - Last Chance
8482: 97/12/20: VIUF Fall 1998 Prelim Call for Papers
Peter Ashford:
Peter Averkamp:
50: 94/08/04: Re: Does the iFX780 qualify for discussion here?
539: 94/12/28: Re: multipliers!
Peter Baltazarovic:
45691: 02/08/01: Safe design speed
45765: 02/08/05: Re: Safe design speed
45844: 02/08/07: Modelsim glbl.GTS problem
45868: 02/08/08: Re: Modelsim glbl.GTS problem
47052: 02/09/16: Re: Post Synthesis Simulation w/Mentor
52513: 03/02/12: Floorplanning of design written in verilogHDL Designer question
Peter Bennett:
51816: 03/01/22: Re: Lecroy Research Systems - what happened?
Peter Beukelman:
17351: 99/07/22: Re: License sharing for synopsys/cadence/modeltech
Peter Boot:
45501: 02/07/25: FPGA expert needed
peter Brandt:
10243: 98/05/06: EPF10K100ABC356-1 HELP US !
Peter Brenner:
44111: 02/06/11: Searching for high performance PLD
44157: 02/06/12: Re: Searching for high performance PLD
44158: 02/06/12: Re: Searching for high performance PLD
Peter Buschhorn:
44300: 02/06/17: impacts batch mode....
44392: 02/06/19: Re: impacts batch mode....
Peter C:
18609: 99/11/03: Re: Xlinx FPGA
Peter C Clarke:
5015: 97/01/13: Problems with XILINX sdt2xnf
Peter C. Wallace:
53605: 03/03/17: Cheapest Spartan II/IIE configuration flash EEPROM!
53607: 03/03/17: Re: Cheapest Spartan II/IIE configuration flash EEPROM!
54109: 03/04/02: Re: [Question] FPGA/PLX9054
55691: 03/05/15: Re: smallest embedded cpu.
56115: 03/05/28: Re: JTAG madness
56569: 03/06/09: Re: PC-104 dev Boards
56573: 03/06/09: Re: Info on Spartan-II PCI Development Kit
56822: 03/06/16: Re: BGA Xray inspection costs?
58487: 03/07/24: Re: Pricing question....
58501: 03/07/24: Re: Active Probe
60788: 03/09/22: Re: Parallel JTAG cable on a USB-only W2K laptop?
60798: 03/09/22: Re: Parallel JTAG cable on a USB-only W2K laptop?
61048: 03/09/26: Re: Graphics rendering
62140: 03/10/20: What is Spartan3 DLL per tap delay
63521: 03/11/24: Re: 400 Mb/s ADC
64362: 03/12/30: Re: Parallel Cable 4 & Linux
66406: 04/02/18: Re: Can FPGA bootstrap itself?
68832: 04/04/19: Re: FPGA techniques for D/A and A/D
73213: 04/09/15: Re: adder VS increment
85304: 05/06/07: Re: Pissed off with Xilinx - Spartan 3
86613: 05/06/30: Re: Direct audio output from FPGA pins
87006: 05/07/12: Re: 16-bit Acesses on ISA bus
90621: 05/10/17: Re: Best Async FIFO Implementation
99311: 06/03/22: Spartan2 and Spartan3 BlockRAMS Can they work thesame?
99319: 06/03/22: Re: Spartan2 and Spartan3 BlockRAMS Can they work thesame?
100869: 06/04/19: XC9500XL Keeper - can it be disabled?
106118: 06/08/07: Re: Open source Xilinx JTAG programmer with Digilent USB support
Peter Chen:
72158: 04/08/09: XC4010E/XC2V1000 problem
Peter Clarke:
1101: 95/04/28: Call for Participaton at UK Fifth Annual Advanced PLD & FPGA Day
3214: 96/04/26: Call for Participation - 6th Annual Advanced PLD & FPGA Conference
6198: 97/04/24: Call for participation, Advanced PLD & FPGA Day UK and Sweden
6223: 97/04/29: Re: Call for participation, Advanced PLD & FPGA Day UK and Sweden
peter cnudde sh146 8218:
2551: 96/01/02: Re: Career value: VHDL or Verilog?
Peter Collins:
4969: 97/01/06: Linux & EDA at Usenix 97
Peter D. Gray:
1006: 95/04/12: Need "fusemap" information from vendor, likely?
1381: 95/06/10: Re: Low cost ISA board
Peter da Silva:
10387: 98/05/15: Re: Minimal ALU instruction set.
12832: 98/10/31: Re: New free FPGA CPU
12891: 98/11/03: Re: New free FPGA CPU
12900: 98/11/04: Re: New free FPGA CPU
19759: 00/01/11: Re: HW resources increased
19772: 00/01/11: Re: HW resources increased
19794: 00/01/12: Re: HW resources increased
19860: 00/01/14: Re: HW resources increased
46556: 02/09/03: Re: Hardware Code Morphing?
46557: 02/09/03: Re: Hardware Code Morphing?
46629: 02/09/04: Re: Hardware Code Morphing?
Peter de Vries:
47990: 02/10/08: extreme cell usage minimization req.
Peter Dennett:
15664: 99/04/06: Re: LCD Ip Core
26880: 00/11/02: ISO C -> VHDL translator, prefer open source
26985: 00/11/06: Re: ISO C -> VHDL translator, prefer open source
27021: 00/11/07: Re: ISO C -> VHDL translator, prefer open source
27090: 00/11/10: Re: ISO C -> VHDL translator, prefer open source
Peter Desmet:
25317: 00/09/06: About XNF, EDIF and UCF
25342: 00/09/07: Re: About XNF, EDIF and UCF
Peter Desnoyers:
63485: 03/11/22: Re: 400 Mb/s ADC
Peter Dickerson:
110647: 06/10/19: Re: ANNC: Open Source, Free 32-bit soft processor webcast
Peter Drescher:
4936: 97/01/02: Foundation X-Block Support
peter dudley:
18143: 99/10/03: Re: Fine grain vs. Coarse grain
18275: 99/10/11: Re: Xilinx Alliance 2.1i Virus
18417: 99/10/23: floating point synthesis
18418: 99/10/23: Re: Seeking for FPGA/CPLD (Starter) kit
18429: 99/10/23: Re: floating point synthesis
18437: 99/10/24: Re: Xilinx FPGA Programmer
18461: 99/10/25: Re: Delta-Sigma DAC
18531: 99/10/28: Re: Hold times for Xilinx FPGAs
18532: 99/10/28: Re: schematics ==> www
18661: 99/11/05: Re: Xilinx M2.1i SP2?
18704: 99/11/08: Re: Need a good Pullup for a VHDL Test Bench
19482: 99/12/24: Re: PCI slot 3.3V pins.
19518: 99/12/28: Re: HDL to graphic conversion
19539: 99/12/29: Re: Virtex Config Help
19540: 99/12/29: IRDY/TRDY Dedicated or Special Pin Name
19977: 00/01/20: Re: Xilinx vs. other FPGAs manufactrers
20457: 00/02/11: Re: Xilinx Virtex Decoupling Cap Guidelines
20908: 00/02/26: Re: PCI 64 bit / 66 MHz
20570: 00/02/15: Re: Xilinx Virtex Decoupling Cap Guidelines
21229: 00/03/11: Xilinx IP Protection
22574: 00/05/12: Re: simulation of Xilinx Coregen modules in schematic environment
23198: 00/06/17: Re: Xilinx Virtex E
23197: 00/06/17: Re: Hand soldering a PQ208 - It looks tough to do.
23703: 00/07/05: Re: Powering XCV300
24067: 00/07/25: Power PC with Xilinx - what do you think?
24322: 00/08/03: XST?
24390: 00/08/06: Xilinx Alliance Base
154904: 13/02/12: Re: Vivado - Pack I/O Registers?
154905: 13/02/12: Re: Chisel as alternative HDL
154910: 13/02/12: Re: Vivado - Pack I/O Registers?
155341: 13/06/24: Pure HDL Xilinx Zynq Arm Instantiation
155496: 13/07/02: Re: Pure HDL Xilinx Zynq Arm Instantiation
155833: 13/09/27: good SDC reference
155834: 13/09/27: Re: Vivado - Pack I/O Registers?
155835: 13/09/28: Re: Problem in Xilinx xapp1052 DMA PCIE custom flow
155836: 13/09/28: Re: VHDL syntheses timestamp
156180: 14/01/10: Altera Primitives Library
Peter Dudley:
40787: 02/03/15: Re: exceeding 2GB limits in xilinx
Peter Elliot:
23325: 00/06/22: Looking for 'FREE' FPGA software
23328: 00/06/22: Looking for 'FREE' FPGA software
23631: 00/07/03: Graphic LCD controller design
Peter Fenn:
1588: 95/07/22: Xilinx EPLD's
2896: 96/02/26: Programming ATMEL config. PROMs ?
3561: 96/06/23: FPGA & PCB Design tools?
4356: 96/10/19: Comment/opinion on ACTEL's annonced SPGA devices?
5620: 97/03/02: Printing VHDL source?
8410: 97/12/13: JTAG configuration of Xilinx XC4000E FPGAs?
8411: 97/12/13: JTAG configuration of Xilinx XC4000E FPGAs?
9653: 98/03/28: Outsource for design + test
9780: 98/04/05: "Offshore" Design Services
20046: 00/01/25: Atmel config PROMs
21008: 00/03/02: Comment on Atmel AT40K ?
37660: 01/12/18: Spartan-IIE schematic symbol?
Peter Flass:
145415: 10/02/08: Re: using an FPGA to emulate a vintage computer
145416: 10/02/08: Re: using an FPGA to emulate a vintage computer
145762: 10/02/22: Re: using an FPGA to emulate a vintage computer
145798: 10/02/24: Re: using an FPGA to emulate a vintage computer
145892: 10/02/26: Re: using an FPGA to emulate a vintage computer
145954: 10/03/01: Re: using an FPGA to emulate a vintage computer
145999: 10/03/02: Re: using an FPGA to emulate a vintage computer
146056: 10/03/04: Re: using an FPGA to emulate a vintage computer
146057: 10/03/04: Re: using an FPGA to emulate a vintage computer
146119: 10/03/05: Re: using an FPGA to emulate a vintage computer
146127: 10/03/06: Re: using an FPGA to emulate a vintage computer
146129: 10/03/06: Re: using an FPGA to emulate a vintage computer
146145: 10/03/06: Re: using an FPGA to emulate a vintage computer
146186: 10/03/07: Re: using an FPGA to emulate a vintage computer
146246: 10/03/09: Re: using an FPGA to emulate a vintage computer
Peter Foord:
65787: 04/02/06: Online debate: Programmable Logic vs ASIC vs Gate Array
65930: 04/02/10: Re: Online debate: Programmable Logic vs ASIC vs Gate Array
Peter Glar:
131509: 08/04/23: superscalar processor design
Peter Graeme Cobb:
13328: 98/11/26: DynaChi -> Have you used there devices?
Peter Gustafsson:
36919: 01/11/26: PCI-CORE in XC4000XLA using Leonardo Spectrum
Peter Gutmann:
437: 94/11/16: Re: Anybody used FPGA as Encryption Device?
441: 94/11/17: Re: Anybody used FPGA as Encryption Device?
11408: 98/08/11: Re: Security
13038: 98/11/12: Re: DES in VHDL?
Peter Hanely:
25457: 00/09/12: Re: hardware compatibility and patent infringement
Peter Harrison:
89218: 05/09/08: Re: Signed addition
96614: 06/02/07: Re: Tefzel or Kynar for PCB mods ?
Peter Hazenberg:
5513: 97/02/21: Re: Q: Search Engines for Electronic Parts?
Peter Heidrich:
19310: 99/12/13: Silicon instead of FPGA for Ethernet-to-Ethernet MAC Switch?
Peter Heitzer:
35987: 01/10/25: Cheap programming of XC2018?
35990: 01/10/25: Re: GAL compiler
36017: 01/10/26: Re: Cheap programming of XC2018?
Peter Hermansson:
70620: 04/06/22: Re: CPLD mistery. Help.... reHelp.
80794: 05/03/11: Re: Over-Sampling
Peter Hiscocks:
5075: 97/01/20: GAL programming timing
15132: 99/03/09: Jedec programming standard?
47838: 02/10/05: DDS in PLD?
Peter Horst:
65804: 04/02/06: Xilinx WARNING:NetListWriters:117
Peter J. Ashenden:
9919: 98/04/14: Final reminder: VIUF Fall 98 call for Workshops, Tutorials and Papers
12100: 98/09/29: WORKSHOPS '98 - VHDL for Power Users
31487: 01/05/28: APChDL-2001/SLDL-2001 call for papers
Peter J. Kootsookos:
22427: 00/05/09: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
57931: 03/07/10: Re: Make file ...........Help Please
Peter J. Rieck:
4611: 96/11/20: Free Money
Peter Jahnke:
39343: 02/02/06: Altera MAX7000 PLD's
Peter Jamieson:
64605: 04/01/08: Verilog Benchmarks for FPGA research
Peter K.:
87446: 05/07/24: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87494: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87495: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87549: 05/07/25: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87572: 05/07/26: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87622: 05/07/27: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87623: 05/07/27: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87644: 05/07/27: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87687: 05/07/28: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87737: 05/07/29: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87755: 05/07/30: Re: Best Practices to Manage Complexity in Hardward/Software Design?
96037: 06/01/28: Re: [OT]Re: encryption
108018: 06/09/04: Re: Performance Appraisals
Peter Kampmann:
108433: 06/09/11: Re: Xilinx Platform Studio 8.2i - Add custom peripheral, adress Space calculation
108566: 06/09/13: Xilinx Platform Studio, build up System: "block-RAM components require the adjacent multiplier"
108630: 06/09/14: Re: Xilinx Platform Studio, build up System: "block-RAM components require the adjacent multiplier"
108690: 06/09/15: Xilinx Connect custom peripheral to PPC
109021: 06/09/20: Re: Xilinx Connect custom peripheral to PPC
109036: 06/09/20: Xilinx PowerPC slower than FPGA Design?
109039: 06/09/20: Re: Xilinx PowerPC slower than FPGA Design?
109042: 06/09/20: Re: Xilinx PowerPC slower than FPGA Design?
109049: 06/09/20: Re: Xilinx PowerPC slower than FPGA Design?
109162: 06/09/21: Timing Behaviour PPC <-> Peripheral Communication Virtex 2 Pro
109225: 06/09/22: Re: Timing Behaviour PPC <-> Peripheral Communication Virtex 2 Pro
109230: 06/09/22: Re: Timing Behaviour PPC <-> Peripheral Communication Virtex 2 Pro
111025: 06/10/27: Implementing Direct Memory Access for Peripheral (Xilinx Virtex 2 Pro)
114233: 07/01/08: Generate ACE File: *.elf does not contain start address
114238: 07/01/08: Re: Generate ACE File: *.elf does not contain start address
Peter Klemperer:
117417: 07/03/30: ModelSim VHDL Pragmas
117437: 07/03/30: Re: ModelSim VHDL Pragmas
126081: 07/11/14: Xilinx ISE Timing Report Question
126088: 07/11/14: Re: Xilinx ISE Timing Report Question
Peter Korsgaard:
86559: 05/06/30: Re: Linux 2.6 on the Xilinx ML310 board
106602: 06/08/16: Re: (uc)Linux support for Xilinx FPGAs is going to next level
108024: 06/09/04: Re: linux 2.4 v 2.6 on xilinx
Peter L. Montgomery:
19605: 00/01/04: Re: An online division unit with constant divisor
31777: 01/06/05: Re: FPU IEEE-754 calculation
54523: 03/04/13: Re: An Improvement for the Booth multiplier
Peter Lang:
16006: 99/04/27: High speed PLL inside FPGA
19748: 00/01/11: PCI Bus Problems with Burst Transfers
19818: 00/01/13: Re: PCI Bus Problems with Burst Transfers
19851: 00/01/14: Re: PCI Bus Problems with Burst Transfers
26632: 00/10/23: log2 function in VHDL
26725: 00/10/26: Re: log2 function in VHDL
26726: 00/10/26: How to Compile a hierarchical VHDL Design to a LIB?
27156: 00/11/13: XC4000 maps better than Spartan2
27238: 00/11/16: VHDL & Spartan: How to power-up a Register to '1' ?
27286: 00/11/17: Re: VHDL & Spartan: How to power-up a Register to '1' ?
27293: 00/11/17: Re: VHDL & Spartan: How to power-up a Register to '1' ?
31525: 01/05/29: Spartan2 PCI-IP Core @ power-up
32755: 01/07/07: Large Power up Current on Spartan2
32936: 01/07/12: Problems: Xilinx 3.1i Service Pack 8
35182: 01/09/25: FPGA with embedded Memory
41187: 02/03/22: Altera Stratix compared to Xilinx Virtex
41799: 02/04/08: How to use Block-Ram via VHDL
Peter Liebert-Adelt:
36530: 01/11/11: Re: ZX81 production run, is there any interest?
peter Lin:
13357: 98/11/30: Re: Verilog Simulators
Peter Mash:
58176: 03/07/16: Xilinx ECS Schematic Entry
58178: 03/07/16: Re: Xilinx ECS Schematic Entry
58210: 03/07/17: Re: Xilinx ECS Schematic Entry
59373: 03/08/17: Translate: Map
59381: 03/08/18: Re: xilinx PAR removing Logic
59382: 03/08/18: Re: Xilinx Webpack ISE and Verilog-2001?
Peter Mason:
23292: 00/06/21: Re: VHDL synthesis.
Peter Matthijs:
56385: 03/06/04: Xilinx Virtex development board for cPCI
56443: 03/06/05: Re: Xilinx Virtex development board for cPCI
Peter Mayne:
46550: 02/09/03: Re: Hardware Code Morphing?
Peter McGrath:
8871: 98/02/03: research project
Peter McLeod Wilcox:
4337: 96/10/17: Re: xc4000 and 2 clocks
Peter Mendham:
101715: 06/05/05: Xilinx SelectMAP Question
101717: 06/05/05: Re: Xilinx SelectMAP Question
101726: 06/05/05: Re: Xilinx SelectMAP Question
101870: 06/05/08: Re: Xilinx SelectMAP Question
102164: 06/05/11: Power for Spartan 3
102318: 06/05/15: Re: Power for Spartan 3
102332: 06/05/15: Re: Power for Spartan 3
102333: 06/05/15: Re: Power for Spartan 3
102431: 06/05/16: Re: Power for Spartan 3
102432: 06/05/16: Re: Power for Spartan 3
102510: 06/05/17: Re: Power for Spartan 3
102521: 06/05/17: EdaXML
102620: 06/05/18: Re: "disappointing" performance
102621: 06/05/18: Re: Power for Spartan 3
102677: 06/05/19: Re: "disappointing" performance
102678: 06/05/19: Re: FPGA Configuration Question
102689: 06/05/19: Re: generate a square signal with a 3.8 ns "plate"
102690: 06/05/19: Re: "disappointing" performance
105881: 06/08/02: Virtex-4 RocketIO
105935: 06/08/03: Re: Virtex-4 RocketIO
106129: 06/08/08: New to RocketIO
106144: 06/08/08: Re: verilog versus vhdl
106493: 06/08/14: RocketIO MGT Tile/Column Question
106545: 06/08/15: Re: RocketIO MGT Tile/Column Question
106546: 06/08/15: Re: RocketIO MGT Tile/Column Question
106561: 06/08/15: Re: RocketIO MGT Tile/Column Question
106562: 06/08/15: Spartan 3 Mask Code determination
106624: 06/08/16: Power Supply Sequencing to V4 MGTs
106686: 06/08/17: Re: Power Supply Sequencing to V4 MGTs
111462: 06/11/03: EDK 8.2i/cygwin issues
111465: 06/11/03: Re: EDK 8.2i/cygwin issues
111470: 06/11/03: Re: EDK 8.2i/cygwin issues
111476: 06/11/03: Re: EDK 8.2i/cygwin issues
112098: 06/11/16: Compiling Linux Kernel for ML405
112155: 06/11/17: Re: Compiling Linux Kernel for ML405
112372: 06/11/21: Re: Compiling Linux Kernel for ML405
115543: 07/02/13: SelectMAP Configuration and Readback
118057: 07/04/17: plb_tft_cntlr_ref for an ML405 EDK Project
118082: 07/04/17: Re: plb_tft_cntlr_ref for an ML405 EDK Project
118091: 07/04/17: Re: plb_tft_cntlr_ref for an ML405 EDK Project
118103: 07/04/17: Re: plb_tft_cntlr_ref for an ML405 EDK Project
123628: 07/08/31: Wifi with a Virtex 4
Peter Molesworth:
62268: 03/10/23: Re: Are clock and divided clock synchronous?
62275: 03/10/23: Re: Are clock and divided clock synchronous?
62301: 03/10/24: Re: Are clock and divided clock synchronous?
62414: 03/10/29: Re: How to protect fpga based design against cloning?
Peter Monta:
52906: 03/02/25: Re: Delay element in Virtex2
60384: 03/09/11: Xilinx 6.1i on Red Hat 9
60465: 03/09/13: Re: Xilinx 6.1i on Red Hat 9
61240: 03/09/30: Re: Can I use pullup/pulldown to bias LVDS input?
66207: 04/02/14: Re: Peter's 1Hz-640MHz Synth project
70508: 04/06/18: Linux on Xilinx v2pro: OCM access?
70528: 04/06/18: Re: Linux on Xilinx v2pro: OCM access?
77189: 04/12/28: Re: vvp problem
82541: 05/04/14: Re: Reverse engineering masked ROMs, PLAs
99776: 06/03/29: Re: Storing variables into data ocm memory
114470: 07/01/17: Re: PowerPC_DDR_controller
121568: 07/07/08: Re: Question on Virtex2p DCMs usability
Peter Montgomery:
555: 95/01/03: Xilinx and Protel for Windows?
559: 95/01/04: Re: Xilinx and Protel for Windows?
Peter Moreton:
104223: 06/06/21: Xilinx XC4VSX25 development board?
104249: 06/06/21: Re: Xilinx XC4VSX25 development board?
Peter Nilsson:
118667: 07/05/01: Re: debounce state diagram FSM
Peter Ormsby:
32156: 01/06/16: Re: efficient CAM in Virtex or Spartan II?
32744: 01/07/06: Re: Altera ACEX
32888: 01/07/11: Re: Altera synthesis tools WAS: What chip!?
32940: 01/07/12: Re: Xilinx FPGA density estimation
32942: 01/07/12: Re: Erasing Altera EPC-1441?
33184: 01/07/18: Re: Spartan2XC2S30 vs ACEXEP1K30
33186: 01/07/18: Re: FPGAs in Safety Involved Applications
33280: 01/07/22: Re: free VHDL and/or Verilog tools?
33663: 01/08/01: Re: May I connect two pins to the same net?
33666: 01/08/02: Re: Altera MPLD
33722: 01/08/02: Re: May I connect two pins to the same net?
33747: 01/08/03: Re: May I connect two pins to the same net?
34015: 01/08/11: Re: Low Cost FPGA or PLD
34237: 01/08/17: Re: I need help disassembling a JEDEC .jed file from a PLHS18P8A
34645: 01/09/01: Re: WebPack Con-Game
34684: 01/09/04: Re: How do I configure Altera Apex 20K via JTAG?
34685: 01/09/04: Re: APEX20KE: Global Line for internal logic
34687: 01/09/04: Re: Segmented interconnects
35209: 01/09/26: Re: FPGA with embedded Memory
35219: 01/09/26: Re: FPGA with embedded Memory
35760: 01/10/17: Re: PLLs & DLLs
35761: 01/10/17: Re: System Gates
35765: 01/10/17: Re: PLLs & DLLs
36154: 01/10/31: Re: Can anyone guide me in selecting an FPGA?
36248: 01/11/03: Re: Implementing NIOS softcore in ACEX
36250: 01/11/03: Re: what about FPGA with embedded processor?
36308: 01/11/06: Re: Can anyone guide me in selecting an FPGA?
36709: 01/11/16: Re: CAM
37172: 01/12/03: Re: quartus do not support parameter value assignment in module instantation
38395: 02/01/13: Re: Homebrew computers using FPGA?
38402: 02/01/14: Re: Homebrew computers using FPGA?
38652: 02/01/20: Re: Altera Nios v2
39492: 02/02/12: Re: Altera's new family Stratix
39947: 02/02/22: Re: Beginner Altera Questions
39990: 02/02/23: Re: Beginner Altera Questions
40080: 02/02/26: Re: RAM question
40122: 02/02/28: Re: RAM question
40162: 02/03/01: Re: Altera FPGAs
40216: 02/03/02: Re: Altera Excalibur
40235: 02/03/03: Re: Altera Excalibur
40358: 02/03/06: Re: Quartus II 2.0 fast fit option
40426: 02/03/07: Re: exceeding 2GB limits in xilinx
40496: 02/03/08: Re: How can I install Xilinx ISE 4.1i under Linux?
41265: 02/03/23: Re: QuartusII 2.0!!!!!
41380: 02/03/27: Re: How to activate 5V PCI I/O pads in FLEX10KE/ACEX1K?
41513: 02/04/01: Re: Any Virtex II pro development board on market?
41561: 02/04/02: Re: Laying out the design
41776: 02/04/08: Re: Laying out the design
41778: 02/04/08: Re: Marquis of Queensbury Rules
41989: 02/04/12: Re: prototyping an ASIC
42018: 02/04/12: Re: Marquis of Queensbury Rules
42357: 02/04/21: Re: NIOS ISS, MicroBlaze Cycle Accurate ISS
Peter Presti:
2093: 95/10/12: Re: Sockects for AMD MACH-445 anywhere ?
2166: 95/10/23: Re: Programming AMD Mach Parts
Peter Rauschert:
33948: 01/08/09: Problem with fft16 generated by Xilinx Core Gen 3.1i
40503: 02/03/07: Xilinx 32 Point FFT for post synthesis simulation ?
40569: 02/03/11: Cannot access header information - Modelsim Error with XilinxCoreLib ?
55533: 03/05/12: Re: where to buy 1 virtex-e fg680
55542: 03/05/12: Re: CRC Generator for 6Byte serial Transmission
59164: 03/08/11: Re: FPGA advantage 5.3 & unisim package
60046: 03/09/04: Re: Memory
60257: 03/09/09: Re: Clock Synchronization of PC and FPGA
65654: 04/02/04: Spartan II and 100MHz SBSRAM Interface
90115: 05/10/05: Where to get informations about Virtex 4 FX Engineering Samples
90121: 05/10/05: Re: Where to get informations about Virtex 4 FX Engineering Samples
93282: 05/12/19: Powering unused MGTs in XC4VFX20CES2
93283: 05/12/19: Re: Powering unused MGTs in XC4VFX20CES2
Peter Rush:
8814: 98/01/28: MAX+II Version 8.2
Peter Ryser:
52508: 03/02/11: Re: Virtex-II Pro PowerPC cache memory as main program/data storage?
54060: 03/04/01: Re: Looking for Virtex2Pro and Linux (PPC)
57516: 03/07/01: Re: Xilinx ML300 JTAG Configuration Problem
57602: 03/07/02: Re: Virtex 2Pro, ML300, VP2PDK, EDK, etc..
57796: 03/07/07: Re: Virtex 2Pro, ML300, VP2PDK, EDK, etc..
58274: 03/07/18: Re: "ML300 Embedded" Mapping Help
58320: 03/07/20: Re: "ML300 Embedded" Mapping Help
58450: 03/07/23: Re: "ML300 Embedded" Mapping Help
58645: 03/07/29: Re: "ML300 Embedded" Mapping Help
58646: 03/07/29: Re: "ML300 Embedded" Mapping Help
58647: 03/07/29: Re: "ML300 Embedded" Mapping Help
58661: 03/07/30: Re: Spurious Machine Check Exceptions [WAS: Re: Insight ReferenceBoard
58969: 03/08/05: Re: "ML300 Embedded" Mapping Help
58971: 03/08/05: Re: Xuart Lite Linux driver
58972: 03/08/05: Re: Xuart Lite Linux driver
58982: 03/08/05: Re: Xuart Lite Linux driver
58983: 03/08/05: Re: Xuart Lite Linux driver
58995: 03/08/05: Re: Xuart Lite Linux driver
59031: 03/08/06: Re: Xuart Lite Linux driver
59884: 03/08/30: Re: V2Pro, ML300 Linux reference design
59931: 03/09/01: Re: Update on Virtex II Pro Linux
60627: 03/09/17: Re: Virtex II Pro Linux
67771: 04/03/18: Re: Virtex2P OCM is not cachable?
67927: 04/03/22: Re: What's the flow V2P SysAce handles the software inside the ACE
67928: 04/03/22: Re: cpu and linux on a fpga (new to FPGAs)
68532: 04/04/07: Re: Virtex2PV20 programming failed, DONE pin doesn't go HIGH
68614: 04/04/09: Re: Virtex2PV20 programming failed, DONE pin doesn't go HIGH
70520: 04/06/18: Re: Linux on Xilinx v2pro: OCM access?
72405: 04/08/17: Re: linux on virtex 2 pro board
72673: 04/08/27: Re: using GNU to compile for PPC405?
72930: 04/09/08: Re: EDK 3.2 and modelsim ppc simulation
73116: 04/09/14: Re: Bus Frequecy in virtex2p powerpc
73117: 04/09/14: Re: EDK
73658: 04/09/27: Re: embedded linux on FPGA?
74411: 04/10/10: Re: Use Xilinx VP20 with 2 ppc and one DRAM chip
74508: 04/10/12: Re: Use Xilinx VP20 with 2 ppc and one DRAM chip
74670: 04/10/15: Re: Question on Xilinx VirtexPro II FPGA chip... please
76823: 04/12/13: Re: pausing execution on ppc405
77105: 04/12/22: Re: DSOCM BRAM I/F Controller
79232: 05/02/15: Re: V4LX25-ES and systemACE
79345: 05/02/17: Re: VGA core
79366: 05/02/17: Re: PPC 405 in Virtex 2 Pro 30-Turning off "Critical-word first"
80335: 05/03/03: Re: Xilinx ML310 board's IO
81265: 05/03/20: Re: About the usb access in board ML310!
81946: 05/04/04: Re: XMD : Running XMD with Caches on
83320: 05/04/27: Re: x on ml300?
83391: 05/04/28: Re: Change OCM Clock
84075: 05/05/12: Re: RS 232 receiver using spartan 3 board
84077: 05/05/12: Re: Any Virtex 4 development/prototyping boards out there???
84177: 05/05/13: Re: PowerPC and application in external RAM
84178: 05/05/13: Re: PowerPC and application in external RAM
84749: 05/05/25: Re: powerpc startup
84767: 05/05/26: Re: powerpc startup
84960: 05/06/01: Re: powerpc startup
84994: 05/06/02: Re: ppc405 cache using bram
86059: 05/06/21: Re: Microblaze address space and variables
86068: 05/06/21: Re: Microblaze address space and variables
86144: 05/06/22: Re: ppc 405 in debug halt mode
86244: 05/06/23: Re: ppc 405 in debug halt mode
86427: 05/06/27: Re: ppc 405 in debug halt mode
86618: 05/06/30: Re: PPC405 Question
86785: 05/07/06: Re: Program from external memory
86810: 05/07/06: Re: Cheking out Linux Kernel Source
89138: 05/09/06: Re: PPC405 32 bit aligned accesses
89140: 05/09/06: Re: PCI on ML310 Xilinx board
89155: 05/09/06: Re: Linux on Viretex-II pro
89158: 05/09/06: Re: PPC405 32 bit aligned accesses
89163: 05/09/06: Re: PPC405 32 bit aligned accesses
89234: 05/09/08: Re: PPC405 32 bit aligned accesses
89878: 05/09/28: Re: Req to Xilinx: eCos port for Microblaze
90283: 05/10/07: Re: PowerPC interrupt latency
90388: 05/10/11: Re: Virtex-4 FX20 PPC405 Startup Issue
90495: 05/10/14: Re: xilinx fpga beginner question
90592: 05/10/17: Re: Virtex-4 FX20 PPC405 Startup Issue
91206: 05/11/01: Re: Xilinx ML403 Error 1 LED
91234: 05/11/01: Re: Xilinx ML403 Error 1 LED
91471: 05/11/07: Re: Malloc on PowerPC on VirtexII pro
91473: 05/11/07: Re: xapp807-Minimal Footprint Tri-Mode Ethernet MAC Processing Engine
91561: 05/11/08: Re: pci ml310 board
91596: 05/11/09: Re: pci ml310 board
91954: 05/11/17: Re: downloading with XMD ?
92664: 05/12/03: Re: ML403 "small" problem
92881: 05/12/08: Re: Embedded ppc405 w/o RAM?
93300: 05/12/19: Re: Virtex-4 Startup
93358: 05/12/20: Re: software application on the virtex-ii pro
93370: 05/12/20: Re: software application on the virtex-ii pro
93937: 06/01/03: Re: PPC405 on ISE
93938: 06/01/03: Re: PPC405 on ISE
95723: 06/01/25: Re: porting linux on ml403
95982: 06/01/27: Re: PPC Memory Management
96355: 06/02/02: Re: xilinx linux source?
96424: 06/02/03: Re: xilinx linux source?
96494: 06/02/04: Re: multi-processor linux on xilinx
96495: 06/02/04: Re: question for the EDK users out there...
96681: 06/02/08: Re: porting linux on ml403
96682: 06/02/08: Re: porting linux on ml403
96699: 06/02/08: Re: question for the EDK users out there...
97986: 06/03/02: Re: PPC LUTS registers
98199: 06/03/06: Re: Question for the EDK ppc users ...
99845: 06/03/29: Re: Linux on ml403
99929: 06/03/31: Re: question about Virtex-II Pro program execution time
101913: 06/05/08: Re: booting problem ML300 :eth0: Could not read PHY control register;
102548: 06/05/17: Re: SystemACE bootloader for PowerPC on Virtex4 FX
102585: 06/05/17: Re: SystemACE bootloader for PowerPC on Virtex4 FX
102608: 06/05/17: Re: SystemACE bootloader for PowerPC on Virtex4 FX
102643: 06/05/18: Re: SystemACE bootloader for PowerPC on Virtex4 FX
103418: 06/06/01: Re: Using ChipScope with EDK flow?
102598: 06/05/17: Re: SystemACE bootloader for PowerPC on Virtex4 FX
107297: 06/08/26: Re: UltraController II + SystemAce
107348: 06/08/27: Re: UltraController II + SystemAce
107558: 06/08/29: Re: I2C on Xilinx Virtex-4/ML403
110223: 06/10/12: Re: Am I blind or? (Virtex-4 issues)
114061: 07/01/03: Re: PPC cache errata
114062: 07/01/03: Re: PPC PLB <=> FPGA fabric
114069: 07/01/03: Re: xilinx spi example under linux
115161: 07/02/01: Re: Porting MontaVista Linux on ML403
119022: 07/05/09: Re: ML405 LCD
120427: 07/06/06: Re: Power PC heap initialisation on Reset
120428: 07/06/06: Re: Unable to connect to PowerPC target. Invalid Processor Version
120429: 07/06/06: Re: No output while booting ML403 board
121329: 07/07/02: Re: 32bit multiplication in a PowerPC405 of a VirtexIIPro
121330: 07/07/02: Re: 32bit multiplication in a PowerPC405 of a VirtexIIPro
122903: 07/08/09: Re: V4FX PPC suspend/resume
123304: 07/08/22: Re: Burst Memory Transfer Request from PPC
124007: 07/09/10: Re: load/read/ commands assembly PowerPC. Help Needed!
127198: 07/12/13: Re: How do you initialize Xilinx ISOCM memory using DCR interface
127225: 07/12/14: Re: How do you initialize Xilinx ISOCM memory using DCR interface
127299: 07/12/17: Re: How do you initialize Xilinx ISOCM memory using DCR interface
128853: 08/02/07: Re: ML410 and documentation on ALi M1535D+
Peter S:
160488: 18/02/12: Most power efficient FPGA?
Peter Sander:
58220: 03/07/17: Using Quartus II 3.0 w/ self-made byteblaster cable
Peter Scheuter:
60192: 03/09/07: PIC Programming Help
Peter Schmand:
63225: 03/11/18: HDL-Designer 2002: cannot edit generic mapping in Block-Diagram-view
63277: 03/11/19: Re: HDL-Designer 2002: cannot edit generic mapping in Block-Diagram-view
Peter Schulz:
16339: 99/05/17: Re: Glue logic
22163: 00/04/28: Re: A Question on Virtex Configuration
22630: 00/05/15: XC1804 JTAG Programming Problems
25312: 00/09/06: Re: XC3000A Configuration data
25527: 00/09/13: Re: Virtex 1800 series ISP proms
25887: 00/09/25: Re: Virtex 1800 series ISP proms
Peter Seebach:
14309: 99/01/25: Re: The development of a free FPGA synthesis tool
14356: 99/01/27: Re: The development of a free FPGA synthesis tool
14389: 99/01/28: Re: The development of a free FPGA synthesis tool
14390: 99/01/28: Re: The development of a free FPGA synthesis tool
14577: 99/02/05: Re: The development of a free FPGA synthesis tool
14578: 99/02/05: Re: The development of a free FPGA synthesis tool
19915: 00/01/18: Re: HW resources increased
Peter Seed:
34184: 01/08/16: Re: star-wars ascii-animation:)
Peter Sels:
5046: 97/01/16: ILP formulation of DRL Scheduling Problem
15747: 99/04/12: FPGA board
16368: 99/05/19: Aries Ballnet sockets?
16488: 99/05/25: Re: floating points to fixed points on a FPGA
16492: 99/05/25: Re: floating points to fixed points on a FPGA
Peter Seng:
54630: 03/04/15: Search for most relevant FPGA sites on the net
54916: 03/04/22: Re: Xilinx programming (xc9500)
55051: 03/04/25: ANN: bootable Spartan2 board with PC interface and CPU
56025: 03/05/27: Re: Xilinx Spartan download with Parallel III cable
56067: 03/05/28: Re: Xilinx Spartan download with Parallel III cable
56846: 03/06/17: VGA LCD display controller in FPGA
56879: 03/06/18: Re: Configuring Virtex with rbt files
57834: 03/07/08: Re: wired downloading bitstream to spartan2
59006: 03/08/06: Re: Parallel Port EPP in FPGA
59938: 03/09/02: Re: parallel port
64095: 03/12/16: Re: datasheet needed!
64144: 03/12/18: www.fpga-faq.com
64244: 03/12/22: Re: www.fpga-faq.com
66315: 04/02/17: Re: Dual-stack (Forth) processors
66686: 04/02/25: PC parallel port interface and configuration sources for free
68562: 04/04/08: Re: Cyclone and ByteBlasterMV?
68659: 04/04/13: Re: Problem downloading with parallel converter
68683: 04/04/14: Re: Problem downloading with parallel converter
68788: 04/04/19: Re: Problem downloading with parallel converter
72411: 04/08/18: Re: Spooling from FPGA to the PC
72746: 04/08/31: Ann: Link-list to FPGA related topics / sites
74954: 04/10/22: Re: interfacing a PC based program with a FPGA
74333: 04/10/08: Re: Advice for a Beginner?
75992: 04/11/22: Re: Spartan 3 output voltage level
76035: 04/11/23: Re: Spartan 3 output voltage level
77276: 05/01/03: Re: USB JTAG programmers?
77315: 05/01/04: Re: USB JTAG programmers?
77358: 05/01/05: Re: Getting started with Xilinx CPLD
77359: 05/01/05: Re: USB JTAG programmers?
Peter Siegrist:
2699: 96/01/25: Re: HowTo access a SRAM with a XC4000
Peter Sinander:
3275: 96/05/08: Re: Please help with CRC hardware implementation - crcgen.zip (0/1)
Peter Soegaard:
116543: 07/03/12: PAL
Peter Soerensen:
78535: 05/02/02: EDK IPIF Wizard : How to get started?
78675: 05/02/05: EDK+IPIF: Customizing wizard result
83337: 05/04/27: EDK 7.1 : ML40x / ML401 Reference Design
83779: 05/05/06: Cant link with xil_malloc() function
85471: 05/06/09: Re: ISE/EDK 6.3 vs 7.1...
Peter Sommerfeld:
47485: 02/09/26: Nios interrupt latency?
52165: 03/02/03: Using Quartus II SignalTap with Tcl
52389: 03/02/07: Re: FFT Size and speed
52417: 03/02/08: JBits
52418: 03/02/08: Re: Quartus II problems
53103: 03/03/03: Re: Nios - > 8 bit Ram
53508: 03/03/14: LogicLock and SOPC Builder
53586: 03/03/17: LogicLock and SOPC Builder
55580: 03/05/13: Altera SignalTap and Incremental Route
56610: 03/06/10: What's in a bitstream?
57427: 03/06/30: Re: I need a commercial PCI FPGA board, please help
57547: 03/07/02: Re: why so many problems Xilinx ?
57615: 03/07/02: Re: NIOS tutorial for the Stratix1S10
57843: 03/07/08: Re: Nios bash acting bizzar
58312: 03/07/20: Re: Is a Virtex-II Pro family a hands-down winner for DSP ?
62053: 03/10/17: Re: Quartus 2.2, SOPC builder and leonardo
63160: 03/11/17: Altera's altsyncram MAXIMUM_DEPTH
63226: 03/11/18: Re: Active-HDL 6.1 pricing
63227: 03/11/18: Re: Active-HDL 6.1 pricing
63253: 03/11/18: Re: Altera's altsyncram MAXIMUM_DEPTH
64130: 03/12/17: VHDL comments in Vim?
65028: 04/01/19: Re: Avalon DMA problems
65226: 04/01/22: Why is router software not multi-threaded?
65326: 04/01/24: Timing model for MultiTrack interconnects in Stratix?
65403: 04/01/27: Re: Timing model for MultiTrack interconnects in Stratix?
65680: 04/02/04: Re: Stratix II NIOS sizes ?
65681: 04/02/04: Re: Experiences with Microblaze and Nios
66492: 04/02/20: Re: Simulation MODEL for SRAM
66972: 04/03/02: Re: Need to speed up Stratix compiles.
67476: 04/03/12: Re: Quartus II version 4 (Web Edition) DOES NOT WORK AT ALL !?
67700: 04/03/17: Re: Logiclock TCL flow for Quartus II
67750: 04/03/18: LogicLock
67761: 04/03/18: Re: Printing from Altera SOPC Builder
67764: 04/03/18: Re: LogicLock
67801: 04/03/19: Re: Altera Quartus Compilation Report
68067: 04/03/25: Re: Altera NIOS SOPC Builder---- Can I edit a text file
68148: 04/03/27: Re: AHDL, VERILOG or VHDL??
68149: 04/03/27: Re: study verilog or vhdl?
68150: 04/03/27: Re: study verilog or vhdl?
68184: 04/03/29: Re: Logiclock TCL flow for Quartus II
68222: 04/03/30: Re: AHDL, VERILOG or VHDL??
68431: 04/04/04: Re: AHDL, VERILOG or VHDL??
68649: 04/04/12: Re: Apples to Apples? Stratrix Two <> Virtex II Pro
68806: 04/04/19: Re: NIOS: Run program from SDRAM
69100: 04/04/27: Design PAR in Stratix
69103: 04/04/27: Re: Design PAR in Stratix
69128: 04/04/27: Re: Design PAR in Stratix
69144: 04/04/28: Re: Error in SoPC Builder
69145: 04/04/28: Re: FMF library
69313: 04/05/05: Re: How to drive record fields from procedure AND testbench?
69333: 04/05/06: Re: How to drive record fields from procedure AND testbench?
69342: 04/05/07: Re: How to drive record fields from procedure AND testbench?
69376: 04/05/09: Re: How to drive record fields from procedure AND testbench?
69768: 04/05/19: Re: Nios II Going Live...
69857: 04/05/22: Re: Never right, always room for improvement
70165: 04/06/07: Good SDRAM Controller
70188: 04/06/08: Re: Good SDRAM Controller
70189: 04/06/08: Re: Good SDRAM Controller
70214: 04/06/09: Re: Good SDRAM Controller
70486: 04/06/17: Re: Quartus II - Disabling the Optimizer to use gate delay
70487: 04/06/17: Re: Quartus II - Disabling the Optimizer to use gate delay
70782: 04/06/28: Re: Nios stops responding to interrupts
70784: 04/06/28: Re: Nios stops responding to interrupts
70834: 04/06/29: Re: Nios stops responding to interrupts
70850: 04/06/30: Re: Altera Nios Ethernet Development Kit: "spurious interrupt number: 0000 001C"
70853: 04/06/30: Re: File format *.eqn in Altera IDE
71411: 04/07/17: Problem with LogicLock and register packing
71495: 04/07/20: Re: Problem with LogicLock and register packing
76320: 04/11/30: Re: Verilog newbie with clocking question
77971: 05/01/21: Re: Quartus II v4.2 LogicLock Regions
79190: 05/02/15: Re: Any Altera FIFO not a power of 2?
80296: 05/03/03: Re: Altera Quartus II 4.2 SP1 fit problem and Altera APEX20KE clock problem
80493: 05/03/07: Asynchronous processor !?!
80561: 05/03/08: Re: Asynchronous processor !?!
80918: 05/03/14: Re: Which HDL?
80976: 05/03/15: Re: Which HDL?
81182: 05/03/18: Re: Which HDL?
81291: 05/03/21: Re: Spartan 3E vs. Cyclone2
81562: 05/03/27: Re: some +. for Altera
82335: 05/04/11: Re: Neural Networks in FPGA
83077: 05/04/22: Re: ispTRACY-Lattice vs. SignalTap-Altera
83083: 05/04/22: Xilinx multiplier out of slices
83346: 05/04/27: Cygwin & Nios II
83377: 05/04/28: Re: Cygwin & Nios II
84121: 05/05/12: Re: "Mine is bigger than yours..."
84124: 05/05/12: Re: V4 vs. Stratix-II...
84125: 05/05/12: Re: "Mine is bigger than yours..."
84493: 05/05/19: Re: Unable to Download on STRATIX (EP1S25F1020C5) Development Board using NIOS IDE
84741: 05/05/25: Re: lpm_counter bug?
85804: 05/06/16: Re: Auto pipeline logic??
85806: 05/06/16: Re: Deisgn partitioning issues
85808: 05/06/16: Re: LUT, how to?
86868: 05/07/07: Re: Max Sample Rate for Signal Tap in Altera Quartus?
142154: 09/07/27: Simulating Altera scfifo in ModelSim
142155: 09/07/27: Re: Simulating Altera scfifo in ModelSim
Peter Sorensen:
85420: 05/06/09: Ml40x Reference Design not working with EDK 7.1?
Peter Sutton:
21306: 00/03/16: Xilinx 6200 devices?
73670: 04/09/28: Call for Participation, ICFPT04, Brisbane 6-8 December
82538: 05/04/14: Re: Neural Networks in FPGA
Peter Særensen:
81110: 05/03/17: ISE 7.1 WebPack + EDK 6.3
Peter Sørensen:
17439: 99/07/28: Re: Problem with Max+PlusII / Flex10k
84284: 05/05/16: Re: EDK 7.1 with xilinx ML401 ref design
Peter Tawdross:
52931: 03/02/26: FPGA arch.
52937: 03/02/26: Re: FPGA arch.
52939: 03/02/26: Re: interfacing keyboard to a xilinix fpga board
52940: 03/02/26: Re: Static 1 and Static 0 Hazard
Peter TB Brett:
85551: 05/06/10: Re: How do I find out the connection of the LCD I took out from a digital camera?
85587: 05/06/11: Re: Selecting FPGA synthesis, place and route and simulation tools
85594: 05/06/11: Re: Selecting FPGA synthesis, place and route and simulation tools
Peter Trei:
4995: 97/01/09: DES Keysearch by FPGA: $10,000 prize
5017: 97/01/13: Re: DES Keysearch by FPGA: $10,000 prize
5034: 97/01/14: Re: Efficient DES Keysearch
9168: 98/02/27: DES: beginner FPGA questions.
9973: 98/04/19: Demonstrate the power of your FPGA system. Win $10k.
Peter van Beek:
38053: 02/01/03: PCI Solution: LogiCore?
38078: 02/01/04: Re: PCI Solution: LogiCore?
39091: 02/01/31: Re: PCI Solution: LogiCore?
39093: 02/01/31: meeting time critical conditions
Peter Van Epp:
144123: 09/11/12: Ethernet PCIe boards and PHY daughter cards?
144230: 09/11/21: Re: FPGA + Ethernet
144233: 09/11/21: Re: FPGA + Ethernet
144264: 09/11/23: Re: PCI card unrecognized
144273: 09/11/24: Re: PCI card unrecognized
144666: 09/12/22: Re: Configuring the ML402
144737: 09/12/30: Re: Seeking some advice
144749: 09/12/30: Re: Seeking some advice
144757: 09/12/30: Re: Seeking some advice
144758: 09/12/31: Re: Seeking some advice
144792: 10/01/04: Re: Video Processing
144852: 10/01/08: Re: Difference among Virtex Families, FPGA Books
144882: 10/01/12: Re: Old School Hurts
145051: 10/01/22: Re: Networking Board Recommendation
145464: 10/02/11: Re: Reading UDP with FPGA
145483: 10/02/11: Re: DONE_cycle:6 setting neccessary in bitgen
145492: 10/02/12: Re: DONE_cycle:6 setting neccessary in bitgen
145766: 10/02/23: Re: Reading UDP with FPGA
Peter Vandenabeele:
47572: 02/09/29: Re: virtex II pro development board
50770: 02/12/19: Re: Embedded Linux for V2Pro
Peter Verplaetse:
11798: 98/09/10: Xilinx ncd files
Peter Waldeck:
40500: 02/03/08: Error in Foundation 4.1i
55264: 03/05/02: Re: programmable oscillators
67878: 04/03/22: Re: cpu and linux on a fpga (new to FPGAs)
71055: 04/07/07: Re: RAMB16_Sx instantiation template
Peter Wallace:
37390: 01/12/09: Re: ISA syncronization?
37391: 01/12/09: Re: PCI card - 2 layers versus four layers
42353: 02/04/21: Re: 8051 Core for Motor Electronics
46867: 02/09/10: Re: 555 schematic or vhdl for xilinx or other clock circuit ?
47130: 02/09/18: Re: Simple parallelport IP for Spartan2
48344: 02/10/16: Re: xilinx: VirtexII in a pqfp208 or pqfp240 ?
49074: 02/10/31: Re: Spartan-II configuration
49083: 02/10/31: Re: Spartan-II configuration
49223: 02/11/05: Re: WebPACK 5.1 SP2
51649: 03/01/17: Re: Booting Spartan IIE from SPI
52413: 03/02/08: Re: USB2 or firewire or 100Mb ethernet link to FPGA design
52642: 03/02/17: Re: About automatically programming my FPGA
53274: 03/03/09: Re: Motion Control IP Cores , anyone do them ?
53563: 03/03/16: Re: blockram optimized away
53688: 03/03/19: Re: Cheapest Spartan II/IIE configuration flash EEPROM!
53995: 03/03/30: Re: [Question] FPGA/PLX9054
54189: 03/04/04: Re: Spartan vs. Cyclone for arithmetic functions
54513: 03/04/12: Re: Too early to throw away Parallel Cable III...
54570: 03/04/14: Re: Too early to throw away Parallel Cable III...
54717: 03/04/16: Re: Xilinx has released SpartanIII
54736: 03/04/16: Re: Xilinx has released SpartanIII
55502: 03/05/10: Re: Encrypted bitstream - battery lifetime problem
55754: 03/05/18: Re: smallest embedded cpu.
56080: 03/05/28: Re: FIFO Controller
56121: 03/05/28: Re: JTAG madness
56230: 03/05/31: Re: FPGA's an Flash
56238: 03/05/31: Re: FPGA's an Flash
56613: 03/06/10: Re: PC-104 dev Boards
56676: 03/06/11: Re: PC-104 dev Boards
56893: 03/06/18: Re: Downloading bit-stream with a microprocessor.
58045: 03/07/13: Re: edge card connectors and high speed design
58457: 03/07/23: Re: Active Probe
58825: 03/08/01: Re: PLL / DPLL phase question
59360: 03/08/15: Re: Old Xilinx FPGAs
59480: 03/08/20: Re: Xilinx FPGA pin locking/assignment
59742: 03/08/27: Re: How to listen to music through an FPGA pin?
59743: 03/08/27: Re: How to listen to music through an FPGA pin?
60750: 03/09/21: Re: Parallel JTAG cable on a USB-only W2K laptop?
61280: 03/10/01: Re: Automatic I/O voltage sensing (as XILINX ParallelCable IV)
65532: 04/02/01: Re: New USB chip for fast FPGA bitstream download
68418: 04/04/03: Low cost Improved Parallel Cable 3 PCB + El Cheapo CPLD card
69883: 04/05/23: Re: More fun with VHDL
72830: 04/09/03: Re: [XC96xxXL] Maximum Value for the external Pull-Up resistor ...
72888: 04/09/07: Re: VHDL code for 16-32 bit counter for quadrature encoder signals (A-B)
86849: 05/07/07: Re: PC104 (ISA) bus in FPGA (Spatan 2E)
89599: 05/09/20: Re: Reprogramming FPGA over PCI???
97764: 06/02/27: Re: fpga to 5v ttl logic
102645: 06/05/18: Re: Xilinx Platform Cable USB protocol specifications and/or open-source firmware replacement
106313: 06/08/11: Re: Open source Xilinx JTAG programmer with Digilent USB support
107302: 06/08/26: Re: FPGA -> SATA?
107304: 06/08/26: Re: Why isn't there a thermal diode on large FPGAs?
107344: 06/08/26: Re: Why isn't there a thermal diode on large FPGAs?
111233: 06/10/31: Re: Taking forever to synthesise (XILINX ISE 8.1i)
114973: 07/01/28: Re: Minimal design for xilinx?
115453: 07/02/11: Re: FPGA configuration direct from PLX
117373: 07/03/29: Re: Problems with Xilinx Parallel III Cable
122013: 07/07/17: XC9572XL bus hold - Cant be disabled
122934: 07/08/10: Re: Webpack 9.1 and Samba
124846: 07/10/07: Re: Daisy chaining FPGA with CPLDs
127084: 07/12/11: Re: PCI Parallel port card for JTAG / programming?
Peter Welten:
6956: 97/07/15: Selection Criteria for CPLD's/FPGA's
7021: 97/07/23: Why fast message delete in this group?
Peter Winkler:
100426: 06/04/09: C-Compiler for free VHDL controller core ?
100439: 06/04/09: Re: C-Compiler for free VHDL controller core ?
100442: 06/04/09: Re: C-Compiler for free VHDL controller core ?
100505: 06/04/10: Re: C-Compiler for free VHDL controller core ?
100549: 06/04/12: Re: C-Compiler for free VHDL controller core ?
Peter Wtorek:
50956: 02/12/23: Altera SOPC Builder 2.61 problems ...
Peter Wurbs:
2171: 95/10/25: Help needed: TNM attributes (Xilinx)
2706: 96/01/26: Re: HowTo access a SRAM with a XC4000
2794: 96/02/09: Help: Xilinx behavior if Power down
2833: 96/02/14: Re: Xilinx is NOT specified MINIMUM delay -
2952: 96/03/05: Re: SYNARIO tool for CPLD and FPGA ?
5713: 97/03/10: Accolade
Peter Y:
81529: 05/03/26: Initializing Altera MEGARAMs in simulation
81611: 05/03/28: Re: Initializing Altera MEGARAMs in simulation
114234: 07/01/08: Re: what are your current SoC design for ?
114356: 07/01/12: Stratix RAM limitations
114361: 07/01/12: Re: Stratix RAM limitations
117408: 07/03/30: Re: RISC implementation questions
Peter Young:
42423: 02/04/23: Re: Xilinx 4.2i not working on my design
42742: 02/05/01: Re: DCM off chip deskew
42930: 02/05/07: Re: Timing Scores
46041: 02/08/15: Re: changing width of array
47530: 02/09/27: Re: Unpredictable Place and Route
47533: 02/09/27: Re: Finding nets in hierarchy
peter.halford@alarmip.com:
93464: 05/12/22: Going insane - Xilinx VGA controller...
93471: 05/12/22: Re: Going insane - Xilinx VGA controller...
93688: 05/12/28: Re: Going insane - Xilinx VGA controller...
93754: 05/12/29: Re: Going insane - Xilinx VGA controller...
93796: 05/12/30: Re: Going insane - Xilinx VGA controller...
peter.kampmann@googlemail.com:
108430: 06/09/11: Xilinx Platform Studio 8.2i - Add custom peripheral, adress Space calculation
<peter.kampmann@googlemail.com>:
106614: 06/08/16: Xilinx PowerPC run Program out of SDRAM
106846: 06/08/21: Re: Xilinx PowerPC run Program out of SDRAM
107794: 06/09/01: Synthesize IEEE fixpoint Library with Xilinx ISE 8.2i
<peter.trott@vantis.com>:
14546: 99/02/04: Re: Opinions requested : Minc/Synario alternatives
15052: 99/03/04: Re: Getting started in programmable logic
<peter8888844@gggggserve.com>:
4586: 96/11/18: Re: UART FOR FPGAS
4634: 96/11/23: Re: FPGA Gate Counts: No Truth in Advertising
<peter@diguserve.com>:
4876: 96/12/23: Re: Xilinx loading problem?
<peter@geckoaudio.com>:
86676: 05/07/03: ModelSim Timing Simulation Signal Names
86677: 05/07/03: Re: interpolation in FPGA
<Peter@he.net>:
<peter@kksystems.com>:
3271: 96/05/07: Please help with CRC hardware implementation - crcgen.zip (0/1)
3272: 96/05/07: Please help with CRC hardware implementation - crcgen.zip (1/1)
3302: 96/05/11: THANK YOU all for the CRC generator responses
<peter@nowhere.com>:
4751: 96/12/11: Re: GAL STARTER KIT
4805: 96/12/17: Re: ASICs Vs. FPGA in Safety Critical Apps.
4889: 96/12/25: Re: Integer divide IC
4940: 97/01/02: Re: NT 4.0, ViewOffice 7.2 and Xilinx tools...96->97 problem...
<peter@xilinx.com>:
139706: 09/04/09: Re: xilinx ram dual-edge?
140216: 09/05/04: Re: FIFO that latches data asynchronic manner
140321: 09/05/08: Re: Dual Port RAM Inference
140373: 09/05/11: Re: Dual Port RAM Inference
140378: 09/05/11: Re: Dual Port RAM Inference
140392: 09/05/12: Re: Dual Port RAM Inference
140975: 09/06/01: Re: Maximum tilemap size for Virtex6 devices?
140985: 09/06/01: Re: phase locking a slow (2Mhz) signal.
peter_b:
58917: 03/08/04: interface with 860
<peter_raeth@juno.com>:
27684: 00/12/02: Column on FPGAs
peterc:
9797: 98/04/06: Re: Xilinx routing optimization?
9812: 98/04/07: Re: Xilinx routing optimization?
9986: 98/04/21: Re: Xilinx FPGAs: Usable Pins on XS Boards (Help)
10263: 98/05/08: Re: Low power FPGA design
13221: 98/11/20: Re: Xilinx 5.2/6 tools v M1.5 tools for an XC4013E part.....
13222: 98/11/20: Re: Major Xilinx design problems using XC4013XL or XC4020XL, M1.3-M1.5
13450: 98/12/03: Re: Xilinx FPGA configuration problems... Help!
35262: 01/09/27: Re: Timing constraints...
35382: 01/10/02: Re: Xchecker and NT???
PeterC:
86703: 05/07/04: Re: ModelSim Timing Simulation Signal Names
86706: 05/07/04: Re: ModelSim Timing Simulation Signal Names
86806: 05/07/06: Re: ModelSim Timing Simulation Signal Names
88164: 05/08/10: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
88167: 05/08/10: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
88168: 05/08/10: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
88172: 05/08/10: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
88199: 05/08/11: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
88204: 05/08/11: Re: Generating 44.1 kHz clock from 98.304 MHz crystal on FPGA ?
89835: 05/09/27: Dolby Digital AC-3 Decode on an FPGA - Possible ? Big ?
96687: 06/02/08: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest possible speed?
96739: 06/02/09: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest possible speed?
96749: 06/02/09: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest possible speed?
96752: 06/02/09: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest possible speed?
96754: 06/02/09: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest possible speed?
96763: 06/02/09: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest possible speed?
96880: 06/02/12: Re: Parallel NCO (DDS) in Spartan3 for clock synthesis - highest possible speed?
98813: 06/03/16: Measuring pulse width in ModelSim simulation without using cursors and writing the widths to a text file
98819: 06/03/16: Re: Measuring pulse width in ModelSim simulation without using cursors and writing the widths to a text file
98831: 06/03/16: Re: Measuring pulse width in ModelSim simulation without using cursors and writing the widths to a text file
99168: 06/03/20: Re: DDS
99677: 06/03/27: Hand-drawn schematic symbols of ISE coregen cores revert to rectangles when underlying core parameters are changed!
99743: 06/03/28: Re: Hand-drawn schematic symbols of ISE coregen cores revert to rectangles when underlying core parameters are changed!
100184: 06/04/04: Dual-edge synthesizable D flip-flop - any pitfalls?
100189: 06/04/04: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
100190: 06/04/04: Re: Streamlining FIRs in System Generator
100196: 06/04/04: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
100261: 06/04/05: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
100454: 06/04/09: Re: How does the DCM phase shifting circuitry work? Xilinx Spartan 3
104572: 06/06/29: Carry-chain based tapped delay line in Spartan3 - resolution? PVT variability?
104925: 06/07/09: LUT4 INIT value to implement 2:1 MUX ?
104958: 06/07/10: Re: LUT4 INIT value to implement 2:1 MUX ?
104959: 06/07/10: Re: LUT4 INIT value to implement 2:1 MUX ?
106263: 06/08/10: Switching two (synchronous) clocks with variable phase difference, without glitching or period loss
106601: 06/08/15: Re: Switching two (synchronous) clocks with variable phase difference, without glitching or period loss
PeterK:
117771: 07/04/10: Newbie with bus width mismatch problem. Quartus II
117826: 07/04/11: Re: Newbie with bus width mismatch problem. Quartus II
117910: 07/04/13: Re: Are there Quartus II Web Edition limitations?
PeterS:
22436: 00/05/09: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
22447: 00/05/09: Re: ANNOUNCE: Embedded Systems Glossary and Bibliography
PeterSmith1954@googlemail.com:
104744: 06/07/05: Re: Can I use all 18bits of a BlockRAM?
104788: 06/07/06: Re: DDR Controller problems
104881: 06/07/07: Re: DDR Controller problems
104954: 06/07/10: Re: High-speed DAC/ADC with FPGA
PeterUK:
141059: 09/06/04: Urgent help with a Simple AND simulation
peterzhu:
59985: 03/09/03: How to extend a pulse width without clock!
60036: 03/09/03: How to extend a pulse width without clock in CPLD!
60093: 03/09/04: Re: How to extend a pulse width without clock!
PeteS:
85037: 05/06/03: Re: PCI master clock trace
85100: 05/06/04: Re: PCI master clock trace
90508: 05/10/15: Re: How many decoupling capacitors need on one device?
90509: 05/10/15: Re: How to Reduce Interconnects (VDD and VSS)
90533: 05/10/16: Re: Implementing I2C master
90534: 05/10/16: Re: How to Reduce Interconnects (VDD and VSS)
90535: 05/10/16: Re: Mixed voltage in JTAG chain.
90566: 05/10/17: Re: How to Reduce Interconnects (VDD and VSS)
91083: 05/10/28: Re: Physical interface for PCI express(PIPE) electrical information
91084: 05/10/28: Re: Physical interface for PCI express(PIPE) electrical information
91462: 05/11/07: Re: Xilinx Package/Logic Options
91792: 05/11/13: Re: i2c slave does not acknowlege
91856: 05/11/15: Re: RoHS
91860: 05/11/15: Re: RoHS
91893: 05/11/16: Re: 3 devices on the same external bus
92026: 05/11/20: Re: Asynchronous design
92027: 05/11/20: Re: Asynchronous design
92031: 05/11/20: Re: Asynchronous design
92278: 05/11/25: Re: Configuration PROM XC18V02 bit error
92310: 05/11/27: Re: Mobile Chips
92337: 05/11/28: Re: AD9218, what will the negative values be in binary mode?
92339: 05/11/28: Re: AD9218, what will the negative values be in binary mode?
92347: 05/11/28: Re: boot from flah
92421: 05/11/29: Re: boot from flah
92462: 05/11/30: Re: nallatech benone fpga board
92464: 05/11/30: Re: first time managing a project
92468: 05/11/30: Re: open-sourced FPGA (vhdl, verilog, C variants) design libraries, working toward a GNU (for hardware) paradigm
92485: 05/11/30: Re: Q-bus or Unibus bus transactions in FPGA?
92970: 05/12/10: Re: How to connect 2 FPGA?
93079: 05/12/13: Re: How can I surpress noise in an ADC board?
93129: 05/12/14: Re: J Tag Protocol
93130: 05/12/14: Re: SGMII Interface
93189: 05/12/15: Re: Xilinx DCM Shuts down at 75degree centigrade
93235: 05/12/16: Re: Xilinx DCM Shuts down at 75degree centigrade
93726: 05/12/29: Re: PCI interface on CYCLONE(ep1c6)
93727: 05/12/29: Re: Power Optimization: can the routing and placement really save power?
94636: 06/01/15: Re: what happens in SDR-SDRAM if i exceed tRAS(max)
94849: 06/01/18: Re: FPGA interface to FLASH
94929: 06/01/19: Re: FPGA interface to FLASH
95000: 06/01/20: Re: Sorting large amounts of floats
94988: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95042: 06/01/20: Re: OT:Shooting Ourselves in the Foot
96529: 06/02/06: Re: RocketIO & Infiniband BERs?
96866: 06/02/12: Re: Creating low freq. clock on Altera FPGA
96899: 06/02/13: Re: Newb question about Xilinx Impact and parallel cable III ....
96964: 06/02/14: Re: SCHEMATICS ... Is anybody as frustrated as I am with the software?
97022: 06/02/14: Re: Altera RoHS Irony
97284: 06/02/20: Re: DDR SDRAM Controller
97348: 06/02/21: Re: DDR SDRAM Controller
97445: 06/02/22: Re: DDR SDRAM Controller
97478: 06/02/23: Re: DDR SDRAM Controller
97497: 06/02/23: Re: DDR2 Memory Design: Layout, timing
97501: 06/02/23: Re: DDR2 Memory Design: Layout, timing
97503: 06/02/23: Re: DDR2 Memory Design: Layout, timing
97813: 06/02/28: Re: New XC9572 decoupling newbie question :-)
97814: 06/02/28: Re: New XC9572 decoupling newbie question :-)
104993: 06/07/11: Re: High-speed DAC/ADC with FPGA
105012: 06/07/11: Re: High-speed DAC/ADC with FPGA
105130: 06/07/14: Re: Need for reset in FPGAs
105134: 06/07/14: Re: Need for reset in FPGAs
105201: 06/07/17: Re: Need for reset in FPGAs
105234: 06/07/18: Re: Virtex 4, LVDS I/O: Sanity check please
105420: 06/07/22: Re: Virtex 4, LVDS I/O: Sanity check please
105447: 06/07/23: Re: Virtex 4, LVDS I/O: Sanity check please
105597: 06/07/26: Re: How to phase align a 10MHz clock using V4LX60 DCM
105665: 06/07/28: Re: Spartan3 5V PCI
105773: 06/07/31: Re: Accessing one SDRAM from two MicroBlazes
105874: 06/08/02: Re: Minimum frequency at which ddr can operate
105896: 06/08/02: Re: Minimum frequency at which ddr can operate
106000: 06/08/04: Re: DDR Controller
106034: 06/08/06: Re: verilog versus vhdl
106267: 06/08/10: Re: Switching two (synchronous) clocks with variable phase difference, without glitching or period loss
106268: 06/08/10: Re: Switching two (synchronous) clocks with variable phase difference, without glitching or period loss
106283: 06/08/10: Re: Switching two (synchronous) clocks with variable phase difference, without glitching or period loss
106320: 06/08/11: Re: Embedded clocks
106321: 06/08/11: Re: Embedded clocks
106358: 06/08/12: Re: Clock domain crossing (again)
106431: 06/08/13: Re: Maximum Current Draw of FPGA
106432: 06/08/13: Re: Embedded clocks
106441: 06/08/13: Re: Maximum Current Draw of FPGA
106549: 06/08/15: Re: Crystal input for FPGA
106577: 06/08/15: Re: Maximum Current Draw of FPGA
106638: 06/08/16: Re: Open-source JTAG software?
106825: 06/08/20: Re: CPU design
106828: 06/08/20: Re: xilinx or altera?
106831: 06/08/20: Re: xilinx or altera?
106942: 06/08/22: Re: Running DDR below the min frequency
107039: 06/08/23: Re: CPU design
107100: 06/08/24: Why isn't there a thermal diode on large FPGAs?
107103: 06/08/24: Re: Why isn't there a thermal diode on large FPGAs?
107259: 06/08/25: Re: Running DDR below the min frequency
107290: 06/08/26: Re: FPGA -> SATA?
107291: 06/08/26: Re: RocketIO over cable
107307: 06/08/26: Re: FPGA -> SATA?
107914: 06/09/02: Re: Impossible to download WebPACK?
107929: 06/09/02: Re: Impossible to download WebPACK?
107977: 06/09/03: Re: Please help me with (insert task here)
107978: 06/09/03: Re: Impossible to download WebPACK?
107981: 06/09/03: Re: Please help me with (insert task here)
107982: 06/09/03: Re: Please help me with (insert task here)
108418: 06/09/11: Re: RESET Signals
108442: 06/09/11: Re: Performance Appraisals
108689: 06/09/15: Re: Spartan3 driving mosfets
108744: 06/09/15: Re: Spartan3 driving mosfets
108825: 06/09/17: Re: What resources do the Xilinx tools require on a PC?`
109335: 06/09/24: Re: Odd error in timing analyzer
109703: 06/10/03: Re: Are you ready for Virtex-5? We are...
109804: 06/10/05: Re: Just a matter of time
109811: 06/10/05: Re: a clueless bloke tells Xilinx to get a move on
110320: 06/10/13: Re: DDR SDRAM static timing analysis
110556: 06/10/17: Re: Newbie : Please give me an idea about programming an FPGA
110582: 06/10/18: Re: 8B/10B vs. Start/Stop for SERDES
110728: 06/10/20: Re: Reversing SPI shift out order on Microblaze design
110765: 06/10/21: Re: Can ISE text editor generate CRLF line endings?
110845: 06/10/24: Re: Please Help
110859: 06/10/24: Re: Please Help
110860: 06/10/24: Re: Memory
111039: 06/10/27: Re: Xilinx Virtex-4 Clock Multiplexer Inputs
111051: 06/10/27: A pre-emptive strike against blaming the chip
111056: 06/10/27: Re: A pre-emptive strike against blaming the chip
111085: 06/10/28: Re: A pre-emptive strike against blaming the chip
111089: 06/10/28: Re: A pre-emptive strike against blaming the chip
111090: 06/10/28: Re: A pre-emptive strike against blaming the chip
111119: 06/10/29: Re: A pre-emptive strike against blaming the chip
111248: 06/10/31: Re: A pre-emptive strike against blaming the chip
111264: 06/10/31: Re: Question about bandwidth of scope?
111265: 06/10/31: Re: Question about bandwidth of scope?
111338: 06/11/01: Re: Spectre of Metastability Update
111415: 06/11/02: Re: Spectre of Metastability Update
111998: 06/11/14: Re: sending data across a 32 bit bus
111999: 06/11/14: Re: Influence of temperature and manufacturing to propagation delay
112007: 06/11/14: Re: Influence of temperature and manufacturing to propagation delay
112009: 06/11/14: In defence of Austin and Xilinx
112011: 06/11/14: Re: Influence of temperature and manufacturing to propagation delay
112038: 06/11/15: Re: Impedance I/O SPARTAN3 board
112063: 06/11/15: Re: In defence of Austin and Xilinx
112064: 06/11/15: Re: Influence of temperature and manufacturing to propagation delay
112067: 06/11/15: Re: Impedance I/O SPARTAN3 board
112068: 06/11/15: Re: 8080 FSGA model in an FPGA
112069: 06/11/15: Re: Power-on reset
112072: 06/11/15: Re: how to filter glitches and mutliple transitions?
112073: 06/11/15: Re: how to filter glitches and mutliple transitions?
112120: 06/11/16: Re: In defence of Austin and Xilinx
112122: 06/11/16: Re: Influence of temperature and manufacturing to propagation delay
112123: 06/11/16: A minor addendum
112126: 06/11/16: Re: how to filter glitches and mutliple transitions?
112128: 06/11/16: Re: how to filter glitches and mutliple transitions?
112201: 06/11/17: Re: pulse jitter due to clock
112204: 06/11/17: Re: 8080 FSGA model in an FPGA
112211: 06/11/17: Re: PCMCIA interface
112235: 06/11/18: Re: Xilinx Virtex-4 Clock Multiplexer Inputs
112261: 06/11/18: Re: board - T562.jpg
112262: 06/11/18: Re: board - T562.jpg
112265: 06/11/19: Re: board - T562.jpg
112334: 06/11/20: Re: board - T562.jpg
112336: 06/11/20: Re: board - T562.jpg
112337: 06/11/20: Re: board - T562.jpg
112393: 06/11/21: Re: board - T562.jpg
112409: 06/11/21: Re: board - T562.jpg
112411: 06/11/21: Re: board - T562.jpg
112413: 06/11/21: Re: board - T562.jpg
112465: 06/11/22: Re: board - T562.jpg
112469: 06/11/22: Re: Protecting netlist for Xilinx
112590: 06/11/25: Re: board - T562.jpg
112599: 06/11/25: Re: board - T562.jpg
112623: 06/11/26: Re: vccaux and vccint
112625: 06/11/26: Re: board - T562.jpg
112626: 06/11/26: Re: board - T562.jpg
112752: 06/11/28: Re: Bus structures question (Spartan 3)
112761: 06/11/28: So who has used Lattice FPGAs recently?
112821: 06/11/29: Re: So who has used Lattice FPGAs recently?
112822: 06/11/29: Re: Bus structures question (Spartan 3)
112837: 06/11/29: Re: Spartan3 Configuration Puzzler
112840: 06/11/29: Re: Spartan-3E or Generic FPGA -> PC133 interface details??
112900: 06/11/30: Re: So who has used Lattice FPGAs recently?
112936: 06/12/01: Re: Avoiding meta stability?
112943: 06/12/01: Re: So who has used Lattice FPGAs recently?
112952: 06/12/02: Re: Video Mux using FPGA
113039: 06/12/05: Re: How to check high impedance of a RAM with Logic Analyzer
113060: 06/12/05: Re: First Look at QuartusII 6.1
113320: 06/12/11: Re: How to read data from intel strata flash using microblaze?
113323: 06/12/11: Re: How to read data from intel strata flash using microblaze?
113333: 06/12/11: Re: spartan3E : which differential inputs level fits CAN2B bus level ?
113347: 06/12/11: Re: spartan3E : which differential inputs level fits CAN2B bus level
113384: 06/12/12: Re: . What is the sign-and-magnitude of the following 4's complement number? (Leave answer in base 4).
113394: 06/12/12: Re: ISP interface
113396: 06/12/12: Re: ISP interface
113436: 06/12/13: Re: NOR Flash Controller
113464: 06/12/14: Re: NOR Flash Controller
113465: 06/12/14: Re: NOR Flash Controller
113492: 06/12/14: Re: NOR Flash Controller
113570: 06/12/17: Re: Frequency divider?
113571: 06/12/17: Re: Frequency divider?
113638: 06/12/18: Re: solder mask for fpga dissipation
113639: 06/12/18: Re: Frequency divider?
113710: 06/12/19: Re: Need book for verilog on xc9536?
113991: 07/01/02: Re: xilinx xc9536?
113994: 07/01/02: Re: Surface mount ic's
114002: 07/01/02: Re: lead free bga pads
114006: 07/01/02: Re: xilinx xc9536?
114057: 07/01/03: Re: newbie needs help
114115: 07/01/04: Re: lead free bga pads
114153: 07/01/05: Re: lead free bga pads
114162: 07/01/05: Re: Anyone seen eASIC?
114301: 07/01/11: Quick question on Coolrunner II IO voltages
114497: 07/01/17: Re: microcode in verilog?
114588: 07/01/19: Re: FPGA implementation of UHF transmitter in airborne applications
114590: 07/01/19: Re: Phasse Detector
114595: 07/01/20: Re: Phasse Detector
114716: 07/01/23: Re: FPGA power supply design
114724: 07/01/23: Re: FPGA power supply design
114752: 07/01/23: Re: FPGA power supply design
114753: 07/01/23: Re: FPGA power supply design
115080: 07/01/30: Re: 1 Gbps - state of the art?
115087: 07/01/30: Re: 1 Gbps - state of the art?
116499: 07/03/11: Re: ddr sdram controller
119403: 07/05/17: Re: Seeking the solutions of high speed interconnection for the long
119708: 07/05/24: Re: clarification: clock doubling in Spartan 3
119938: 07/05/29: Re: 6502 FPGA core
122028: 07/07/17: Re: XC9572XL bus hold - Cant be disabled
122479: 07/07/28: Re: Best CPU platform(s) for FPGA synthesis
123188: 07/08/19: Re: DDR controller - best device to perform
123189: 07/08/19: Re: DDR controller - best device to perform
123201: 07/08/19: Re: DDR controller - best device to perform
123367: 07/08/24: Re: Samtec PowerPoser power filtering solution.
123546: 07/08/29: Re: PCIe question
123610: 07/08/30: Re: PCB Impedance Control
123665: 07/08/31: Re: PCB Impedance Control
123667: 07/08/31: Re: PCB Impedance Control
123669: 07/08/31: Re: PCIe question
123671: 07/08/31: Re: PCB Impedance Control
123673: 07/08/31: Re: PCIe question
123675: 07/08/31: Re: PCB Impedance Control
123839: 07/09/05: Re: PCB Impedance Control
123918: 07/09/06: Re: PCB Impedance Control
123919: 07/09/06: Re: PCB Impedance Control
124153: 07/09/12: Re: PCI byte enalbes in read cycles
124691: 07/09/30: Re: Walking 1's
125549: 07/10/28: Re: Power supply filter capacitors
Petr P.:
48418: 02/10/17: Extest problem
Petres, Zoltan:
46397: 02/08/28: Neural hardware containing many neurons but very simple computation
Petri Havanto:
2301: 95/11/17: Re: [Q] FPGA Software for Linux
2599: 96/01/10: Re: [q][Reverse Engineering Protection]
2614: 96/01/11: Re: [q][Reverse Engineering Protection]
Petrov:
141748: 09/07/06: Re: How to keep documentation of control and status registers and
141750: 09/07/06: Re: TimingAnalyzer is now freeware
<Petrov_101@hotmail.com>:
81981: 05/04/05: Re: Structural vs Behavioral
82893: 05/04/19: Re: source control and Xilinx ISE 6 and 7
110836: 06/10/24: Re: Can ISE text editor generate CRLF line endings?
125709: 07/11/01: Another way to handle floating inputs.
125714: 07/11/01: Re: Another way to handle floating inputs.
125715: 07/11/01: Re: Another way to handle floating inputs.
125717: 07/11/01: Re: Another way to handle floating inputs.
127928: 08/01/10: Re: True Dual Port RAM
137439: 09/01/16: Re: Actel IGLOO FPGA has lower power consumption then Xilinx
petrus bitbyter:
56516: 03/06/07: Re: Logical analyzer via USB or printer port
112288: 06/11/19: Re: board - T562.jpg
118589: 07/04/30: Re: debounce state diagram FSM
118649: 07/05/01: Re: debounce state diagram FSM
118656: 07/05/02: Re: debounce state diagram FSM
145974: 10/03/02: Re: Help with avoiding ground-loops on my PCB+external
Petrus Pelser:
4320: 96/10/14: Re: Anyone using Altera MaxPlus VHDL ???
Petter Gustad:
660: 95/01/30: Re: [shin]Synthesis tools ported to Linux available???
3285: 96/05/09: Re: Please help with CRC hardware implementation - crcgen.zip (0/1)
5751: 97/03/12: Re: ACTEL RAM BASED FPGAs
9337: 98/03/06: Re: The case for free operating systems and EDA
9319: 98/03/06: Re: Using Java for PLI?
26515: 00/10/18: Re: scripting with xilinx tools (foundation) ????
26809: 00/10/30: Re: Undergraduate PLD Studies
26830: 00/10/31: Alliance under Linux?
26950: 00/11/04: Re: Alliance under Linux?
28068: 00/12/20: 18v04 programming
28397: 01/01/11: Re: Methodology
28289: 01/01/05: Re: FPGA Compiler2 question
28343: 01/01/08: Alliance for Linux
28351: 01/01/09: Re: Alliance for Linux
28391: 01/01/11: Re: grey code counters
28393: 01/01/11: Re: Alliance for Linux
28394: 01/01/11: Re: Alliance for Linux
28398: 01/01/11: Re: Alliance for Linux
28413: 01/01/11: Re: Alliance for Linux
28446: 01/01/12: Re: JTAG configuration fails with XC95144XL
28502: 01/01/15: Re: revision control tools ??
28567: 01/01/17: Re: revision control tools ??
28574: 01/01/17: Re: revision control tools ??
28674: 01/01/20: Re: revision control tools ??
29008: 01/02/01: Re: Xilinx JEDEC files to SVF format
30203: 01/03/28: Re: Xilinx FPGA Config file sizes.
30204: 01/03/28: Xilinx par -m
31607: 01/05/31: Xilinx Software Installer on Solaris
31746: 01/06/05: Xilinx SP8 install problems under Solaris
31843: 01/06/06: Xilinx RapidIO?
31868: 01/06/07: Xilinx RapidIO?
32311: 01/06/22: CoolRunner Synopsys libraries?
32359: 01/06/24: Re: what tools run OK on windows 2000?
32408: 01/06/26: Re: Xilinx logic usage
32602: 01/07/02: Re: Xillinx WebPack PAR problem
33767: 01/08/03: Re: Alliance tools going away?
33984: 01/08/09: Re: Alliance tools going away?
34004: 01/08/10: Re: Alliance tools going away?
34469: 01/08/27: PCI-X based hosts, availability?
34620: 01/08/31: Xilinx Device Update under Solaris
34661: 01/09/02: Re: Xilinx Device Update under Solaris
34719: 01/09/05: Xilinx Multilinx schematics?
34830: 01/09/10: Re: ModelSim Licensing SW Installation Opens Computer to Hacking?
35052: 01/09/19: MCS overflow? promgen and xc2v6000
35062: 01/09/20: Re: MCS overflow? promgen and xc2v6000
35756: 01/10/16: Re: Instantiating Virtex II library macros.
36124: 01/10/30: Re: Guided Design, Xilinx Virtex-E
36219: 01/11/02: Re: High level synthesis will never work well :)
36279: 01/11/05: Re: High level synthesis will never work well :)
36369: 01/11/07: Xilinx machine readable package info
36425: 01/11/08: Re: Xilinx machine readable package info
36426: 01/11/08: Re: Xilinx machine readable package info
36434: 01/11/08: Re: Xilinx machine readable package info
36448: 01/11/09: Re: Xilinx machine readable package info
36454: 01/11/09: Re: Xilinx machine readable package info
36492: 01/11/09: Re: Xpower and vcd files
36608: 01/11/13: Re: Virtex 2 parts availability???
36613: 01/11/13: Re: FPGA synthesis
36621: 01/11/13: Re: Place your orders....
36890: 01/11/23: wget of WebPack
36945: 01/11/27: Re: wget of WebPack
37054: 01/11/29: Re: Xilinx JTAG programmer: how to generate SVF
37088: 01/11/29: Re: wget of WebPack
37206: 01/12/03: Re: What do you like/dislike about place and route tools?
37322: 01/12/07: Re: using UNIX Environment variables in "ncvlog -file option" - Help!
37331: 01/12/07: Re: Has anyone successfully used opencores PCI?
37515: 01/12/13: Re: svf files in webpack 4.2
37531: 01/12/13: Re: svf files in webpack 4.1
38004: 01/12/30: Re: CRC-32 48bit(width)
38005: 01/12/30: Re: CRC-32 verilog source code
38060: 02/01/03: Re: Q: Cable for multiple LVDS signals - ?
38362: 02/01/12: Re: asic vs. fpga
38363: 02/01/12: Re: Xilinx PAR and Editor speed up
38468: 02/01/15: Xilinx XC4003A-6, docs and tools?
39939: 02/02/22: Re: Linux tools
39977: 02/02/22: Re: Linux tools
40232: 02/03/02: Re: Altera Excalibur
40392: 02/03/06: Re: exceeding 2GB limits in xilinx
40435: 02/03/07: Re: exceeding 2GB limits in xilinx
40436: 02/03/07: Re: exceeding 2GB limits in xilinx
40476: 02/03/07: Re: exceeding 2GB limits in xilinx
40519: 02/03/08: Re: exceeding 2GB limits in xilinx
40542: 02/03/09: Re: exceeding 2GB limits in xilinx
40552: 02/03/09: Re: exceeding 2GB limits in xilinx
40586: 02/03/11: Re: exceeding 2GB limits in xilinx
40666: 02/03/12: Re: exceeding 2GB limits in xilinx
40984: 02/03/19: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
41002: 02/03/19: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
41003: 02/03/19: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
41004: 02/03/19: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
41160: 02/03/21: coregen under Solaris
41170: 02/03/22: Re: coregen under Solaris
41185: 02/03/22: Re: coregen under Solaris
41226: 02/03/22: Re: coregen under Solaris
42015: 02/04/12: Re: Price List ?
42132: 02/04/16: Re: Command-line utility for loading Xilinx XC9572XL and Spartan II via JTAG
42849: 02/05/04: Re: Xilinx 2GB limit... something has to be done
42853: 02/05/05: Re: Xilinx 2GB limit... something has to be done
42936: 02/05/07: RocketIO simulations, ISE 4.2iSP2 GT_SWIFT simulation
42947: 02/05/08: Re: Xilinx MicroBlaze, Opinion?
42949: 02/05/08: Re: Opinions on FPGA cores - best for a commercial project?
43109: 02/05/14: Re: Opinions on FPGA cores - best for a commercial project?
43417: 02/05/21: Re: RocketIO simulations, ISE 4.2iSP2 GT_SWIFT simulation
43623: 02/05/27: Re: How can I create an encrypted netlist for Altera?
44135: 02/06/12: MicroBlaze uClinux port?
44333: 02/06/18: Re: MicroBlaze uClinux port?
44640: 02/06/25: Re: Xilinx cpld under Windows?
44645: 02/06/25: Re: Xilinx tools under WinXP
44668: 02/06/26: Re: Xilinx tools under WinXP
45090: 02/07/12: Re: Deterministic Output?
45389: 02/07/22: Re: Spartan II JTAG connection with other devices
46396: 02/08/28: ISE 5.1 Linux?
47158: 02/09/19: Re: ISE 5.1 Linux?
47335: 02/09/24: Re: Xilinx ISE5.1 and Windows NT
47339: 02/09/24: Re: Xilinx ISE5.1 and Windows NT
47395: 02/09/25: Re: Installing ISE5.1i (Alliance) on Solaris 7.
47692: 02/10/02: Re: question on ISE 5.1 and SMP machines...
47790: 02/10/04: Re: Low power design
47805: 02/10/04: Re: Low power design
47908: 02/10/07: Re: Xilinx WebPack ISE 5.1.01i XC9500 Implement problems
47998: 02/10/09: Re: Why can Xilinx sw be as good as Altera's sw?
47999: 02/10/09: Re: Why can't Altera sw be as good as Xilinx's sw?
48007: 02/10/09: Re: Why can't Altera sw be as good as Xilinx's sw?
48021: 02/10/09: Re: Why can't Altera sw be as good as Xilinx's sw?
48022: 02/10/09: Re: Why can't Altera sw be as good as Xilinx's sw?
48042: 02/10/10: Re: Why can't Altera sw be as good as Xilinx's sw?
48046: 02/10/10: Re: Why can't Altera sw be as good as Xilinx's sw?
48047: 02/10/10: Re: Why can't Altera sw be as good as Xilinx's sw?
48048: 02/10/10: Re: Intel ARM 'XScale' cores as IP blocks that can be synthesized into an FPGA/ASIC?
48054: 02/10/10: Re: Why can't Altera sw be as good as Xilinx's sw?
48081: 02/10/10: Re: Why can Xilinx sw be as good as Altera's sw?
48112: 02/10/11: Re: Why can Xilinx sw be as good as Altera's sw?
48117: 02/10/11: Re: Why can't Altera sw be as good as Xilinx's sw?
48178: 02/10/12: Re: Why can't Altera sw be as good as Xilinx's sw?
48681: 02/10/22: Re: Cyclic Redundancy Check generator
48814: 02/10/24: Re: Serial PROM Configuration
48879: 02/10/25: Re: 3.3V Device Programmer Suggestions ?
48880: 02/10/25: Re: 3.3V Device Programmer Suggestions ?
48895: 02/10/26: Re: #1's in verilog
48986: 02/10/28: Re: 3.3V Device Programmer Suggestions ?
48988: 02/10/28: Re: From NCD to Bitstream (Xilinx FPGA)
49069: 02/10/31: Re: 3.3V Device Programmer Suggestions ?
49220: 02/11/05: Re: WebPACK 5.1 SP2
49619: 02/11/18: Re: Webpack and Virtex Pro?
50881: 02/12/21: Re: Hi xilinx
51018: 02/12/26: Re: distributed computing with Modesim
51020: 02/12/26: Re: distributed computing with Modesim
51021: 02/12/26: Re: Pin definition in Quartus
51088: 02/12/31: Re: distributed computing with Modesim
51217: 03/01/07: Stratix IOE "Input Pin to Input Register Delay"
51414: 03/01/13: Re: Stratix IOE "Input Pin to Input Register Delay"
51847: 03/01/23: Re: Xilinx Impact on a SUN/Solaris
51896: 03/01/24: Re: Using an EPC16 as ONLY flash memory (ie. no configuration) - overkill?
51940: 03/01/27: Re: IEEE 1149.1
51994: 03/01/28: Re: Using an EPC16 as ONLY flash memory (ie. no configuration) - overkill?
52301: 03/02/06: Re: Switching synthesis tools
52391: 03/02/07: Xilinx ISE 4.2i killing Windows 2000?
52396: 03/02/08: Re: Xilinx ISE 4.2i killing Windows 2000?
52431: 03/02/09: Re: Xilinx ISE 4.2i killing Windows 2000?
52432: 03/02/09: Re: Xilinx ISE 4.2i killing Windows 2000?
52439: 03/02/10: Re: Xilinx ISE 4.2i killing Windows 2000?
52493: 03/02/11: Re: Synthesis Scripts
52648: 03/02/18: Re: Synopsys FC2 version 3.7.2 best so far
52724: 03/02/20: Re: Should I choose Xilink or Altera for a small project
52725: 03/02/20: Re: Should I choose Xilink or Altera for a small project
53093: 03/03/03: Re: scripting leonardo spectrum
53197: 03/03/06: Re: Bus Functional Model
53655: 03/03/19: Re: unsupported switches of PAR
53672: 03/03/19: Re: unsupported switches of PAR
53695: 03/03/20: Re: unsupported switches of PAR
53746: 03/03/21: Re: programmer adapter for Xilinx XC9572
53747: 03/03/21: Re: source code for crc
54023: 03/03/31: Re: microblaze gnu tool info ?
54088: 03/04/02: Re: Excel and FPGA's
54094: 03/04/02: quartus_cmd under Linux
54108: 03/04/02: Re: quartus_cmd under Linux
54124: 03/04/03: Re: Excel and FPGA's
54129: 03/04/03: Re: quartus_cmd under Linux
54306: 03/04/07: Re: precision RTL/Synplify/LeonardoSpectrum/Quartus
54397: 03/04/10: Re: Cheap(er) FPGA configuration?
54403: 03/04/10: Re: Cheap(er) FPGA configuration?
54404: 03/04/10: Re: Cheap(er) FPGA configuration?
54406: 03/04/10: SOPC Builder under Linux?
54463: 03/04/11: Re: Ethernet MAC (was Re: Cheap(er) FPGA configuration?)
54558: 03/04/14: Re: SOPC Builder under Linux?
54644: 03/04/15: nios-build under Solaris?
54702: 03/04/16: Re: nios-build under Solaris?
54922: 03/04/22: Re: quartus_cmd under Linux
55093: 03/04/26: Re: ise4.2i and wine
55208: 03/04/30: Re: nios-build under Solaris?
55760: 03/05/19: XILINX ISE 5.2iSP2 ngdbuild: File Pr_Logical.dfa is not found!
55761: 03/05/19: Re: a (PC) workstation for FPGA development
55796: 03/05/20: Re: a (PC) workstation for FPGA development
55811: 03/05/20: Re: a (PC) workstation for FPGA development
55835: 03/05/21: Opteron support?
56236: 03/05/31: Re: Xilinx Spartan download with Parallel III cable
56326: 03/06/03: Building NIOS GNU toolkit under Linux
57131: 03/06/24: Re: Quartus II for Linux
57136: 03/06/24: Re: MIPS instruction set?
57315: 03/06/27: Re: MIPS instruction set?
57594: 03/07/02: Re: NIOS tutorial for the Stratix1S10
57646: 03/07/03: Using Quarus to create SVF files?
57683: 03/07/03: Re: Using Quarus to create SVF files?
60233: 03/09/08: Re: Impact error
60267: 03/09/09: Re: Impact error
60680: 03/09/19: NIOS: plugs without an uart?
60895: 03/09/24: Re: ISE 6.1 and Redhat 9
61031: 03/09/26: Re: Synchronous Binary counter question.
61116: 03/09/29: Re: Free WebPack 6.1i Download Available Now for Spartan-3
61117: 03/09/29: Re: NIOS and OCI
61120: 03/09/29: Re: ISE: Parallel Processing
61160: 03/09/29: Re: development-tools under linux for altera excalibur
61206: 03/09/30: Re: ISE: Parallel Processing
61274: 03/10/01: Re: Any chance to buy Cyclone?
61311: 03/10/02: Re: Any chance to buy Cyclone?
61422: 03/10/03: Linux support in SDK 6.1i
61431: 03/10/03: Re: Quartus II tutorial vs the real world
62084: 03/10/18: Re: pci protocol analyzer
62177: 03/10/21: Re: Running Quartus II on ReadHat Linux 9.0
62272: 03/10/23: Re: Running Quartus II on ReadHat Linux 9.0
62274: 03/10/23: Scripting (was: Re: Running Quartus II on ReadHat Linux 9.0)
62299: 03/10/24: Re: Scripting (was: Re: Running Quartus II on ReadHat Linux 9.0)
62317: 03/10/26: Re: Running Quartus II on ReadHat Linux 9.0
62421: 03/10/29: Re: Sort of Running Quartus II on SuSE Linux 8.1-- sp2=fix!
62423: 03/10/29: Re: Xilinx Spartan3: Price
62424: 03/10/29: Re: How to protect fpga based design against cloning?
62442: 03/10/29: Re: Xilinx Spartan3: Price
62475: 03/10/30: Re: PicoBlaze for Altera (ACEX1K)?
62634: 03/11/03: Re: Running Quartus II on ReadHat Linux 9.0
62761: 03/11/06: Impact, SVF, assumed TCK frequency?
62809: 03/11/07: Re: Impact, SVF, assumed TCK frequency?
62966: 03/11/11: Re: Linux and FPGA compatibility
62968: 03/11/11: Re: Home grown CPU core legal?
63188: 03/11/17: Re: ISE5.2 on solaris, can't use promgen
63880: 03/12/07: NIOS: Running code from flash
63898: 03/12/08: Re: NIOS: Running code from flash
63911: 03/12/08: Re: NIOS: Running code from flash
63975: 03/12/10: Re: NIOS: Running code from flash
64316: 03/12/28: Re: Anyone has the AMD flash AM29LV800B verilog model?
64668: 04/01/11: Re: FLASH memory programming with Altera NIOS and same question for Xilinx
64738: 04/01/12: Re: Synthesis in VHDL vs. Verilog
64845: 04/01/15: Re: Altera NIOS cyclone edition development board problem
64918: 04/01/16: Re: What does nios-run do?
64988: 04/01/18: Re: Programming and debugging the Altera Cyclone family
65236: 04/01/22: Re: Non deterministic routing in Quartus 3.0 ?
65575: 04/02/02: Re: Differences between Xilinx ISE and Altera Quartus software
65925: 04/02/10: Re: Is nobody using c++ and/or plugs-lib? was Re: nios c++ and ethernet [may by ot?]
65926: 04/02/10: Re: Quartus II taking forever to compile
66979: 04/03/02: Re: Need to speed up Stratix compiles.
67007: 04/03/03: Re: Need to speed up Stratix compiles.
67012: 04/03/03: Re: Need to speed up Stratix compiles.
67016: 04/03/03: Re: Need to speed up Stratix compiles.
67018: 04/03/03: Re: Need to speed up Stratix compiles.
67021: 04/03/04: Re: Need to speed up Stratix compiles.
67041: 04/03/04: Re: Need to speed up Stratix compiles.
67071: 04/03/04: Re: Need to speed up Stratix compiles.
67092: 04/03/05: Re: Need to speed up Stratix compiles.
67317: 04/03/10: Re: LVDS
67669: 04/03/17: Re: Speed of Linux vs Solaris
67675: 04/03/17: Re: Speed of Linux vs Solaris
67958: 04/03/23: Re: Quartus with AMD64 processors?
67989: 04/03/24: Re: Quartus with AMD64 processors?
67992: 04/03/24: Re: Quartus with AMD64 processors?
68008: 04/03/24: Re: Quartus with AMD64 processors?
68049: 04/03/25: Re: Quartus with AMD64 processors?
68256: 04/03/31: Re: Athlon FX vs Pentium 4 benchmarks for xilinx's par
68312: 04/04/01: Re: Athlon FX vs Pentium 4 benchmarks for xilinx's par
68338: 04/04/01: Re: simulation time
68423: 04/04/04: Re: The Logic Behind License Renewal
68737: 04/04/16: Re: PCI Express specification.
68757: 04/04/16: Re: how to pass a date user code from Synplify to Quartus?
68789: 04/04/19: Re: PCI Express specification.
69136: 04/04/28: Re: Error in SoPC Builder
69162: 04/04/28: Re: Stupid question
69288: 04/05/05: Altera SoPC builder command line system generator
69315: 04/05/06: Re: Altera SoPC builder command line system generator
69319: 04/05/06: Re: bitgen progarm in ISE
69338: 04/05/07: Re: Mutiple Quartus Instances?
69459: 04/05/11: Re: Easypath question (was "Hard-tocopy" rant)
69460: 04/05/11: Re: EasyPath
69471: 04/05/11: Re: EasyPath
69534: 04/05/13: ISE 6.2i Synopsys Design Compiler libraries?
69564: 04/05/14: Re: program flash memory through JTAG on FPGA
69687: 04/05/18: Re: ISE 6.2i Synopsys Design Compiler libraries?
69777: 04/05/19: Re: NIOS Board Stratix Edition - FPGA won't configure
69833: 04/05/21: Re: program flash memory through JTAG on FPGA
69844: 04/05/21: Re: program flash memory through JTAG on FPGA
70014: 04/05/27: Re: What can I do if my chip can't meet timing?
70182: 04/06/08: Re: SOPC BUILDER - SOFTWARE GENERATION
70183: 04/06/08: Virtex-4 availability?
70733: 04/06/25: Re: Xilinx's interp on EDIF properties
70780: 04/06/28: GT10_PCI_EXPRESS_n
70817: 04/06/29: Re: GT10_PCI_EXPRESS_n
70924: 04/07/01: Re: *RANT* Ridiculous EDA software "user license agreements"?
71003: 04/07/05: NIOS generated code
71409: 04/07/17: Re: FPGA Development board with onboard Ethernet PHY
71422: 04/07/18: Re: Xilinx 6.2i ISE WebPACK running under wine?
72276: 04/08/13: NIOS SDRAM controller simulation
73004: 04/09/10: Re: EDIF generation from Verilog in ISE 6.2i
73012: 04/09/10: Re: Simple FPGA board
73105: 04/09/14: Re: EDIF generation from Verilog in ISE 6.2i
73352: 04/09/20: RocketIO simulation w ISE6.2iSP3 and VCS-7.1.1 under Linux
73806: 04/09/29: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
73490: 04/09/22: Generating SVF files from Quartus?
73491: 04/09/22: Re: RocketIO simulation w ISE6.2iSP3 and VCS-7.1.1 under Linux
73492: 04/09/22: Re: From whence the MAC on an Altera NIOS devel kit board?
73600: 04/09/24: Re: Problem with the SOPC-Builder from Altera
75047: 04/10/25: Re: Assembler for PicoBlaze in Perl
74117: 04/10/04: Re: MicroBlaze is no available as Open-Source!! (from independant 3rd party)
75402: 04/11/04: Number of FPGA users?
75410: 04/11/04: Re: Number of FPGA users?
75420: 04/11/05: Re: how to get SDF file from netlist
75839: 04/11/16: Re: Suggestion for Xilinx parallel port cable replacement.
75910: 04/11/18: Re: Suggestion for Xilinx parallel port cable replacement.
75985: 04/11/22: Re: Suggestion for Xilinx parallel port cable replacement.
76139: 04/11/25: Re: Programming flash connected to CPLD via JTAG
76853: 04/12/14: Re: Linking FPGAs with RocketIOs
79395: 05/02/18: RocketIO swift simulation under VCS
79579: 05/02/21: Re: Is Altera Cyclone a good choice ?
79595: 05/02/21: Re: Is Altera Cyclone a good choice ?
79790: 05/02/24: Re: Hardcopy Vs ASIC
79859: 05/02/25: Re: NiosII Vs MicroBlaze
80171: 05/03/02: Re: Is Altera Cyclone a good choice ?
80228: 05/03/02: Re: FPGA tool benchmarks on Linux systems
80231: 05/03/02: Re: FPGA tool benchmarks on Linux systems
80233: 05/03/02: Re: FPGA tool benchmarks on Linux systems
80234: 05/03/02: Re: Xilinx ISE history?
80235: 05/03/02: Re: RocketIO swift simulation under VCS
80443: 05/03/05: Re: spart 3 uart example
81481: 05/03/24: Re: Xilinx ISE 7.1 - Can this get any worse?
82800: 05/04/18: Re: combining two EDF netlist in ISE
82869: 05/04/19: Re: salary ballpark please guys
82877: 05/04/19: Re: salary ballpark please guys
82895: 05/04/19: Re: source control and Xilinx ISE 6 and 7
82945: 05/04/20: Re: source control and Xilinx ISE 6 and 7
82955: 05/04/20: Re: source control and Xilinx ISE 6 and 7
83022: 05/04/21: Re: Xilinx Impact in Linux 2.6.x
83215: 05/04/26: quartus_pgm under Linux?
83234: 05/04/26: MAX II UFM data specification and programming
83235: 05/04/26: Re: quartus_pgm under Linux?
83311: 05/04/27: Re: MAX II UFM data specification and programming
83322: 05/04/27: Re: MAX II UFM data specification and programming
83754: 05/05/06: Re: MAX II UFM data specification and programming
85514: 05/06/10: xmodem/kermit for edk/ppc
85663: 05/06/13: Re: xmodem/kermit for edk/ppc
88993: 05/09/02: Re: Embedded Processors/Serdes
89699: 05/09/22: Re: Reprogramming FPGA over PCI???
91789: 05/11/13: Re: Add files to Xilinx ISE Project w/script
92860: 05/12/08: Re: I2C controller chipset to interface with FPGA
93637: 05/12/27: Re: Microblaze in a EDK pcore
94110: 06/01/05: Re: Synplify Pro batch mode
94178: 06/01/07: Re: Programming Xilinx PowerPC
94353: 06/01/10: Re: FPGA configuration time for PCI identification ?
94355: 06/01/10: Altera MAX-II: User logic access to USERCODE_REGISTER?
94416: 06/01/11: Re: Altera MAX-II: User logic access to USERCODE_REGISTER?
94878: 06/01/18: Re: Altera MAX-II: User logic access to USERCODE_REGISTER?
94901: 06/01/19: Re: Altera MAX-II: User logic access to USERCODE_REGISTER?
96093: 06/01/30: Re: Remotely updating Altera FPGA configuration
96479: 06/02/04: Re: Quartus programmer problem
98374: 06/03/09: Re: for all those who believe in ASICs....
98644: 06/03/14: Re: Why does Xilinx hate version control?
98645: 06/03/14: Re: Why does Xilinx hate version control?
99344: 06/03/23: Re: regarding synopsys design anlyzer
99583: 06/03/27: Re: Altera web site inaccessible
99593: 06/03/27: Re: Altera web site inaccessible
99594: 06/03/27: Re: Altera IP address?
100046: 06/04/02: Re: JTAG programing specs for XC18V01 PROM
100284: 06/04/06: Re: JTAG programing specs for XC18V01 PROM
101361: 06/04/29: Re: Quartus and source control
101680: 06/05/04: Re: Quartus and source control
101746: 06/05/05: Re: Quartus and source control
102906: 06/05/23: Re: Urgent help programming SPI-flash trough JTAG (Spartan3E)
103240: 06/05/29: Re: ngdbuild:604 - storing netlists in other directories than the project dir
105633: 06/07/27: Re: Guided MAP/PAR in ISE
105981: 06/08/04: Re: RocketIO simulation in VCS
106675: 06/08/17: Re: Quartus and source control (continued)
106740: 06/08/18: Re: Quartus and source control (continued)
110593: 06/10/18: Re: EDIF netlist timing simulation
110608: 06/10/18: Re: EDIF netlist timing simulation
110621: 06/10/18: Re: Cheapest FPGA board to study VHDL on
110657: 06/10/19: Re: Cheapest FPGA board to study VHDL on
110659: 06/10/19: Re: Cheapest FPGA board to study VHDL on
112554: 06/11/24: Re: Verilog problem: default case to set signal xxxx
112606: 06/11/26: Re: Verilog problem: default case to set signal xxxx
112607: 06/11/26: Re: Verilog problem: default case to set signal xxxx
113196: 06/12/08: Re: Xilinx PAR crashing with 'make'
114330: 07/01/12: Re: EDIF generation from C
114426: 07/01/15: Re: EDIF format
114646: 07/01/22: Re: edif format
114683: 07/01/23: Re: edif format
116898: 07/03/20: Re: Programming XCF from MicroBlaze over JTAG???
116939: 07/03/21: Re: How to make use of two processors with Xilinx ISE (on Linux)
117818: 07/04/11: Re: Query in Parallel CRC(urgent)
117906: 07/04/13: Re: How do I use the Xilinx USB download cable for testing?
118035: 07/04/16: Re: dual port memory from single port RAM.
118042: 07/04/16: Re: License Key based on WLAN/Bluetooth MAC
118098: 07/04/17: Re: 80000 Bit Shift Register
118640: 07/05/01: Re: synthesis tools
120918: 07/06/20: Re: another Forth CPU design
121229: 07/06/28: Re: Bit error counter - how to make it faster
122211: 07/07/24: Re: VCD file doesn't show anything in GtkWave
122282: 07/07/25: Re: VCD file doesn't show anything in GtkWave
122328: 07/07/25: Re: Altera or Xilinx
122341: 07/07/26: Re: Altera or Xilinx
122364: 07/07/26: Re: Xilinx, converting ncd back to edif
122440: 07/07/27: Re: X values in ASIC
122553: 07/07/31: Re: Looking for PLD with embedded memory
124113: 07/09/12: Re: Command line quartus_pgm very slow
124183: 07/09/13: Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
124206: 07/09/14: Re: Xilinx ISP JTAG progaramming (XCF32P using GPIO from V4FX12)
125571: 07/10/29: Re: XMD with CableServer OR remote EDK solution
125998: 07/11/12: Re: Programming connection
126006: 07/11/12: Re: Programming connection
127353: 07/12/19: Emacs as GUI for NIOS-II
127522: 08/01/01: Re: Sparkfun FPGA board ?
130947: 08/04/06: Re: Spartan3 JTAG flash In System Programming over Ethernet
130999: 08/04/08: Re: Modify POF with new ESB (ROM) content?
131005: 08/04/08: Re: Modify POF with new ESB (ROM) content?
131014: 08/04/08: Re: Modify POF with new ESB (ROM) content?
131022: 08/04/08: Re: Modify POF with new ESB (ROM) content?
131040: 08/04/08: Re: Modify POF with new ESB (ROM) content?
131060: 08/04/09: Re: Modify POF with new ESB (ROM) content?
133231: 08/06/21: Re: which commercial HDL-Simulator for FPGA?
133267: 08/06/23: Re: which commercial HDL-Simulator for FPGA?
133299: 08/06/24: Re: which commercial HDL-Simulator for FPGA?
134828: 08/09/03: Quartus II priority 19 under Linux
134894: 08/09/05: Re: Quartus II priority 19 under Linux
135076: 08/09/13: Re: ASIC Prototyping
136252: 08/11/07: Re: Tilera multicore replaces FPGA?
137219: 09/01/04: Re: Altera - Create sof file with software inside.
137276: 09/01/07: Re: Which revision control do fpga designers use (2009)
137277: 09/01/07: Re: Which revision control do fpga designers use (2009)
138540: 09/02/26: Re: Configure FPGA via PCIe
138800: 09/03/11: Re: Checking HDL syntax on command line with xilinx tools
138994: 09/03/18: Re: Zero operand CPUs
139788: 09/04/14: Re: Low-cost Altera FPGA roadmap
139792: 09/04/14: Re: Low-cost Altera FPGA roadmap
139818: 09/04/15: Re: Low-cost Altera FPGA roadmap
140094: 09/04/28: Re: FPGA/DSP/Video Board
140100: 09/04/28: Re: FPGA/DSP/Video Board
140118: 09/04/29: Re: FPGA/DSP/Video Board
140137: 09/04/30: Re: ASIC from working FPGA design
140419: 09/05/13: Re: cheapest FPGA?
140459: 09/05/14: Re: cheapest FPGA?
140460: 09/05/14: Re: XCF32P programming via JTAG
140467: 09/05/14: Re: cheapest FPGA?
140828: 09/05/27: Re: Online tool that generates parallel CRC and Scrambler
140829: 09/05/27: Re: Online tool that generates parallel CRC and Scrambler
141095: 09/06/05: Re: Help with Remote debugging ideas.
141101: 09/06/05: Re: Help with Remote debugging ideas.
142074: 09/07/23: Re: FPGA development tools for FreeBSD?
142085: 09/07/24: Re: FPGA development tools for FreeBSD?
142086: 09/07/24: Re: FPGA development tools for FreeBSD?
142609: 09/08/20: Re: Wildcards in Quartus TCL Scripting
142614: 09/08/21: Re: Xilinx 3E design programs fine with 500E but fails with 250E
142773: 09/08/31: Re: program spartan3 under linux
142800: 09/09/02: Re: program spartan3 under linux
142847: 09/09/03: Re: Choice of Language for FPGA programming
143066: 09/09/18: Re: Quartus top level entity name vs names of generated files
143211: 09/09/25: Re: Super Small MIPS-compatible Altera-Based Soft Processor and compiler
143266: 09/09/29: Re: Searching for cost effective PCI express x1 core..
143929: 09/11/03: Re: 50+ pages fresh from Antti's brain
144017: 09/11/07: Re: Cyclone IV announced
144457: 09/12/09: Re: Cheapest way to get a chipscope compatible cable?
144488: 09/12/10: Re: Cheapest way to get a chipscope compatible cable?
144544: 09/12/14: Re: Cheapest way to get a chipscope compatible cable?
144764: 09/12/31: Re: Seeking some advice
144958: 10/01/17: Re: Altera Quartus II on Debian GNU/Linux
144959: 10/01/17: Re: SystemVerilog Verification Example using Quartus and ModelSim
144972: 10/01/18: Re: Altera Quartus II on Debian GNU/Linux
144975: 10/01/18: Re: Altera Quartus II on Debian GNU/Linux
145209: 10/02/01: Re: In system memory editor of Altera for Xilinx
145228: 10/02/02: Re: In system memory editor of Altera for Xilinx
145250: 10/02/03: Re: What is the most area efficient CRC method
145522: 10/02/13: Re: VHDL vs Verilog
145554: 10/02/14: Re: VHDL vs Verilog
145561: 10/02/14: Re: VHDL vs Verilog
145570: 10/02/14: Re: VHDL vs Verilog
145571: 10/02/14: Re: Can the Altera USB cable attach to a KVM XP VM?
145572: 10/02/14: Re: VHDL vs Verilog
145578: 10/02/14: Re: Can the Altera USB cable attach to a KVM XP VM?
145710: 10/02/20: Re: System design in FPGA
145711: 10/02/20: Re: System design in FPGA
145776: 10/02/23: Re: FPGA platform??
145791: 10/02/24: Re: data2mem and rodata/data (Xilinx)
145819: 10/02/25: Re: FPGA platform??
145862: 10/02/26: Re: FPGA platform??
146089: 10/03/05: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146218: 10/03/09: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146514: 10/03/21: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146528: 10/03/22: Quartus: rpm: Command not found.
146529: 10/03/22: Re: Modelsim PE vs. Aldec Active-HDL (PE)
146548: 10/03/22: Re: Quartus: rpm: Command not found.
146550: 10/03/22: Re: Finally, selling my old Xilinx/Viewlogic software package
146551: 10/03/22: Re: Why hardware designers should switch to Eclipse
146571: 10/03/23: Re: Why hardware designers should switch to Eclipse
146575: 10/03/23: Re: Why hardware designers should switch to Eclipse
146581: 10/03/23: Re: Why hardware designers should switch to Eclipse
147509: 10/04/29: Re: Quartus: rpm: Command not found.
147510: 10/04/29: Re: Why hardware designers should switch to Eclipse
147511: 10/04/29: Re: xilinx arm finally announced
147557: 10/05/02: Re: Cheap FPGAs for tutorial
147606: 10/05/06: Re: FPGA Compilation Time Windows vs Linux
147620: 10/05/08: Re: FPGA Compilation Time Windows vs Linux
147722: 10/05/19: Re: sensor-FPGA-DSP image processing
147724: 10/05/19: Re: sensor-FPGA-DSP image processing
147737: 10/05/20: Re: sensor-FPGA-DSP image processing
147851: 10/05/27: Re: crc16 with 16 bit inputs
149193: 10/10/06: Re: Driving a design via TCP/IP
149448: 10/10/26: Re: Ncvhdl Problem with simple logical operators
149546: 10/11/04: Achronix
149776: 10/11/24: Re: Synthesis/place and route with Solid-State Drives
149790: 10/11/24: Re: Synthesis/place and route with Solid-State Drives
149807: 10/11/24: Re: Synthesis/place and route with Solid-State Drives
149808: 10/11/24: Re: Atom 6000C perspective, anyone?
149820: 10/11/25: Re: Synthesis/place and route with Solid-State Drives
149848: 10/11/28: Re: EDIF netlist access in Xilinx ISE 8.1i
150118: 10/12/15: Re: ISIM simulation speed
150200: 10/12/31: Re: I Give Up!
150364: 11/01/12: Re: FPGA to PHY/MAC chip
150441: 11/01/21: Re: Verilog Book for VHDL Users
150541: 11/01/26: Re: how to read an image from the PC and store it in FPGA ROM
150713: 11/02/05: Re: Trivia: Where are you on the HDL Map?
150971: 11/02/25: Re: Simulating mutiplication of 'X' with '0'
150976: 11/02/25: Re: Simulating mutiplication of 'X' with '0'
151238: 11/03/17: Re: pcb&bitstream
152542: 11/09/09: Re: interfacing Xilinx platform usb jtag with other vendor devices
152936: 11/11/02: Xilinx USB II Cable driver under Gentoo Linux
152941: 11/11/03: Re: Xilinx USB II Cable driver under Gentoo Linux
152945: 11/11/03: Re: Xilinx USB II Cable driver under Gentoo Linux
153093: 11/11/29: Re: Compatible Xilinx USB Cables: worth to bother?
153096: 11/11/29: Re: Compatible Xilinx USB Cables: worth to bother?
153105: 11/12/01: Re: Compatible Xilinx USB Cables: worth to bother?
153275: 12/01/24: Re: Semi-OT: Good Tcl Book
153321: 12/01/31: Re: Design Notation VHDL or Verilog?
153341: 12/02/03: Re: Design Notation VHDL or Verilog?
153342: 12/02/03: Re: Design Notation VHDL or Verilog?
153344: 12/02/03: Re: Design Notation VHDL or Verilog?
153378: 12/02/12: Re: Design Notation VHDL or Verilog?
153380: 12/02/12: Re: Design Notation VHDL or Verilog?
154202: 12/09/07: Re: Verilog file operations
154991: 13/03/21: Re: Using Quartus II without GUI
155128: 13/04/24: Re: FPGA for large HDMI switch
155129: 13/04/24: Re: Inferring Xilinx BlockRAM FIFO
155840: 13/09/29: Re: VHDL syntheses timestamp
157120: 14/10/14: Non-project mode Vivado simulation?
157123: 14/10/14: Re: Non-project mode Vivado simulation?
157155: 14/10/19: Re: Need ideas for FYP
157200: 14/10/31: Re: XILINX PCIe read of slow device
157204: 14/11/04: Re: Quartus II TCL or Command line
157749: 15/02/28: Re: Program Xilinx with Altera JTAG Programmer?
158838: 16/04/28: Re: Challenges in data science which can be solved with FPGAs
159770: 17/02/26: Re: Intel (Altera) announces Cyclone-10
<petter@scimba.dolphinics.no>:
25811: 00/09/21: Alliance 3.1i CAE Libs install hangs under Solaris
25827: 00/09/22: Re: Alliance 3.1i CAE Libs install hangs under Solaris
25891: 00/09/25: Re: Alliance 3.1i CAE Libs install hangs under Solaris
pfaisalbe:
149221: 10/10/09: Pack:2309 - Too many bonded comps of type
PFC:
121060: 07/06/24: Re: EDK - Microblaze question
121062: 07/06/24: Desperate to find the right FPGA board
121133: 07/06/26: Re: Desperate to find the right FPGA board
121134: 07/06/26: Re: How to choose FPGA for a huge computation?
121135: 07/06/26: Re: DARNAW! - PGA Style FPGA Module
121509: 07/07/06: Re: Xilinx ISE, EDK and some ground roules in software development
121614: 07/07/10: Re: A Way for a DSP to tell an FPGA to load itself from Flash
121615: 07/07/10: Re: Interesting problems about high performance computing
121815: 07/07/13: Re: Counter ?
121825: 07/07/13: Re: Designing the right clock tree for a multi-FPGA setup
121826: 07/07/13: Newbie's first FPGA board !
121887: 07/07/14: Re: Newbie's first FPGA board !
121896: 07/07/14: Re: Newbie's first FPGA board !
121897: 07/07/14: Re: Newbie's first FPGA board !
121901: 07/07/15: Re: ESR Meter - design contest
121916: 07/07/15: Re: Newbie's first FPGA board !
121952: 07/07/16: Re: Newbie's first FPGA board !
121962: 07/07/16: Re: Newbie's first FPGA board !
121973: 07/07/16: Re: Newbie's first FPGA board !
122006: 07/07/17: Re: Newbie's first FPGA board !
122099: 07/07/19: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122133: 07/07/19: Re: DDR2 vs SDR on Spartan3
122141: 07/07/20: Re: DDR2 vs SDR on Spartan3
122151: 07/07/20: Re: Xilinx fpgas...
122163: 07/07/21: Re: Can multiple Ferrite Beads be used to connect ...?
122168: 07/07/21: Re: Can multiple Ferrite Beads be used to connect ...?
122175: 07/07/22: Re: Can multiple Ferrite Beads be used to connect ...?
122213: 07/07/24: Re: Connecting Bram LMB Controller to Microblaze
122216: 07/07/24: Re: Connecting Bram LMB Controller to Microblaze
122242: 07/07/24: Re: Connecting Bram LMB Controller to Microblaze
122285: 07/07/25: Re: Beginners question
122312: 07/07/25: Re: Beginners question
122345: 07/07/26: Re: Anyone know any good vhdl ethernet tutorials?
122388: 07/07/26: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122431: 07/07/27: Re: Xilinx XC3S400-4PQ208C pin name files?
122432: 07/07/27: Re: Xilinx XC3S400-4PQ208C pin name files?
122501: 07/07/29: Re: Best CPU platform(s) for FPGA synthesis
122599: 07/08/01: Re: DDR Simulation Model
122600: 07/08/01: Re: DDR Simulation Model
122791: 07/08/07: Re: SDR SDRAM controller for Xilinx Spartan-3E
122796: 07/08/07: Re: TEMAC Performance Issues with Virtex 4FX
122812: 07/08/07: Re: TEMAC Performance Issues with Virtex 4FX
122813: 07/08/07: Re: SDR SDRAM controller for Xilinx Spartan-3E
122815: 07/08/07: Re: TEMAC Performance Issues with Virtex 4FX
122902: 07/08/09: Re: secure interfacing between an fpga and a connected device
123438: 07/08/28: Re: tricking bitgen into creating rom-like behavior
127423: 07/12/23: Re: UK Supplier XILINX spartan 3 development board??
127424: 07/12/23: Re: FPGA pin swapping utility
127443: 07/12/25: Re: FPGA Project Support
128001: 08/01/12: Re: XAPP924 Doesnt work
128436: 08/01/25: Re: Thoughts about memory controller problems
128437: 08/01/25: Re: Virtex-4 driving a 5V CMOS
128634: 08/02/01: Re: I need a SDRAM controller
128781: 08/02/06: Re: Minimum Oscillator Frequency
129433: 08/02/23: Re: scanf problem in EDk 9.1i (Microbaze)
132259: 08/05/20: Re: Incorporating FPGAs on PCBs
132272: 08/05/20: Re: my Spartan-4 wishlist
132287: 08/05/20: Re: my Spartan-4 wishlist
132408: 08/05/26: Xilinx XCL woes
132411: 08/05/26: Re: Xilinx XCL woes
132641: 08/06/04: Re: Using ethernet on a Xilnx board (Help appreciated)
132645: 08/06/04: Xilinx vs Altera
132646: 08/06/04: Re: Xilinx Fifo Generator Direct Instantiation?
132647: 08/06/04: Re: Using ethernet on a Xilnx board (Help appreciated)
132649: 08/06/04: Re: Using ethernet on a Xilnx board (Help appreciated)
132655: 08/06/05: Re: Xilinx vs Altera
132675: 08/06/05: Re: Xilinx vs Altera
132679: 08/06/05: Re: Xilinx vs Altera
132709: 08/06/05: Re: Xilinx vs Altera
132736: 08/06/06: Re: Xilinx vs Altera
132763: 08/06/06: Re: Xilinx vs Altera
132772: 08/06/06: Re: JTAG + PROM error!
132773: 08/06/06: Re: Xilinx cuts 250 jobs.
132774: 08/06/06: Re: JTAG + PROM error!
132843: 08/06/09: Re: FPGA reprogrammable? (urgent)
132844: 08/06/09: Re: FPGA clock frequency
132846: 08/06/09: Re: NIOS-II+LAN91C111
132864: 08/06/09: Re: FPGA clock frequency
132867: 08/06/09: Re: SDRAM controller
132868: 08/06/09: Re: how to prevent timer code firmware running on Microblaze from being optimised
132885: 08/06/10: Re: how to prevent timer code firmware running on Microblaze from being optimised
132898: 08/06/10: Re: where is the IP address assigned to the fpga in Trimode Ethernet MAC Core???
132899: 08/06/10: Re: FPGA clock frequency
132971: 08/06/11: Re: Trouble programming V4FX40
132973: 08/06/11: Re: fpga reprogrammable?
132974: 08/06/11: Re: FPGA to solve the two most annoying problems on usenet - Suggestions Welcome
132975: 08/06/11: Re: Trouble programming V4FX40
132984: 08/06/12: Re: Trouble programming V4FX40
132986: 08/06/12: Re: Trouble programming V4FX40
133015: 08/06/14: Re: CPLD beginner questions
133032: 08/06/14: Re: CPLD beginner questions
133305: 08/06/24: Re: Image Sensor Interface.
133306: 08/06/24: Re: FPGA based database searching
133307: 08/06/24: Re: is lwIP absolutely necessary for tcp-ip?
133371: 08/06/26: Re: edk peripheral communication
133441: 08/06/30: Re: EDK DMA peripherals?
Pfna:
72571: 04/08/25: Re: Xilinx version ROM with automatic increment
pfor:
35051: 01/09/19: Re: configuration latency for PCI bridge in FPGA
35877: 01/10/22: Maser Serial Config Problem
pforyt:
33245: 01/07/20: Spartan XL Readback Problem
pfraser:
153385: 12/02/14: Anybody here got a Xilinx ML605?
153391: 12/02/15: Re: Anybody here got a Xilinx ML605?
153392: 12/02/15: Re: Anybody here got a Xilinx ML605?
153842: 12/06/01: Re: PRNG
153890: 12/06/22: Re: Data transfers between MicroBlaze and VHDL
154050: 12/07/22: Interface Xilinx KC705 to BeagleBone?
154056: 12/07/23: Re: Interface Xilinx KC705 to BeagleBone?
154057: 12/07/23: Re: Interface Xilinx KC705 to BeagleBone?
154064: 12/07/23: Re: Interface Xilinx KC705 to BeagleBone?
154065: 12/07/23: Re: Interface Xilinx KC705 to BeagleBone?
154464: 12/11/06: Re: help
156144: 13/12/10: Re: Interface Xilinx KC705 to BeagleBone?
<pfrinec@yahoo.co.uk>:
135717: 08/10/13: writing files to micro-SD with spartan 3e
135737: 08/10/14: Re: writing files to micro-SD with spartan 3e
135768: 08/10/15: Re: writing files to micro-SD with spartan 3e
136373: 08/11/13: Re: writing files to micro-SD with spartan 3e
137900: 09/02/02: microblaze bootloader problems
137915: 09/02/02: Re: microblaze bootloader problems
PG:
131955: 08/05/08: ML300 evaluation board broken?
PG Williams:
6421: 97/05/22: test
pg4100:
128037: 08/01/14: Debbuging a RISC processor on an FPGA
128050: 08/01/14: Re: Debbuging a RISC processor on an FPGA
128052: 08/01/14: Re: Debbuging a RISC processor on an FPGA
128098: 08/01/15: Re: Debbuging a RISC processor on an FPGA
128104: 08/01/15: Re: Debbuging a RISC processor on an FPGA
pgaMiramar Associates:
2989: 96/03/09: pga...Renters .... Buy a Home with No $$ Downpga
<pgreaves@my-dejanews.com>:
12677: 98/10/23: Re: Xilinx F1.5/FPGA Express wackiness (& Floorplanner)
PGS:
139350: 09/03/27: Using LVDS in Lattice ECP3
pgw:
122912: 07/08/10: DDR/DDR2 controller - core
122943: 07/08/11: Re: DDR/DDR2 controller - core
122953: 07/08/12: Re: DDR/DDR2 controller - core
122994: 07/08/13: Re: DDR/DDR2 controller - core
123179: 07/08/18: DDR controller - best device to perform
123183: 07/08/19: Re: DDR controller - best device to perform
123185: 07/08/19: Re: DDR controller - best device to perform
123225: 07/08/20: Re: DDR controller - best device to perform
123809: 07/09/05: Re: DDR controller - best device to perform
124858: 07/10/08: Cyclone II - PLL differential output
124868: 07/10/09: Re: Cyclone II - PLL differential output
124880: 07/10/09: DDR DIMM clock distribution
124978: 07/10/14: Altera devices connecting to DDR memory.
124980: 07/10/14: Re: Altera devices connecting to DDR memory.
124981: 07/10/14: Re: Altera devices connecting to DDR memory.
125210: 07/10/18: Re: Altera devices connecting to DDR memory.
PH:
78923: 05/02/10: Flash problem
phaeton:
108221: 06/09/06: Re: Please help me with (insert task here)
phanhuyich:
155246: 13/06/17: Ask about finding maximum and second's maximum number in array is given.
Phani Putrevu:
6419: 97/05/22: Any designs to avoid in FPGAs
PHD567:
7769: 97/10/14: $$$ NOW
Phichai Liangtong:
14104: 99/01/14: System reset
phil:
35683: 01/10/13: Re: Maxplus waveform simulations
35936: 01/10/24: handel-C
36747: 01/11/19: Re: How can I solve the "clock" warning of synplify.
40279: 02/03/04: Re: Altera FPGAs
51977: 03/01/28: Re: Switching clock ( Altera ACEX )
55876: 03/05/22: Re: Programming Altera EPC1 and EPC1441
70665: 04/06/23: Re: Asteroids Deluxe in an FPGA
111846: 06/11/11: Re: Graphics-2-FPGA
115378: 07/02/08: Re: Actel FIFO in Synplify: blackbox is missing a user supplied timing model
115444: 07/02/11: Re: Actel FIFO in Synplify: blackbox is missing a user supplied timing model
115446: 07/02/11: Re: query in P&R of FPGA
149698: 10/11/17: Does anyone have die sizes for Xilinx Virtex V devices
Phil:
33356: 01/07/24: Re: Register Chain
40265: 02/03/04: Re: Altera FPGAs
81803: 05/04/01: Re: Achieving required speed in Virtex-II Pro FPGA
106331: 06/08/11: Dio5 interface with ps2 port
106392: 06/08/12: Re: Dio5 interface with ps2 port
111690: 06/11/08: Graphics-2-FPGA
115023: 07/01/29: Change ROM contents, .bit file
123251: 07/08/21: System Generator Question: Flopping the inputs and outputs
123255: 07/08/21: Re: System Generator Question: Flopping the inputs and outputs
142713: 09/08/27: Re: Is free-to-use IP included with downloadable FPGA tools?
149099: 10/10/01: Flash Card Reader
154073: 12/07/29: Re: Spartan 6 IBERT confusion
Phil Allison:
150454: 11/01/23: Re: Xilinx news
150455: 11/01/23: Re: Xilinx news
150466: 11/01/24: Re: Xilinx news
150468: 11/01/24: Re: Xilinx news
Phil Carmody:
126691: 07/11/29: Re: lossless compression in hardware: what to do in case of uncompressibility?
126789: 07/12/02: Re: lossless compression in hardware: what to do in case of uncompressibility?
126809: 07/12/03: Re: lossless compression in hardware: what to do in case of uncompressibility?
Phil Chong:
1184: 95/05/12: Re: Overheating (was Re: Compression algo's for FPGA's)
Phil Cole:
20284: 00/02/03: Re: Renoir problem: several engineers sharing a common setup?
20319: 00/02/04: Re: Renoir problem: several engineers sharing a common setup?
Phil Connor:
38766: 02/01/24: Re: IDT7204 Using CoreGen
39607: 02/02/14: Re: Modelsim questions
40142: 02/02/28: Re: stuck in state in Spartan-II!
40445: 02/03/07: Re: high active and low active reset signal mixed in a design
40643: 02/03/12: Re: Mystery two wire interface, or am I being dense?
41288: 02/03/25: Re: Xilinx Async Fifo trouble
41601: 02/04/03: Re: Marquis of Queensbury Rules
41639: 02/04/04: Re: Marquis of Queensbury Rules
41701: 02/04/05: Re: Monostable multivibrator
41702: 02/04/05: Re: Schematic Stuff
42272: 02/04/19: ModelSim closes for unknown reason
42374: 02/04/22: Re: ModelSim closes for unknown reason
42611: 02/04/29: Re: Does Vertex II PRO Really work?
42650: 02/04/30: Re: Does Vertex II PRO Really work?
42945: 02/05/08: Re: State machine synthesis
43009: 02/05/09: Re: Opinions on FPGA cores - best for a commercial project?
43616: 02/05/27: Re: State machine synthesis
43633: 02/05/28: Re: State machine synthesis
46234: 02/08/22: Re: rising_edge detector?
48572: 02/10/21: Re: FIFO Simulation problem
48724: 02/10/23: Re: slow slew rate signal...
48778: 02/10/24: Re: slow slew rate signal...
49543: 02/11/14: Re: The "Do"s and "Don't"s of Synthesizing VHDL?
49690: 02/11/19: What combinational logic will produce a falling edge only.
49747: 02/11/20: Re: What combinational logic will produce a falling edge only.
49748: 02/11/20: Re: What combinational logic will produce a falling edge only.
49751: 02/11/20: Re: What combinational logic will produce a falling edge only.
49752: 02/11/20: Re: What combinational logic will produce a falling edge only.
49790: 02/11/21: Re: What combinational logic will produce a falling edge only.
49857: 02/11/22: Re: What combinational logic will produce a falling edge only.
Phil Cook:
10253: 98/05/07: Low power FPGA design
Phil Curry:
39498: 02/02/11: student F2.1i printing problem
Phil Emmup:
152312: 11/08/07: Re: FPGA
152314: 11/08/07: Re: RS232
152386: 11/08/17: Re: Altera Flex10K support ?
Phil Endecott:
19989: 00/01/21: Re: Indexing functions
20019: 00/01/24: Xilinx programming from a Linux PC
20192: 00/01/31: Re: Xilinx programming from a Linux PC
20348: 00/02/07: Linux Xilinx Download program
22350: 00/05/05: Re: edif
22351: 00/05/05: Re: edif
22396: 00/05/08: Re: Virtex clock buffers
22406: 00/05/08: Re: Virtex clock buffers
22429: 00/05/09: Re: Xilinx Block Select Ram+ and LeonardoSpectrum
23318: 00/06/22: Xilinx PAR & Tristate busses
23515: 00/06/28: Re: How to speed it up? :-)
23620: 00/07/03: Re: How can I search this newsgroup archive?
Phil Everett:
153109: 11/12/02: Re: Is it possible to save the FPGA state periodically?
Phil Hays:
9827: 98/04/08: Xilinx placement and floorplanning was: Xilinx routing optimization?
10731: 98/06/12: Re: Fastest and biggest FPGA fast and big enough?
10803: 98/06/21: Re: Control skew due to routing in Xilinx M1
11244: 98/07/29: Re: TRISTATE in FPGA
11755: 98/09/07: Re: 22V10 programming
11779: 98/09/08: Re: 22V10 programming
12031: 98/09/24: Re: FPGA information
12059: 98/09/25: Re: FPGA information -- maybe
12227: 98/10/05: Re: Power estimation of XILINX XV series
12584: 98/10/18: Re: ABEL vs. VHDL
13047: 98/11/12: Re: placement&routing problems
13684: 98/12/17: Re: Problem with clock IOB placement
14291: 99/01/23: Re: PLL in FPGA
14453: 99/01/29: Re: Ratings for Synplicity Synplify
14469: 99/01/31: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14470: 99/01/31: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14476: 99/01/31: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14605: 99/02/05: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14606: 99/02/05: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14678: 99/02/10: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
14734: 99/02/13: Re: Benchmarks: Schematic vs Synthesis (Exemplar vs Synplicity)
16295: 99/05/13: Re: Spartan Metastability parameters
16506: 99/05/25: Re: Virtex based PCI cards
16275: 99/05/12: Re: How synthesize tools concern with size of the design?
16533: 99/05/26: Re: FPGA express : Schematic viewing options w/o Vista?
17194: 99/07/07: Re: Tristate Register in Xilinx 4000XLA IO block
17569: 99/08/10: Re: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
17625: 99/08/15: Re: Best synthesis tools for virtex?
17668: 99/08/22: Re: synthesis comparion between Synplify and FPGA express
17682: 99/08/23: Re: synthesis comparion between Synplify and FPGA express
17740: 99/08/27: Re: Feasibility of 200 MHz, 12K design on FPGA
17760: 99/08/31: Re: Feasibility of 200 MHz, 12K design on FPGA
17782: 99/09/02: Re: Feasibility of 200 MHz, 12K design on FPGA
17785: 99/09/02: FreeDES and Free6502 Comments
17795: 99/09/04: Re: FreeDES and Free6502 Comments
17796: 99/09/04: Re: FreeDES and Free6502 Comments
18253: 99/10/10: Re: DLL and programmable delay in Xilinx FPGA
18560: 99/10/31: Re: Xilinx TPSYNC constraint
18977: 99/11/22: Re: VHDL vs. schematic entry
18978: 99/11/22: Re: VHDL vs. schematic entry
19445: 99/12/21: Re: M1 timings
19566: 99/12/31: Re: Design security
19781: 00/01/11: Assignment of pins for thousand+ pin packages
20001: 00/01/21: Re: Assignment of pins for thousand+ pin packages
20957: 00/02/29: Re: Delay Lines using FPGA ??
21015: 00/03/02: Re: SpartanXL route and place
21105: 00/03/06: Re: SpartanXL route and place
21138: 00/03/07: Re: SpartanXL route and place
21202: 00/03/09: Re: SpartanXL route & place, Corrected
23092: 00/06/13: Re: FS: FpgaGuru.com DOMAIN
23405: 00/06/23: Re: What tools do people use for Xilinx FPGAs?
23428: 00/06/24: Re: What tools do people use for Xilinx FPGAs?
23607: 00/07/02: Re: BIST in FPGAs?
23655: 00/07/04: Re: BIST in FPGAs?
24405: 00/08/06: Re: Crossing Clock Domains. (Hey Peter Alfke!)
24494: 00/08/10: Re: Further FPGA metastability questions
24836: 00/08/19: Re: Permanently programming FPGAs
24838: 00/08/19: Re: Further FPGA metastability questions
25192: 00/08/29: Re: Large amout of Interconnect between FPGAs
25447: 00/09/11: Re: How do I mix vhdl and verilog source files in Synplify?
25557: 00/09/13: Re: How do I mix vhdl and verilog source files in Synplify?
25656: 00/09/16: Re: FPGA Express Strikes Again!
25658: 00/09/16: Re: FPGA Express Strikes Again!
26076: 00/10/02: Amplify experience, was: FPGA Express strikes again! Xilinx response
26097: 00/10/03: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26101: 00/10/03: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26217: 00/10/08: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26293: 00/10/10: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26331: 00/10/11: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26332: 00/10/11: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26482: 00/10/17: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26522: 00/10/18: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
26848: 00/10/31: Re: High fan out CE signal.
26908: 00/11/02: Re: Need a PCB speaker driven by XCV100
27225: 00/11/15: Re: Problem with Endianess in Xilinx Tools.
27482: 00/11/23: Re: Clock Skew : Does Xilinx know what they're doing?
27898: 00/12/13: Re: Synplify PRO 6.1 + Foundation 3.1i
28132: 00/12/21: Re: Synplicity and multiple input IOB flops...how to specify which one
28843: 01/01/26: Re: VirtexII and high speed counter
28846: 01/01/26: Re: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
29180: 01/02/09: Re: on making it too convenient to download PDFs
29223: 01/02/10: Re: Wired-or on Virtex FPGAs
29242: 01/02/10: Re: Wired-or on Virtex FPGAs
29409: 01/02/20: Re: meeting high hold time input requirement with Virtex
29830: 01/03/13: Re: VirtexE LVPECL I/O Ports? experience?
29855: 01/03/14: Re: Low volume production was VirtexE LVPECL I/O Ports? experience?
30096: 01/03/23: Re: Looking for Processor Core info/advice
30198: 01/03/28: Pinout tables
30227: 01/03/29: Re: Pinout tables
30420: 01/04/07: Re: Pinout tables
30781: 01/04/28: Re: BlockRAM outputs and the Placer
30782: 01/04/28: Re: C++ To Gates
31121: 01/05/12: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31130: 01/05/12: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31132: 01/05/12: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31142: 01/05/13: Re: Finally, an FPGA tool chain for Linux (Altera Quartus II)
31740: 01/06/05: Re: one state machine
32216: 01/06/20: XPower
32569: 01/06/30: Re: Newbee and FAQ
32646: 01/07/04: Re: Are these typical VirtexE timing values?
32817: 01/07/10: Re: Simulation problems with BlockRAM's INIT values !
33288: 01/07/22: Re: Measuring power consumption
33304: 01/07/23: Re: Measuring power consumption
33420: 01/07/26: Re: prospects for tiny FPGA supercomputer?
33726: 01/08/03: Re: Alliance tools going away?
34175: 01/08/16: Re: Replication of FFs in Xilinx XC4000
34234: 01/08/17: Re: Replication of FFs in Xilinx XC4000
34425: 01/08/24: Re: Slowing PCI for FPGA
34451: 01/08/25: Re: Slowing PCI for FPGA
34461: 01/08/26: Re: Slowing PCI for FPGA
34494: 01/08/28: Re: Slowing PCI for FPGA
34535: 01/08/29: Re: Slowing PCI for FPGA
34717: 01/09/05: Re: Segmented interconnects
35348: 01/09/30: Re: Virtex II current consumption
35349: 01/09/30: Re: Xilinx 4.1 software
37480: 01/12/12: Re: What do you like/dislike about place and route tools?
37481: 01/12/12: Re: What do you like/dislike about place and route tools?
37626: 01/12/18: Re: Xilinx ChipScope - experiences ?
37833: 01/12/21: Re: How can I reduce Spartan-II routing delays to meet 33MHz PCI's Tsu < 7 ns requirement?
38110: 02/01/05: Re: full custom design
39456: 02/02/10: Re: Xilinx synthesis tools
39702: 02/02/16: Handel-C, System-C, Formal verification ???
39742: 02/02/18: Re: Power estimation for Virtex-2 device
39803: 02/02/20: Re: Faster designs
39914: 02/02/22: Re: Handel-C, System-C, Formal verification ???
39915: 02/02/22: Re: Handel-C, System-C, Formal verification ???
39919: 02/02/22: Re: Handel-C, System-C, Formal verification ???
39920: 02/02/22: Re: Handel-C, System-C, Formal verification ???
40137: 02/02/28: Re: stuck in state in Spartan-II!
40218: 02/03/02: Re: stuck in state in Spartan-II!
40619: 02/03/12: Re: Article in March Embedded Systems - "The Death of Hardware
41384: 02/03/27: Re: Handel-C useless.. Move to SystemC
41687: 02/04/05: Re: hand placement
41977: 02/04/12: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
42040: 02/04/13: Re: new to fpga's need insight
42065: 02/04/15: Re: "free" tools ... ?
42103: 02/04/16: Re: OT? - Comments on "The Death of Hardware Engineering"
42327: 02/04/20: Re: logic does not work at higher frequency
42330: 02/04/20: Re: Xilinx Easypath- Selling parts with known defects
43035: 02/05/10: Re: Have you designed a PCI/Ethernet Adapter using a HDL?
43106: 02/05/14: Re: Architecture for high-level reconfigurable computing
43234: 02/05/17: HardPath
43299: 02/05/18: Re: HardPath
43311: 02/05/18: Re: HardPath
43345: 02/05/20: Re: HardPath
43473: 02/05/22: Re: P&R times
43477: 02/05/22: Re: HardPath
43531: 02/05/23: Re: P&R times
44009: 02/06/09: Re: OFFSET timing contraints
44012: 02/06/10: Re: Do you know a e-mail list where I can make questions about Handel-C?
44533: 02/06/22: Re: Bad Virtex2 devices - any similar experiences
45364: 02/07/20: Re: spiral / waterfall /watersluice : Which are your methods?
46759: 02/09/07: Re: Metastability numbers
47112: 02/09/18: Re: Has ISE 5.1i shipped?
47394: 02/09/25: Re: Altera Cyclone low-cost FPGA chips?
47850: 02/10/05: Re: TCP/IP in FPGA
47874: 02/10/06: Re: C\C++ to VHDL Converter
47929: 02/10/08: Re: C\C++ to VHDL Converter
48474: 02/10/18: Re: Locating IOBs with shared routing resources in VirtexII.
48495: 02/10/18: Re: Locating IOBs with shared routing resources in VirtexII.
49202: 02/11/05: Re: C\C++ to VHDL Converter
49316: 02/11/09: Re: BUFT bus contention
49318: 02/11/09: Re: External memory or on-chip?
49320: 02/11/09: Re: functional test for Xilinx virtex II Pro
49335: 02/11/09: Re: new to fpga, what language is better to start with
49401: 02/11/12: Re: C\C++ to VHDL Converter
49412: 02/11/12: Re: new to fpga, what language is better to start with
49474: 02/11/13: Re: new to fpga, what language is better to start with
49476: 02/11/13: Re: C\C++ to VHDL Converter
49675: 02/11/19: Re: Metastability in FPGAs
50400: 02/12/10: Re: How to assign pins in VHDL?
50574: 02/12/13: Re: Suggestions required for Handel-C code
50812: 02/12/20: Re: stupid rookie timing question
50877: 02/12/21: Re: stupid rookie timing question
50878: 02/12/21: Re: How to handle Fautly Interconnection in Virtex ?
51166: 03/01/04: Re: How can you tell if your clock signals are on the clock net?
51502: 03/01/15: Re: SChematic design approach compared to VHDL entry approach
51908: 03/01/25: Re: Why so many pins?
53870: 03/03/26: Re: Microblaze:Timing constraints
54003: 03/03/31: Re: $4000 FPGAs
54250: 03/04/05: Re: gated clock
54452: 03/04/11: PCI-X and LARGE base address register with X86 compact PCI
54474: 03/04/11: Re: Xilinx IOB flip flop mapping
54900: 03/04/21: Re: PCI-X and LARGE base address register with X86 compact PCI
55858: 03/05/22: Re: FPGA design: firmware or hardware?
57243: 03/06/26: Re: Xilinx Webpack bugs bugs bugs
57518: 03/07/02: Re: memory
57971: 03/07/11: Re: memory
58102: 03/07/15: Re: memory
58838: 03/08/02: Re: Problem in Xilinx (Freq Counter) design
59148: 03/08/10: Re: FPGA for a Newcomer
59541: 03/08/21: Re: performance tweaking FPGA designs
59545: 03/08/21: Re: performance tweaking FPGA designs
59673: 03/08/26: Re: Thinking out loud about metastability
59681: 03/08/26: Re: Enhancing PAR with FPGA floorplanners
60185: 03/09/07: Re: CMOS camera w/ USB2 -- crazy?
62166: 03/10/21: Re: Should I worry about metastability
62741: 03/11/06: Re: Programmer's unpaid overtime.
62825: 03/11/08: Re: FPGAs and DRAM bandwidth
63121: 03/11/15: Re: Newbie Question about Block Ram & Xilinx ECS
63719: 03/12/02: Re: Exact Timing Constraints vs. Over-Constraining
63749: 03/12/03: Re: Exact Timing Constraints vs. Over-Constraining
65119: 04/01/21: Re: Why doesn't NGDBuild recognize some UCF formatting?
68002: 04/03/24: Re: study verilog or vhdl?
68124: 04/03/27: Re: study verilog or vhdl?
69013: 04/04/25: Re: Newbie question: which choice is right for my engineering project?
69484: 04/05/12: Re: Easypath question (was "Hard-tocopy" rant)
69838: 04/05/21: Re: XIlinx V2P7: DCM won't lock
70240: 04/06/10: Xilinx Co-Founder Bernard 'Bernie' Vonderschmitt Passes Away
70257: 04/06/10: Re: Virtex4: I don't understand their thinking....
70273: 04/06/11: Re: tri-state in altera and xilinx
70560: 04/06/21: Re: XST: Inferring dual-port RAM from VHDL with BlockRAM
71010: 04/07/05: Re: [Xilinx 2VP] DDR + Differential Input
71046: 04/07/06: Re: [Xilinx 2VP] DDR + Differential Input
71077: 04/07/07: Re: FSM in illegal state
71087: 04/07/07: Re: FSM in illegal state
71211: 04/07/12: DCM / DLL issues was: FSM in illegal state
72873: 04/09/07: Re: I NEED HELP / MENTOR
72912: 04/09/08: Re: I NEED HELP / MENTOR
76639: 04/12/08: Re: "Hello World" project for an FPGA (on a Spartan3 board)
77399: 05/01/05: Re: Utilisation of Xilinx FPGAs
77523: 05/01/09: Re: a general question
78006: 05/01/22: Re: Poblem with Xilinx ISE
78539: 05/02/02: Re: Synchronizing multibit bus
79516: 05/02/20: Re: hdl:lament
80253: 05/03/02: EDK evaluation version with Spartan 3 board arrived today
80259: 05/03/02: Re: EDK evaluation version with Spartan 3 board arrived today
81536: 05/03/26: Re: cheap Xilinx tricks
82886: 05/04/19: Re: source control and Xilinx ISE 6 and 7
84211: 05/05/14: Re: floorplanning
84228: 05/05/15: Re: floorplanning
84360: 05/05/17: Re: About back annotated simulations...
84511: 05/05/19: Re: About back annotated simulations...
86362: 05/06/26: Re: Module integration, odd state machine behaviour (verilog), etc!
86705: 05/07/04: Re: ModelSim Timing Simulation Signal Names
86750: 05/07/05: Re: ModelSim Timing Simulation Signal Names
87386: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87513: 05/07/25: Re: Excalibur full strip simulation on solaris.
87520: 05/07/25: Re: Excalibur full strip simulation on solaris.
88015: 05/08/05: Re: Xilinx Best Source for Reset
89264: 05/09/09: Re: Post synthesis simulation errors
89314: 05/09/12: Re: place and route
89315: 05/09/12: Re: Post synthesis simulation errors
89362: 05/09/13: Re: 24 Counters on one board
89717: 05/09/23: Re: Synchronizer Flip Flop / Metastability
89836: 05/09/27: Re: Sythesis software for Virtex-4
89881: 05/09/28: Re: newbie questions: Xilinx vs. Altera tools and parts
90043: 05/10/03: Re: going backwards, Xilinx ISE 7.1 to ISE 6.3
90158: 05/10/05: Re: Avoiding meta stability?
90191: 05/10/06: Re: Avoiding meta stability? No where in this thread...
90340: 05/10/10: Re: Eliminates meta stability (yes or no)?
90423: 05/10/12: Re: Avoiding meta stability?
90427: 05/10/12: Re: Avoiding meta stability?
90583: 05/10/17: Re: ADC implementation on fpga? Information and procudures wanted.
90889: 05/10/24: Re: a few questions
90903: 05/10/24: Re: a few questions
90933: 05/10/25: Re: a few questions
91040: 05/10/27: Re: locking hdl to a particular fpga
91620: 05/11/09: Re: In Xilinx, how do I delay a signal by a fraction of a clock cycle?
91778: 05/11/12: Re: Add files to Xilinx ISE Project w/script
91802: 05/11/13: Re: Add files to Xilinx ISE Project w/script
92140: 05/11/22: Re: Stupid reset question
92209: 05/11/23: Re: Stupid reset question
92373: 05/11/28: Re: Stupid reset question
92450: 05/11/29: Re: Stupid reset question
92922: 05/12/09: Re: ISE 8.1 release delayed?
93431: 05/12/21: Re: Place and Route Algorithms: where's the fat?
93722: 05/12/28: Re: Going insane - Xilinx VGA controller...
94275: 06/01/09: Re: "failed to create empty document"
96383: 06/02/02: Re: Microblaze question
96417: 06/02/03: Re: BGA central ground matrix
96422: 06/02/03: Re: BGA central ground matrix
96425: 06/02/03: Re: BGA central ground matrix
97237: 06/02/19: Re: FPGA - software or hardware?
97607: 06/02/24: Re: implement IP TCP Layer in FPGA
98153: 06/03/06: Re: Par error in Spartan-3
98638: 06/03/13: Re: Why does Xilinx hate version control?
98639: 06/03/13: Re: Coregen in ISE 8.1i webpack not working quite right
98775: 06/03/16: Re: for all those who believe in ASICs....
98879: 06/03/17: Re: for all those who believe in ASICs....
98921: 06/03/17: Re: for all those who believe in ASICs....
99197: 06/03/21: Re: for all those who believe in ASICs....
99205: 06/03/21: Re: for all those who believe in ASICs....
100000: 06/03/31: Re: deglitching a clock
101397: 06/04/30: Re: Book Software for XC3190A?
102215: 06/05/11: Re: Synplify - Not satisfactory results with re-timing option
102271: 06/05/13: Re: Synplify - Not satisfactory results with re-timing option
102272: 06/05/13: Re: How to check IOB register packing?
102331: 06/05/15: Re: How to decide Setup/Hold time values ?
103076: 06/05/25: Re: Metastability question (newbie)
103252: 06/05/29: Re: Remote Application delivery for EDA
104163: 06/06/20: Re: FSM State Minimization on FPGAs
104342: 06/06/24: Re: newbie wants to do VHDL on an FPGA
104660: 06/07/03: Re: Chaos in FF metastability
104665: 06/07/03: Re: stable reset in fpga
104683: 06/07/03: Re: Chaos in FF metastability
104696: 06/07/04: Re: stable reset in fpga
104829: 06/07/06: Re: Chaos in FF metastability
104920: 06/07/09: Re: Chaos in FF metastability
106040: 06/08/06: Re: verilog versus vhdl
106194: 06/08/08: Re: 100 Mbit manchester coded signal in FPGA
phil hays:
134264: 08/08/02: Re: Is there a totally command-line driven way to use Xilinx
137251: 09/01/06: Re: Xilinx Timing Constraint Woes
137757: 09/01/29: Re: Spartan-6
138945: 09/03/16: Re: Send data from FPGA to PC via USB
140476: 09/05/14: Re: EMACS VHDL mode: how to rescan project so that makefile
140668: 09/05/21: Re: Can we expect ISE Gui and makefile to produce identical bit
140897: 09/05/29: Re: Can we expect ISE Gui and makefile to produce identical bit
140989: 09/06/01: Re: Has anyone tried to install a Xilinx floating license? The
143073: 09/09/18: Re: FPGA for acoustic adaptive beamforming
143080: 09/09/18: Re: FPGA for acoustic adaptive beamforming
143089: 09/09/19: Re: FPGA for acoustic adaptive beamforming
143116: 09/09/22: Re: To Xilinx: Regarding the download manager
150692: 11/02/04: Re: Trivia: Where are you on the HDL Map?
Phil Hobbs:
155768: 13/08/29: Re: FPGA temperature measurement
155771: 13/08/29: Re: FPGA temperature measurement
155773: 13/08/29: Re: FPGA temperature measurement
156077: 13/11/22: Re: microZed adventures
156455: 14/04/08: Re: on-chip bypass caps
156460: 14/04/08: Re: on-chip bypass caps
156495: 14/04/10: Re: on-chip bypass caps
Phil James-Roxby:
25333: 00/09/06: Re: XC3000A Configuration data
25347: 00/09/07: Re: XC3000A Configuration data
25713: 00/09/18: Re: MAX PLUS 2
25792: 00/09/20: Re: VHDL to SCHEMATIC
25946: 00/09/27: Re: hdl
26144: 00/10/05: Re: Xilinx BoardScope
26373: 00/10/13: Re: const coeff multiplier w/ LUTs
26855: 00/11/01: Re: JBits
26900: 00/11/02: Re: OT: Xilinx T-Shirt
27162: 00/11/13: Re: LUT and EDIF
27163: 00/11/13: Re: XC4000 maps better than Spartan2
27191: 00/11/14: Re: LUT and EDIF
27673: 00/12/01: Re: Virtex ROM ques.
27705: 00/12/04: Re: Virtex ROM ques.
27702: 00/12/04: Re: Xess - XS40-005XL question
27703: 00/12/04: Re: Wide AND function.
27732: 00/12/05: Re: Wide AND function.
27797: 00/12/08: Re: Need help regarding Partial reconfiguration
28190: 00/12/27: Re: evolving bitstreams
28200: 00/12/28: Re: Question about programming xcv100
28243: 01/01/03: Re: Partial reconfiguration using jbits
28650: 01/01/19: Re: FPGAs with a partial reconfiguration
28945: 01/01/30: Re: Advice on FPGA board.
29486: 01/02/23: Re: programmable coefficient fir filter?
29487: 01/02/23: Re: Partial reconfig
29723: 01/03/06: Re: Virtex partial reconfig...
29849: 01/03/13: Re: JBits drivers for XESS boards
31761: 01/06/05: Re: Xilinx Configuration Bitstream
32539: 01/06/29: Re: Is the Grass Greener for an Engineer in the USA?
33760: 01/08/03: Re: 4 (8) bit Microporcessor Implementation
35796: 01/10/17: Re: pci-card with Virtex2?
37013: 01/11/28: CALL FOR PAPERS - RTC 2002
38315: 02/01/11: Re: Avoid routing through a certain area (Xilinx)
38430: 02/01/14: Re: Avoid routing through a certain area (Xilinx)
42088: 02/04/15: Re: new to fpga's need insight
46109: 02/08/19: Re: onboard reconfiguration of Xilinx FPGA
46733: 02/09/06: Re: Virtex-II bit-file and strange configuration command
71497: 04/07/20: Re: FPGA in a Compact Flash format.
99280: 06/03/22: Re: How to get eps file from XST RTL viewer for LATEX
107495: 06/08/29: Re: FPGA -> SATA?
Phil Jessop:
140948: 09/05/30: Re: time constraining asynchronous fifo
141021: 09/06/02: Re: Xilinx GbE performance
141282: 09/06/15: Re: bidirectional buffer
141324: 09/06/18: Re: Preselection counter in verilog
141360: 09/06/20: Re: Preselection counter in verilog (Verilog Version)
141832: 09/07/11: Re: What is Clock Input? (Proofread)
142745: 09/08/30: Re: low power FPGA
142767: 09/08/31: Re: Virtex 5 HDMI
142900: 09/09/07: Re: Choice of Language for FPGA programming
142973: 09/09/11: Re: Behavior of crystal oscillator?
143520: 09/10/14: Re: Power consumption of FF
145834: 10/02/25: Re: Altera data sheets.
146768: 10/03/28: Re: Maximum output rate
147573: 10/05/04: Re: FIFO Depth Calculation
148022: 10/06/14: Re: Altera Quartus - how to create small roms & rams for Cyclone 3
150205: 10/12/31: Re: Verilog inout, I2C
150849: 11/02/16: Re: Regarding passing a control signal from fast to slow cloak domain
150850: 11/02/16: Re: Regarding passing a control signal from fast to slow cloak domain
151291: 11/03/21: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
151481: 11/04/12: Re: Source of Dynamic Power Consumption in FPGAs
151511: 11/04/16: Re: Oscilloscope recommendations Ghz range?
151513: 11/04/16: Re: Oscilloscope recommendations Ghz range?
151520: 11/04/16: Re: Oscilloscope recommendations Ghz range?
Phil Layton:
233: 94/09/29: Re: XC1765DPD8C
3111: 96/04/04: Re: Does X-BLOX Work?
Phil Logan:
23211: 00/06/17: PCI for a fpga board
Phil Martel:
76138: 04/11/25: Re: how to evaluate the needed number of gate?
Phil Martin:
27529: 00/11/27: Re: Synthesis & Routing speed
27655: 00/12/01: Re: Synthesis & Routing speed
30209: 01/03/28: P4 vs Athlon
Phil Moore:
70604: 04/06/21: New: read/write to D2SB fpga
70605: 04/06/21: Exponential Function
70606: 04/06/21: Neural Network on fpga
70650: 04/06/22: Re: New: read/write to D2SB fpga
Phil Ngai:
19: 94/07/28: definition of FPGA
65: 94/08/08: Re: How pricey is FPGA development?
300: 94/10/15: in circuit programming, was Re: PALASM versions?
310: 94/10/18: Re: in circuit programming, was Re: PALASM versions?
353: 94/10/27: linear feedback shift registers
745: 95/02/22: Re: PLA? PAL? PLD? GAL?
752: 95/02/23: Re: PLA? PAL? PLD? GAL?
935: 95/03/31: Re: Excuse me while I vent about Data I/O & Abel...
960: 95/04/04: pinout changes
972: 95/04/05: Re: Excuse me while I vent about Data I/O & Abel...
980: 95/04/06: Re: AT&T Statement ref Neocad
985: 95/04/07: Re: Excuse me while I vent about Data I/O & Abel...
1090: 95/04/26: Re: Lattice low-cost start kit
1133: 95/05/03: Re: Lattice EPLDs
1136: 95/05/04: Re: Lattice EPLDs
1284: 95/05/26: Re: CUPL manual/info
1400: 95/06/15: Re: Any one working on Cypress PLD's ?
3237: 96/05/01: Re: Synario Universal FPGA Design System
5859: 97/03/20: Re: VHDL & ABEL synthesis tools on 95/NT
Phil Ptkwt Kristin:
7322: 97/08/26: Re: ANNOUNCE: VHDL Synthesis for $495
9198: 98/03/01: Re: The case for Linux and EDA
9260: 98/03/04: Re: The case for Linux and EDA
9323: 98/03/06: Re: The case for free operating systems and EDA
9364: 98/03/07: Re: The case for Linux and EDA
9383: 98/03/08: Re: The case for Linux and EDA
10246: 98/05/06: Re: Xilinx Foundation and Linux
10247: 98/05/06: Re: Xilinx Foundation and Linux
10292: 98/05/10: Re: Xilinx Foundation and Linux
Phil Roberts:
3509: 96/06/11: Re: Double Port Ram - Xact Libs
Phil Sailer:
2500: 95/12/19: Re: Floor Planning for Xilinx
2573: 96/01/04: Re: What does VHDL stand for?
2774: 96/02/05: Re: help ! pci-interface
3110: 96/04/03: Re: PCI Support...
Phil Short:
6494: 97/05/28: Re: Glitches in timing simulation of Xilinx FPGAs with Synopsys
6648: 97/06/09: Re: XC6200 Gate Count
6788: 97/06/27: Re: Are Xilinx 4000XL I/O's truly 5V tolerant?
14560: 99/02/04: Re: Off topic DRAM/SIMM question....
16290: 99/05/13: Re: Fancy Dram problem
16312: 99/05/15: Re: Fancy Dram problem
28503: 01/01/15: Re: CRC - from long division to XOR, how?
28591: 01/01/17: Re: CRC - from long division to XOR, how?
35686: 01/10/13: FPGA Asynchronous Design
35695: 01/10/14: Re: FPGA Asynchronous Design
74945: 04/10/22: Re: unstable fpga design
75239: 04/10/30: Re: Low-power FPGAs?
75242: 04/10/30: Re: Low-power FPGAs?
75260: 04/10/31: Re: Low-power FPGAs?
75262: 04/10/31: Re: Low-power FPGAs?
75265: 04/10/31: Re: Low-power FPGAs?
75278: 04/11/01: Re: Low-power FPGAs?
81545: 05/03/27: Re: Multi-FPGA PCB data aggregation?
Phil Tomson:
47707: 02/10/02: Re: ANN: Embedded processor for Tcl language
47866: 02/10/06: Re: ANN: Embedded processor for Tcl language
47883: 02/10/07: Re: ANN: Embedded processor for Tcl language
51329: 03/01/10: Re: VLSI training and prospects?
51354: 03/01/11: Re: VLSI training and prospects?
61057: 03/09/26: Re: FPGA implementation of a lexer and parser - feasible?
70875: 04/06/30: Re: Xilinx $99 Spartan-3 kit
70878: 04/06/30: Re: Xilinx $99 Spartan-3 kit
70879: 04/06/30: Re: Xilinx $99 Spartan-3 kit [Windows Only]
70955: 04/07/02: Re: Xilinx $99 Spartan-3 kit
70963: 04/07/02: Re: Xilinx $99 Spartan-3 kit
71131: 04/07/09: EDA apps on Mac OSX?
71275: 04/07/13: Re: Available: Open Source VHDL parser - for free
71502: 04/07/20: Re: Xilinx 6.2i ISE WebPACK running under wine?
71504: 04/07/20: Re: Xilinx 6.2i ISE WebPACK running under wine?
71505: 04/07/20: Re: Xilinx 6.2i ISE WebPACK running under wine?
71515: 04/07/20: Re: Xilinx 6.2i ISE WebPACK running under wine?
71517: 04/07/20: Re: Xilinx 6.2i ISE WebPACK running under wine?
72212: 04/08/11: Re: Xilinx ParallelCable IV vs. Linux
72322: 04/08/15: Re: Free Spartan3 download program for GNU/Linux
72352: 04/08/16: Re: Free Spartan3 download program for GNU/Linux
72431: 04/08/18: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72447: 04/08/19: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72448: 04/08/19: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72449: 04/08/19: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72468: 04/08/19: Re: Free Flash PROM programming tool for GNU/Liunx
72535: 04/08/23: Re: Announcing JOLT - Yet Another Xilinx Programming Tool
72737: 04/08/31: Installing Xilinx ISEWebPack under Wine
76938: 04/12/16: Re: Exportability of EDA industry from North America?
76949: 04/12/16: Re: Exportability of EDA industry from North America?
76969: 04/12/17: Re: Exportability of EDA industry from North America?
78064: 05/01/24: dsp, arithmetic scaling questions, advice
78144: 05/01/25: Re: dsp, arithmetic scaling questions, advice
78951: 05/02/10: ROM inference in Spartan3
79017: 05/02/11: Re: ROM inference in Spartan3
79026: 05/02/11: ISE and IEEE.Fixed_pkg (fixed point math for synth?)
79032: 05/02/11: Re: ISE and IEEE.Fixed_pkg (fixed point math for synth?)
79058: 05/02/12: Re: ISE and IEEE.Fixed_pkg (fixed point math for synth?)
79059: 05/02/12: Re: ROM inference in Spartan3 (ISE bug)
79163: 05/02/15: ISE:ERROR:Xst:829: Constant Value expected for Generic 'U'?
79259: 05/02/16: Re: ISE:ERROR:Xst:829: Constant Value expected for Generic 'U'?
79633: 05/02/22: accessing external RAM on Spartan3 starter board
82661: 05/04/15: Hobby or job? (FPGA User's groups anyone?)
82671: 05/04/16: Re: Hobby or job? (FPGA User's groups anyone?)
82672: 05/04/16: Re: Hobby or job? (FPGA User's groups anyone?)
82685: 05/04/16: Re: salary ballpark please guys
82707: 05/04/16: Re: salary ballpark please guys
82708: 05/04/16: Re: Xilinx tools on Linux
82710: 05/04/16: Xilinx tools from the commandline
82712: 05/04/16: Re: ISE 7.1 GUI (slightly OT)
82724: 05/04/17: Re: Xilinx tools from the commandline
82725: 05/04/17: Re: Xilinx tools on Linux
82761: 05/04/17: Re: Xilinx tools from the commandline
82762: 05/04/17: Re: Xilinx tools on Linux
82766: 05/04/18: Re: Xilinx tools from the commandline
82815: 05/04/18: Re: Xilinx tools unusable on Linux
82818: 05/04/18: Re: Declining a job offer
82828: 05/04/18: Re: Xilinx tools unusable on Linux
82829: 05/04/18: Re: Xilinx tools on Linux
82859: 05/04/19: Re: Xilinx tools on Linux
82860: 05/04/19: Re: Declining a job offer
82926: 05/04/19: Re: Perl Preprocessor for HDL
83206: 05/04/26: Re: New FPGA Development Board
83353: 05/04/28: Re: *RANT* Ridiculous EDA software "user license agreements"?
83354: 05/04/28: Re: *RANT* Ridiculous EDA software "user license agreements"?
83373: 05/04/28: Xilinx Webpack 7.1 under Wine(and libQt_Qt.dll)
83378: 05/04/28: Re: Xilinx Webpack 7.1 under Wine(and libQt_Qt.dll)
83380: 05/04/28: Re: Xilinx Webpack 7.1 under Wine(and libQt_Qt.dll)
83399: 05/04/29: Re: Xilinx Webpack 7.1 under Wine(and libQt_Qt.dll)
83986: 05/05/11: Re: Impact Kernel 2.6
84293: 05/05/17: Re: FPGA design under Mac OS X ?
84296: 05/05/17: Re: FPGA design under Mac OS X ?
84297: 05/05/17: Re: FPGA design under Mac OS X ?
84421: 05/05/19: Re: Which Simulators
88510: 05/08/20: Re: Evolutionary VHDL code example
89216: 05/09/08: Re: Spartan-3E Starter Kit availability slips to December
90464: 05/10/13: Re: 64 bit processor for FPGA workstation?
91445: 05/11/07: Re: icarus verilog
91446: 05/11/07: Re: FPGA C Compiler on sourceforge.net (TMCC derivative)
94512: 06/01/13: Re: FPGA Journal Article
94642: 06/01/15: Re: FPGA Journal Article
94806: 06/01/18: Re: FPGA Journal Article
94807: 06/01/18: Re: FPGA Journal Article
94805: 06/01/18: Re: FPGA Journal Article
94865: 06/01/18: Re: FPGA Journal Article
94810: 06/01/18: Re: FPGA Journal Article
94808: 06/01/18: Re: FPGA Journal Article
94897: 06/01/19: Re: FPGA Journal Article
94804: 06/01/18: Re: Raggedstone specifications ...
94803: 06/01/18: Re: Raggedstone specifications ...
94899: 06/01/19: Re: Raggedstone specifications ...
94866: 06/01/18: Re: ISE8.1 on Linux, first impressions
95454: 06/01/23: Re: ISE8.1 on Linux, first impressions
95117: 06/01/21: working with XDL
95174: 06/01/21: Re: working with XDL
95253: 06/01/21: Re: working with XDL
95379: 06/01/23: Re: working with XDL
95598: 06/01/24: Re: working with XDL
95653: 06/01/25: So what happened to JHDLBits?
95731: 06/01/25: Re: So what happened to JHDLBits?
95728: 06/01/25: Re: So what happened to JHDLBits?
95760: 06/01/26: Re: So what happened to JHDLBits?
95767: 06/01/26: Re: So what happened to JHDLBits?
95848: 06/01/26: Re: So what happened to JHDLBits?
95852: 06/01/26: Re: So what happened to JHDLBits?
95872: 06/01/26: Re: So what happened to JHDLBits?
95870: 06/01/26: Re: So what happened to JHDLBits?
95866: 06/01/26: Re: So what happened to JHDLBits?
95857: 06/01/26: Re: So what happened to JHDLBits?
95854: 06/01/26: Re: So what happened to JHDLBits?
95914: 06/01/27: Re: So what happened to JHDLBits?
95748: 06/01/25: Re: open source fpga programmer programs
95880: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source interface?
95896: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source interface?
95910: 06/01/27: Re: So Xilinx, is XDL and related libraries an available open source interface?
95878: 06/01/26: Re: So Xilinx, is XDL and related libraries an available open source
95993: 06/01/27: Re: C to FPGA Tools (Impulse C and others) and necessary trig IP
96048: 06/01/29: XDL Tools wiki site
96076: 06/01/30: Re: XDL Tools wiki site
96078: 06/01/30: Re: XDL Tools wiki site
96077: 06/01/30: Re: XDL Tools wiki site
96075: 06/01/30: Re: XDL Tools wiki site
96121: 06/01/30: Re: XDL Tools wiki site
96140: 06/01/30: Re: Xilinx Legal
96142: 06/01/31: Re: Xilinx Legal
96144: 06/01/31: Re: Xilinx Legal
96143: 06/01/31: Re: Xilinx Legal
94986: 06/01/20: Re: OT:Shooting Ourselves in the Foot
94987: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95120: 06/01/21: Re: OT:Shooting Ourselves in the Foot
99846: 06/03/30: Re: FpgaC developers wanted :)
100154: 06/04/04: ISE under 64-bit Linux?
100179: 06/04/05: Re: ISE under 64-bit Linux?
101945: 06/05/09: Re: FPGA-based hardware accelerator for PC
101946: 06/05/09: Re: FPGA-based hardware accelerator for PC
101950: 06/05/09: Re: FPGA-based hardware accelerator for PC
101951: 06/05/09: Re: FPGA-based hardware accelerator for PC
102048: 06/05/10: Re: FPGA-based hardware accelerator for PC
102051: 06/05/10: Re: FPGA-based hardware accelerator for PC
103013: 06/05/24: Re: Verilog vs VHDL
103046: 06/05/25: Re: Verilog vs VHDL
105313: 06/07/20: [ANN] RHDL-0.5.0 released
105375: 06/07/21: Re: Hardware book like "Code Complete"?
106198: 06/08/09: Simple code to check out Spartan3 starter kit?
106200: 06/08/09: Re: Simple code to check out Spartan3 starter kit?
106299: 06/08/10: Re: Simple code to check out Spartan3 starter kit?
106523: 06/08/14: Re: Open source Xilinx JTAG programmer with Digilent USB support
106793: 06/08/19: Anyone use XC3Sprog?
106865: 06/08/21: Re: Anyone use XC3Sprog?
124925: 07/10/10: Re: What happened to Confluence and HDCaml?
<phil-news-nospam@ipal.net>:
121799: 07/07/13: Re: Designing the right clock tree for a multi-FPGA setup
<phil_jackson@my-deja.com>:
17567: 99/08/10: Re: VHDL OPTIMIZATION FOR FPGA's: (Anyone have suggestions?)
18964: 99/11/23: Re: VHDL vs. schematic entry
23063: 00/06/12: Re: Altera vs Xilinx
<phil_jackson@my-dejanews.com>:
14435: 99/01/29: Re: Hazard
16031: 99/04/29: Re: Counters
phile:
46037: 02/08/15: Re: Modelsim VHDL problem
Philemon John Chose:
17233: 99/07/13: Why can't output flops be pulled into the IOB's when a module is floorplanned?
Philip:
142020: 09/07/22: Re: Why do both Xilinx and Altera DPS use 18*18?
144892: 10/01/12: Xilinx ISE 10.1.03
151188: 11/03/14: Re: Nanosecond pulse generator using Spartan-3E
philip:
62401: 03/10/29: Re: Logic Analyzer for FPGAs
Philip Americus:
3932: 96/08/21: FPGA vs. Custom design
philip bowden @ home:
72362: 04/08/17: where to post job in china
Philip Buchholz:
12748: 98/10/27: Re: FPGA Decouple Capacitor values
Philip Chong:
5096: 97/01/22: Re: XC6200 Announcement by VCC
Philip Cummins:
38249: 02/01/10: Re: Where can I download Maxlock`s PCI core (It`s freecore, but I can`t download this from their WWW). Can anyone sent me this by email ?
Philip Freidin:
221: 94/09/27: Re: Xilinx 4000
274: 94/10/11: Re: Any documentation for Xilinx XNF file format?
288: 94/10/13: Re: Xilinx FPGA Pics: LCA, CLB etc.?
289: 94/10/13: Re: Xilinx configuration
337: 94/10/24: Re: High Bus Drive (24mA) FPGAs/CPLDs?
354: 94/10/27: Re: I/O pin currents on Xilinx FPGAs?
355: 94/10/27: Re: Suggestions for low power FPGAs/CPLDs needed
356: 94/10/27: Re: SRAM and antifuse for interconnects
358: 94/10/28: Re: linear feedback shift registers
375: 94/11/01: Re: about downloading FPGAs
402: 94/11/08: Re: about downloading FPGAs
408: 94/11/10: Re: Using Xilinx Wide edge Decoders
413: 94/11/11: Re: about downloading FPGAs
432: 94/11/15: Re: Anybody used FPGA as Encryption Device?
448: 94/11/19: Re: any XC4000 Horror Stories?
468: 94/11/27: Re: Viewdraw's Change Label Sense
514: 94/12/16: Re: Any Way to Download a XNF to FPGA?
558: 95/01/04: Re: Dual Xilinx 4000->3000 question
850: 95/03/13: Re: FPGA multi-chip modules ?
901: 95/03/26: Re: Any suggestions for chips to implement uCode machines?
951: 95/04/02: Re: How do I connect an external crystal to a XC4000?
992: 95/04/10: Re: Xilinx XC3000a/4000 as LCD-driver
1200: 95/05/12: Re: Overheating (was Re: Compression algo's for FPGA's)
1223: 95/05/18: Re: Can the X4010 replace a X4003 ?
1257: 95/05/23: Re: Xilinx Download
1258: 95/05/23: Re: Projects, assignments, and exam.
1345: 95/06/03: Re: Xilinx Master/Slave Serial Configuration
1296: 95/05/30: Re: Help on Programming FPGAs
1380: 95/06/10: Re: 256k Serial Configuration PROM for Xilinx???
1460: 95/06/26: Place-n-Route service
1470: 95/06/27: Re: Place-n-Route service
1484: 95/06/28: Re: Digital IO capture board / Digital Camera
1582: 95/07/21: Re: letter from Olga! =)
1621: 95/08/03: Re: How to: dual port memory
1663: 95/08/12: Re: external connections for efficient internal routing
1709: 95/08/18: Re: high pinout - low logic devices
1710: 95/08/18: Re: Obscuring Code For Customers (was VHDL Obfuscators)
1711: 95/08/18: Re: Simulation not matching lab results
1712: 95/08/18: Re: Timespecs in XNF format
1713: 95/08/18: Re: FPGAs with embedded RAM
1799: 95/09/04: Re: Help Needed-FPGA Apps Eng.-Allentown,PA.-Recruiter
1876: 95/09/14: Re: XC3030 XC1736 "Done still low"
2045: 95/10/06: Re: FPGA for a 20k gates micro-controller
2058: 95/10/07: Re: Programming a daisy chain of XC4000
2059: 95/10/07: Re: Sockects for AMD MACH-445 anywhere ?
2063: 95/10/09: Re: Powerdown & Xilinx devices
2186: 95/10/28: Re: PLD in small package ?? anyone
2187: 95/10/28: Re: Xilinx Configuration Memory Hacking
2216: 95/11/03: Re: altera problems
2217: 95/11/03: Re: AT&T vs. Xilinx
2279: 95/11/16: Re: Tape
2311: 95/11/19: Re: [q][Reverse Engineering Protection]
2438: 95/12/05: Re: Median filter
2522: 95/12/27: Re: Xiling 4025E routing info
2592: 96/01/09: Re: [q][Reverse Engineering Protection]
2769: 96/02/05: Re: GAL programming for hobby use...Is there no hope?
2840: 96/02/15: Re: New Reconfigurable Computing Threads.
3002: 96/03/12: Re: DIY Bitblaster ?
3030: 96/03/18: Re: Xact6.o too slow
3037: 96/03/19: Re: Problems with Altera Bitblaster
3501: 96/06/11: Re: Double Port Ram - Xact Libs
3502: 96/06/11: Re: Schematic compare
3503: 96/06/11: Re: Xtal Osc. at XC31xxA
3544: 96/06/18: Re: Wanted Info on faults in FPGAs
3735: 96/07/23: Re: Daisychain or SPROM?
3743: 96/07/24: Re: Mentor->XC3064
3744: 96/07/24: Re: Designing Dual Port RAM with 4000 series.
3888: 96/08/15: Re: Xilinx/FPGA Timing Problems
3889: 96/08/15: Re: Xilinx XC3090 intermittent place/route problem
3905: 96/08/17: Re: Xilinx: question about bitstream and parallel download
3939: 96/08/23: Re: XC6200 FPGAs
3940: 96/08/23: Re: xilinx programing
3966: 96/08/26: Re: XC4010E en downloading bitstream
3975: 96/08/28: Re: Anyone know about Viewlogic v4 with QEMM?
4001: 96/09/01: Re: CHEAP XILINX FPGA ROUTING SOFTWARE ?
4030: 96/09/04: Re: speed up Xilinx P & R
4046: 96/09/05: Re: What is the REAL address of XOILINX and ALTERA?
4085: 96/09/09: Re: INDUSTRY GADFLY: EDA Goes OJ
4093: 96/09/10: Re: ORCA and Viewlogic - any good?
4112: 96/09/12: Re: ORCA and Viewlogic - any good?
4195: 96/09/25: Re: FPGA Routing Question
4232: 96/10/03: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4243: 96/10/04: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4244: 96/10/04: Re: Q on Xilinx/Viewsim macros
4276: 96/10/09: Re: Reversible LFSR?
4279: 96/10/09: Re: Reversible LFSR?
4351: 96/10/18: Re: xc4000 and 2 clocks
4352: 96/10/18: Re: (no subject) attempted humor
4423: 96/10/28: Re: Altera Configuration EPROM Equivalents
4472: 96/11/02: Re: What is the fastest fpga for ...
4602: 96/11/20: Re: Configuring Xilinx XC4000 device in Asynch. Peripheral Mode
4644: 96/11/25: Re: Asymetrix Embraces KaiZenWare
4712: 96/12/05: Re: Looking for hc0324
4745: 96/12/10: Re: what is "token chain"?
4823: 96/12/18: Re: what is "token chain"?
4869: 96/12/21: Re: Xilinx loading problem?
4881: 96/12/23: Re: Integer divide IC
4934: 97/01/02: Re: NT 4.0, ViewOffice 7.2 and Xilinx tools...96->97 problem...
4945: 97/01/03: Re: NT 4.0, ViewOffice 7.2 and Xilinx tools...96->97 problem...
4990: 97/01/09: Re: Oscillator with PLD's or FPGA's
5199: 97/01/30: Re: Safety Critical Apps -> Xilinx Checker.
5247: 97/02/01: Re: Suggestions how wire wrap mount a Xilinx PG223
5249: 97/02/01: Re: Altera support better than Xilinx
5297: 97/02/05: Re: Safety Critical Apps -> Xilinx Checker.
5386: 97/02/12: Re: bonding of XC4025
5629: 97/03/03: Re: Using internal clock of XC4000
5668: 97/03/05: Re: XILINX LIBRARY FOR VIEWLOGIC
5797: 97/03/16: Re: Pentium 166 with AA type Keys
5913: 97/03/26: Re: Xilinx 4013 cannot configuration
5916: 97/03/26: Viewlogic, A company that listens
6133: 97/04/15: Re: Cisco's SIBU is looking for ASIC and Systems Engineers
6065: 97/04/09: Re: bidirectional buses in xilinx 3000 fpgas
6190: 97/04/24: Re: Download Xilinx Fpga (XC4***)
6398: 97/05/21: Re: FPGA technology: No truth in MARKETING
6630: 97/06/06: Re: Fine Pitch PQFP : anyone any hassles?
6592: 97/06/04: Re: XILINX CONFIGUTATION CRCs
6775: 97/06/26: Re: FPGA prototype board
6781: 97/06/27: Re: Asynchronous Peripheral Download Mode, Probs
6932: 97/07/10: Re: Xilinx Prom Generation Problem
6947: 97/07/13: Re: Xilinx Prom Generation Problem
6958: 97/07/16: Re: Selection Criteria for CPLD's/FPGA's
7023: 97/07/24: Re: Why fast message delete in this group?
7033: 97/07/25: Re: How do FPGAs outperform DSP at FFT?
7045: 97/07/26: Re: FPGA die photograph
7068: 97/07/29: Re: San Diego/Santa Clara/Boston--MTS-FPGA Field Applications Engineer-Recruiter
7070: 97/07/29: Re: Design Protection in FPGAs
7101: 97/07/31: Re: Design Protection in FPGAs
7102: 97/07/31: Re: Quick prototyping? Best solution?
7120: 97/08/02: Re: Programming the Xilinx 4036XL :)
7122: 97/08/02: Re: Incremental changes of FPGA's possibel ?
7229: 97/08/16: Re: CDMA corellator
7238: 97/08/18: Re: Help!!!!
7262: 97/08/19: Re: FPGA prototyping board
7337: 97/08/28: Re: daisy-chained bitstreams
7338: 97/08/28: Re: FIFO in Altera
7346: 97/08/29: Re: xlinx shift regs equilivelent parts
7347: 97/08/29: Re: Xilinx PCI simulation problem...
7695: 97/10/03: Re: XILINX and ALTERA development boards
7737: 97/10/09: Re: bidirectional bus problem
7741: 97/10/09: FPGA based CPU ideas, and novel extensions
7944: 97/11/01: Re: Complex Multiplier
8046: 97/11/11: Re: switching between clock domains in Xilinx FPGA's
8263: 97/12/04: Re: Xilinx P&R - how does M1 compare to XACT6?
8285: 97/12/05: Re: what is metastability time of a flip_flop
8381: 97/12/11: Re: what is metastability time of a flip_flop
8229: 97/12/01: Re: Bugs in M1.3.7 mapper ?
8264: 97/12/04: Re: Xilinx .bit file format.
8271: 97/12/04: Re: Xilinx 3000 Series (old software) to 4000 on New Software
8338: 97/12/09: Re: gates
8461: 97/12/17: Re: FPGA Prototyping on the ISA Bus
8595: 98/01/12: Clock net skew simulation
8611: 98/01/13: Re: Clock net skew simulation
8529: 98/01/05: Re: Interfacing 3.3V FPGA with ISA bus
8758: 98/01/24: Re: Xilinx M1.4 and Viewlogic
9167: 98/02/26: Re: XC4000E CLB utilization (again...)
8894: 98/02/05: Re: Can XACT6 run in a NT4 DOS box?
8895: 98/02/05: Re: Q: Workview Office and M1
8936: 98/02/07: Re: Can XACT6 run in a NT4 DOS box?
9102: 98/02/20: Re: buft and bufe
9238: 98/03/04: Re: Debugging question.
9453: 98/03/14: Re: Strange Xilinx question?
9565: 98/03/24: Re: Dual port
9593: 98/03/25: Re: Dual port
9594: 98/03/25: Re: Orca Floorplanning tools
9596: 98/03/25: Re: Dual port
9614: 98/03/26: Re: Dual port
9765: 98/04/03: Re: Dual port
9719: 98/04/01: Re: New Technology !!!!
10590: 98/06/03: Re: Foundation M1.4 functional simulation problems
10893: 98/06/29: Re: Xilinx Foundation simulator problem?
10942: 98/07/06: Re: FREE ASIC ESTIMATOR
10950: 98/07/07: Re: Configure with BIT file
10974: 98/07/08: Re: Spartan S30 DOUT/SGCK4 pin
11001: 98/07/09: Re: Spartan S30 DOUT/SGCK4 pin
11026: 98/07/12: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
11028: 98/07/12: Re: Need to know Xilinx M1.4's routing times -- large(?) designs
11046: 98/07/15: Re: high-speed place and route
11129: 98/07/20: Re: Old Contace Information
11175: 98/07/22: Re: unknown speedgrade question
11218: 98/07/27: FloorPlanning with some examples
11240: 98/07/29: Re: Caluclation of gates in FPGA
11292: 98/08/02: Re: Symbols, design changes, pin changes
11529: 98/08/21: Re: Parallel Xilinx Xchecker Cable Pinouts
11773: 98/09/08: Re: Altera 10K20 Register File Implementation??
11786: 98/09/09: Re: Altera 10K20 Register File Implementation??
11801: 98/09/10: Re: Design Security Question
11806: 98/09/10: Re: Design Security Question
11846: 98/09/14: Re: ASIC -> FPGA async issues
11847: 98/09/14: Re: Xilinx ncd files
11918: 98/09/18: Re: programming xilinx fpga
11933: 98/09/20: Re: ASIC -> FPGA async issues
11960: 98/09/21: Re: Xilinx tools
12112: 98/09/29: Re: strange problem of 4028XL
12278: 98/10/07: Re: Help Desperately Needed with Altera Microprocessor Design.
12426: 98/10/12: FOCUS FOCUS FOCUS
12427: 98/10/12: Re: Xilinx may not support schematics for Virtex?????
12558: 98/10/16: Re: gray code counter in a Xilinx fpga???
12572: 98/10/16: Re: gray code counter in a Xilinx fpga???
12789: 98/10/29: Re: Xilinx mode pins.
12790: 98/10/29: Re: Question on setting M0, M1, M2 for XC4028XL
12858: 98/11/02: Re: Q: 3.3 V regulators suitable for XILINX - ?
12884: 98/11/03: Re: Xilinx bit file format question
13011: 98/11/11: Re: CCLK on Spartan
13042: 98/11/12: Re: placement&routing problems
13094: 98/11/16: Re: Help with identifying possible programmable logic chip
13115: 98/11/16: Re: Xilinx 4k programming
13529: 98/12/08: Re: A short digression...
13446: 98/12/03: Re: Xilinx FPGA configuration problems... Help!
14316: 99/01/25: Re: Xilinx flip flops hold time
14709: 99/02/12: Re: Very Long Write Enable in Xilinx Dual Port RAMs
14746: 99/02/14: Re: Synplify resource usage report for Virtex devices
14784: 99/02/17: Re: Flex6016 config. problem.
14786: 99/02/17: Re: Synplify resource usage report for Virtex devices
14820: 99/02/18: Re: Xilinx Spartan and pin-locking
14821: 99/02/18: Re: P&R times for Altera10K200E and Virtex
14822: 99/02/18: Re: Flex6016 config. problem.
14885: 99/02/23: Re: Problem with xilinx M1
14886: 99/02/23: Re: High Fanout Signals
15809: 99/04/15: Re: What's the best way to learn about fpga's?
15951: 99/04/23: Re: xc40110xv data into xc40150xv
16155: 99/05/06: Re: Configuring Xilinx FPGAs
16305: 99/05/14: Re: Who do you know? Motorola FPGA
16485: 99/05/25: Re: LUT implementation in XC3000
16675: 99/06/02: Re: Printing to picture files : my experience with Viewlogic
16771: 99/06/08: Re: Evolutionary computation
16723: 99/06/04: Re: Xilinx symbols, Viewlogic
16734: 99/06/04: Re: Xilinx symbols, Viewlogic
16828: 99/06/11: Re: Place & Route Xilinx F1.5 Student ed.
16975: 99/06/21: Re: FPGA in Wireless Designs
17015: 99/06/24: Re: Request for information on discontinued Xilinx XC4000-series variants
17043: 99/06/27: Re: Request for information on discontinued Xilinx XC4000-series variants
17114: 99/07/01: New tools for FPGA design
17344: 99/07/22: Re: Xilinx Foundation Beginner Question
17546: 99/08/09: Re: RLOC constraint not interpreted correctly?
17739: 99/08/28: Re: map hang
17745: 99/08/29: Re: size of configuration data?
17875: 99/09/15: Re: differences between ALTERA-XILINX
17921: 99/09/17: Re: speeding up place and route
17922: 99/09/17: Re: Xilinx XC4005E
18038: 99/09/25: Re: Help for viewlogic73!
18415: 99/10/23: Re: Xilinx Orientation Question
18445: 99/10/25: Re: Foundation 1.5i Map fatal error
18447: 99/10/25: Re: xilinx foundation: bit_gen warning becasue of pullUps
18454: 99/10/25: Re: Xilinx Orientation Question
18522: 99/10/28: Re: Comparison between Altera and Xilinx
19792: 00/01/12: Re: Help for EDIF format !
19816: 00/01/13: Re: Help for EDIF format !
20092: 00/01/27: Re: Pin to pin
20503: 00/02/12: Re: RLOC_RANGE property.
22133: 00/04/26: Re: Xilinx Virtex problem (schematic)
22134: 00/04/26: Re: Xilinx Virtex problem (schematic)
22135: 00/04/26: Re: How to Prevent theft of FPGA design
22294: 00/05/04: Re: Init/ line - CRC error ???
22359: 00/05/05: Re: Init/ line - CRC error ???
22419: 00/05/09: Re: INIT pin on Virtex FPGAs
22626: 00/05/15: Re: Configuration process %-(
22717: 00/05/19: Re: [Part II] - Pb FPGA Xilinx config process
22829: 00/05/25: Re: Programming using *.rbt file
22982: 00/06/07: Re: Where's OptiMagic?
23125: 00/06/15: Re: PAR Times for XILINX Foundation Express Student Edition 1.5
23183: 00/06/16: Re: Virtex ".FFX" contraint???
23347: 00/06/22: Re: dual processor PC for PPR - are they worth the extra cost?
23392: 00/06/23: Re: Xilinx xc4000
23395: 00/06/23: Re: What tools do people use for Xilinx FPGAs?
23410: 00/06/24: Re: a lot of basic questions - where's the FAQ?
23427: 00/06/24: Re: Different ?
23506: 00/06/28: I cant stand it any more.
23532: 00/06/28: Re: PSN Generator
23593: 00/07/02: Re: Viewlogic schematic from Synplify edif output?
23594: 00/07/02: Re: Viewlogic schematic from Synplify edif output?
23717: 00/07/06: Re: ORCA4 (was Re: Altera Ships Largest PLD)
23723: 00/07/06: Using LUTs in Virtex with ViewDraw and ViewSim
23772: 00/07/07: Re: Using LUTs in Virtex with ViewDraw and ViewSim
23965: 00/07/18: Re: Dual Port RAM
24064: 00/07/25: Re: Spartan II Pin
24269: 00/08/01: Re: Viewlogic Licencing
24282: 00/08/02: Re: FPGA selection
24395: 00/08/06: Re: Circuit Drawing
24421: 00/08/07: Re: Xilinx Foundation 3.1i
24440: 00/08/08: Re: help -- of RAMs, FFs, latches, inverted clocks, and other curiosities
24469: 00/08/09: Re: 3-state busses on Virtex?
24546: 00/08/13: Re: Virtex 2.5V part with 5V IO problems
24558: 00/08/13: Re: Virtex 2.5V part with 5V IO problems
24568: 00/08/14: Re: Xilinx chip not programming correctly
24647: 00/08/16: Re: clock variable problem
24664: 00/08/16: Re: error during synthesis
24872: 00/08/21: Some notes on metastability
24895: 00/08/21: Re: Usage of ROC (Foundation 2.1i)
24907: 00/08/21: Re: xdl documentation
25013: 00/08/23: Re: xdl documentation
25400: 00/09/09: Re: FPGA Express, Xilinx, and Powerview
25780: 00/09/20: Re: An Online Course for CPLD and FPGA design
26560: 00/10/20: Re: Mailbox (was "Asynchronous pulse generation with Spartan.")
26656: 00/10/23: Re: How safe is the algorithm implemented with FPGA?
26698: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
26719: 00/10/25: Re: How safe is the algorithm implemented with FPGA?
26664: 00/10/24: Re: New PACT 50 GOP Reconfigurable Processor
27107: 00/11/10: Re: ViewLogic ViewDraw questions
27266: 00/11/16: Re: BUFT conflict with LOC
27329: 00/11/17: In the news
27405: 00/11/20: Re: Spartan and XC4000 configuration
27436: 00/11/21: Re: Another simple Xilinx question
27809: 00/12/09: Re: Linear Regulator troubles
27822: 00/12/11: Re: Linear Regulator troubles
27916: 00/12/14: Re: Spartan configuration : Why Done returns to Low?
27918: 00/12/14: Re: Is it necessary to synchronize the reset signal in an FPGA ?
28051: 00/12/19: Re: Setup violation
28083: 00/12/20: Re: dual port ram for altera
28177: 00/12/24: Re: Question about programming xcv100
28198: 00/12/28: Re: Question about programming xcv100
28282: 01/01/04: Re: Nondeterministic FSMs in hardware?
28865: 01/01/26: Re: RAM reset question - Xilinx Virtex
28901: 01/01/28: Re: Actel's FPGA : A54SX32A
28958: 01/01/31: Re: Virtex Engineering Samples timing problem
29087: 01/02/05: Installed Documentation
29125: 01/02/06: FAQ
29142: 01/02/07: Re: 8B/10B Encoding
29267: 01/02/11: Re: OT: SEIKO-EPSON LCD behaving strange.
29356: 01/02/15: Re: Configuration file of SpartanXL
29506: 01/02/23: Re: Samll quantities ordering
29916: 01/03/16: Re: FPGA : Simple FD latch glitchs
30019: 01/03/20: Re: IRDY/TRDY (was Re: More detailed Spartan II CLB drawings?)
30041: 01/03/21: Re: Trouble with assigning output pins on Xilinx (foundation)
30139: 01/03/24: Re: How to find out where par placed things?
30518: 01/04/12: Re: How to specify Spartan2 GSR/GTS for Synthesis
30908: 01/05/02: Re: Shannon Capacity
31013: 01/05/09: Re: floorplaning and layout
31078: 01/05/10: Re: Spartan Annoyances
31468: 01/05/26: The FAQ is Live and so is the Archive
31504: 01/05/28: Re: what cables and softwares do you need to use "Xilinx FPGA Demonstration Evaluation Board"?
31538: 01/05/29: Searching the Archive
31689: 01/06/02: Re: simulation of Viewdraw schematics containing VirtexII flip flops.
31938: 01/06/08: Re: Studentlab with Xilinx tools
31962: 01/06/09: Re: FPGA comparsion
32183: 01/06/18: Re: ee
32184: 01/06/18: Re: FPGA Boards
32563: 01/06/30: Re: Newbee and FAQ
32564: 01/06/30: Re: Newbee and FAQ
32574: 01/06/30: Re: Where are the BUFE and BUFT symbols in Xilinx WebPACK???
32638: 01/07/03: Re: poor man's floating point...
32759: 01/07/07: Re: Large Power up Current on Spartan2
32767: 01/07/08: Re: Shift and Add Multiplier With Signed Numbers
32866: 01/07/10: Re: Problems with JTAG on XC95144 was:Best JTAG H/W,...
32893: 01/07/11: Re: Virtex2: Is it possible to place distributed DPRAM
32915: 01/07/11: Re: need help implementing state diagram of a 2input mealy machine!
33109: 01/07/17: Re: MCS file format
33451: 01/07/26: Re: PCI-Interface
33654: 01/08/01: Re: Xilinx Foundation 2.1i Update
33728: 01/08/02: Re: Xilinx Spartan XL length count question.
33886: 01/08/07: Re: Reconfigurable Computational Accelerator
34081: 01/08/13: Re: virtex2 Block Ram: dual port ram with different da
34119: 01/08/14: Re: virtex2 Block Ram: dual port ram with different da
34121: 01/08/14: Re: Xilinx foundation multi-pad pin assignments
34133: 01/08/15: Re: Xilinx pin lists in text format
34182: 01/08/15: Re: Internal clock skew when using DLL
34220: 01/08/16: Re: Virtex Pro Info
34297: 01/08/20: Re: Internal clock skew when using DLL
34311: 01/08/20: Re: JTAG
34313: 01/08/20: Re: Internal clock skew when using DLL
34343: 01/08/21: Re: hardware damage to a Virtex or Spartan-II?
34344: 01/08/21: Re: Help the clueless guy....
34378: 01/08/22: Re: hardware damage to a Virtex or Spartan-II?
34416: 01/08/23: Re: Optical Bay Area Start-up! SW/HW Engs needed
34498: 01/08/27: Defending Austin Franklin
34546: 01/08/29: Re: download bitstream to FPGA
34566: 01/08/29: Re: Urgent Help Needed
34567: 01/08/29: Re: Level sensitive latches in Xilinx Virtex
34589: 01/08/30: Re: download bitstream to FPGA
34693: 01/09/04: Re: Open collector outputs
34779: 01/09/07: Re: Spartan II configuration
34817: 01/09/09: Re: Alliance: xlmap, XC3020
34857: 01/09/11: Re: Innoveda and ISE Alliance 4.1i ?
35097: 01/09/20: Re: Spartan configuration
35098: 01/09/20: Re: Increase routing delay in XILINX FPGA editor
35099: 01/09/20: Re: Clockin on rising AND falling edge
35316: 01/09/28: Re: Spartan-IIE?
35319: 01/09/28: Re: Meta-stability
35512: 01/10/09: Re: FPGA reset
35609: 01/10/11: Re: High level synthesis will never work well :)
35687: 01/10/13: Re: how do I avoid glitches in this design?
35992: 01/10/25: Re: SpartanXL: DOUT or GCK6?
36004: 01/10/25: FCCM02 Call for Papers
36132: 01/10/31: Re: Can anyone guide me in selecting an FPGA?
36134: 01/10/31: Re: Shift Registers with Xilinx Foundation 2.1
36524: 01/11/11: Re: Xilinx ISE false timing errors?
36730: 01/11/18: Re: Q: XILINX binary .bit file header - ?
36882: 01/11/23: Re: how can define function in terms of equation rather than gates in XC4000 series
36883: 01/11/23: Re: fix LOC on LUT1
37064: 01/11/29: Re: palette LUT design(searching ROM)
37177: 01/12/03: Re: Crossing a clock domain
37253: 01/12/05: Re: Crossing a clock domain
37388: 01/12/09: Re: [Spartan-II] Global Timing Constraints valid for Block RAM's ?
37438: 01/12/11: Re: ISA syncronization?
37469: 01/12/12: Re: Crosstalk on clocks
37470: 01/12/12: Re: DCM error
37521: 01/12/13: Re: Crosstalk on clocks
37529: 01/12/13: Re: Fondation 4.1 and SpartanXL
37605: 01/12/17: Re: Certicom challenge and FPGA based modular math
37624: 01/12/18: Re: division 64
37988: 01/12/29: Re: Spartan LUT question
38323: 02/01/11: Re: Runtime reconfiguration internals
38615: 02/01/19: Re: Should clock skew be included for setup time analysis?
38801: 02/01/25: Re: Dynamic Reconfiguration of single Xilinx FPGA
39013: 02/01/30: Re: Xilinx webpack
39049: 02/01/30: Re: glitchless clock enable/disable in spartanII
39076: 02/01/31: Re: glitchless clock enable/disable in spartanII
39097: 02/01/31: Re: Xilinx XC3020-70
39121: 02/02/01: Re: glitchless clock enable/disable in spartanII
39291: 02/02/05: Re: FPGA vs GAL : Lattice Its a TROLL
39399: 02/02/08: Re: Xilinx DCM question anyone? (or Peter if he is there?)
39650: 02/02/15: Re: Orca ngdbuild error: could not expand block
40077: 02/02/26: Re: EDIF netlist in FPGA Express
40081: 02/02/26: Re: Creation of FPGA tips and tricks forum - help required
40292: 02/03/05: Re: Constraining help required for clk_enable
40617: 02/03/12: Re: FPGA wich supports LVDS
41211: 02/03/22: Call for Participation FCCM-2002
41254: 02/03/23: Re: Pipelined sorting algorithms...
41379: 02/03/27: Re: I2C Slave sampling edge
41703: 02/04/05: Re: hand placement
41704: 02/04/05: Re: hand placement
41720: 02/04/05: Re: hand placement
41844: 02/04/09: Re: How to INIT ROM in VHDL for WebPack/ModelSimXE?
41918: 02/04/11: Re: Initializing the ram values on virtex.
41974: 02/04/12: Re: shift registers using virtex block RAM
42029: 02/04/13: Re: Stupid .ngd file questions....
42042: 02/04/13: Re: Slave serial loading of spartan II bitstream
42243: 02/04/18: Re: 8051 Core for Motor Electronics
42244: 02/04/18: Re: Schematic editor and module descriptions
42247: 02/04/18: Re: Addressing Error Ram on Virtex E.
43701: 02/05/30: Re: Can we edit an RBT Configuration file for a Xilinx FPGA?
43947: 02/06/07: Re: xc3042
44563: 02/06/24: Re: Initial of virtex II block ram
44773: 02/06/30: Re: virtex2 : 180 deg. phase clocks
44824: 02/07/02: Re: Xilinx XAPP622: Info on ROUTE constraint?
44889: 02/07/04: Re: Virtex II - IO TILE, IOB PAD #4
45922: 02/08/11: Re: comp.arch.fpga : How can I join the newsgroup?
46309: 02/08/25: Re: Floorplanning 101
46501: 02/09/01: Re: Thermoelectric Controller by FPGAs
46502: 02/09/01: Re: Multiplexing a tristate bus?
47289: 02/09/22: Re: Overheat with XCV-600E
48171: 02/10/12: Re: where can I find the FAQs for this news group???
49801: 02/11/21: Re: Metastability in FPGAs
50075: 02/11/30: Re: XC5204 bitstream
50383: 02/12/10: Re: hardware image processing - log computation
51027: 02/12/27: Re: Want to buy an board with Xilinx FPGA Virtex II
51963: 03/01/27: Re: Somewhat OT - TECO
52291: 03/02/06: Re: Clock Enables
52518: 03/02/12: Re: Fast BlockRAM updates
52519: 03/02/12: Re: Fast BlockRAM updates
52594: 03/02/15: Re: Implementing BIG state machhine
52638: 03/02/17: Re: PCMCIA + FPGA/CPLD
52668: 03/02/18: Re: PCMCIA + FPGA/CPLD
52783: 03/02/21: Re: Gate boosting
52791: 03/02/22: Re: spartan III what is it?
52870: 03/02/25: Re: LVDS LCD
53640: 03/03/18: Re: Conversion of Xilinx bit file
54796: 03/04/18: Re: How to configure USER1 and USER2 of JTAG on Xilinx Virtex2!!
55121: 03/04/28: Re: Reason Xess discontinued XSV prototyping boards?
55122: 03/04/28: Re: How to configure USER1 and USER2 of JTAG on Xilinx Virtex2!!
55123: 03/04/28: Re: visualising a shift register using an LUT
55482: 03/05/09: Re: help on FPGA-programming tutorial for students
55483: 03/05/09: Re: Info about development kit
55507: 03/05/10: Re: help on FPGA-programming tutorial for students
55659: 03/05/15: Re: multiplexing resources in xilinx fpga
55979: 03/05/25: Re: FPGA Board
56299: 03/06/02: Re: Virtex 2 evaluation board
56325: 03/06/03: Attn Stewart Cobb and others posting via the Xilinx gateway to this news group
56637: 03/06/10: Re: Xilinx's Device Pin Configuration
56673: 03/06/11: Re: PAR REPORT SUGGESTED BY PHILIP
56761: 03/06/13: Re: Contraint File Problem
56767: 03/06/14: Re: Kit Recommendation
56771: 03/06/14: Re: adders for xilinx virtex2..
56836: 03/06/17: Re: Downloading bit-stream with a microprocessor.
56838: 03/06/17: Re: Implementaion of Mux-DFF with Virtex ..
56857: 03/06/17: Re: Downloading bit-stream with a microprocessor.
56881: 03/06/18: Re: Configuring Virtex with rbt files
56932: 03/06/19: Re: Configuring Virtex with rbt files
57033: 03/06/21: Re: FPGA configure through a PC parallel port.
57046: 03/06/22: Re: Convert rbt to bit
57504: 03/07/01: Re: Xilinx ISE drops support for more parts
57570: 03/07/02: Re: Xilinx Methodology Questions : Unconstrained Paths and DLL output phase alignment.
57620: 03/07/03: Re: What a fascinating board!
57958: 03/07/10: Re: okay what am I missing??? Please
58000: 03/07/11: Re: From one clock domain to another
58035: 03/07/13: Re: How to choose FPGA device?
58143: 03/07/15: Re: programming a PLD/CPLD with a PIC?
58271: 03/07/18: Re: bit to rbt conversion
58313: 03/07/20: Re: CPLD Interface to PC's requirements
58394: 03/07/22: Re: FPGA Editor
58435: 03/07/23: Re: FPGA Editor
58577: 03/07/27: Re: FPGA Editor
58581: 03/07/27: Re: FPGA Editor
58878: 03/08/03: Re: beginner
59316: 03/08/14: Re: Proto-Board with VirtexII and multiple DDR SDRAM banks?
59490: 03/08/20: Re: Legacy 4005 series and current Xilinx ISE offerings?
59524: 03/08/21: Re: Legacy 4005 series and current Xilinx ISE offerings?
59592: 03/08/22: Re: LVPECL I/O and Fndtn4.2
59760: 03/08/28: Re: Thinking out loud about metastability
59792: 03/08/28: Re: Thinking out loud about metastability
59908: 03/09/01: Re: A student's question
59911: 03/09/01: Re: Mitigating metastability.
60747: 03/09/21: Re: show-ahead FIFOs
60767: 03/09/22: Re: FPGA implementation in (V)HDL
61512: 03/10/06: Re: Should I worry about metastability
61804: 03/10/12: Re: Initilization of block rams to create rom
62078: 03/10/18: Re: Configuration Blues
62093: 03/10/19: Re: Configuration Blues
62654: 03/11/04: Re: Building the 'uber processor'
62656: 03/11/04: Re: Prototyping board with 4+ MB SRAM?
62786: 03/11/07: Re: Crossing/muxing clocks thru TBUF mux (w/DLL "stunts")
63472: 03/11/22: Re: XILINX Foundation F1.5 Build 3.1.1.35 with XCS10PC84 and Digilab XLA
63475: 03/11/22: Re: New ASCII-figure
63492: 03/11/23: Re: Aurora_401 reference allows 8B/10B bypass?
63547: 03/11/25: Re: Slightly unmatched UART frequencies
63614: 03/11/26: Re: Slightly unmatched UART frequencies
63873: 03/12/06: Re: Floorplanning techniques
64012: 03/12/12: Re: USB basic doubts
64110: 03/12/17: Re: Multi-FPGA PCI board recommendations???
64162: 03/12/18: Re: www.fpga-faq.com
64652: 04/01/10: Re: Xilinx ECS - connecting a single net to multiple bus lines?
64653: 04/01/10: Re: old articels of this newsgroup
64655: 04/01/10: Re: ERROR:HDLCompilers:200 - ../../../src/iq_gen.v line 35 Target of defparam 'lut_vdd.init' does not exist
64656: 04/01/10: Re: ISE6.1 rom16X1 initialization INIT
64694: 04/01/11: Re: PCB for FG456: layers Please dont use the Xilinx gateway to post articles
64754: 04/01/13: Re: ERROR:HDLCompilers:200 - ../../../src/iq_gen.v line 35 Target of defparam 'lut_vdd.init' does not exist
65137: 04/01/21: Re: QUES: Where can I find Xilinx M1 tools
65138: 04/01/21: Re: Good/Affordable Stater kits
65140: 04/01/21: Re: Which version of ISE Webpack has FPGA Editor on it?
65345: 04/01/25: Re: Can XILINX run in multiple instances?
65633: 04/02/03: Re: QUES: ODFX/IDFX inferred in syplify, and not in XACT libraries ????
66302: 04/02/16: Re: Plea for help - 29PL141
66306: 04/02/17: Re: how to priotize multiple conflicting constraints
66707: 04/02/25: Re: Basic jitter from a CPLD (XC7500XL)
66821: 04/02/27: Re: Suggestions: Eval/Demo Board.
66852: 04/02/27: Re: Suggestions: Eval/Demo Board.
66868: 04/02/28: Re: Stratix 2 ALUT architecture patented ?
66952: 04/03/02: Re: area constrains in UCF (or PACE)
67577: 04/03/15: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
67581: 04/03/15: Which should I use, Floorplanner or PACE
67755: 04/03/18: Re: PCI Development Board
68135: 04/03/27: Re: RocketIO 8/10b bypass
68362: 04/04/02: Re: How to advertise in www.fpga-faq.com/FPGA_Boards.shtml
68363: 04/04/02: Re: Best price per I/O
68628: 04/04/11: Re: rocket IO MGT location constraint?
68810: 04/04/19: Re: FPGA techniques for D/A and A/D
69007: 04/04/25: Re: FPGA within demonstration
69642: 04/05/17: Re: Phase relationship management
69688: 04/05/18: Re: Phase relationship management
69846: 04/05/21: Re: DS-BD-V2M1000 datasheets?
70049: 04/05/30: Re: Propogation delays and setup times
70108: 04/06/03: Re: FPPTA?
70177: 04/06/08: Re: Hardware implementation of the Xilinx configuration CRC generator
70196: 04/06/08: Re: Hardware implementation of the Xilinx configuration CRC generator
70413: 04/06/16: Re: pulse generation using SRL16E on a Virtex-II
70436: 04/06/16: Re: XCS10-84PC: How JTAG-Pins as I/O ?
70441: 04/06/17: Re: help for finding a company which can provide FPGA based PCI board with ethernet port
70444: 04/06/17: Re: Xilinx ParallelCable IV vs. Linux
71100: 04/07/08: Re: FSM in illegal state
71117: 04/07/08: Re: FSM in illegal state
71700: 04/07/28: Re: configuration SRAM cells in Xilinx/Altera FPGAs
71836: 04/08/02: Pointer to a good article on clock domain crossing
71862: 04/08/03: Re: Pointer to a good article on clock domain crossing
71863: 04/08/03: Re: Compact FPGA Board?
72174: 04/08/10: Re: Sync data between two clock domains
72213: 04/08/11: Re: scheduling in run-time reconfiguration
72296: 04/08/13: Re: Altera winner?
72336: 04/08/15: Re: let me have logic design for traffic light
72587: 04/08/26: Re: ring oscillator calibration
72693: 04/08/29: Re: 6.1 vs. 6.2
72708: 04/08/30: Re: Counter counting on both clock edges.
72793: 04/09/02: Re: The Effect of Pin Assginment
72812: 04/09/03: Completed my first Virtex4 design
73720: 04/09/28: Re: MicroBlaze & SRAM
73847: 04/09/30: Re: Evaluation Board for Xilinx Virtex
72839: 04/09/04: Re: Completed my first Virtex4 design
72844: 04/09/05: Re: more than one clock
72876: 04/09/07: Re: OD/OC outputs with Xilinx Spartan II
72878: 04/09/07: Re: I NEED HELP / MENTOR
72961: 04/09/09: Re: OD/OC outputs with Xilinx Spartan II
73011: 04/09/10: Re: Simple FPGA board
73046: 04/09/12: Re: why systemc?
73110: 04/09/14: Re: Adding a Delay2
73112: 04/09/14: Re: Need some help with some technical claims...
73121: 04/09/14: Re: Spartan 2E gets hot after configuration
73176: 04/09/15: Re: constraints coverage
73177: 04/09/15: Re: EDK OPB Uart 16550
73354: 04/09/20: Re: Regarding FPGA
74190: 04/10/06: Re: Xilinx Multiple Clock Domains
74259: 04/10/06: Re: Constant instantiation
74319: 04/10/08: Re: add/sub 2:1 mux and ena in a single LE (Cyclone)
74451: 04/10/11: Re: low cost MPEG4 codec (from Atmel )
74453: 04/10/11: Re: GLKP and GLKS
74460: 04/10/12: Re: newbie question
74555: 04/10/14: Re: GLKP and GLKS
74598: 04/10/14: Re: Xilinx to Make Image Processing FPGA
75452: 04/11/06: Re: USB2.0
75929: 04/11/19: Re: VHDL is correct but when burn into chip is not correct. Help me to solve this problem please
75931: 04/11/19: Re: digital analog conversion
75961: 04/11/20: Re: FPGA development board
75984: 04/11/21: Re: 18x18 Multipliers - Spartan III
76288: 04/11/30: Re: fpga prices
76298: 04/11/30: Re: RocketIO success?
76654: 04/12/08: Re: Xilinx Read First Write First
76774: 04/12/10: Re: What is the purpose of the 2 registers on A and B in the V4 Extreme DSP?
77804: 05/01/17: Re: What is the difference between ASIC and FPGA?.
77805: 05/01/17: Re: What is the difference between ASIC and FPGA?.
78996: 05/02/11: Re: Impact with Linux Kernel 2.6.x
79089: 05/02/14: Re: second flop in asyn reset distribution
80835: 05/03/12: Re: Spontaneous Board Reset
80839: 05/03/12: Re: XC3000 non-recoverable lockup problem
80942: 05/03/15: Re: XC3000 non-recoverable lockup problem
81200: 05/03/19: Re: XC3000 non-recoverable lockup problem
81204: 05/03/19: FCCM 2005 Final Call for Participation (note 3/20 deadline!)
81333: 05/03/22: Re: Block RAM Initialization - RAMB16_S2
81533: 05/03/26: Re: When will outsourcing hit FPGA'ers?
81566: 05/03/27: Re: A newbie question (Xilinx or Altera Env?)
81587: 05/03/28: Re: Multi-FPGA PCB data aggregation?
81653: 05/03/29: Re: XC3000 non-recoverable lockup problem
81711: 05/03/30: Re: FPGA programming via Slave-Serial-Mode
81733: 05/03/30: Re: XC3000 non-recoverable lockup problem
81781: 05/03/31: Re: XC3000 non-recoverable lockup problem
81888: 05/04/04: Re: how to use both FFs in a CLB's slice using LOC or RLOC
82166: 05/04/07: Re: Reverse engineering ASIC into FPGA
82340: 05/04/11: Re: Spartan II/E Configuration readback
82676: 05/04/16: Re: LUT in fpga
82693: 05/04/16: Re: sharing a common resource... potential problems...
83148: 05/04/25: Re: Relative number of CLBs
83175: 05/04/25: Re: Relative number of CLBs
83448: 05/04/29: Re: How to implement this C function in FPGA
83795: 05/05/07: Re: Using capacitor to slow the rise time.
83817: 05/05/07: Re: how can i join the comp.arch.fpga group
83853: 05/05/08: Re: Using capacitor to slow the rise time.
83950: 05/05/10: Re: dividing the clcok by 2.5
84041: 05/05/11: Re: Virtex4 running at 360Mhz DDR
84045: 05/05/11: Re: Xilinx VIIPro mixed configuration voltages
84106: 05/05/12: Re: Slice Virtex II = Equivalent gates ??
84474: 05/05/19: Re: How many logic cells are there in one slice
84475: 05/05/19: Re: floorplanning
84651: 05/05/24: Re: VHDL vs. Schematic Capture
84815: 05/05/28: Re: Accessing BRAM as a SRAM
84820: 05/05/28: Re: Accessing BRAM as a SRAM
84926: 05/06/01: Re: Xilinx DDR output registers
85085: 05/06/04: Re: Protecting IP in China
85377: 05/06/08: Re: Available under the terms of the SignOnce IP License
85620: 05/06/12: Re: [Vir2] Can I use a 18k ram as 2 single-port ram?
85621: 05/06/12: Re: Can I use a 18k ram as 2 single-port ram?
85633: 05/06/13: Re: Searching FPGA board for private use
85954: 05/06/19: Re: Ideal CPU for FPGA?
86162: 05/06/22: Re: Xilinx MacFir5.0 - Block Ram requirenments
86164: 05/06/22: Re: choosing an fpga board
86193: 05/06/22: Re: Xilinx MacFir5.0 - Block Ram requirenments
86716: 05/07/05: Re: proth siever in FPGA?
86859: 05/07/07: Re: Bit serial, book, other info???
86918: 05/07/09: Re: Timespec for DCM outputs (Spartan 3) ?
87294: 05/07/20: Re: July 20th Altera Net Seminar: Stratix II Logic Density
87431: 05/07/24: Re: Fastest way to compute floating point log and exp
87432: 05/07/24: Re: Overmapped
87762: 05/07/31: Re: some virtexII clock pads are useless??
88090: 05/08/09: Re: Spartan-3: Own P&R, generate bitstream from
88120: 05/08/10: Re: Spartan-3: Own P&R, generate bitstream from
88333: 05/08/15: Re: Clock generation
88521: 05/08/21: Re: What is the diffrences between lattice's FPGA and Xilinx's FPGA
88522: 05/08/21: Re: Why some firmware is made by lattice's FPGA instead of C language?
88609: 05/08/23: Re: Stdin / stdout through RS232
88727: 05/08/26: Re: Stdin / stdout through RS232
88790: 05/08/28: Re: mails from Aman Mediratta
88920: 05/08/31: Re: ZIF press-fit socket for QFP FPGA packages
89062: 05/09/04: Re: Spartan 3 Ram Instantiation
89309: 05/09/12: Re: future of antifuse fpgas?
89519: 05/09/17: Re: Reading a PAL fusemap with a microscope
89744: 05/09/24: Re: downlaoding bit files to Xilinx FPGA
90025: 05/10/03: Re: altera new bee
90148: 05/10/05: Re: Avoiding meta stability?
90177: 05/10/06: Re: Avoiding meta stability? No where in this thread...
90199: 05/10/06: Re: Avoiding meta stability? No where in this thread...
90470: 05/10/14: Re: Anyone remember the really early Xilinx FPGAs?
90477: 05/10/14: Re: Storing a file onto FPGA
90530: 05/10/16: Re: About with Synplify Pro?
90609: 05/10/17: Re: ADC implementation on fpga? Information and procudures wanted.
90709: 05/10/19: Re: Newbie question: XC3S400 Gate Count
91056: 05/10/28: Re: another FPGA/asic vendor dead :(
91059: 05/10/28: Re: another FPGA/asic vendor dead :(
91062: 05/10/28: Re: crc on only data or including the address
91129: 05/10/30: Re: Why are there two patents with same title
91281: 05/11/02: Re: crc code using vhdl found , few questions on it!!!
91300: 05/11/03: Re: FPGA : PCI-CORE
91504: 05/11/08: Re: Adder synthesis
91566: 05/11/09: Re: old xilinx components
92223: 05/11/24: Re: FPGA and metastability once again
92295: 05/11/25: Re: XST :division and mod in vhdl
92308: 05/11/27: Re: Virtex 4 Tapped Delay Lines
92341: 05/11/28: Re: Virtex 4 Tapped Delay Lines
92350: 05/11/28: Re: Virtex 4 Tapped Delay Lines
92739: 05/12/06: Re: Is it legal to write an logical equation for a FPGA LUT in claims of a patent?
93626: 05/12/27: Re: Looking for 64 bit IEEE802.3 Verilog code or tips for code
94203: 06/01/07: Re: What kind of cpu is suit for me?
94628: 06/01/15: Re: FPGA Journal Article
95150: 06/01/21: Re: need for a group FAQ?
95630: 06/01/25: Re: Starting with LVDS
95799: 06/01/26: Re: How to handle the "gate count" issue?
96044: 06/01/28: Re: [OT]Re: encryption
96269: 06/02/01: Re: Die Area
96450: 06/02/03: Re: Looking for literature on microprogrammed machines
96560: 06/02/06: Re: Tefzel or Kynar for PCB mods ?
96817: 06/02/11: Re: Altera EPLD
97214: 06/02/19: Re: equivalent time sampling
97244: 06/02/19: Re: FPGA - software or hardware?
97267: 06/02/20: Re: multiphase data extraction question
97524: 06/02/23: Re: DSP
97680: 06/02/26: Re: Combinatorial Division?
98362: 06/03/09: Re: what do the following constraints mean?
99025: 06/03/19: Re: Support software for XC3042
100565: 06/04/12: Re: FPGA FAQ and the spam problem
102239: 06/05/12: Re: Xilinx 3s8000?
102266: 06/05/12: Re: Crossing clock domains
104037: 06/06/17: Re: bga routing
104091: 06/06/19: Re: --.-Low Cost High quality pcb prototype and Assembly manufacturer(CHINA).
104140: 06/06/20: Re: Processor Design
104378: 06/06/26: Re: newbie wants to do VHDL on an FPGA
105208: 06/07/18: Re: Fastest platform to run ISE?
108314: 06/09/08: Re: 2 FF synchronizer
109345: 06/09/25: Re: What is the difference ?
109600: 06/09/30: Re: state machine dead problem
110772: 06/10/22: Re: Cheapest FPGA board to study VHDL on
110773: 06/10/22: Re: cross-post: newsgroup servers
110966: 06/10/26: Re: Meta-stable problem with MAX-II ?
110967: 06/10/26: Re: Am I seeing meta-stable or what?
111510: 06/11/04: Re: Dual-port BlockRAM "write first" puzzler...
113191: 06/12/07: Re: XC3020-50 board documentation
113907: 06/12/29: Re: ethernet checksum nightmare
114159: 07/01/05: Re: Surface mount ic's
116670: 07/03/15: Re: Xilin X-Fest Lunacy
124695: 07/09/30: Re: FPGA Archives
133004: 08/06/12: Re: HELP: a Funny asynchronous input design
133023: 08/06/13: Re: HELP: a Funny asynchronous input design
Philip Herzog:
113092: 06/12/06: Timing constraint on DCM input ignored after update ISE 8.1 -> 8.2?
115314: 07/02/07: Re: Multiple MicroBlaze based Multiprocessor system
116325: 07/03/07: Re: Where do I find CMOS image sensors and lenses?
125239: 07/10/18: VHDL trivia?
125242: 07/10/18: Re: VHDL trivia?
125281: 07/10/19: Re: VHDL trivia?
125283: 07/10/19: Re: VHDL trivia?
125292: 07/10/19: Re: VHDL trivia?
126176: 07/11/16: Re: jitter-sensitive multi-output clk distribution for multi-gigabit-transceivers
133356: 08/06/26: FPGA area use by module?
138433: 09/02/23: Re: Combining FPGA design with Microblaze
148429: 10/07/22: Re: WTB: Xilinx USB JTAG Cable
149815: 10/11/25: Re: Spartan3 device with long availability
153008: 11/11/11: Re: ASIC design job vs FPGA design job
154152: 12/08/22: Re: recruit FPGA design engineer in Scotland
155008: 13/03/27: Re: Xilinx tools for XC3020???
155498: 13/07/03: Re: Pure HDL Xilinx Zynq Arm Instantiation
Philip James-Roxby:
6762: 97/06/25: Re: Java and Giga Ops FPGA Boards
6869: 97/07/04: Re: EDIF for Xilinx tools
Philip Joe:
131939: 08/05/08: Re: PCI Express Switch
Philip Koopman:
20981: 00/03/01: Re: Extremely fault tolerant strategies
Philip Leong:
44925: 02/07/06: VHDL/FPGA research position at CUHK
Philip Martel:
86096: 05/06/21: Re: Xilinx
Philip Pemberton:
44976: 02/07/08: Getting started with FPGAs
45020: 02/07/10: Re: Getting started with FPGAs
49350: 02/11/10: Altera MAX7000E (EPM7128ELC84) - programmer?
49393: 02/11/11: Re: Altera MAX7000E (EPM7128ELC84) - programmer?
49678: 02/11/19: Re: Altera MAX7000E (EPM7128ELC84) - programmer?
88979: 05/09/01: Modelsim XE and multi-file Verilog projects
89039: 05/09/03: Modelling latches in Verilog
89053: 05/09/04: Re: Modelling latches in Verilog
93304: 05/12/19: Mixing XC9500 and XC9500XL, also small qty suppliers
93307: 05/12/19: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
93311: 05/12/20: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
93473: 05/12/22: Re: Mixing XC9500 and XC9500XL, also small qty suppliers
117732: 07/04/09: Clocking data into a shift register on positive AND negative edges
117746: 07/04/09: Re: Clocking data into a shift register on positive AND negative
137958: 09/02/03: Terasic DE1 - expansion port power ratings
142224: 09/07/29: Re: cool chart
143314: 09/10/01: Up-counter with async load/clear and overflow detection (Verilog)
143318: 09/10/01: Re: Up-counter with async load/clear and overflow detection
143321: 09/10/01: Re: Up-counter with async load/clear and overflow detection
143326: 09/10/02: Re: Up-counter with async load/clear and overflow detection
143327: 09/10/02: Re: Up-counter with async load/clear and overflow detection
143344: 09/10/03: Re: Up-counter with async load/clear and overflow detection
144290: 09/11/25: Going mad trying to solve PLL setup/hold timing violation issues in
144295: 09/11/25: Re: Going mad trying to solve PLL setup/hold timing violation
144298: 09/11/25: Re: Going mad trying to solve PLL setup/hold timing violation
144320: 09/11/26: Re: Going mad trying to solve PLL setup/hold timing violation
146967: 10/04/05: A few LatticeMico32 questions
146974: 10/04/07: Re: A few LatticeMico32 questions
147559: 10/05/03: ISE 11.1 - readmemh issues
147563: 10/05/03: Re: ISE 11.1 - readmemh issues
147728: 10/05/19: Problems inferring blockram in ISE12.1
147739: 10/05/21: Debugging SDRAM interfaces
147741: 10/05/21: Re: Debugging SDRAM interfaces
147752: 10/05/21: Re: Debugging SDRAM interfaces
147754: 10/05/21: Re: Debugging SDRAM interfaces
147766: 10/05/23: Re: Debugging SDRAM interfaces
147772: 10/05/23: Re: Debugging SDRAM interfaces
147773: 10/05/23: Do Xilinx really want people to report INTERNAL_ERRORs?
147775: 10/05/24: Re: Do Xilinx really want people to report INTERNAL_ERRORs?
147785: 10/05/24: Re: Debugging SDRAM interfaces
147817: 10/05/25: Re: Xilinx Xact software for XC2018 Logic Cell Array
147819: 10/05/25: Re: Software bloat (Larkin was right)
148039: 10/06/15: Decoupling for Altera Cyclone II 2C8
148350: 10/07/13: WTD: WISHBONE SDRAM interface or some Vlog HDL synthesizing...
148352: 10/07/13: Re: WTD: WISHBONE SDRAM interface or some Vlog HDL synthesizing...
148391: 10/07/17: Re: WTD: WISHBONE SDRAM interface or some Vlog HDL synthesizing...
148642: 10/08/11: Spartan3a: improving DCM performance and "To achieve optimal
148648: 10/08/12: Re: Spartan3a: improving DCM performance and "To achieve optimal
148650: 10/08/12: Re: Spartan3a: improving DCM performance and
149720: 10/11/20: Debugging with a single LED
149754: 10/11/22: Re: Debugging with a single LED
149782: 10/11/24: Re: Debugging with a single LED
149784: 10/11/24: Altera EP2C8A -- dead PLL
149793: 10/11/24: Re: Altera EP2C8A -- dead PLL
149799: 10/11/24: Re: Altera EP2C8A -- dead PLL
153192: 12/01/06: Handling overflow in a self-repeating frequency counter
153204: 12/01/06: Re: Handling overflow in a self-repeating frequency counter
Philip Potter:
122233: 07/07/24: Spurious NULs using uartlite
122895: 07/08/09: SystemACE, xilfatfs and feof()
122989: 07/08/13: Problems using xilfatfs on XUP V2Pro board
122992: 07/08/13: Re: Problems using xilfatfs on XUP V2Pro board
124268: 07/09/17: Re: Guess: what is the largest number of state machines in a current
125087: 07/10/16: Re: FPGA quiz: what can be wrong
125106: 07/10/16: Re: FPGA quiz: what can be wrong
125186: 07/10/17: xil_printf and %u specifier
125211: 07/10/18: Re: xil_printf and %u specifier
125227: 07/10/18: Re: xilinx Edititons
125584: 07/10/29: Re: FPGA vs ASIC
125613: 07/10/30: Re: FPGA vs ASIC
125938: 07/11/09: EDK 9.2 install problem
126017: 07/11/12: Re: Students: where to go for help
126037: 07/11/13: Re: Students: where to go for help
126045: 07/11/13: Re: EDK 9.2 install problem
126147: 07/11/15: Re: EDK 9.1 Issues
126351: 07/11/20: Re: EDK 9.2 and virtex 2 devices
126360: 07/11/20: Re: EDK 9.2 and virtex 2 devices
129104: 08/02/14: Microblaze 7.0 on V2pro?
129114: 08/02/14: Re: Microblaze 7.0 on V2pro?
129150: 08/02/15: Re: Microblaze 7.0 on V2pro?
129487: 08/02/26: Re: Interview questions
129496: 08/02/26: Re: Interview questions
129543: 08/02/27: Re: Interview questions
130511: 08/03/26: Re: Power Estimation of Microblaze (Power PC) based architectures
131477: 08/04/22: Re: Newbie: Testbench question
131574: 08/04/25: Re: noob question
Philip Ryan:
7635: 97/09/30: Synthesis and module generation for FPGAs.
Philip S.W.C Toms:
44931: 02/07/06: Re: 3.3 volt tolerance in Virtex-II Pro?
PHILIP TSANG:
7786: 97/10/15: Previous FPGA articles
<philip.freidin@fpga-faq.com>:
68334: 04/04/01: Re: How to advertise in www.fpga-faq.com/FPGA_Boards.shtml
PhilipKD:
29191: 01/02/09: what exactly is the dff between fpga and cpld?
29208: 01/02/09: Re: what exactly is the dff between fpga and cpld?
<philipnchill@gmail.com>:
157944: 15/05/19: Re: AHDL VS. VHDL
Philipp:
22022: 00/04/13: Demo - board
78703: 05/02/06: How to fix this synthese warnings?
78707: 05/02/06: Re: How to fix this synthese warnings?
78737: 05/02/07: Re: warning messages,NgdBuild:454,DesignRules:331
78762: 05/02/07: Mixed Language synthese Microblaze
79109: 05/02/14: Weird Mircroblaze programm execution
79152: 05/02/15: Re: Weird Mircroblaze programm execution
79159: 05/02/15: Re: Weird Mircroblaze programm execution
84157: 05/05/13: Whats going on here?
126368: 07/11/20: Virtex5 Evaluation Board
126373: 07/11/20: Re: Virtex5 Evaluation Board
126377: 07/11/20: Why doesnt XST RAM for this VHDL description
126379: 07/11/20: Re: Why doesnt XST RAM for this VHDL description
126382: 07/11/20: Re: Why doesnt XST RAM for this VHDL description
126433: 07/11/22: PCI Mezzanine Card with Xilinx Virtex-II
126439: 07/11/22: Re: PCI Mezzanine Card with Xilinx Virtex-II
126447: 07/11/22: Re: PCI Mezzanine Card with Xilinx Virtex-II
126544: 07/11/27: Xilinx Multilink Connection not working
126550: 07/11/27: Re: Xilinx Multilink Connection not working
127962: 08/01/11: FPGA evaluation board with > 32K slices
127963: 08/01/11: Re: FPGA evaluation board with > 32K slices
128173: 08/01/17: Chipscope compatible with Synopsis or Cadence sythesise tools?
128176: 08/01/17: Re: Chipscope compatible with Synopsis or Cadence sythesise tools?
128177: 08/01/17: Re: Chipscope compatible with Synopsis or Cadence sythesise tools?
128183: 08/01/17: Re: Chipscope compatible with Synopsis or Cadence sythesise tools?
136030: 08/10/28: Register File distributed all over the FPGA
136032: 08/10/28: Re: Register File distributed all over the FPGA
136036: 08/10/28: Re: Register File distributed all over the FPGA
136037: 08/10/28: Re: Register File distributed all over the FPGA
136050: 08/10/29: Re: Register File distributed all over the FPGA
136052: 08/10/29: Re: Register File distributed all over the FPGA
136057: 08/10/29: Re: Register File distributed all over the FPGA
136060: 08/10/29: Re: Register File distributed all over the FPGA
136061: 08/10/29: Re: Register File distributed all over the FPGA
136072: 08/10/30: Re: Register File distributed all over the FPGA
136075: 08/10/30: Re: Register File distributed all over the FPGA
136538: 08/11/21: Student FPGAs
Philipp Falke:
135822: 08/10/16: Comparing power consumption of two different processor designs
Philipp Georg:
2675: 96/01/23: HowTo access a SRAM with a XC4000
Philipp Grabher:
77562: 05/01/11: synthesizable RAM problem
78069: 05/01/24: EDK6.2i - Error message during PlatGen after adding in HDL files to User IP core
78375: 05/01/31: EDK 6.2 Synthese Error
83365: 05/04/28: MIcroblaze FSL Datasheet
83494: 05/05/01: Microblaze FSL interface timing diagram
Philipp Hachtmann:
110533: 06/10/17: Picoblaze + Blockram + Data3Mem = help needed
110536: 06/10/17: Re: Picoblaze + Blockram + Data3Mem = help needed
120222: 07/06/04: Problem with System ACE
120245: 07/06/04: Re: Problem with System ACE -> Solved!
132359: 08/05/23: Software instabilities with EDK 10.01 and PPC405?!??!!!
132382: 08/05/24: Re: Software instabilities with EDK 10.01 and PPC405?!??!!!
132399: 08/05/26: Re: Software instabilities with EDK 10.01 and PPC405?!??!!!
132487: 08/05/29: Re: Software instabilities with EDK 10.01 and PPC405?!??!!!
133437: 08/06/29: EDK DMA peripherals?
134358: 08/08/07: ML403, U-Boot+Linux and Ethernet?
134402: 08/08/09: Re: ML403, U-Boot+Linux and Ethernet?
134493: 08/08/13: Again: EDK10.1 and TEMAC - I'm despairing
145432: 10/02/09: Re: using an FPGA to emulate a vintage computer
Philipp Jacobsohn:
Philipp Klaus Krause:
100461: 06/04/10: Re: C-Compiler for free VHDL controller core ?
101359: 06/04/29: Re: What would be the tariff classification of an FPGA development
101366: 06/04/29: Re: What would be the tariff classification of an FPGA development
120123: 07/06/01: Cyclone 3 Starter Board connector?
122422: 07/07/27: Re: completely open source fpga toolchain
122517: 07/07/30: Re: completely open source fpga toolchain
122547: 07/07/31: Looking for PLD with embedded memory
122548: 07/07/31: Re: Looking for PLD with embedded memory
122556: 07/07/31: Re: Looking for PLD with embedded memory
122559: 07/07/31: Re: Looking for PLD with embedded memory
122692: 07/08/03: Re: Looking for PLD with embedded memory
124922: 07/10/10: Re: What happened to Confluence and HDCaml?
124929: 07/10/11: Re: What happened to Confluence and HDCaml?
124930: 07/10/11: Re: What happened to Confluence and HDCaml?
132723: 08/06/05: Re: Xilinx vs Altera
136404: 08/11/14: What happened to the Cyclone IV?
136418: 08/11/15: Re: What happened to the Cyclone IV?
144024: 09/11/08: Re: free software/open source projects and FPGA?
147204: 10/04/18: Re: Which 32 bit cores support full Linux?
148174: 10/06/25: Re: fooling the compiler
150715: 11/02/05: Why is the Cyclone IV so expensive?
154660: 12/12/13: Re: Where to move for an embedded software engineer.
155805: 13/09/18: Re: Legal Issues Reproducing Old CPU
156425: 14/04/04: Tristates in synthesis
156571: 14/05/03: Free alternatives to Xilinx iMPACT?
156577: 14/05/04: Re: Free alternatives to Xilinx iMPACT?
158088: 15/08/05: Re: Finally! A Completely Open Complete FPGA Toolchain
158100: 15/08/06: Re: Finally! A Completely Open Complete FPGA Toolchain
158124: 15/08/13: Re: Finally! A Completely Open Complete FPGA Toolchain
158128: 15/08/13: Re: Finally! A Completely Open Complete FPGA Toolchain
161108: 19/02/03: Re: Open Source Synthesis Tools
161244: 19/03/20: Re: Tiny CPUs for Slow Logic
Philipp Krause:
33269: 01/07/21: free VHDL and/or Verilog tools?
35861: 01/10/21: Re: I search a free 8086 core...
36259: 01/11/04: Re: 64-bit PCI core for Lattice CPLD?
52311: 03/02/06: Re: difference between pci2.1 and pci2.2
Philippe:
40766: 02/03/14: Re: 32-taps FIR !
44942: 02/07/07: Re: Fixed point arithmetic
146545: 10/03/22: Why hardware designers should switch to Eclipse
146574: 10/03/23: Re: Why hardware designers should switch to Eclipse
146604: 10/03/23: Re: Why hardware designers should switch to Eclipse
149816: 10/11/25: Re: Brain Cramps...
150837: 11/02/15: Most popular VHDL/Verilog
150935: 11/02/23: Re: Most popular VHDL/Verilog
151117: 11/03/08: Anti-benchmarking clauses
151133: 11/03/09: Re: Anti-benchmarking clauses
Philippe Bataille:
45887: 02/08/09: RAM simlulation with WebPack4.2
Philippe Chagny:
27498: 00/11/24: FPGA Express warning ???
Philippe Faes:
153892: 12/06/24: Call for beta users for Sigasi integration with Altera Quartus
Philippe Molson:
54791: 03/04/17: Re: Advice on FPGA IIR Filter
56615: 03/06/10: Re: Fixed point divider cores?
Philippe Robert:
19833: 00/01/13: DDC Core for FPGA
35582: 01/10/11: Dual Port Fifo for Virtex II
36463: 01/11/09: Decoupling capacitors on Virtex II
36680: 01/11/15: Re: Decoupling capacitors on Virtex II
36858: 01/11/22: Re: Decoupling capacitors on Virtex II
38412: 02/01/14: Hard macro for Xilinx FPGA
38419: 02/01/14: test
40965: 02/03/19: Unused I/Os + External Clock on Virtex II
41864: 02/04/09: Excel Sheet for Virtex-II power estimation
42265: 02/04/19: Virtex-II core power supply
43005: 02/05/09: Re: clock multiplication in xilinx
43206: 02/05/16: XC95108+XC4036EX
43565: 02/05/24: SDRAM controler for Virtex-II
43671: 02/05/29: LOC constraint
44588: 02/06/24: Driving memory with an FPGA
44665: 02/06/26: IBIS simulator
49299: 02/11/08: Modular Design for Project Manager 5.1.02
<philippe.faes@gmail.com>:
140585: 09/05/19: Sigasi Public Beta: future of VHDL design
140595: 09/05/19: Re: Sigasi Public Beta: future of VHDL design
<philippe_molson@my-deja.com>:
20223: 00/02/01: Re: DDC Core for FPGA
Philipper CHAGNY:
42724: 02/05/01: free core DSTN LCD controller VHDL?
<PhilippeThomas>:
74722: 04/10/18: Re: How can FPGAs be used for high speed data acquisition????
Phillip:
36141: 01/10/31: Re: Clock attribute problem
Phillip Cook:
11689: 98/09/01: Wait statements and while loops
11702: 98/09/02: Re: Wait statements and while loops
Phillip Roberts:
503: 94/12/12: FPGA Design Consulting Service Available
536: 94/12/27: Re: multipliers!
1330: 95/06/02: Re: AT&T serial EEPROMS
Philllip Cook:
11419: 98/08/12: Power Consumption
Phlip:
87334: 05/07/21: Re: Best Practices to Manage Complexity in Hardward/Software Design?
87381: 05/07/22: Re: Best Practices to Manage Complexity in Hardward/Software Design?
pho:
88627: 05/08/24: Send IP packets at the Ethernet level with VIRTEX4
phoenix:
102069: 06/05/10: jhdlbits: source files
113016: 06/12/05: Readback Jtag Problem
113098: 06/12/06: Re: Readback Jtag Problem
phoenix3051:
78954: 05/02/10: Problem with JBits 3.0 Tutorial
78970: 05/02/10: Re: Problem with JBits 3.0 Tutorial
<phony@see.sig.for.real>:
4717: 96/12/05: Re: Looking for hc0324
4833: 96/12/19: Re: Exemplar's Leonardo on Linux
<phooey>:
113784: 06/12/21: How to simulate from the xilinx ISE
Phunjapa Ruangsinsup:
24385: 00/08/06: Asynchronous circuit on FPGA
24406: 00/08/07: Can i see Gate-delay and Interconnection-delay of circuit on FPGA and where??
24472: 00/08/10: Where i can found Gate-delay or CLB internal-delay
phuture_project:
71662: 04/07/27: Re: New WinFilter Digital Filter design freeware tool release available.
71676: 04/07/27: Re: New WinFilter Digital Filter design freeware tool release available.
phw:
9598: 98/03/25: Architectures, Languages and Patterns (Final Call)
<phxagent@gmail.com>:
133498: 08/07/01: How do I program an fpga once it has been designed and layout is
133506: 08/07/01: Re: How do I program an fpga once it has been designed and layout is
133516: 08/07/01: Re: How do I program an fpga once it has been designed and layout is
Pi:
82293: 05/04/10: Re: Reverse engineering masked ROMs, PLAs
piaoliuren:
41048: 02/03/20: Re: the server to access to this newgroup
PicInfo:
6823: 97/06/30: Re: Smart Card Design and Interface. How?
<picnanard@yahoo.fr>:
130237: 08/03/18: to view vhdl variable with gtkwave
130241: 08/03/18: Re: to view vhdl variable with gtkwave
130263: 08/03/19: Re: to view vhdl variable with gtkwave
pico:
79358: 05/02/17: Re: C compiler for Picoblaze
Pictographer:
145186: 10/01/31: Re: DPA vs FPGA Security?
Pier Paolo:
19367: 99/12/16: Foundation 2.1 GTS problem
Pierce Chen:
23724: 00/07/06: 3.3v supply 2.5v chips
Piergiorgio Sartor:
85962: 05/06/19: Re: Idea exploration - Image stabilization by means of software.
Pierpaolo:
146704: 10/03/26: Wrong DDR communication
146890: 10/03/31: Re: Wrong DDR communication
Pierre:
80551: 05/03/08: malloc doesn't work when I use OCM (with Virtex II Pro and PPC405)
85240: 05/06/07: PowerPC crash down
85276: 05/06/07: Re: PowerPC crash down
86503: 05/06/29: read & write on SDRAM speed with PPC 300 MHz
86504: 05/06/29: read & write on SDRAM speed with PPC 300 MHz
86684: 05/07/04: Re: read & write on SDRAM speed with PPC 300 MHz
88633: 05/08/24: Spartan and Flash PROM : Boundary Scan
93950: 06/01/03: Re: S3e starter kits available
Pierre Cluzel:
3003: 96/03/12: Xact6.o too slow
Pierre de Vos:
34158: 01/08/15: DPLL frequency synthesis
69194: 04/04/29: Re: Altera ByteBlaster II schematic
88879: 05/08/30: LCD Interface
88888: 05/08/31: Re: LCD Interface
Pierre Lafrance:
47171: 02/09/19: Re: C\C++ to VHDL Converter
47174: 02/09/19: Overheat with XCV-600E
47309: 02/09/23: Re: Overheat with XCV-600E
47525: 02/09/27: Re: Looking for a dead Virtex
49099: 02/10/31: Simple question on Xilinx CPLD 9500
75134: 04/10/26: Re: Small survey for Handel-C writer
74908: 04/10/21: Small survey for Handel-C writer
Pierre Langlois:
15013: 99/03/03: keeping mapping information - VHDL based design
15014: 99/03/03: experience with Xilinx 4K series I/Os
15343: 99/03/19: FPGA vendor comparison
15551: 99/03/30: FPGAs with ECL-compatible I/Os
Pierre Ragon:
9411: 98/03/11: Re: Whats wrong with this method
Pierre VERNEL:
19938: 00/01/19: configurable 8-16 bits processor IP
27535: 00/11/28: hard or soft core for FPGA?
Pierre Wadier:
71686: 04/07/27: Re: ramdon noise generation
Pierre-François (f5bqp_pfm):
136035: 08/10/28: Re: TimingAnalyzer beta version 0.90 -- beta testers wanted
136044: 08/10/29: Re: TimingAnalyzer beta version 0.90 -- beta testers wanted
Pierre-Jules Tremblay:
26: 94/07/29: Re: Welcome new XILINX users
Pierre-Louis:
68749: 04/04/16: how to pass a date user code from Synplify to Quartus?
73683: 04/09/28: Altera Apex20KE -x pll problem
Pierre-Olivier Laprise:
46726: 02/09/06: Virtex-II bit-file and strange configuration command
46870: 02/09/10: Re: C/C++ to Verilog/VHDL ?!
47287: 02/09/22: Re: Spartan II JTAG reconfiguration bug - workaround
48867: 02/10/25: Re: Virtex2 5V tolerant I/O ??
49805: 02/11/21: Re: Metastability in FPGAs
49827: 02/11/21: Re: Metastability in FPGAs
50249: 02/12/06: Re: HowTo 'freeze' a placement
Pierre-Yves BRETECHER:
7689: 97/10/02: Pin allocation on ALTERA FLEX10K
Pierrick:
86700: 05/07/04: Re: FPGA development board - urgently
124884: 07/10/09: Re: FFT core
124891: 07/10/09: Re: FFT core
124908: 07/10/10: Re: FFT core
Piet du Toit:
4487: 96/11/05: Re: XACT under WinNT is very slow
6907: 97/07/08: Xilinx Prom Generation Problem
<piet@parsec.co.za>:
76551: 04/12/06: Re: quartus and pll
Pieter Hulshoff:
8363: 97/12/10: Z80 in FPGA: clockspeed?
53381: 03/03/12: Re: RESET --- Synchronous Vs Asynchronous
53878: 03/03/26: Re: How to avoid this Latch
74219: 04/10/06: Re: Changing clock domain
Pieter Op de Beeck:
17628: 99/08/16: fpga board : make it or buy it?
17645: 99/08/18: multiplier Virtex
Pieter Op De Beeck:
15843: 99/04/16: std_logic_arith
Pietro Carratu':
2441: 95/12/05: Search for programs implementing Finite State Machine
Piggy:
28979: 01/01/31: How to program FPGA with PROTEL? (ORCA OR2C06 serie)
piiszo:
38964: 02/01/28: random
39071: 02/01/30: Re: random
pillar2012@gmail.com:
130707: 08/03/30: Re: Webpack 10.1 on 64-bit linux
130744: 08/03/31: Re: Webpack 10.1 on 64-bit linux
130898: 08/04/04: Re: Webpack 10.1 on 64-bit linux
Pillock:
128218: 08/01/18: Re: effect of xray on fpga electronic circuits
128484: 08/01/28: Re: effect of xray on fpga electronic circuits
128486: 08/01/28: Re: effect of xray on fpga electronic circuits
<pilot172@gmail.com>:
83064: 05/04/22: Re: OCM interface to SDRAM
83073: 05/04/22: Re: OCM interface to SDRAM
pilwoochun@rogers.com:
97824: 06/02/28: 32 bit select map
Pinco Pallino:
50216: 02/12/05: external ACEX DMA controller interfacing to a StrongArm prob.
Pine:
71525: 04/07/20: xilinx ngdbuild old command flow problem
71681: 04/07/27: Re: xilinx ngdbuild old command flow problem
<pineji@my-deja.com>:
28472: 01/01/14: Re: FPGA to ASIC conversion
28473: 01/01/14: Re: async interface
28471: 01/01/14: Re: Newbie question on clock timing generation
28469: 01/01/14: Re: APEX
28470: 01/01/14: Re: HELP: Problem with interfacing an Altera MAX7000 device to the ISA bus
pingboypulsar<spamoff>@hotmail.com:
90560: 05/10/17: ADC implementation on fpga? Information and procudures wanted.
90563: 05/10/17: Re: ADC implementation on fpga? Information and procudures wanted.
90568: 05/10/17: Re: ADC implementation on fpga? Information and procudures wanted.
90571: 05/10/17: Re: ADC implementation on fpga? Information and procudures wanted.
90577: 05/10/17: Re: ADC implementation on fpga? Information and procudures wanted.
Pinhas:
25389: 00/09/09: Re: timing simulation vs functional one
89751: 05/09/24: Re: Modelsim XE, what's the latest version?
121401: 07/07/03: USB full speed final project proposal
122911: 07/08/10: I2C master connected and tested with LEON Processor
134442: 08/08/10: Re: Newbie question : Xilinx Webpack examples
134467: 08/08/12: SDIO open source code
135796: 08/10/15: Re: free cpu 8051 verilog code
136597: 08/11/24: Extracting data from a VCD waveform format.
136630: 08/11/26: Re: Infer Dual Port Block ROM for Xilinx FPGA
Pinhas Krengel:
25453: 00/09/12: Re: Clock skew in XILINX CPLD
<pinhas@my-deja.com>:
28104: 00/12/21: synchronize and split reset
28181: 00/12/25: Actel DeskTop Design Tool Set
pini:
31694: 01/06/03: Re: [Q]setup-time violation
65818: 04/02/06: Re: need desperate help!
Pini:
23454: 00/06/26: Re: I need an advice here pls!
25676: 00/09/17: Re: Reassurance on Xilinx Sought
69125: 04/04/28: Data transfer for real time analysis
69196: 04/04/29: Re: Data transfer for real time analysis
pini_45:
147433: 10/04/27: Re: Free VHDL or Verilog Simulator
147434: 10/04/27: Re: Writing Hex values to file in VHDL?
147437: 10/04/27: Re: Ethernet development kit
147438: 10/04/27: Re: Ethernet development kit
147441: 10/04/27: Re: Reading UDP with FPGA
147461: 10/04/27: Re: VHDL vs Verilog
147462: 10/04/27: vhdl versus verilog
147476: 10/04/28: Re: Icarus Verilog opinions
147483: 10/04/28: share a script for GTK vcd wave viewer
147484: 10/04/28: Re: Controlling the I2C master from Opencores.org
pini_kr:
155705: 13/08/11: Is a block spoof IP filter in hardware is required
156553: 14/04/26: Re: How to implement Ethernet packet classification with vhdl on FPGA? does any one has vhdl code or reference? Thank you.
157043: 14/09/13: Re: Know any good public FPGA projects to contribute to?
157044: 14/09/13: Re: VHDL gate level from Xilinx XST
157045: 14/09/13: Re: Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments
157046: 14/09/13: Re: VHDL comments in Vim?
157047: 14/09/13: Re: Good VHDL reference?
157048: 14/09/13: Re: Free VHDL or Verilog Simulator
157838: 15/04/11: does anybody use systemc in FPGA flow?
pinkisntwell:
146197: 10/03/08: Using the SignalTap Logic Analyzer
pinkotronic:
89587: 05/09/20: problem with Thold violation under quartus
pinku:
97361: 06/02/21: How to use Gigabit transciever
97435: 06/02/22: configuring stratix GX Fpga
98798: 06/03/16: SDRAM controller selection
99955: 06/03/31: Doubt about SERDES
100084: 06/04/03: Re: Doubt about SERDES
100087: 06/04/03: virtual slot implementation
103407: 06/06/01: Ethernet Snooping in the FPGA
103983: 06/06/16: Hold margin for asynchronous Interface
<pinku1979@gmail.com>:
110308: 06/10/13: DDR SDRAM static timing analysis
Pino:
70763: 04/06/26: How to Connect User-Defined Master Peripheral to SDRAM Slave Peripheral in SOPC Builder
70832: 04/06/29: Altera SOPC Master Peripheral Design?
70925: 04/07/01: Re: Altera SOPC Master Peripheral Design?
70926: 04/07/01: Re: Altera SOPC Master Peripheral Design?
71260: 04/07/13: Re: Altera SOPC Master Peripheral Design?
71264: 04/07/13: Altera SOPC SDRAM & CLK Input?
71335: 04/07/14: Re: Altera SOPC SDRAM & CLK Input?
71336: 04/07/14: Re: micron sdram module
71449: 04/07/18: Re: Altera SOPC SDRAM & CLK Input?
71450: 04/07/18: Altera Avalon Bus Signal Monitoring?
71480: 04/07/19: Re: How Bidirectional (AHDL) or INOUT (VHDL) are displayed in the Waveform Simulation?
71789: 04/07/30: Altera Bidi ports, Tristate Buffers & Prop. Delay?
71817: 04/07/31: Re: Altera Bidi ports, Tristate Buffers & Prop. Delay?
72064: 04/08/06: Re: Altera Bidi ports, Tristate Buffers & Prop. Delay?
72389: 04/08/17: Re: Altera Bidi ports, Tristate Buffers & Prop. Delay?
72733: 04/08/30: Re: Nios Development Kit, STRATIX Edition
72869: 04/09/06: Altera Quartus FSM Simulation Delay?
72874: 04/09/06: Altera Master Peripheral & Avalon Bus Timing?
73087: 04/09/13: Re: Altera Quartus FSM Simulation Delay?
74176: 04/10/05: Re: Altera SDRAM controller - Only 2 words burst???
pinod01@sympatico.ca:
106042: 06/08/06: Counter status flags don't stay asserted not sure why?
106111: 06/08/07: Re: Counter status flags don't stay asserted not sure why?
109329: 06/09/24: Altera Avalon Bus VHDL stop error?
109358: 06/09/25: Re: Altera Avalon Bus VHDL stop error?
<pinod01@sympatico.ca>:
87752: 05/07/30: Altera Avalon Address format between Master & SDRAM controller?
88294: 05/08/14: VHDL Array indexing Issue in Modelsim
88349: 05/08/15: Re: VHDL Array indexing Issue in Modelsim
88769: 05/08/27: Altera Avalon Master/Slave User Defined Logic?
89764: 05/09/25: Altera_VHDL_support library into Modelsim?
89785: 05/09/26: Re: vhdl state maching problem
89786: 05/09/26: Re: Altera_VHDL_support library into Modelsim?
89793: 05/09/26: Re: Altera_VHDL_support library into Modelsim?
89889: 05/09/29: Altera SOPC testbenching in Modelsim?
90350: 05/10/10: Compiling Altera LPM FIFO into Modelsim Error
90593: 05/10/17: Re: Compiling Altera LPM FIFO into Modelsim Error
Piotr:
44023: 02/06/10: OFFSET constraint for internal clock
Piotr Foryt:
46511: 02/09/02: Re: problem configration spartan2 with prom.
Piotr Wiszowaty:
87853: 05/08/02: Re: Xilinx 7.1, Kernel 2.6 and modules for install_driver_installscript
Piotr Wyderski:
79136: 05/02/15: Cyclone clock
79154: 05/02/15: Re: Cyclone clock
79155: 05/02/15: Re: Cyclone clock
79287: 05/02/16: Re: Cyclone clock
79437: 05/02/19: Nios performance
79441: 05/02/19: Re: Nios performance
79468: 05/02/19: Re: Nios performance
79480: 05/02/20: Re: why to use FIFO on FPGA?
80874: 05/03/13: Which HDL?
80920: 05/03/14: Re: Which HDL?
80922: 05/03/14: Re: Which HDL?
80974: 05/03/15: Re: Which HDL?
81195: 05/03/19: Re: Spartan 3E vs. Cyclone2
81240: 05/03/20: Re: Spartan 3E vs. Cyclone2
81285: 05/03/21: Re: Spartan 3E vs. Cyclone2
81312: 05/03/21: Re: Spartan 3E vs. Cyclone2
81316: 05/03/21: Free simulator
81472: 05/03/24: Re: Free simulator
81538: 05/03/26: Bus expansion
81597: 05/03/29: Re: Multi-FPGA PCB data aggregation?
81712: 05/03/30: Re: exp(-x) function
81849: 05/04/02: [info] Sine generation
81899: 05/04/04: Re: [info] Sine generation
82700: 05/04/16: Power supply design
83798: 05/05/07: Re: 40% less SEU's! in V4: another good reason to choose Xilinx
83800: 05/05/07: Which chip should I use?
83822: 05/05/07: Re: Which chip should I use?
83825: 05/05/07: Re: Which chip should I use?
83856: 05/05/08: Re: Which chip should I use?
83859: 05/05/08: Re: Which chip should I use?
83953: 05/05/10: Re: Which chip should I use?
83954: 05/05/10: Re: Which chip should I use?
84210: 05/05/14: Re: "Mine is bigger than yours..."
84226: 05/05/15: Serial communication
84727: 05/05/25: Single-endec clocks
84738: 05/05/25: Re: Single-endec clocks
84759: 05/05/26: Re: Single-endec clocks
84768: 05/05/26: Re: Single-endec clocks
84797: 05/05/27: Re: ethernet
84798: 05/05/27: Re: ethernet
84896: 05/05/31: Re: Implementing sin function in fpga
84901: 05/05/31: Re: Implementing sin function in fpga
84935: 05/06/01: Re: Implementing sin function in fpga
85043: 05/06/03: XP for NIOS2
85108: 05/06/04: Re: re:XP for NIOS2
85145: 05/06/06: Re: XP for NIOS2
85185: 05/06/06: Re: XP for NIOS2
85186: 05/06/06: Re: XP for NIOS2
85991: 05/06/20: Re: Ideal CPU for FPGA?
86050: 05/06/21: Re: damage Atmel AT40k/AT94k with wrong bitstream?
86060: 05/06/21: Re: damage Atmel AT40k/AT94k with wrong bitstream?
86098: 05/06/22: Re: FPGAs: Where will they go?
86411: 05/06/27: Good FPGA for an encryptor
86452: 05/06/28: Re: Good FPGA for an encryptor
86453: 05/06/28: Re: Good FPGA for an encryptor
86454: 05/06/28: Re: Good FPGA for an encryptor
86459: 05/06/28: Re: Good FPGA for an encryptor
86460: 05/06/28: Re: Good FPGA for an encryptor
86463: 05/06/28: Re: Good FPGA for an encryptor
86465: 05/06/28: Re: Good FPGA for an encryptor
86466: 05/06/28: Re: Good FPGA for an encryptor
86467: 05/06/28: Re: Good FPGA for an encryptor
86536: 05/06/29: Re: Good FPGA for an encryptor
86601: 05/06/30: Re: Good FPGA for an encryptor
86633: 05/07/01: Re: Good FPGA for an encryptor
89760: 05/09/25: Cyclone on a shared configuration bus
92991: 05/12/11: About Spartan 3
93587: 05/12/25: Spartan 3 power requirements
93589: 05/12/25: Re: Spartan 3 power requirements
93591: 05/12/25: Re: Spartan 3 power requirements
93647: 05/12/27: Re: Place and Route Algorithms
93686: 05/12/28: Lattice XP simple simulator
94596: 06/01/14: Re: FPGA Journal Article
95107: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95112: 06/01/21: Re: OT:Shooting Ourselves in the Foot
96863: 06/02/12: Spartan3 configuration
101748: 06/05/05: Re: LVDS inputs on Cyclone II
101785: 06/05/06: Re: FPGA-based hardware accelerator for PC
101788: 06/05/07: Re: DRC has announced its newest FPGA that drops into AMD's Socket 940
101815: 06/05/07: Re: FPGA-based hardware accelerator for PC
101919: 06/05/08: Re: FPGA-based hardware accelerator for PC
101920: 06/05/08: Re: FPGA-based hardware accelerator for PC
102291: 06/05/14: Spartan 3E
102294: 06/05/14: Re: Spartan 3E
102707: 06/05/19: Re: DCM and Clock
102777: 06/05/20: Re: Spartan 3E
102778: 06/05/20: Re: ispLEVER Starter 6.0 FPGA Design Software Available
102861: 06/05/22: Re: ispLEVER Starter 6.0 FPGA Design Software Available
113959: 06/12/30: Memory controller design
113963: 06/12/31: Re: Memory controller design
113970: 06/12/31: Re: Memory controller design
128259: 08/01/19: Re: Source of accurate frequency
149780: 10/11/24: Re: Atom 6000C perspective, anyone?
149814: 10/11/25: Re: Atom 6000C perspective, anyone?
159844: 17/04/11: Re: FPGA as heater
160492: 18/02/18: Is Zynq7000 leaky?
160495: 18/02/18: Re: Is Zynq7000 leaky?
160498: 18/02/18: Re: Is Zynq7000 leaky?
160502: 18/02/20: Re: Is Zynq7000 leaky?
160555: 18/04/14: FPGA selection recommendation
160557: 18/04/14: Re: FPGA selection recommendation
160560: 18/04/14: Re: FPGA selection recommendation
160562: 18/04/14: Re: FPGA selection recommendation
160564: 18/04/14: Re: FPGA selection recommendation
161180: 19/02/23: Cyclone V decimation
161183: 19/02/23: Re: Cyclone V decimation
161185: 19/02/23: Re: Cyclone V decimation
161188: 19/02/24: Re: Cyclone V decimation
161190: 19/02/25: Re: Cyclone V decimation
161196: 19/03/01: Re: Cyclone V decimation
161353: 19/04/22: FIFO timing, the right way
161356: 19/04/22: Re: FIFO timing, the right way
<piotr.nowak21@gmail.com>:
128325: 08/01/22: Problem with UART EDK 9.2.02i
128378: 08/01/23: Re: Problem with UART EDK 9.2.02i
128393: 08/01/24: Re: Problem with UART EDK 9.2.02i
128483: 08/01/28: Re: Problem with UART EDK 9.2.02i
<piotrek.blachnio@gmail.com>:
157075: 14/09/23: Some newbe questions.
pipjockey:
81731: 05/03/30: Re: Xilinx- Extract a pin layout
85618: 05/06/12: Re: OrCAD Symbol For Xilinx V2PRO
85619: 05/06/12: Re: OrCAD Symbol For Xilinx V2PRO
89173: 05/09/07: Re: Disconnect the FPGA I/O pads from the outside world
89592: 05/09/20: Re: Unknown price difference for xilinx fpga
90440: 05/10/13: Re: IDELAYCTRL floorplanner/fpga editor/pace problem
90441: 05/10/13: Re: how to implement 8x8 circular shifter on FPGA
<pipjockey@my-dejanews.com>:
10982: 98/07/08: Re: Xilinx Foundation Frustartions
11034: 98/07/13: Re: Consultants
11173: 98/07/22: Re: Aldec's Active-VHDL Behavorial Simulator-Thanx
12016: 98/09/24: Re: US ASIC jobs+work visa
12153: 98/10/01: Re: Which FPGA tool is better
12179: 98/10/02: Re: Verilog Simulators
12626: 98/10/21: Re: Schematic entry?
12695: 98/10/23: Re: Need VHDL tools for Win NT/ Win 95
12699: 98/10/23: Re: Schematic entry?
pippo:
72298: 04/08/13: Re: Free Seminar
104977: 06/07/11: DIFFICULT MULTICYCLE PATH WITH QUARTUS II
105025: 06/07/12: Re: DIFFICULT MULTICYCLE PATH WITH QUARTUS II, or any other tool
<pirger@astrosun.tn.cornell.edu>:
10171: 98/04/30: XC6200 and Reconfigurable Computing
21090: 00/03/06: Apex vs. 10K
Pistony2k:
86856: 05/07/07: Verilog Coding Guidelines
Pit:
84990: 05/06/02: ppc405 cache using bram
85047: 05/06/03: re:ppc405 cache using bram
116254: 07/03/05: Re: LCD code
pivvosh:
125208: 07/10/17: Re: High level FPGA work flow: available tool?
<pixelsmart@gmail.com>:
115596: 07/02/14: wintel CPU reads across the PCI Express bus
Piyush Kaul:
123552: 07/08/29: Xilinx FPGA Based Board Problem
123942: 07/09/07: Re: Xilinx FPGA Based Board Problem
PiyushG:
91811: 05/11/14: Help needed to design recursive digital circuit
PJ:
60472: 03/09/14: fft size in fpga
60584: 03/09/16: Re: fft size in fpga
Pjc:
31397: 01/05/22: fast divider
PJD:
18211: 99/10/07: Token-Ring MAC in FPGA?
pjjones:
61385: 03/10/02: Quartus II tutorial vs the real world
61614: 03/10/07: Re: Quartus II tutorial vs the real world
73890: 04/09/30: Re: Quartus and VDHL misbehavior
73674: 04/09/27: Quartus and VDHL misbehavior
74924: 04/10/21: strange behavior in lpm_counter
74927: 04/10/21: Re: Quartus and VDHL misbehavior
74928: 04/10/21: lpm_counter instantiated in VHDL has a glitch
75592: 04/11/10: Timing Issues in Quartus design
pk:
120296: 07/06/05: OPB IPIF Master Attachment
pkirchhoff:
136309: 08/11/10: Re: XAUI v7.2 - timing issue - *channel bonding attributes*
pkkeng88:
87992: 05/08/04: Re: Spartan-3 configuring problem
pkuanfm:
59619: 03/08/25: quetions about configure altera fpga(apex20k) using ppa scheme
60051: 03/09/04: question about configue apex20k with ppa scheme
PL:
86907: 05/07/08: Xilinx ISE 7.1 : Macro search path in Transalate
pl[N0SP4M]apri:
63775: 03/12/04: Re: Design analyse methods
63884: 03/12/07: Re: Mixing simulation of behavioral and synthesized code
<pladow@gmail.com>:
121381: 07/07/03: Xilinx DCM Reset
<pladow@gocougs.wsu.edu>:
18960: 99/11/23: Re: VHDL vs. schematic entry
<planning@cyberpromo.com>:
7408: 97/09/07: Insurance Update
<plaquidara@gmail.com>:
141099: 09/06/05: Actel Fusion AFS600 FPGA Flash Memory Bug
PlayDough:
121400: 07/07/03: Re: Xilinx DCM Reset
121416: 07/07/03: Re: Xilinx DCM Reset
121420: 07/07/03: Re: Xilinx DCM Reset
121484: 07/07/05: Re: Xilinx DCM Reset
PLD Hacker:
107350: 06/08/27: is ISE coded in Java?
107357: 06/08/27: Re: is ISE coded in Java?
109303: 06/09/23: Re: PCI Express
111728: 06/11/09: Where can I get a opencore of a fifo with atlantic interface?
Pleae_do_my_homework:
97246: 06/02/19: Re: FPGA - software or hardware?
<please@dont.mail.me.com>:
19259: 99/12/09: Re: press release
Pleg:
111656: 06/11/07: Upgrading spartan-II: possible?
Plenolo:
61669: 03/10/08: Re: beginner - exisit some free schematics programmer for fpga ?
<plewer@my-dejanews.com>:
12156: 98/10/01: Re: Which FPGA tool is better
12157: 98/10/01: Re: Which FPGA tool is better
Pliers:
78140: 05/01/25: ADPLL I Think ?
<plogic1@my-deja.com>:
28583: 01/01/17: Re: CMOS or TTL
28589: 01/01/17: Re: Spartan programming error
28616: 01/01/18: Re: DSP->FPGA development board
ploog:
3635: 96/07/05: size of fpga
6265: 97/05/06: Re: Global GSR net in a Xilinx design (Synopsys)
Plutonium:
148829: 10/08/31: BRAM initialization in EDK 12.2
<plz.spam.here@gmail.com>:
78952: 05/02/10: Re: Virtual Pins in QuartusII
78983: 05/02/10: Re: NIOS - newbie
PM:
63442: 03/11/21: Implementing submodules with their own constraint files
63502: 03/11/24: Has anyone had any luck complining examples for a Virtex-II multimedia board
PM X:
159159: 16/08/26: Help me choose an FPGA to design network protocols
159165: 16/08/27: Re: Help me choose an FPGA to design network protocols
159175: 16/08/28: Re: Help me choose an FPGA to design network protocols
159176: 16/08/28: Re: Help me choose an FPGA to design network protocols
159180: 16/08/29: Re: Help me choose an FPGA to design network protocols
159186: 16/08/29: Re: Help me choose an FPGA to design network protocols
159187: 16/08/29: Re: Help me choose an FPGA to design network protocols
159272: 16/09/19: Re: Help me choose an FPGA to design network protocols
<pm940@yahoo.com>:
77492: 05/01/07: Re: San Jose job offer - need advice
77627: 05/01/12: Re: Looking for low-cost protoboards.
<pmaupin@gmail.com>:
105655: 06/07/27: Re: Wanted: CPU config register code generator
106731: 06/08/17: Re: Using an FPGA as USB HOST without PHY
106878: 06/08/21: Re: Using an FPGA as USB HOST without PHY
107514: 06/08/29: Location of Virtex4 ASCII pinout tables
107519: 06/08/29: Re: Location of Virtex4 ASCII pinout tables
107520: 06/08/29: Re: Location of Virtex4 ASCII pinout tables
<pminmo@gmail.com>:
154071: 12/07/28: Spartan 6 IBERT confusion
<pmolson@my-deja.com>:
18205: 99/10/07: Re: DSP in FPGA
18403: 99/10/22: Re: Interleaver
pmueller:
20181: 00/01/30: Re: Lucent Orca designs
20202: 00/01/31: Re: Lucent Orca designs
21027: 00/03/03: Re: ORCA 3T - input/output delay reduction?
<pmulliki@yahoo.com>:
130424: 08/03/23: Re: Virtex-5 FXT coming soon?
130425: 08/03/23: Re: Altera vs Xilinx
<pmyg@ix.netcom.com>:
9382: 98/03/08: Re: Altera MaxPlus II version 8.1 delays
pnc:
78657: 05/02/04: Orcad schematic and footprint libraries for Xilinx Spartan 3 FPGA's
78664: 05/02/04: Re: Orcad schematic and footprint libraries for Xilinx Spartan 3 FPGA's
pnowe:
83925: 05/05/09: Re: newbie question
PNowe:
77425: 05/01/06: Spartan 3 Experimenter's Board
77464: 05/01/07: Re: Spartan 3 Experimenter's Board
77474: 05/01/07: Re: signals inside a process
77792: 05/01/17: Re: Questions from a beginner...
78891: 05/02/09: Re: Help on a FPGA design
90020: 05/10/02: Re: Getting started VHDL, VHDL for Dummies, Easy Steps for FPGA experiments
PO Laprise:
60332: 03/09/10: Re: VGA display
60333: 03/09/10: Re: 200MHz ucf constraints for Xilinx DA Decimation by 2
61549: 03/10/06: Re: Should I worry about metastability
61944: 03/10/15: Re: Electronic Dice ( 3 die ) In VHDL
62875: 03/11/10: Re: VirtexII-Pro: Why is ICAP slower than SelectMAP?
62939: 03/11/11: Re: VirtexII-Pro: Why is ICAP slower than SelectMAP?
63717: 03/12/01: Exact Timing Constraints vs. Over-Constraining
63933: 03/12/09: Re: Xilinx 5.2 and EDK 3.2: Simulation given 'Z' ouput form tutorial
63962: 03/12/10: Re: programming with sockets on Xilinx Virtex2Pro
64068: 03/12/15: Extracting timing from a demo board (V2MB1000)
64104: 03/12/16: Re: Extracting timing from a demo board (V2MB1000)
64149: 03/12/18: Re: VHDL comments in Vim?
64151: 03/12/18: Re: Exporting a EDK design to Project Navigator
64415: 04/01/02: Re: Net name convention for Xilinx UCF files.
64472: 04/01/05: Re: p160 connector
65107: 04/01/20: Re: SDRAM Controller timing problem
65108: 04/01/20: Re: Tristate buffer
65174: 04/01/21: Re: changing values in a fifo
65228: 04/01/22: Re: Post-Place & Route simulation with MicroBlaze
65421: 04/01/28: Re: Which Environment for Xilinx Design?
65613: 04/02/03: Re: 4 bit divisor with flip-flop ?
65738: 04/02/05: Re: Reconfiguring at runtime internally?
65786: 04/02/06: Re: Reconfiguring at runtime internally?
65882: 04/02/09: Re: Xilinx EDK and FSL
66588: 04/02/23: Re: OpenCore.org DDR SDRAM problems
66789: 04/02/26: Re: Inquiry on configuration file analysis
67103: 04/03/05: Re: Global reset question?
67110: 04/03/05: Re: Global reset question?
67687: 04/03/17: Re: Xilinx bit-file format?
68286: 04/03/31: Re: maybe a stupid question
68330: 04/04/01: Re: XAPP134's VHDL code
68331: 04/04/01: Re: The mapper is getting rid of all my logic!!
68333: 04/04/01: Re: newbie - TCP/IP
68337: 04/04/01: Inserting timing in behavioural simulations
68376: 04/04/02: Re: signal names in modelsim
68383: 04/04/02: Verifying multi-cyclicity of multi-cycle paths
68453: 04/04/05: Re: The Logic Behind License Renewal
68898: 04/04/21: Re: VCD file generation
Pocket Door:
83172: 05/04/25: re:College Project
point308:
42368: 02/04/22: FoxFire II PCI Latency cards
poirjh:
40861: 02/03/16: pipeline
POK:
45506: 02/07/25: Where can get the CISC core(8-bit) for Verilog??
<Politics@usa.com>:
1950: 95/09/23: Proposed State & Federal Regulations for the INTERNET!
<polkid@gmail.com>:
106939: 06/08/22: ISE 8.2i and EDK 8.1i
<polovnikov.rtf@gmail.com>:
161348: 19/04/18: Re: Field update
161350: 19/04/19: Re: Field update
pomerado@hotmail.com:
106294: 06/08/10: Anyone really using Virtex-5 FPGAs yet?
106312: 06/08/11: Re: Switching two (synchronous) clocks with variable phase difference, without glitching or period loss
106714: 06/08/17: Re: FFT on an FPGA
107701: 06/08/31: Re: Performance Appraisals
108132: 06/09/05: Virtex4 FPGA minimum power
108180: 06/09/06: Re: Virtex4 FPGA minimum power
115368: 07/02/08: Re: question abt DPRAM
124802: 07/10/04: Daisy chaining FPGA with CPLDs
ponnagantiraju:
157836: 15/04/10: Aurora IP 8B10B problem with TVALID
Pontus:
147127: 10/04/14: Re: Implementing bidirectional bus inside the FPGA
147146: 10/04/15: Re: Implementing bidirectional bus inside the FPGA
147273: 10/04/21: Re: Synplify synthesis error
147317: 10/04/22: Re: Synplify synthesis error
149986: 10/12/05: Re: FPGA project structure definition
150026: 10/12/06: Re: FPGA project structure definition
150606: 11/01/27: Re: Wow! No TestbenchWow!
Pontus Andersson:
8969: 98/02/10: Synario schematic to Xilinx Foundation conversion?
9153: 98/02/25: Xilinx foundation optimization
<pontus.stenstrom@gmail.com>:
119655: 07/05/24: Re: Xilinx 8.2 : Multippass P&R
119970: 07/05/30: Re: Use BRAM as ROM (Xilinx)
120863: 07/06/19: Re: want to pay for DCM active phase shift controller.
121262: 07/06/29: Re: modelsim search path
128088: 08/01/15: Re: Complex Multiply
132904: 08/06/10: Re: Aldec Active-HDL and Xilinx/Altera FPGA-vendor library support
135126: 08/09/17: Re: Compiler Options
140292: 09/05/07: Re: Environmental variables to point at libraries with Modelsim?
140790: 09/05/26: Re: EMACS VHDL mode: how to rescan project so that makefile generates
154221: 12/09/10: Re: General Build Question
Pooh Bear:
95585: 06/01/24: Re: Very OT: Americanized family names
95013: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95026: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95095: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95096: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95098: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95101: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95102: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95105: 06/01/20: Re: OT:Shooting Ourselves in the Foot
95116: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95123: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95216: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95220: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95258: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95259: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95260: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95262: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95263: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95264: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95268: 06/01/21: Re: OT:Shooting Ourselves in the Foot
95275: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95303: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95331: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95332: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95353: 06/01/22: Re: OT:Shooting Ourselves in the Foot
95558: 06/01/24: Re: OT:Shooting Ourselves in the Foot
Pooja from LA:
56502: 03/06/06: outsourcing hardware verification
Poojan Wagh:
138120: 09/02/06: Req for Recommendations: Modelsim vs IUS & VCS
138137: 09/02/07: Re: Req for Recommendations: Modelsim vs IUS & VCS
138367: 09/02/17: Problem with ModelSim and Xilinx PCIe endpoint block plus simulation
138473: 09/02/24: Re: Fm digital baseband demodulation
139969: 09/04/21: Re: Why is XST optimizing away my registers and how do I stop it?
140477: 09/05/14: Survey: What's a good FPGA-related conference?
141468: 09/06/25: Re: Virtex-6 shipping?
141946: 09/07/18: Re: Do you prefer paper or plastic... er, I mean paper or e-books?
142097: 09/07/24: Re: FPGA development tools for FreeBSD?
142125: 09/07/25: Altera M9K + M144K RAM: do they get combined
142126: 09/07/25: Looking for Virtex-6 PCIe development board
142866: 09/09/04: Re: Choice of Language for FPGA programming
143201: 09/09/25: Automated test framework
Poolar Bear:
52058: 03/01/29: Writing and Reading into RC100 Flash RAM
Poonam:
127123: 07/12/12: FPGA Board design basics
127143: 07/12/12: Re: FPGA Board design basics
127152: 07/12/12: Re: FPGA Board design basics
127162: 07/12/12: Re: FPGA Board design basics
127182: 07/12/13: Re: FPGA Board design basics
127221: 07/12/14: Re: FPGA Board design basics
136776: 08/12/04: PCI9656RDK from PLX Technologies
Pootle (AT DOT DOT):
45222: 02/07/16: LVDS interface cable recommendation sought
pop:
70162: 04/06/07: comp.arch.fpga: reset strategy
<porterboy76@yahoo.com>:
87998: 05/08/05: Re: Good intro books on OFDM?
92758: 05/12/06: Re: xilinx research labs
92833: 05/12/07: Re: xilinx research labs
<posedge52@yahoo.com>:
126063: 07/11/13: Synthesis-place&route performance test.
126582: 07/11/28: I/O short circuit protection?
126602: 07/11/28: Re: I/O short circuit protection?
126640: 07/11/28: Re: I/O short circuit protection?
126926: 07/12/06: Spartan-3E starter kit, USB Jtag
126927: 07/12/06: Re: Drigmorn1 - The Cheapest FPGA Development Board???
127236: 07/12/14: Using LVDS_25 with 3.3V Vcco.
127240: 07/12/15: Spartan-3E starter kit, what's "J8" 6-pin for?
127241: 07/12/15: Re: Using LVDS_25 with 3.3V Vcco.
127250: 07/12/15: Re: Using LVDS_25 with 3.3V Vcco.
127481: 07/12/28: Initialization of arrays
127494: 07/12/28: Re: Initialization of arrays
127672: 08/01/05: DDR SDRAM demo for Spartan-3E starter kit?
127674: 08/01/05: Re: Vendors of FPGA's
127714: 08/01/06: Re: Spartan 3E Sarter Kit Ethernet
127717: 08/01/06: Re: DDR SDRAM demo for Spartan-3E starter kit?
127727: 08/01/06: Re: Ethernet on recent FPGAs
127832: 08/01/08: Using DDR SDRAM as single data rate ..?
127835: 08/01/09: Re: Using DDR SDRAM as single data rate ..?
127869: 08/01/09: Re: Identification of FPGA Development Board
128561: 08/01/30: Re: PC requirements for ISE webpack
128564: 08/01/30: Re: PC requirements for ISE webpack
128588: 08/01/31: Re: PC requirements for ISE webpack
128692: 08/02/04: Re: Xilinx BSCAN primitives proper use
poste libre:
39355: 02/02/07: MC6800 vhdl design
<postmaster@lsantist.dfrf.nasa.gov>:
379: 94/11/02: Re: linear feedback shift registers
391: 94/11/04: Re: Xilinx chip partitioning
588: 95/01/12: Re: Backannotating Xilinx pinouts to ViewLogic symbols... BUT Not by hand!
590: 95/01/12: Re: PCB design with Xilinx
1222: 95/05/17: Re: 1000 pin fpga's ?
posts:
72364: 04/08/16: How to download USENET News **in-spite** of firewall blocks
<potral@e5sf.hweng.syr.ge.com>:
249: 94/10/03: PREP info needed
potter:
101045: 06/04/24: XDL router info needed
Potxoka:
139054: 09/03/19: Update code in board
144220: 09/11/20: FPGA + Ethernet
144231: 09/11/21: Re: FPGA + Ethernet
144232: 09/11/21: Re: FPGA + Ethernet
Poul-Henning Kamp:
8546: 98/01/07: simple FPGA project for somebody...
<pourewoiur@qopreoiruewoi.com>:
Pouria:
94482: 06/01/12: Re: PCI compliance ?
94402: 06/01/11: SDRAM Clock Skew
Pouya Razavi:
44252: 02/06/14: TTL library in Xilinx?
PovTruffe:
151122: 11/03/08: Pull up/down resistors on Spartan-3E configuration inputs
151130: 11/03/09: Re: Pull up/down resistors on Spartan-3E configuration inputs
151150: 11/03/11: Re: Pull up/down resistors on Spartan-3E configuration inputs
151270: 11/03/19: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
151288: 11/03/21: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
151290: 11/03/21: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
151297: 11/03/21: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
151298: 11/03/22: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
151308: 11/03/22: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
151314: 11/03/22: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
151338: 11/03/24: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
151339: 11/03/24: Re: RAM - DIMM vs SO-DIMM: price vs. (hardware & software) ease of use
151398: 11/04/02: Re: Ideal FPGA Development Kit
151450: 11/04/10: Re: Altium Limited closing up shop - Altium Designer discontinued
<powermail787@gmail.com>:
159819: 17/03/22: Re: Xilinx Virtex4 Outputs for Camera Link
Powermos:
53405: 03/03/12: Re: footprints
55057: 03/04/25: Re: WANTED ALTERA CYCLONE PCI BOARD
55058: 03/04/25: Re: Complex FIR in FPGA
55059: 03/04/25: Re: Cyclone power up problem - Summery
55060: 03/04/25: Re: Advice on FPGA IIR Filter
55096: 03/04/26: Re: Cyclone power up problem - Summery
55097: 03/04/26: Re: Advice on FPGA IIR Filter
55099: 03/04/26: ISE 5.2i evaluation and problem with Windows ME
55101: 03/04/26: Re: ISE 5.2i evaluation and problem with Windows ME
55102: 03/04/26: Re: ISE 5.2i evaluation and problem with Windows ME
55104: 03/04/26: Re: ISE 5.2i evaluation and problem with Windows ME
55178: 03/04/29: Re: ISE 5.2i evaluation and problem with Windows ME
58243: 03/07/17: Re: programming a PLD/CPLD with a PIC?
<pp12479@gmail.com>:
133699: 08/07/10: Re: QPSK SymbolRate generator ...
ppc:
71813: 04/07/31: How much salary for RTL design engineer in Toronto Canada?
<pperogil@gmail.com>:
133883: 08/07/18: a question about linker map file
133886: 08/07/18: Re: a question about linker map file
133994: 08/07/21: Strange behaviour with Xilkernel
133995: 08/07/21: Strange behaviour with Xilkernel
134020: 08/07/22: Re: Strange behaviour with Xilkernel
134024: 08/07/22: Re: Strange behaviour with Xilkernel
<ppetener@my-deja.com>:
28466: 01/01/14: IDS 6.0 - FPGA Compiler Problem
ppirrip:
90952: 05/10/25: newbie question
91183: 05/10/31: question on sw tools for xilnx FPGA
<pra.vlsi@gmail.com>:
116327: 07/03/07: Query regarding Project.Plz help very urgent
116376: 07/03/07: Re: Query regarding Project.Plz help very urgent
Prabhat Gupta:
66824: 04/02/27: DesignCon 2002 Paper
66949: 04/03/01: Re: DesignCon 2002 Paper
Prad:
75795: 04/11/15: Neural nets
80208: 05/03/02: Fault Tolerant FPGA design
80260: 05/03/02: Re: Fault Tolerant FPGA design
pradeep:
49657: 02/11/19: Re: Tristate buffers + leonardo Spectrum
49961: 02/11/27: Initialising Spartan's Block RAM
56824: 03/06/17: Re: XILINX Error Message
56894: 03/06/19: Re: XILINX Error Message
63406: 03/11/20: verification vs validation
63430: 03/11/21: Re: verification vs validation
63540: 03/11/25: Re: Dual port RAM for Xilinx
65525: 04/02/01: Syn. warning
65546: 04/02/01: Re: Syn. warning
Pradeep:
59515: 03/08/21: Re: BlockRAM in VHDL
Pradeep Rao:
20075: 00/01/27: Reed Solomon codes and Intelsat specs
20439: 00/02/10: Simulation problem
20611: 00/02/16: multiplier
20909: 00/02/27: Galois Coefficients g0,g1,...
praetorian:
85457: 05/06/09: ISE tools to use SMP?
85459: 05/06/09: Persist option in bitgen
86805: 05/07/06: Re: Cheking out Linux Kernel Source
87089: 05/07/14: Bus Macros
87115: 05/07/15: Re: Bus Macros
87127: 05/07/15: Re: Virtex-2 Pro: Configuration Frames
87174: 05/07/18: Re: Bus Macros
87407: 05/07/22: Re: Transfert data to Memec Virtex II Pro Card from PC
87527: 05/07/25: Virtex 2 Pro Routing Constraints
87799: 05/08/01: Modifying opb_bram under EDK
87806: 05/08/01: Re: Modifying opb_bram under EDK
87864: 05/08/02: Area Group IOB Range
87918: 05/08/03: Re: Area Group IOB Range
89613: 05/09/20: EDK libgen cc choice
Pragathi:
150244: 11/01/05: Dual port Ram
Prager Roman:
43615: 02/05/27: Re: ALtera SOPC Builder
43721: 02/05/31: Re: ALtera SOPC Builder
43796: 02/06/03: Re: FPGA destruction possible?
43880: 02/06/05: Re: ALtera SOPC Builder
44016: 02/06/10: Re: Bad Behavior of JTAG Download on Altera CPLD with Other Devices
46598: 02/09/04: Re: QUARTUS II V2.1 LINUX (C) ALTERA
46611: 02/09/04: Re: Altera APEX clock problem
48584: 02/10/21: Re: Unused pins in Apex20KE
48722: 02/10/23: Re: Nios and quartus linux version
48984: 02/10/28: Re: Leonardo and lpm (Altera)
49275: 02/11/07: Re: Compiling Altera Nios Designs
49366: 02/11/11: Re: Compiling Altera Nios Designs
49388: 02/11/11: Re: How to instanciate Altera primitive component in VHDL for FPGA Compiler synthesis?
53337: 03/03/11: Re: Cyclone power up problem
53670: 03/03/19: Re: Quartus2 : assigning I/O pins
53681: 03/03/19: Re: Quartus2 : assigning I/O pins
54100: 03/04/02: Re: ALTERA APEX 20K Series: Are there configurable pullups in IO cells?
prakash:
115376: 07/02/08: DCT/IDCT on FPGA
Prakash:
53225: 03/03/06: JTAG
100462: 06/04/10: xilinx JTAG
100470: 06/04/10: Re: xilinx JTAG
100472: 06/04/10: unused pins
100477: 06/04/10: Re: xilinx DCM Timing warning
100479: 06/04/10: Re: unused pins
100482: 06/04/10: location constraint doubt
100527: 06/04/10: xilinx XCVU2P-XC2VP30
100557: 06/04/11: xilinx board xupv2p xc2v30 software dev. doubt
101712: 06/05/04: Xilinx-XUPV2P- AC97 Audio BSP
prakash.na@gmail.com:
100125: 06/04/03: xilinx xc2vp30
100237: 06/04/05: opensource vs commercial
100238: 06/04/05: design flow xilinx ise 7.1+synplify pro8.4
100458: 06/04/10: xilinx DCM Timing warning
<prakash.na@gmail.com>:
100103: 06/04/03: embedded design prototyping
Pramod:
54697: 03/04/15: Advice on FPGA IIR Filter
55193: 03/04/30: Re: Advice on FPGA IIR Filter
pramod kappagantula:
46421: 02/08/29: Xilinx ISE , using Xpower for dynamic power determination
Pramod Subramanyan:
90720: 05/10/19: Re: MAC Architectures
Pranay:
125044: 07/10/16: Re: FIFO depth
praneeth87:
150997: 11/02/28: serial loading of image pixels????????????
prasad:
58614: 03/07/28: how to design hardware for 2's complement parallel multiplier(at gate level)
prasad babu:
89874: 05/09/28: help needed
Prasad Pandit:
158826: 16/04/23: Challenges in data science which can be solved with FPGAs
<prasad.anirudh@gmail.com>:
115941: 07/02/26: Virtex 4
117499: 07/04/02: Re: Virtex 4
117500: 07/04/02: Dynamic Reconfig
117969: 07/04/14: Re: Dynamic Reconfig
<prasad.naga@gmail.com>:
121427: 07/07/03: Unable to use xmd or mb-gdb with microblaze cycle accurate simulator target
Prasanna:
58675: 03/07/30: Re: Multi Cycle path and False paths
58733: 03/07/31: Re: Multi Cycle path and False paths
59021: 03/08/06: Re: How to use EAB in Altera FPGA?
59418: 03/08/18: Re: Problem with Modelsim Lisence server...
Prasanna Sundararajan:
18400: 99/10/22: Re: Virtex Readback
18404: 99/10/22: Re: Virtex Readback
21394: 00/03/21: Re: Xilinx 6200 devices?
Prasanth Anbalagan:
53644: 03/03/18: Implementation error in Xilinx FS 3.1i
53736: 03/03/20: Implementation error ?
53996: 03/03/30: Help reg Target device & synthesis
54547: 03/04/14: Regarding Synthesis
Prasanth Kumar:
29508: 01/02/24: Viewing the netlist after synthesis of Verilog
40629: 02/03/12: Re: SPI interface
40891: 02/03/17: Xilinx Webpack/ModelSim VHDL Question
56770: 03/06/14: Re: Kit Recommendation
59047: 03/08/07: Confusing Xilinx Webpack warning
59634: 03/08/25: Re: Which Adder?
71415: 04/07/18: Re: twos to ones and ones to twos compliments
73604: 04/09/25: Re: Getting info from a digital line
73605: 04/09/25: Re: Getting info from a digital line
73586: 04/09/24: Re: Getting info from a digital line
73335: 04/09/19: Re: Verilog vs VHDL for Loops
74887: 04/10/21: Re: Async reset
74911: 04/10/21: Re: interfacing a PC based program with a FPGA
75615: 04/11/11: Re: Xilinx Tshirts in football package.....
Prashant:
39751: 02/02/18: Multipliers in Altera FPGAs
40152: 02/02/28: Altera FPGAs
40160: 02/02/28: Re: Altera FPGAs
40203: 02/03/01: Re: Altera FPGAs
40679: 02/03/12: Timing Simulations
40711: 02/03/13: IP cores availability
41063: 02/03/20: Modelsim or Quartus II Simulator
42125: 02/04/16: Programming for FPGA or ASIC
42210: 02/04/18: Re: Programming for FPGA or ASIC
42635: 02/04/29: Loading values in Quartus II Waveform editor
42657: 02/04/30: Re: Loading values in Quartus II Waveform editor
42767: 02/05/02: Modelsim testbench problems
42892: 02/05/06: Re: a modelsim problem
43387: 02/05/20: Power Consumption scaling factor
43943: 02/06/06: Quartus v/s Leonardo
44606: 02/06/24: Re: Quartus v/s Leonardo
45469: 02/07/24: FPGA prototyping boards
45541: 02/07/25: logic elements v/s logic cells
45561: 02/07/26: Re: logic elements v/s logic cells
45740: 02/08/02: Modelsim Fatal Error
45772: 02/08/05: Re: Gate level simulation in Quartus II
45807: 02/08/06: Re: Gate level simulation in Quartus II
45826: 02/08/06: Programming bits reverse engineering
45846: 02/08/07: Re: Programming bits reverse engineering
45881: 02/08/08: Re: Programming bits reverse engineering
45891: 02/08/09: Re: Division
45900: 02/08/09: ASIC conversion
46198: 02/08/21: Logic Analyzers with an Altera Board
46715: 02/09/06: Performance degradation when put on an FPGA ?
46746: 02/09/06: Re: Performance degradation when put on an FPGA ?
46869: 02/09/10: Modelsim-Altera gate level simulation
46908: 02/09/11: Re: Modelsim-Altera gate level simulation
46909: 02/09/11: Quartus 2 flow
46939: 02/09/12: Re: Quartus 2 flow
47317: 02/09/23: Unused pins in Apex20KE
47361: 02/09/24: Re: Unused pins in Apex20KE
47779: 02/10/03: Run time error '8005' : Port already open
47880: 02/10/06: Hold time violation during simulation
48233: 02/10/14: Operations / sec FPGA v/s DSP
48426: 02/10/17: Re: Operations / sec FPGA v/s DSP
49179: 02/11/04: Re: FPGA convert to ASIC
49575: 02/11/15: FPGA board random error
49609: 02/11/17: Re: FPGA board random error
49861: 02/11/22: Conversion functions
50257: 02/12/06: Hold time violation
50416: 02/12/10: Re: vlsi implementation of multipliers
50475: 02/12/11: Hold violation in synthesis but not fitting
50521: 02/12/11: Re: Hold violation in synthesis but not fitting
50548: 02/12/12: Re: vlsi implementation of multipliers
50598: 02/12/13: Re: Hold violation in synthesis but not fitting
50737: 02/12/18: Async RAM on an FPGA board
50783: 02/12/19: Re: Async RAM on an FPGA board
50800: 02/12/19: Re: Async RAM on an FPGA board
50844: 02/12/20: Re: Async RAM on an FPGA board
50931: 02/12/23: Re: Async RAM on an FPGA board
51122: 03/01/02: Latch inferring : Async OR Sync ?
51136: 03/01/03: Re: Latch inferring : Async OR Sync ?
51317: 03/01/10: Asynchronous RAM problems
51419: 03/01/13: Re: Asynchronous RAM problems
51491: 03/01/14: Re: RS-232 connection with SOPC Development Kit
51566: 03/01/16: Multiple FPGA-boards integration issues
51587: 03/01/16: Re: Multiple FPGA-boards integration issues
51617: 03/01/17: Re: Multiple FPGA-boards integration issues
51655: 03/01/17: Re: Multiple FPGA-boards integration issues
52221: 03/02/04: Re: Group Multiple tables
52483: 03/02/11: Re: Quartus / ModelSim
53793: 03/03/23: Rake receiver IP core
54417: 03/04/10: Verilog to VHDL or vice-versa converters ??
56417: 03/06/04: Clk between multiple boards
56468: 03/06/05: Re: Clk between multiple boards
56612: 03/06/10: Re: Writing from FPGA to SRAM then to PC
56684: 03/06/11: Drive Capabilities of the FPGA
56867: 03/06/17: XCV 6000 data sheets
56972: 03/06/19: Re: XCV 6000 data sheets
57908: 03/07/09: Synplify and then Quartus
58678: 03/07/30: Altera-to-Xilinx IO
58722: 03/07/31: Re: Altera-to-Xilinx IO 3.3V -> 1.8V
60962: 03/09/25: Strange synthesis behavior from Quartus II 2.2
61086: 03/09/27: Re: Strange synthesis behavior from Quartus II 2.2
61095: 03/09/27: Implementing Bidirectional pins
61106: 03/09/28: Re: Implementing Bidirectional pins
Prashant Arora:
18021: 99/09/23: Altera's MaxplusII: incremental compilation
Prashant B. Maniar:
37: 94/08/02: Literature Survey on FPGA based designs.
<prashant.gyawali@gmail.com>:
137361: 09/01/11: error during ise simulation
140297: 09/05/07: problem during port mapping
140331: 09/05/09: difficulty during processing
prashanth:
30294: 01/04/01: Dist_ram :Memory instantiation
Prashanth:
75250: 04/10/31: Re: JTAG Registers
75110: 04/10/26: JTAG Registers
Prashanth K. Banuru:
8492: 97/12/23: Re: Serial PROMs for Xilinx FPGAs
8493: 97/12/23: Re: PCs vs. workstations
8494: 97/12/23: Re: Simulating Bidi pins/Foundation
8509: 97/12/29: Re: PCs vs. workstations
8511: 97/12/29: Re: dynamic power in Xilinx designs
8512: 97/12/29: Re: PCs vs. workstations
Prashanth Kumar:
140116: 09/04/28: Re: I have some doubts in verilog
PrAsHaNtH@IIT:
137487: 09/01/20: Image enhancement on FPGA
140046: 09/04/24: Error in Verilog Code
140068: 09/04/27: I have some doubts in verilog
140853: 09/05/27: Reading from and writing to a text file in verilog hdl
140857: 09/05/27: Error in Verilog Code
141885: 09/07/15: parallel processing
prashath:
<prastogi@my-deja.com>:
16683: 99/06/02: Re: ANy good recommendations for Books on FPGA
16669: 99/06/02: Re: FPGA Introduction is needed, right?
18361: 99/10/19: Question on Jbits(Xilinx product) for Xc4000 series
<prastogi@my-dejanews.com>:
16531: 99/05/27: C to EDIF translator??Anyone?
Prasunp:
73095: 04/09/14: Unwanted shift in multiplier
<prasunp@gmail.com>:
97255: 06/02/19: Parameterized Comparator Verilog Code
97525: 06/02/23: From ASM to verilog Code
Pratap:
132032: 08/05/10: how to set trigger in ChipScopePro for this
132069: 08/05/12: Re: how to set trigger in ChipScopePro for this
135561: 08/10/08: How to synthesize a delay of around 10 ns in FPGA?
135892: 08/10/20: Re: How to synthesize a delay of around 10 ns in FPGA?
135893: 08/10/20: Re: How to synthesize a delay of around 10 ns in FPGA?
135894: 08/10/20: Re: How to synthesize a delay of around 10 ns in FPGA?
135904: 08/10/21: Re: external differential clock inputs
135906: 08/10/21: Re: How to synthesize a delay of around 10 ns in FPGA?
135982: 08/10/25: Re: How to synthesize a delay of around 10 ns in FPGA?
141460: 09/06/24: Cable autodetection/programming the Xilinx Virtex2Pro FPGA failing.
141497: 09/06/25: Re: Cable autodetection/programming the Xilinx Virtex2Pro FPGA
142571: 09/08/17: VHDL code for finding standard deviation for a chunk of numbers
142574: 09/08/17: Re: VHDL code for finding standard deviation for a chunk of numbers
150611: 11/01/27: How to place some delay blocks adjacent to each other after Xilinx
151341: 11/03/25: Measuring the delay between two rising edges in modelsim simulation
151342: 11/03/25: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors
151345: 11/03/25: Re: Measuring the delay between two rising edges in modelsim
151348: 11/03/26: Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors
151351: 11/03/26: Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors
151355: 11/03/27: Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors
151356: 11/03/27: Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors
151359: 11/03/27: Re: How to take signals fed to EXT_CLK_P and EXT_CLK_N SMA connectors
151794: 11/05/18: How to use the EXT_CLK_P and EXT_CLK_N pins of Virtex II Pro
151796: 11/05/18: Re: How to use the EXT_CLK_P and EXT_CLK_N pins of Virtex II Pro
151808: 11/05/19: Re: How to use the EXT_CLK_P and EXT_CLK_N pins of Virtex II Pro
152517: 11/08/30: Problem in using the A23 HS_IO pin of bank J37 with SSTL2_II IO
152520: 11/08/30: Re: Problem in using the A23 HS_IO pin of bank J37 with SSTL2_II IO
Prateek Singhal:
93199: 05/12/15: Re: Parallel Cable III is not detected
93257: 05/12/16: Re: Parallel Cable III is not detected
93864: 06/01/02: Problem in Serial Port Transmitter
93866: 06/01/02: Re: Problem in Serial Port Transmitter
94409: 06/01/11: Verilog Code for echo on Serial Port
<prathap.ap@gmail.com>:
112316: 06/11/20: Differential to single ended convertion in FPGA
Pratip Mukherjee:
21402: 00/03/22: Good book on learning FPGA/VHDL/Verilog programming
23993: 00/07/20: New Xilinx Student Edition
24052: 00/07/24: Re: New Xilinx Student Edition
28841: 01/01/26: Re: Advice on FPGA board.
28951: 01/01/31: Re: Advice on FPGA board.
29294: 01/02/13: Programming a CPLD
29302: 01/02/13: Re: Programming a CPLD
29429: 01/02/21: Re: Virtex E:Sample price
29976: 01/03/20: Do I need to tie unused CPLD pins to GND?
61801: 03/10/12: Quartus help with package declaration
62310: 03/10/26: Hex display with Quartus simulation
62356: 03/10/28: What's a good book on FPGA CPU design?
62465: 03/10/30: PicoBlaze for Altera (ACEX1K)?
63889: 03/12/08: Quartus-II question
63956: 03/12/10: Re: Quartus-II question
64989: 04/01/18: Re: after the synthesis total logic elements are equal zero
70041: 04/05/28: VHDL test bench in Quartus
70149: 04/06/05: Re: VHDL test bench in Quartus
71183: 04/07/11: Re: xilinx spartan 3 $99 board...help
88041: 05/08/07: NIOS Small C library
91097: 05/10/29: Spartan-3E starter kit
91287: 05/11/02: Re: Spartan-3E starter kit
<pratipm@hotmail.com>:
78412: 05/01/31: Re: i need xilinx edk
prav:
65929: 04/02/10: negative hold time
66062: 04/02/11: regarding opto isolators
66150: 04/02/12: Re: regarding opto isolators
66355: 04/02/17: regarding synchronization
67453: 04/03/11: Issues in Rocket I/O
67574: 04/03/15: Re: Issues in Rocket I/O
68743: 04/04/16: Altera flex 10k library component doubt
68780: 04/04/17: Re: Altera flex 10k library component doubt
68796: 04/04/19: DPLL using 74LS297
69691: 04/05/18: Drive strength on I/O pads
69794: 04/05/19: Re: Drive strength on I/O pads
70420: 04/06/16: MGT pin details(Xilinx Virtex 2 PRO)
70530: 04/06/18: scatter gather DMA in OPB MAC core
91921: 05/11/16: Data recovery (XAPP224)
94727: 06/01/17: PCI arbiter doubt
94890: 06/01/18: PCI arbiter (doubt in REQ signal)
98141: 06/03/06: processor bus tristate at two places
100460: 06/04/10: 8:1 MUX implementaion in XILINX and ALTERA
100784: 06/04/18: Implementation of cascadable shift register in virtex FPGA
103796: 06/06/11: Xilinx timing viloations
103845: 06/06/13: Re: Xilinx timing viloations
104680: 06/07/03: Re: Xilinx timing viloations
Praveen:
40325: 02/03/05: Re: Converting VHDL netlist to EDN/EDF/XNF
82076: 05/04/06: Single Event Functional Interrupts (SEFI) in Virtex
82097: 05/04/06: Re: Single Event Functional Interrupts (SEFI) in Virtex
82109: 05/04/06: Re: Modelsim simulations without ISE
82110: 05/04/06: Re: Modelsim simulations without ISE
82147: 05/04/07: Re: Single Event Functional Interrupts (SEFI) in Virtex
82364: 05/04/11: Re: process trouble, error: multi source
82368: 05/04/11: Re: Timing
82594: 05/04/14: Re: Flowcharts and diagrams
82959: 05/04/20: Virtex II Scrubbing, Readback and Reconfiguration time durations
83088: 05/04/22: Time Borrowing
83135: 05/04/24: Re: Time Borrowing
83529: 05/05/02: Performing Readback from Impact
83545: 05/05/02: Re: Performing Readback from Impact
83789: 05/05/06: Re: newbie question
84997: 05/06/02: Re: Basics FPGA
praveen:
40202: 02/03/01: simulating time_sim.vhd file
40298: 02/03/04: Converting VHDL netlist to EDN/EDF/XNF
41441: 02/03/28: time_sim.vhd and time_sim.sdf
41477: 02/03/29: Re: Core Generator and Modelsim XE
51945: 03/01/27: vhdl core of PCI bridge
52021: 03/01/28: Re: vhdl core of PCI bridge
52024: 03/01/28: Re: PCI protocol - assigning an address to my device
52026: 03/01/28: Re: better clock speed???
52034: 03/01/29: Re: vhdl core of PCI bridge
52147: 03/02/03: difference between pci2.1 and pci2.2
52238: 03/02/04: Re: vhdl core of PCI bridge
52240: 03/02/04: Re: difference between pci2.1 and pci2.2
52296: 03/02/06: Re: difference between pci2.1 and pci2.2
52447: 03/02/10: regarding PCI specification in that configuration register doubt
52826: 03/02/24: expansion ROM in PCI bridge
52966: 03/02/27: PCI specification question
53072: 03/03/03: PCI specification doubt
53117: 03/03/04: Re: PCI specification doubt
53277: 03/03/09: PCI specification
53338: 03/03/11: Re: PCI specification
53499: 03/03/14: Re: PCI specification
53698: 03/03/20: PCI target design
54056: 03/04/01: parity checking trick for PCI core
54139: 03/04/03: Re: parity checking trick for PCI core
54142: 03/04/03: PCI specification
54175: 03/04/03: PCI parity checking module
54272: 03/04/06: prefetching in PCI
54560: 03/04/14: doubts in PCI
54822: 03/04/18: PCI doubts
55127: 03/04/28: visualizing a Counter on a FPGA
55616: 03/05/14: how to calculate the gate count required for a FPGA design
55721: 03/05/17: what and how encrypted VHDL code work
55722: 03/05/17: test cases for testing PCI core
55806: 03/05/20: Re: test cases for testing PCI core
57546: 03/07/02: Fixed point signed multiplication algorithm
60982: 03/09/25: virtex2p power consumption
62117: 03/10/19: Power calculation using Xpower
62501: 03/10/30: Re: Power calculation using Xpower
63273: 03/11/18: regarding clock routing
63354: 03/11/19: Re: regarding clock routing
63639: 03/11/26: Re: Infer DDR registers from RTL?
63641: 03/11/26: DDFS technique problem in generating a few clocks
63895: 03/12/08: clock recovery from HDB3 data
65867: 04/02/09: iteration Vs LUT table entry vs accuracy in Cordic
71704: 04/07/28: FPGA vs CPLD
71899: 04/08/03: Re: FPGAs starting with incorrect bitstream !?
75778: 04/11/15: Gap between layers in PCB
77052: 04/12/20: PCI doubt
77162: 04/12/27: AHB VHDL code
77404: 05/01/06: AHB VHDL code
77563: 05/01/11: PCMCIA interface
77720: 05/01/15: Adding TDM to ZSP400
80555: 05/03/08: Trace length from FPGA to USB PHY
80948: 05/03/14: Re: seriel prom
82031: 05/04/05: Re: DCM LOCKED as reset
Praveen Krishnamurthy:
82332: 05/04/11: Application using coprocessor interface
<praveen.kantharajapura@gmail.com>:
82474: 05/04/13: Regarding driving of SCL and SDA pins of I2C
82545: 05/04/13: Re: Regarding driving of SCL and SDA pins of I2C
82547: 05/04/13: Re: Regarding driving of SCL and SDA pins of I2C
83875: 05/05/09: true dual port memory v/s simple dual port memory
83927: 05/05/09: Re: true dual port memory v/s simple dual port memory
84240: 05/05/15: SPI interface cpol & cpha
84249: 05/05/16: Re: SPI interface cpol & cpha
84833: 05/05/29: Keypad controller implementation
84841: 05/05/30: SPI slave select signals
85027: 05/06/02: keypad scanner
85129: 05/06/05: Re: keypad scanner
85130: 05/06/05: Re: keypad scanner
85131: 05/06/05: Re: keypad scanner
85480: 05/06/09: I2C clock stretching(XILINX reference design)
85483: 05/06/09: SPD interface(Serial presence detect)
85634: 05/06/12: Re: SPD interface(Serial presence detect)
85683: 05/06/13: Re: SPD interface(Serial presence detect)
85697: 05/06/14: PCI arbiter doubt
86509: 05/06/29: Re: SPD interface(Serial presence detect)
86558: 05/06/29: Re: SPD interface(Serial presence detect)
86984: 05/07/11: Clock recovery in FPGA at 300 MHZ
87055: 05/07/13: Re: Clock recovery in FPGA at 300 MHZ
88060: 05/08/08: sequence detection using shift register approach
88082: 05/08/08: Re: sequence detection using shift register approach
88091: 05/08/09: START /STOP sync pattern
88225: 05/08/12: Regarding clock muxing
88539: 05/08/22: Problem in timing simulation(Altera)
88987: 05/09/01: I2C "SCL" line problem
89070: 05/09/04: Re: I2C "SCL" line problem
89935: 05/09/30: Power on reset generation in FPGA
90869: 05/10/24: Doubt in using CD22M3494
<praveen.rajaretnam@gmail.com>:
86305: 05/06/24: FPGA vs. ASIC vs. Processor
praveen.sethuram@gmail.com:
102423: 06/05/15: requirements to select FPGA using LVDS
102692: 06/05/19: Re: requirements to select FPGA using LVDS
<praveen@tarayinc.com>:
135797: 08/10/16: Re: DDR2 timing questions
135798: 08/10/16: Re: Virtex 5, DDR2 access
<praveena.naduviledath@gmail.com>:
155891: 13/10/12: Re: ModelSim view internal signals in instantiated verilog modules
<praveenkumar1979@rediffmail.com>:
84956: 05/06/01: Re: Query -V2Pro fpga programming
84979: 05/06/02: PCI master clock trace
84981: 05/06/02: Re: USB interface With AMBA AHB
85232: 05/06/06: Re: USB interface With AMBA AHB
88811: 05/08/29: Checking the PCI master implemented in FPGA
<praviendre@hotmail.com>:
99695: 06/03/28: actmap looks like not responding
99696: 06/03/28: actmap looks like not responding
99786: 06/03/29: free synthesizer to synthesize VHDL to Actel 1280XL FPGA
99792: 06/03/29: Re: free synthesizer to synthesize VHDL to Actel 1280XL FPGA
99804: 06/03/29: Re: free synthesizer to synthesize VHDL to Actel 1280XL FPGA
100233: 06/04/05: seq and comb modules of the FPGA, pls HELP me out !!
Pravin:
148464: 10/07/26: FPGA < -- > Processor timing Violations
Pravin G:
104187: 06/06/20: comp.arch.fpga : Selection of Device
<pravinsanap5@gmail.com>:
157222: 14/11/05: bitstream support for Artix 7 in torc?
PraZ:
95916: 06/01/26: Re: Constellation symbol to bit's soft-probability?
prc:
27041: 00/11/08: Global buffers in xc40000xla
27059: 00/11/09: Re: Global buffers in xc40000xla
Preben:
79066: 05/02/13: Fast counting in Spartan 3
81219: 05/03/19: Re: One-hot statemachine design problems
81440: 05/03/23: Re: Difference between simulation types
Preben Holm:
76256: 04/11/29: Which programmable clock for Spartan3 starter board and A/D-converter
76268: 04/11/29: Re: Which programmable clock for Spartan3 starter board and A/D-converter
76346: 04/11/30: Re: Which programmable clock for Spartan3 starter board and A/D-converter
79277: 05/02/16: Re: Fast counting in Spartan 3
79796: 05/02/24: Prescalable counter
79963: 05/02/27: Re: Prescalable counter
79964: 05/02/27: Re: Prescalable counter
79977: 05/02/27: Re: Prescalable counter
80005: 05/02/28: Re: Prescalable counter
80006: 05/02/28: Re: Prescalable counter
80024: 05/02/28: Re: Prescalable counter
80570: 05/03/08: ISE Foundation/BaseX 7.1i evaluation for Linux
80636: 05/03/09: RS232 VHDL-core
80652: 05/03/09: Re: RS232 VHDL-core
81014: 05/03/16: Sensitivity list
81025: 05/03/16: Re: Sensitivity list
81026: 05/03/16: type states is std_logic_vector(4 downto 0);
81029: 05/03/16: Filename of Webpack 7.1 installer on linux (anyone who got it on
81202: 05/03/19: One-hot statemachine design problems
81247: 05/03/20: Re: One-hot statemachine design problems
81248: 05/03/20: Post-map simulation models
81323: 05/03/21: Re: ISE Foundation/BaseX 7.1i evaluation for Linux
81351: 05/03/22: Re: One-hot statemachine design problems
81388: 05/03/22: Difference between simulation types
82337: 05/04/11: Timing
82358: 05/04/11: Re: Timing
82741: 05/04/17: Re: Timing
82823: 05/04/18: Re: Timing
82824: 05/04/18: Re: Timing
83130: 05/04/24: "Correct design" and practical trouble and simulation trouble but
83166: 05/04/25: Re: "Correct design" and practical trouble and simulation trouble
83170: 05/04/25: Re: "Correct design" and practical trouble and simulation trouble
83489: 05/05/01: Xilinx input path: Why does the optional delay element with inputFF
83559: 05/05/03: Re: Xilinx input path: Why does the optional delay element with inputFF
83591: 05/05/03: Re: Xilinx input path: Why does the optional delay element with inputFF
83829: 05/05/07: Clock delay vs. clock skew
83910: 05/05/09: Re: Clock delay vs. clock skew
85717: 05/06/14: Re: Selecting FPGA synthesis, place and route and simulation tools
86379: 05/06/27: Individual study-activity on FPGA's - which subsubject?
Preben Mikael Bohn:
62513: 03/10/31: Essential hazards in CPLD's?
62525: 03/10/31: Re: Essential hazards in CPLD's?
Predictor:
96861: 06/02/12: Re: Async Processors
preet:
99537: 06/03/26: Re: miniuart
99538: 06/03/26: need help,test on Spartan3 starter kit
99915: 06/03/30: Re: need help,test on Spartan3 starter kit
99917: 06/03/30: Picoblaze, UART: need help!!
prem:
25959: 00/09/27: Re: An Online Course for CPLD and FPGA design
25961: 00/09/28: Re: An Online Course for CPLD and FPGA design
premrajan:
114170: 07/01/05: query
<PrestonMc@gmail.com>:
123519: 07/08/29: Re: Problems with PLB_DDR2 core and soft reset
PretzelX:
121464: 07/07/05: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
122631: 07/08/02: Re: regarding RTOS in NIOS II
122909: 07/08/10: EDK (XPS) - Path problem causing "Generate Libraries and BSPs" to
Prevailing over Technology:
136465: 08/11/18: Re: What happened to the Cyclone IV?
136767: 08/12/04: Re: Query on Xilinx Nomenclature
136917: 08/12/13: Re: Doubt about the maximum speed of FPGA clock nets
137264: 09/01/06: Re: Digilent
137453: 09/01/17: Re: Spartan 3E reset problem
137454: 09/01/17: Re: Actel IGLOO FPGA has lower power consumption then Xilinx
137474: 09/01/19: Re: Actel IGLOO FPGA has lower power consumption then Xilinx
137538: 09/01/21: Re: FPGA granularity (was Re: Actel IGLOO FPGA)
139136: 09/03/21: Re: Silicon Blue Warm-Boot not working properly
139137: 09/03/21: Re: Xilinx XAPP052 LFSR and its understanding
139261: 09/03/24: Re: Silicon Blue last datesheet correct URL
139263: 09/03/24: Re: Silicon Blue last datesheet correct URL
139475: 09/03/31: Re: Silicon Blue Warm-Boot not working properly
141235: 09/06/11: Re: Latest Xilinx Discontinuations
141236: 09/06/11: Re: Xilinx Block RAM Sim
141237: 09/06/11: Re: AT&T Usenet Netnews Service Shutting Down
141521: 09/06/26: Re: New feauture in Spartan-6 FPGA's: SELF DESTRUCT !!
144869: 10/01/10: Re: new PC specs for Xilinx tools
146483: 10/03/19: Re: FPGA's with on-chip PROM?
147558: 10/05/03: Re: Cheap FPGAs for tutorial
149294: 10/10/14: Happy birthday, Bernie!
149532: 10/11/02: LVDS-based LCD Display, Minimum Clock Rates
149652: 10/11/13: Re: Spartan3 bidirectional 3.3V 5V level shifter
149653: 10/11/13: Re: cool BGA pattern
149772: 10/11/23: Re: Intel Atom + FPGA
149773: 10/11/23: Re: Synthesis/place and route with Solid-State Drives
149965: 10/12/03: [HUMOR]: The Danger of When Programmable Logic Meets the Consumer
priitr:
115293: 07/02/06: Re: 9.1i in Red Hat Enterprise Linux AS 64-bit
primiano:
148374: 10/07/16: Timing analysis of asynchronous bus peripherals
<prince.kiran@gmail.com>:
157016: 14/08/27: Re: How to reduce "Core static thermal dissipation" from fpga design
<prince@dyumnin.com>:
124657: 07/09/29: Re: Does Modelsim work under Windows Vista?
princesse91:
157780: 15/03/16: Re: Handel-C to VHDL
157879: 15/05/07: Re: synthesis tool for systemc
Pritha Ghoshal:
138762: 09/03/09: Image loading into FPGA - from computer
138771: 09/03/09: Re: Image loading into FPGA - from computer
Prithvi Shyam Bhargava:
110868: 06/10/24: Help with SysAce CF
priya:
96051: 06/01/28: XPower- Advanced power report
96198: 06/01/31: Re: XPower- Advanced power report
Priyal:
56434: 03/06/04: Topic for Masters Project
56476: 03/06/05: Masters Project Topic
PROCOM:
29619: 01/03/01: * HOT JOBS * ASIC / FPGA / VLSI designers needed - Canada
29703: 01/03/05: Jobs @ ASIC / FPGA / VLSI designers needed - Canada
29781: 01/03/09: $HOT JOBS$ ASIC / FPGA / VLSI designers needed - Canada
30619: 01/04/19: Jobs@ ASIC / FPGA / VLSI designers needed - Canada
30620: 01/04/19: Senior ASIC Designers Needed - Canada
31459: 01/05/25: Jobs ASIC / FPGA / VLSI designers needed - Canada
Prodatron / SymbiosiS:
101600: 06/05/03: CPC TREX 24MHz Turbo Core available PLUS complete source code
Prof. Dr. B. Steinbach:
8957: 98/02/09: CfP: 3rd International Workshop on Boolean Problems
Prof. Dr. Hermann Haertig:
445: 94/11/18: PC boards with Xilinx fpgas
Prof. Richard J. Auletta:
679: 95/02/04: ASIC '95 Call For Papers
771: 95/02/27: ASIC '95 Call For Papers
Prof. Vitit Kantabutra:
7293: 97/08/21: division paper
7279: 97/08/20: new radix-8 division algorithms
7947: 97/11/01: Re: Division & Multiplication (unsigned/signed) - Need HELP
8027: 97/11/08: Re: Division using FPGAs
9262: 98/03/04: Any not-so-buggy design software?
9868: 98/04/09: Re: Investigate anyone right from your browser!
9867: 98/04/09: Re: Investigate anyone right from your browser!
9980: 98/04/20: Could you help me save CLB's?
9990: 98/04/21: Re: Could you help me save CLB's?
10079: 98/04/26: Re: Could you help me save CLB's?
10215: 98/05/04: Radix-4 CORDIC pipeline -- which chip?
10608: 98/06/05: Is there tiling software?
<prof.brown@gmail.com>:
125793: 07/11/05: Re: Weird behavior : Altera DE2, C++, For loops, SRAM
Professor Frank L. Donaldson:
<programz_4u@writeme.com>:
<programz_d@consultant.com>:
project:
18537: 99/10/29: DSP board for FPGA (I need general info)
18573: 99/11/01: Roots of development of FPGA's
18611: 99/11/03: Why DSP in a FPGA?
18637: 99/11/04: Price of FPGA
project help:
114613: 07/01/20: suggest me the right fpga
114627: 07/01/21: project help
promach:
160237: 17/08/14: Suggestion on methodology/ways to test my internal logic analyzer
160255: 17/08/30: registers delay
160257: 17/09/16: logic scope coding
160259: 17/09/21: duty cycle of clock divider
160261: 17/09/21: Re: duty cycle of clock divider
160263: 17/09/21: Re: duty cycle of clock divider
160264: 17/09/21: Re: duty cycle of clock divider
160265: 17/09/21: Re: duty cycle of clock divider
160266: 17/09/22: Re: duty cycle of clock divider
160276: 17/10/11: UART receiver
160586: 18/04/27: verilog reg usage
PRook41179:
proski:
52978: 03/02/27: Re: SChematic design approach compared to VHDL entry approach
ProSyst:
17416: 99/07/26: Epld to Fpga design.
pruthvi:
74899: 04/10/21: Re: simprim errors
przemek:
35143: 01/09/24: Re: Clockin on rising AND falling edge
Przemek Guzy:
67757: 04/03/18: Re: Logiclock TCL flow for Quartus II
67758: 04/03/18: Re: LogicLock
67902: 04/03/22: Re: Logiclock TCL flow for Quartus II
67967: 04/03/23: Re: Logiclock TCL flow for Quartus II
przemek klosowski:
105312: 06/07/20: Re: An idea for a product (FPGA/ASIC based)
134856: 08/09/04: Re: need fast FPGA suggestions
135280: 08/09/24: Re: Peter says Good Bye
Przemek Klosowski:
156125: 13/12/05: Re: microZed adventures
Przemyslaw Wegrzyn:
38135: 02/01/07: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38147: 02/01/07: Re: Xilinx - Spartan, Spartan II, Virtex, Virtex II differences
38905: 02/01/28: Books on DSP
39290: 02/02/05: Re: FPGA vs GAL : Lattice
39747: 02/02/18: Xilinx IP Core multiplier performance
39831: 02/02/21: Re: Xilinx IP Core multiplier performance
43055: 02/05/11: Adders in Xilinx XC4000
43472: 02/05/22: Aldec Active-HDL 5.1 + Xilinx ISE 4.1 - how to simulate ?
43506: 02/05/22: Re: Aldec Active-HDL 5.1 + Xilinx ISE 4.1 - how to simulate ?
43522: 02/05/22: Re: Aldec Active-HDL 5.1 + Xilinx ISE 4.1 - how to simulate ?
43523: 02/05/22: Xilinx STARTUP and PADS problems
63924: 03/12/09: BUFT resources in Spartan II
63953: 03/12/10: Re: BUFT resources in Spartan II
64978: 04/01/17: Spartan XC2S200 - how many BlockRAMs ?
119261: 07/05/16: SERDES question (Lattice ispHSI)
PSandF:
<psgandhi@gmail.com>:
114460: 07/01/16: Clock Frequency
<pshimizu@fa2.so-net.ne.jp>:
12979: 98/11/09: Synthsizable processor code
13321: 98/11/25: Open source Java processor
psihodelia@googlemail.com:
125834: 07/11/06: Why dynamic partial reconfiguration is still not there?
126192: 07/11/16: VHDL language is out of date! Why? I will explain.
126251: 07/11/18: Re: VHDL language is out of date! Why? I will explain.
126265: 07/11/18: Re: VHDL language is out of date! Why? I will explain.
126564: 07/11/27: Re: VHDL language is out of date! Why? I will explain.
126571: 07/11/27: What tools do you use ? Why ?
126733: 07/11/30: Re: What tools do you use ? Why ?
127224: 07/12/14: Re: VHDL language is out of date! Why? I will explain.
127231: 07/12/14: Re: VHDL language/MyHDL
135176: 08/09/19: What software do use big organizations for Logic Synthesis from HDL?
<psihodelia@googlemail.com>:
117171: 07/03/25: Where is Open Source for FPGA development?
psiinc:
1769: 95/08/29: ATLANTA, DIGITAL DESIGN ENGINEER
psisabel:
25467: 00/09/12: MEMORY
<psommerfeld@gmail.com>:
76634: 04/12/07: Re: Verilog Book Recommendation
psustew:
158391: 15/10/29: Re: recovery/removal timing
158410: 15/10/30: Re: recovery/removal timing
Psycho333221:
21772: 00/03/31: Re: Pipelined ALTERA LPMs - where are the registers introduced?
Pszemol:
65874: 04/02/09: [Quartus] File folders changed -> errors
65895: 04/02/09: Re: [Quartus] File folders changed -> errors
65905: 04/02/09: [Altera/Quartus] Tools to regenerate block schematics from .vhd files
65958: 04/02/10: Re: [Altera/Quartus] Tools to regenerate block schematics from .vhd files
67417: 04/03/11: Altera, Cyclone: pin not connected warning
67474: 04/03/12: Re: Altera, Cyclone: pin not connected warning
69397: 04/05/10: 80186 processor core
70216: 04/06/09: Altera Instructor-led course on Designing with NIOS II
70433: 04/06/16: Many UARTs on Avalon bus with NIOS cpu
97521: 06/02/23: 8051 IP core with JTAG debugger for FPGA?
97535: 06/02/23: Re: 8051 IP core with JTAG debugger for FPGA?
97541: 06/02/23: Re: 8051 IP core with JTAG debugger for FPGA?
124724: 07/10/01: ALTERA Quartus 7.2 under MS Vista
Ptarmigan:
19190: 99/12/04: Re: Leonardo Spectrum Printing Problem
20549: 00/02/14: Verilog DRC?
Ptmsa1:
8968: 98/02/10: TPC1020AFN-068C DEVICES REQUIRED
<ptrei@securitydynamics.com>:
9946: 98/04/15: Problems with Trianus on Windows?
10165: 98/04/30: XC6200: Gate vs site count?
public pc:
59171: 03/08/11: VME FPGA master slave system
Puneet:
53085: 03/03/03: Re: Bus Functional Model
Puneet Goel:
61075: 03/09/27: Re: Free WebPack 6.1i Download Available Now for Spartan-3
<puneetjamrani@gmail.com>:
129334: 08/02/21: Reconfiguration (on the fly) using SPARTAN 3A
129368: 08/02/22: Re: Reconfiguration (on the fly) using SPARTAN 3A
129369: 08/02/22: Re: Reconfiguration (on the fly) using SPARTAN 3A
129422: 08/02/23: Re: Reconfiguration (on the fly) using SPARTAN 3A
<Puneetsingh81@gmail.com>:
82789: 05/04/18: Re: SPROM JTAG confusion!
PureSine:
146812: 10/03/29: infering BRAM for a FIFO in XST(spartan 3)
146835: 10/03/30: Re: infering BRAM for a FIFO in XST(spartan 3)
146839: 10/03/30: Re: infering BRAM for a FIFO in XST(spartan 3)
146947: 10/04/04: Is there a way to implement division by variables other than 2 in
146955: 10/04/04: Re: Is there a way...(Thanks all)
146956: 10/04/04: Re: Is there a way...(Thanks all)
purple_stars:
103202: 06/05/28: fpga uclinux, good starter board ?
Purvesh:
77145: 04/12/25: Re: PCI doubt
77148: 04/12/25: Re: PS: Synchronous design and power consumption
77149: 04/12/25: SATA/SAS designs with FPGA
77297: 05/01/03: Re: Skew between signals
77360: 05/01/05: Re: Help needed getting started with virtex II pro
77495: 05/01/07: Re: San Jose job offer - need advice
78622: 05/02/04: Re: Xilinx Virtex4 / Spartan3 High Speed Designs
puzzled:
73564: 04/09/24: Webpack 6.3 and Spartan3-1000/1500?
<pvnguyen@mail.ucf.edu>:
84893: 05/05/31: Implementing sin function in fpga
84931: 05/06/01: Re: Implementing sin function in fpga
84941: 05/06/01: Re: Implementing sin function in fpga
pwie42:
124454: 07/09/22: DDR RAM timing contraints
124982: 07/10/14: Re: MIG for Linux?
<pwslxk@sssdfdf.org>:
<pxwwxp@you.com>:
31138: 01/05/12: Meet others in you area tonight!! Free AD placement!
PYD:
20021: 00/01/24: Polynomial calculation on FPGA ???
33036: 01/07/16: Re: Altera's ByteBlasterMV cable resistor values (2.2 ohms) ?
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