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There are many different qualifications that apply to "Mil" systems. For example: airworthiness, safety-critical, nuclear certified, and multi-level secure, etc. Each of the branches in the US have their own certifying organizations. Can't speak for Italian military. However, it is safe to say that many military systems use VxWorks, RTEMS, Integrity, Lynx-OS, and even several flavors of real time Linux. I'm sure there are others that are just as good that are not mentioned, but these are a good place to start. Also, there are still a number of systems that are developed without a commercial RTOS, but use a simple cyclic exec or just an Ada Runtime on a 'bare target'. Good luck. "Marco T." <marc@blabla.com> wrote in message news:e60l2c$g0$1@nnrp.ngi.it... > Hallo, > which RTOS have been MIL-Qualified to run on PowerPc 405 (in Virtex-4 FX)? > > Many Thanks > Marco Toschi > >Article: 103551
Rickman, You can also use the "Web Installer" and then select the check boxes to "Install Later" and "Retain Downloaded Files". This will give you the individual install options and you can eliminate some of the tools you don't want, or break it up over multiple CDs. Ryan Laity Xilinx pbdelete@spamnuke.ludd.luthdelete.se.invalid wrote: >>> Try "bzip2 -9z", it will compress most things to the limit. > >> Or you could just binary split the file [use 2 CDs], dunno about MS windows, >> but in Linux in the CD age I used dd, and cat on the other side. > >> There is a similar command even for MSDOS. > >> In Linux, create 2 images: >> dd if=myfile bs=1000000 count=700 of=part1 >> dd if=myfile bs=1000000 skip=700 of=part2 > > There's even simpler command for that :p > > split -b 640m myfile > > Should split myfile in 640 Mbyte chunks. >Article: 103552
Forgot the message :) Anyone know of a decent FPGA/Prom Jtag programmer for Xilinx FPGAs? Thanks, Colin "Colin Hankins" <colinhankins@cox.net> wrote in message news:id4hg.93001$TK1.16745@fed1read06... > >Article: 103553
rickman wrote: > I don't know exactly when this happened, but webpack will no longer fit > on a single CD. I seem to recall when they split the download into > multiple files so that they could be loaded in pieces over a phone > line. Now the size means you have to have a DVD burner to carry it > from one machine to the other. > > Any chance webpack can be provided in two hunks each of which will fit > on a CD? Thanks for all the potential solutions. But they pretty much all won't work for me. I can try the Xilinx web install with the retain files option. But if it has to actually "install" the files, it won't work for me. I am at a facility where we can't install any software ourselves. We have to have IT do it for us. That eliminates most of the other solutions as well. I guess I can just let IT figure out how to get the software onto a machine that is not on the network. I have a 1 GB flash drive, but I don't care to copy all my files off of it and I probably will be violating some rule using my own storage rather than theirs. The solution I like best is to get the latest copy of WinZip which will break up archives to 650 or 700 MB hunks. But this is yet another piece of software I have to get IT to buy and install on *both* machines. The office has a prohibition to taking stuff home or I would use my Flash drive to copy the file to home where I can burn a DVD. I haven't found a DVD burner at work yet. So to make my life, and possibly others who work in the defence community, easier, Xilinx can you provide webpack in two files which will each fit on a CD? I know that I can order a DVD for $6 and in this case I will have to do that. But the ease of downloading a file in a few minutes is such a better solution than to have to have a purchase requisition generated, etc... for just $6! Besides, the secretary who can use the credit card is out of the office all this week!!!Article: 103554
Rickman, there is a simple short-term fix: Pay the $6 out of your own pocket. It's less than a cafeteria lunch... Avoids a lot of hassles, and waste of taxpayers' money. That $6 puchase order easily becomes a $50+ burden for the taxpayer. Please, no flames from people who think that $6 is a fortune. Peter, speaking for himself (and out of experience) ================= rickman wrote: > rickman wrote: > > I don't know exactly when this happened, but webpack will no longer fit > > on a single CD. I seem to recall when they split the download into > > multiple files so that they could be loaded in pieces over a phone > > line. Now the size means you have to have a DVD burner to carry it > > from one machine to the other. > > > > Any chance webpack can be provided in two hunks each of which will fit > > on a CD? > > Thanks for all the potential solutions. But they pretty much all won't > work for me. I can try the Xilinx web install with the retain files > option. But if it has to actually "install" the files, it won't work > for me. I am at a facility where we can't install any software > ourselves. We have to have IT do it for us. That eliminates most of > the other solutions as well. > > I guess I can just let IT figure out how to get the software onto a > machine that is not on the network. I have a 1 GB flash drive, but I > don't care to copy all my files off of it and I probably will be > violating some rule using my own storage rather than theirs. > > The solution I like best is to get the latest copy of WinZip which will > break up archives to 650 or 700 MB hunks. But this is yet another > piece of software I have to get IT to buy and install on *both* > machines. > > The office has a prohibition to taking stuff home or I would use my > Flash drive to copy the file to home where I can burn a DVD. I haven't > found a DVD burner at work yet. > > So to make my life, and possibly others who work in the defence > community, easier, Xilinx can you provide webpack in two files which > will each fit on a CD? > > I know that I can order a DVD for $6 and in this case I will have to do > that. But the ease of downloading a file in a few minutes is such a > better solution than to have to have a purchase requisition generated, > etc... for just $6! Besides, the secretary who can use the credit card > is out of the office all this week!!!Article: 103555
On Mon, 05 Jun 2006 19:05:21 -0700, Peter Alfke top-posted: > Rickman, there is a simple short-term fix: > Pay the $6 out of your own pocket. It's less than a cafeteria lunch... > Avoids a lot of hassles, and waste of taxpayers' money. > That $6 puchase order easily becomes a $50+ burden for the taxpayer. > Please, no flames from people who think that $6 is a fortune. > > Peter, speaking for himself (and out of experience) [Peter, please learn to bottom-post, it's much easier on the flow of the thread.] > rickman wrote: >> I know that I can order a DVD for $6 and in this case I will have to do >> that. But the ease of downloading a file in a few minutes is such a >> better solution than to have to have a purchase requisition generated, >> etc... for just $6! Besides, the secretary who can use the credit card >> is out of the office all this week!!! I'd be willing to bet money that if rickman were to buy something like that out of his own pocket in the high-security military milieu he seems to be in, he'll get in a lot more trouble than if he goes through channels - and since this is taxpayer-funded, they don't care how long it takes, as long as you spend the budget before audit time. ;-) Good Luck! RichArticle: 103556
Sure, short term I don't mind paying $6. My employer has bought me lunch more than once. But I am asking Xilinx for the long term fix. Now that webpack has broken the single CD barrier, how about making this process easier for us by splitting it into CD sized chunks? I will pay the $6 for 8.1, but I don't want to have to repeat this for 8.2 and 8.3 and all the various service packs, etc. I have identified a way that Xilinx can make life easier for some of its customers. I would like to think that this suggestion could be given reasonable consideration. BTW, if you had any idea how much waste there really is in government contracting, you wouldn't worry about even a lousy $50. We just had some 4 or more people (plus a Xliinx FAE) focused on why we could not configure the Spartan 3 on our board. Because the software, gateware and hardware were all done by different people (or groups even) no one person (or even team) had enough knowledge to understand what was wrong. Between the software and FPGA groups stealing my boards and running off in the middle of testing, the first two days were a total waste. On the third day I finally explored why the CCLK (write strobe from the DSP) was spaced the way it was (8 pairs, 16 total with a gap before the next set of 16) with the DSP coder. Seems we were writing 32 bit words to a 16 bit memory space which was generating two strobes for every write. It was such a waste of time and money to spend some 3 man weeks figuring this out! I don't like working like this, but these are the jobs you can get around DC. Defense and telecom. I worked telecom once and did not care for it. Telecom seems to be driven to squeeze every penny out of you by asking you to do a lot of work in a little time with little equipment. Too bad there doesn't seem to be a happy medium around here. In the meantime I am trying to get around the difficulties of dealing with IT, the secretary being out of the office (no credit card purchases) and the general BS of working in a defense company. In case you haven't figured it out yet, I want the webpack on a lab machine because then I can bypass the FPGA and software people and generate my own test code. So yes, I'll spend the $6 this time for webpack 8.1. Any chance Xilinx can meet me halfway and make version 8.2 available in CD sized chunks? Peter Alfke wrote: > Rickman, there is a simple short-term fix: > Pay the $6 out of your own pocket. It's less than a cafeteria lunch... > Avoids a lot of hassles, and waste of taxpayers' money. > That $6 puchase order easily becomes a $50+ burden for the taxpayer. > Please, no flames from people who think that $6 is a fortune. > > Peter, speaking for himself (and out of experience) > ================= > rickman wrote: > > rickman wrote: > > > I don't know exactly when this happened, but webpack will no longer fit > > > on a single CD. I seem to recall when they split the download into > > > multiple files so that they could be loaded in pieces over a phone > > > line. Now the size means you have to have a DVD burner to carry it > > > from one machine to the other. > > > > > > Any chance webpack can be provided in two hunks each of which will fit > > > on a CD? > > > > Thanks for all the potential solutions. But they pretty much all won't > > work for me. I can try the Xilinx web install with the retain files > > option. But if it has to actually "install" the files, it won't work > > for me. I am at a facility where we can't install any software > > ourselves. We have to have IT do it for us. That eliminates most of > > the other solutions as well. > > > > I guess I can just let IT figure out how to get the software onto a > > machine that is not on the network. I have a 1 GB flash drive, but I > > don't care to copy all my files off of it and I probably will be > > violating some rule using my own storage rather than theirs. > > > > The solution I like best is to get the latest copy of WinZip which will > > break up archives to 650 or 700 MB hunks. But this is yet another > > piece of software I have to get IT to buy and install on *both* > > machines. > > > > The office has a prohibition to taking stuff home or I would use my > > Flash drive to copy the file to home where I can burn a DVD. I haven't > > found a DVD burner at work yet. > > > > So to make my life, and possibly others who work in the defence > > community, easier, Xilinx can you provide webpack in two files which > > will each fit on a CD? > > > > I know that I can order a DVD for $6 and in this case I will have to do > > that. But the ease of downloading a file in a few minutes is such a > > better solution than to have to have a purchase requisition generated, > > etc... for just $6! Besides, the secretary who can use the credit card > > is out of the office all this week!!!Article: 103557
rickman wrote: > > In the meantime I am trying to get around the difficulties of dealing > with IT, the secretary being out of the office (no credit card > purchases) and the general BS of working in a defense company. In case > you haven't figured it out yet, I want the webpack on a lab machine > because then I can bypass the FPGA and software people and generate my > own test code. So yes, I'll spend the $6 this time for webpack 8.1. > Any chance Xilinx can meet me halfway and make version 8.2 available in > CD sized chunks? > Thanks, Rickman. For a short while I worried that you or somebody might chastize me for my "arrogant" proposal. But that did not happen... Thanks! I will poke around in Xilinx, if there is a meaningful way to overcome real and also bureaucratic/security obstacles. We are now 3000 people, which unfortunately creates its own bureaucracy, witness our/my inability to resurrect the Xilinx component store... Some things are so much easier in a 100-man start-up (which Xilinx was, when I started here). If somethings needed to be done, you just did it, and asked for permission afterwards. I loved it. I do my best to keep that attitude, with some success... Peter Alfke, Xilinx (from home) >Article: 103558
Rickman, You don't have to install them using the web installer - that's why I suggested that you check the "Install Later" box once the installer downloads and you run it. That makes the Web Installer just act like a download tool. You get installers that can easily be installed from a CD at a later time (even by IT). I've also forwarded this request on the right person within Xilinx, perhaps he will comment. I certainly don't think that the web installer is the most intuitive way to download individual installers so I am motivated to get this suggestion in the hands of someone who can do something about it. Nonetheless, I've used this method for my customers (I'm an FAE) to get a lab-only install of iMPACT standalone, so I've been through it myself. Best regards, Ryan Laity BTW - Rich, I don't like bottom posting, I think that top posting is much easier for the flow of the thread (just start at the bottom and work up). rickman wrote: > Sure, short term I don't mind paying $6. My employer has bought me > lunch more than once. But I am asking Xilinx for the long term fix. > Now that webpack has broken the single CD barrier, how about making > this process easier for us by splitting it into CD sized chunks? I > will pay the $6 for 8.1, but I don't want to have to repeat this for > 8.2 and 8.3 and all the various service packs, etc. > > I have identified a way that Xilinx can make life easier for some of > its customers. I would like to think that this suggestion could be > given reasonable consideration. > > BTW, if you had any idea how much waste there really is in government > contracting, you wouldn't worry about even a lousy $50. We just had > some 4 or more people (plus a Xliinx FAE) focused on why we could not > configure the Spartan 3 on our board. Because the software, gateware > and hardware were all done by different people (or groups even) no one > person (or even team) had enough knowledge to understand what was > wrong. Between the software and FPGA groups stealing my boards and > running off in the middle of testing, the first two days were a total > waste. On the third day I finally explored why the CCLK (write strobe > from the DSP) was spaced the way it was (8 pairs, 16 total with a gap > before the next set of 16) with the DSP coder. Seems we were writing > 32 bit words to a 16 bit memory space which was generating two strobes > for every write. It was such a waste of time and money to spend some 3 > man weeks figuring this out! > > I don't like working like this, but these are the jobs you can get > around DC. Defense and telecom. I worked telecom once and did not > care for it. Telecom seems to be driven to squeeze every penny out of > you by asking you to do a lot of work in a little time with little > equipment. Too bad there doesn't seem to be a happy medium around > here. > > In the meantime I am trying to get around the difficulties of dealing > with IT, the secretary being out of the office (no credit card > purchases) and the general BS of working in a defense company. In case > you haven't figured it out yet, I want the webpack on a lab machine > because then I can bypass the FPGA and software people and generate my > own test code. So yes, I'll spend the $6 this time for webpack 8.1. > Any chance Xilinx can meet me halfway and make version 8.2 available in > CD sized chunks? > > > Peter Alfke wrote: >> Rickman, there is a simple short-term fix: >> Pay the $6 out of your own pocket. It's less than a cafeteria lunch... >> Avoids a lot of hassles, and waste of taxpayers' money. >> That $6 puchase order easily becomes a $50+ burden for the taxpayer. >> Please, no flames from people who think that $6 is a fortune. >> >> Peter, speaking for himself (and out of experience) >> ================= >> rickman wrote: >>> rickman wrote: >>>> I don't know exactly when this happened, but webpack will no longer fit >>>> on a single CD. I seem to recall when they split the download into >>>> multiple files so that they could be loaded in pieces over a phone >>>> line. Now the size means you have to have a DVD burner to carry it >>>> from one machine to the other. >>>> >>>> Any chance webpack can be provided in two hunks each of which will fit >>>> on a CD? >>> Thanks for all the potential solutions. But they pretty much all won't >>> work for me. I can try the Xilinx web install with the retain files >>> option. But if it has to actually "install" the files, it won't work >>> for me. I am at a facility where we can't install any software >>> ourselves. We have to have IT do it for us. That eliminates most of >>> the other solutions as well. >>> >>> I guess I can just let IT figure out how to get the software onto a >>> machine that is not on the network. I have a 1 GB flash drive, but I >>> don't care to copy all my files off of it and I probably will be >>> violating some rule using my own storage rather than theirs. >>> >>> The solution I like best is to get the latest copy of WinZip which will >>> break up archives to 650 or 700 MB hunks. But this is yet another >>> piece of software I have to get IT to buy and install on *both* >>> machines. >>> >>> The office has a prohibition to taking stuff home or I would use my >>> Flash drive to copy the file to home where I can burn a DVD. I haven't >>> found a DVD burner at work yet. >>> >>> So to make my life, and possibly others who work in the defence >>> community, easier, Xilinx can you provide webpack in two files which >>> will each fit on a CD? >>> >>> I know that I can order a DVD for $6 and in this case I will have to do >>> that. But the ease of downloading a file in a few minutes is such a >>> better solution than to have to have a purchase requisition generated, >>> etc... for just $6! Besides, the secretary who can use the credit card >>> is out of the office all this week!!! >Article: 103559
Jim Wu wrote: > I normally use my own script for MPPR. The script "run_mppr" that I use > is available at http://home.comcast.net/~jimwu88/tools/ under > "Makefiles for running ISE command line tools". > > HTH, > Jim Thanks Jim.Article: 103560
Xilinx app note XAPP426 v1.3 (March 2006) indictes that: "Xilinx has no experience or reliability data on flip-chip BGA packages on board after exposure to conformal coating." WTFO ? How is it possible with Xilinx being so tight with Military developers that they haven't tested their parts under the conditions which nearly all military boards are produced? What am I missing? Have they been sworn to secrecy? :-)) -BHArticle: 103561
Mike Treseler kirjoitti: > kevinwolfe@gmail.com wrote: > > This strikes me as more trouble than it is worth. > Normally there are many source files in > a project and each has a different revision number > that could change daily. Product releases don't happen > nearly that often because of QA testing. Subversion has only one version number for whole project. At first it sounded strange, but after half year working with Subversion, that is an excelent thing. When I make a FPGA version (program file) I make a release from trunk (svn copy). Check out the release to specific version directory and run Quartus and check in program files (sof/pof) to repository. Since the .sof and .pof have a version number, it can be easily identify source files based on the .pof/.sof version number. (if source_a.vhdl is lower than fpga.pof, then it must be in pof and vice versa) Antti > If I wanted to read back something, it would > have to do with the overall product release date. > I think I would take Andy's advice and just make > this some kind of constant that I just type in. > Then no one else has to know or worry about it. > > -- Mike TreselerArticle: 103562
Antti a écrit :
>>>the usb micro is cypress fx2
> I did not say the FIFO port is connected - I said that the USB
> controller can be used for user defined protocols, also
> transferring user data
> well they dont provide and user communication over the USB
> controller, but sure it would be possible, maybe not with the max
> transfer rate, but still possible
OK, well, it is a pity (for me, I suppose those pins are more useful
somewhere else for other people).
I guess I have to look towards boards like Orange Tree Tech.'s
ZestSC1, Opal Kelly's XEM3001 or Cesys' USB3FPGA. Only problem is that
they are 2 or 3 or 4 times the price as Xilinx' S3E starter kit without
all the functions this starter kit includes.
Goodbye,
Stéphane.
Article: 103563Peter Alfke schrieb: > rickman wrote: >>with IT, the secretary being out of the office (no credit card >>purchases) and the general BS of working in a defense company. > I will poke around in Xilinx, if there is a meaningful way to overcome > real and also bureaucratic/security obstacles. While I am sure that a defense company can afford a DVD burner to obtain software, as a CAD software developer I always wondered, why a single FPGA device needs more than 40MB of characterisation data. Rethinking the file format for the NPH and GRF files would probably reduce the foundation install size by 1GB. I guess the format was invented in XC2K times and noone really thought that exploiting the regularity in the device would be worth the hassle. Kolja SulimmaArticle: 103564
Ron <News5@spamex.com> writes: > The thing that bothers me most about abstract computer languages such > as COBOL, Lisp, ADA, and I will include VHDL in this category) is > that the hardware the design is implemented on is *not* abstract at > all - it is composed of bits and bytes and elementary operations an > ALU can perform, and so if I care anything at all about performance I > like to use a relatively low level language. > The thing about VHDL is that although it has some highish levels of abstraction, which are great for the test environment. However, if you are writing synthesisable code, you are much more constrained, and the language maps relatively predictably (most of the time) onto device hardware. So you get the best of both worlds. IMHO There's no *design performance* reason to prefer Verilog over VHDL. At the RTL level they are pretty much equivalent nowadays (as I understand it, I'm predominantly a VHDL man myself) > I think it's rather amusing that whenever I do a new Verilog design, I > usually begin by coding the algorithm in the Maple computer > language. Maple is a very high level arbitrary precision language that > can do symbolic algebra, calculus, differential equations, etc. It may > be a surprising choice as a design language for Verilog, but it works > quite well because Maple allows me to do pretty much whatever I want > without regard to implementation specifics. When I wrote the Verilog > implementation of Lenstra's Elliptic Curve Factoring method (ECM), I > started by writing a Maple program from the algorithm described in a > textbook, and then gradually decomposed each of the higher level > operations into simpler operations until I had something that could be > implemented easily in Verilog. :-) > That's always a good way to proceed :-) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.trw.com/conektArticle: 103565
"Brandon Jasionowski" <killerhertz@gmail.com> wrote in message
news:1149546962.801753.53900@h76g2000cwa.googlegroups.com...
> Ok, so I'm working with a COTs DSP board vendor's ISE project and
> customizing the logic (essentially tossing code in a user wrapper).
> Unfortunately, I'm having some 'user-friendly' issues with the project
> file and customizability.
> 1) 'sys_clk_in' is a board clock at 100 MHz (constrained to 112 MHz)
> 2) 'sys_clk' is derived from 'sys_clk_in' via DCM's fx output at 4/3.
> 'sys_clk' needs to operate at 125 MHz (constrained to ~150 MHz).
> -His response:
> <SNIP>"You're right. The Xilinx tool has a bug. Something about
> spinning up a clock using a DCM & subsequent timing analysis. The
> hardware does work."</SNIP>
>
> -My questions to those experienced:
> I've seen clock's overconstrained before with another vendor.
> 1) Is this a common practice? If so, I could envision timing results
> being highly overconstrained when dealing with DCMs.
It is reasonably common to see designs overconstrained in the synthesis
phase, to compensate for the fact that many synthesis tools underestimate
the routing delays in a design. It's not an ideal situation, but often it's
the only way to ensure the design meets timing later on.
The only reason I can think of to overconstrain a design at the PAR stage is
if there is a requirement that the FPGA clock be variable without altering
the FPGA bitstream. That is, in your case, if the sys_clk_in could
theoretically one day be run at up to 112MHz.
Otherwise, overconstraining the clock at PAR is pointless (you just increase
the runtime of the tools without buying yourself any extra performance).
> 2) Is this really a bug or is the project misconstrained?
Hard to say, without seeing the constraints file.
The "hold error" is a little worrying (maybe this is an IO placement
issue?), and the 20us cycle time figure for the 150MHz "TS_clk_fx" domain is
very strange indeed - is there really a path that long in the design? That
sounds like a good candidate for a bug. It's not one I've heard of though
(anyone?).
BTW, what version of the Xilinx tools are you using?
> 3) Am I crazy to think it's unreasonable to be given a
> 'user-defineable' project with timing that is seemingly failing by
> default? (i.e. how am I to modify the project and know it will work if
> the baseline does not meet timing?)
No, you're not crazy.
I've seen some FPGA projects where the engineer just eyeballs the log file
full of timing errors and says, "that's not a problem, that's not a
problem...". Not a good way to work. If you don't have any documentation of
exactly why these timing errors are there and a good engineering
justification of why they don't matter - preferably including timing
diagrams - I would run away. If you have that option, of course. :-)
-Ben-
Article: 103566
Hi all,
I am using 6.3.02i Xilinx editor and Modelsim 5.3 simulator. I am
slightly confused about which type of address decoding logic should be
used when?.
Consider an example where I need to write and read back some 50
registers in FPGA from a host processor.
Consider,
S_Write_Enable <= write_from_cpu or Ce ;
-- /AWE(Write enable) or /CE(chip enable(Active low))
S_Read_Enable <= read_from_cpu or Ce;
-- /ARE(Read enable) or /CE(chip enable(Active low))
I first tried to use the Case logic,as I needed to program 4 channel
parameters, which could be easily written using Case logic.
Process(S_Write_Enable,Reset)
variable Vl_Offset : std_logic_vector(3 downto 0);
variable Vl_ch_num : std_logic_vector(1 downto 0);
begin
if(Reset = '1') then
-- initializatin
elsif(S_Write_Enable'event AND S_Write_Enable = '0') then
Vl_Offset := address_input(3 downto 0);
Vl_ch_num := conv_integer(address_input(5 downto 4));
case Vl_Offset is
when ZERO =>
S_Ch_Control_Reg <= data_bus;
when ONE =>
S_Code_Phase_Inc(Vl_ch_num)(31 downto 16) <= data_bus;
when TWO =>
S_Code_Phase_Inc(Vl_ch_num)(15 downto 0) <= data_bus;
when THREE =>
S_Data_Phase_Inc(Vl_ch_num)(31 downto 16) <= data_bus;
when FOUR =>
S_Data_Phase_Inc(Vl_ch_num)(15 downto 0) <= data_bus;
-
- Other decoding logics-- 15 * 4 registers(4 Channel Parameters)
-
when others => null;
end case;
end if;
end process;
While reading the registers also , I used the same decoding logic to
read back the registers.
I dont know why? i got timing errors i.e when I simulated it using
ModelSim 5.3 ., and programmed setup(/CE low to AWE low) as 30ns ,
strobe time(/AWE low time) as 30 ns and hold time(/AWE high to /CE
high) as 30 ns. The registers were in unknown state.
How does the case logic works? does it do priority encoding or normal
encoding??
I changed my case logic to direct if-else structure which worked fine .
But I still dont understand why the same logic didnot work in Case.
Process(S_Write_Enable,Reset)
variable Vl_Offset := std_logic_vector(3 downto 0);
variable Vl_ch_num := std_logic_vector(1 downto 0);
begin
if(Reset = '1') then
-- initializatin
elsif(S_Write_Enable'event AND S_Write_Enable = '0') then
if(address_input = "0000001000") then
S_Code_Aid1(0) <= data_bus(C_LFSR_LENGTH-1 downto 0);
end if;
if(address_input = "0000001001") then
S_Code_Aid2(0) <= data_bus(C_LFSR_LENGTH-1 downto 0);
end if;
if(address_input = "0000011000") then
S_Code_Aid1(1) <= data_bus(C_LFSR_LENGTH-1 downto 0);
end if;
if(address_input = "0000011001") then
S_Code_Aid2(1) <= data_bus(C_LFSR_LENGTH-1 downto 0);
end if;
if(address_input = X"0028") then
S_Code_Aid1(2) <= data_bus(C_LFSR_LENGTH-1 downto 0);
end if
if(address_input = X"0029") then
S_Code_Aid2(2) <= data_bus(C_LFSR_LENGTH-1 downto 0);
end if;
end if;
Article: 103567Kolja Sulimma <news@sulimma.de> wrote: > Peter Alfke schrieb: > > rickman wrote: > >>with IT, the secretary being out of the office (no credit card > >>purchases) and the general BS of working in a defense company. > > I will poke around in Xilinx, if there is a meaningful way to overcome > > real and also bureaucratic/security obstacles. > While I am sure that a defense company can afford a DVD burner to obtain > software, as a CAD software developer I always wondered, why a single .. Also a big USB stick could carry the whole ISE installer. No hassle with burnibng and such... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 103568
"Andy" <jonesandy@comcast.net> writes: > Rather than creating a constant in a package from the source version > info, you might be able to use a top level generic, and pass the value > for that generic in via the synthesis command line in your build > script? > We do this to store the time of compile (32 bit int) somewhere that the processor can then read back. Also, I put the compile time in human readable (YYMMDDhh) form into the USERID part of the bitstream so it is easily read back with Impact when people want a quick check. All done in the scripts, so no-one has to worry about getting it right. Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.trw.com/conektArticle: 103569
"Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1149563213.194602.82140@u72g2000cwu.googlegroups.com... > > when I started here). If somethings needed to be done, you just did it, > and asked for permission afterwards. I loved it. > I do my best to keep that attitude, with some success... > Peter Alfke, Xilinx (from home) > Hi Peter, Apparently, it was Grace Hopper (appropriately enough for this thread a Rear Admiral in the U.S. Navy, and developer of the first compiler) who said "It's easier to ask forgiveness than it is to get permission.". Wise words indeed! Cheers, Syms. http://en.wikiquote.org/wiki/Grace_Hopper Inviato da X-Privat.Org - Registrazione gratuita http://www.x-privat.org/join.phpArticle: 103570
Hi Subin, It is possible to remove the test bench. If you decide to do so, you may have to bring out the interface signals and tie them up to your application. also, did you check the user guide? We do have the structure documented in the user guide. You can also use the Xilinx Help desk to get answers to these questions. (support@xilinx.com is their email address). thanks, Nagesh subint wrote: > Hello guys, > Is anyone used the Mig tool to generate a DDR SDRAM > controller here.i have some doubts on the code generated by mig.It > include a testbench inside it.I dont need such a interface and also i > want to use this as a sub block of the Full system fpga of the v4lx60 > board. > i am confused with structure of the code.Is it possible to use this > code with out much modification such as not removing the testbench. > regards > subinArticle: 103571
Hi guys,
Thanks for the reply.
I am still confused.
Is it possible to use the code without removing the
testbench?. Where is the actual interface for the data and address bus.
is it in the topmodule or it is the one driven by the testbench.
Actually i didnt understand the difference and working of
these two interfaces. It will be very helpful is anyone help me to
understand the interfacing of this controller.
Regards
Subin.
Nagesh wrote:
> Hi Subin,
>
> It is possible to remove the test bench. If you decide to do so, you
> may have to bring out the interface signals and tie them up to your
> application.
>
> also, did you check the user guide? We do have the structure documented
> in the user guide.
>
> You can also use the Xilinx Help desk to get answers to these
> questions. (support@xilinx.com is their email address).
>
> thanks,
> Nagesh
>
> subint wrote:
> > Hello guys,
> > Is anyone used the Mig tool to generate a DDR SDRAM
> > controller here.i have some doubts on the code generated by mig.It
> > include a testbench inside it.I dont need such a interface and also i
> > want to use this as a sub block of the Full system fpga of the v4lx60
> > board.
> > i am confused with structure of the code.Is it possible to use this
> > code with out much modification such as not removing the testbench.
> > regards
> > subin
Article: 103572
Hi guys,
Thanks for the reply.
I am still confused.
Is it possible to use the code without removing the
testbench?. Where is the actual interface for the data and address bus.
is it in the topmodule or it is the one driven by the testbench.
Actually i didnt understand the difference and working of
these two interfaces. It will be very helpful is anyone help me to
understand the interfacing of this controller.
Regards
Subin.
Nagesh wrote:
> Hi Subin,
>
> It is possible to remove the test bench. If you decide to do so, you
> may have to bring out the interface signals and tie them up to your
> application.
>
> also, did you check the user guide? We do have the structure documented
> in the user guide.
>
> You can also use the Xilinx Help desk to get answers to these
> questions. (support@xilinx.com is their email address).
>
> thanks,
> Nagesh
>
> subint wrote:
> > Hello guys,
> > Is anyone used the Mig tool to generate a DDR SDRAM
> > controller here.i have some doubts on the code generated by mig.It
> > include a testbench inside it.I dont need such a interface and also i
> > want to use this as a sub block of the Full system fpga of the v4lx60
> > board.
> > i am confused with structure of the code.Is it possible to use this
> > code with out much modification such as not removing the testbench.
> > regards
> > subin
Article: 103573"John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> wrote: >Have a look at this module >http://www.enterpoint.co.uk/moelbryn/modules/usb_ps2.html in conjunction >with our Raggedstone1 product. Basically the module is a voltage limiter(bus >switch) on the USB lines leaving the logic to be implemented in the FPGA. Thanks. I'm a bit confused by the "shop" section. The RS1-400 and the RS1-1500 both have the same description including: "FPGA: XilinxTM SpartanTM-3 FPGA, in FG456 package, fitted to the board. Available with XC3S400 fitted." I presume that it should be the XC3S1500 in the latter case. Also the wording is ambiguous. I presume that "Available with XC3S400 fitted" does mean that the FPGA *is* fitted for the that price, rather than being an option? -- Dave FarranceArticle: 103574
Hi *, just installed ISE8.1 with SP3 on a 64bit Linux-machine running OpenSUSE 10. Just thought I'd give it a try, even if it's not officially supported by Xilinx and I haven't read any reports here on people getting it to run successfully (BTW, ISE8.1 works fine on other machines running OpenSUSE, but this is the first 64bit-machine I've tried). Anyhow, most of it seems to work fine. The system is detected correctly as lin64, the GUI works, and the utilities for flow work all right (meaning XST, ngdbuild, map and so on don't crash and seem to do what they should). The only thing that does not work is par. Starts up all right, it reads in the constraints and displays device utilization, but then exits with a fatal error before it starts placing: "Starting Placer FATAL_ERROR:PersonalityModule:baspmdlm.c:164:1.25 - dll library <PlXil_Legal> does not exist. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com" There's nothing on this on the support website. I've opened a web case, but since OpenSUSE is not a supported platform, they probably won't be able to help there. Has anyone else seen this? "Xil_Legal" strikes me as kind of an odd name for a library. It doesn't exist anywhere in the installation directories, but it's not there on other machines running OpenSUSE either, and on those machines the tools work fine. Has anyone gotten this to work? cu, Sean
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