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Take a look at opalkelly.com. They have very elegant boards and excelent abstraction of the USB link (Verilog and VHDL on the board side and C++,Java and Python on Windows and Linux). Check the FrontPanel user's manual. Jim. Dave Farrance wrote: > Hi. I want to get my brain around USB interfaces, how to design the > hardware and the software, and eventually to find what economic > hardware solutions are available, and how USB hardware interfaces can > be arranged to make the best use of generic USB drivers to minimise > problems associated with driver installation. > > It's not something that I've been able to investigate in the > time-limited projects that I've done as an electronic designer, and so > I've tended to use RS485 interfaces or other alternatives. I've decided > that It's high time that I understood USB, so I'll pick up the > knowledge by occasionally dabbling with it at home over a period of a > few months which is something that works OK for me. > > I'm not very good at reading screeds of technical description and > retaining it in my memory, so I need to get my hands dirty with some > experimental design and coding that I can interact with to get the > concepts anchored in my mind. I'm reasonably competent in C, C++, VHDL > and Verilog, and can code quite swiftly. > > To kick off, I'd like to get an FPGA board with a RAM-based FPGA that > can be configured via a serial or USB cable to a laptop. For my > experiments, the board also needs a USB interface that passes the raw > USB data stream directly to the FPGA, or it should be easily > convertible to do so. The FPGA needs to be big enough to hold > open-source HDL USB interfaces and to hold models that mimic the > interfaces to common USB equipment like flash keys, printers and > modems. Any suggestions? I'm aiming to keep the cost reasonable - $100 > to $150 say - and I'm prepared to put up with the limitations of free > software such as the speed-crippled Modelsim HDL simulator. > > -- > Dave FarranceArticle: 103476
bjzhangwn schrieb: > I want to to get the hardware(pcb or shematic) or some other files,and > also I want to know if I want to do this what should i prepare! http://hydraxc.xilant.com/CMS/index.php?option=com_remository&Itemid=41&func=fileinfo&id=10 XCAPP009 in download area ready to run .BIT files and make environment for CPU86 in Virtex-4 AnttiArticle: 103477
A Slice consists of two Look-Up Tables (LUTs) and flip-flops plus some multiplexers. Logic Cell is a measure of logic capacity. Originally, one LC = 1 LUT, but to give credit for the extra logic, a LUTwas then defined as 1.125 LCs. My advice: Forget the marketing numbers, forget LC, and go with: One Slice = exactly 2 LUTs with their flip-flops and multiplexers and carry logic. Peter Alfke, from home ================================= Mich wrote: > Hi > > I have a question. > What is the difference between Logic Cells and Slices on an FPGA? > I have noticed that on the Virtex-II Pro that the amount of Slices = > amount of Logic Cells * 4/9 > > Thanks > MichielArticle: 103478
Michiel, The issue here is what marketing does after we IC designers are done. With good intentions, they want to promote the product, and have it appear competitive in every sense. They also want to be honest, and every claim is backed up by real data. So, if there is one more mux, one more carry input, anything at all that gets added to a LUT+stuff+DFF, they "scale" the "effectiveness" of the "logic cell." To me, I count LUTs and DFFs. With the introduction of V5, I do not count a 6-LUT as some number of 4-LUTs, it is still a 6-LUT. Unfortunately, 6-LUTs are used from hardly at all to as much as 58% of a design, meaning the 6-LUT on average is quite an improvement (more logic done in fewer stages, leading to faster, and lower power). This makes it hard to compare a part with 4-LUTs to a part with 6-LUTs. So, getting back to your question: are you just trying to untangle the data sheet to see the underlying hardware features? Looking at Table 1 from http://direct.xilinx.com/bvdocs/publications/ds083.pdf we see in note 2: "Logic Cell = 1 4-LUT + 1 DFF + Carry Logic Page 6, defines a "CLB" as 4 slices. A Slice is defined as two 4-LUTs (function generators), to FFs, all the arithmetic stuff, large muxes (F5,F6,F7), carry lookahead, horizontal cascade. Back to table 1, a 2VP2 has 1408 slices, so that makes: 1408 X 2 = 2816 4-LUTs 1408 X 2 = 2816 DFFs etc. I like to remember that a 'CLB' has 8 LUTs, 8 DFFs (an octet of useful stuff...) in VII and VII Pro. And a CLB is 4 slices, and each slice is 2 4-LUTs and 2 DFFs. So back to logic cells, the 2VP2 has 3168 logic cells. It has 2816 identifiable LUT+DFF pairs, so where does that factor of 1.125 come from? That is the extra stuff: arithmetic, large muxes (F5,F6,F7), carry lookahead, horizontal cascade. For me, I would not bother to dress up the number, but if you synthesize a few thousand designs, the number holds up (can be justified) as an average improvement compared to synthesizing the design with those resources locked out. Bottom line: this 'inflation factor' is justified by actual data, but it is very confusing (if all you really wanted to know was how many LUTs and flops there are). Austin Mich wrote: > Hi > > I have a question. > What is the difference between Logic Cells and Slices on an FPGA? > I have noticed that on the Virtex-II Pro that the amount of Slices = > amount of Logic Cells * 4/9 > > Thanks > Michiel >Article: 103479
Hello folk, I've been supervising a project on reconfigurable computing at my University whose objective is to create a prototype of a self-reconfigurable FPGA. The board is a small Xess XSA-100 mounting a Spartan-II 100 FPGA. The steps of the project should have been the following: 1) Use two distinct boards, with a "master" board dowloading a bitstream to a "slave" board. 2) Create a partial reconfiguration project (the "classical" Xilinx xapp290) on a single board. 3) Create a partial reconfiguration project, with the fixed portion of the design reconfiguring the FPGA itself, the same way as step 1) but using a single FPGA as both the master and the slave. Well, the first two steps succeeded. The third, unfortunately, didn't. The guy who was working on the project stopped the work as his internship period expired. Anyway, he gave me an almost-finished project which -he says- only need some debugging. He used a SelectMap parallel configuration mode for all the above experiments. Of course, step 1) required a full reconfiguration, while step 3) required partial reconfiguration. He said that, probably, the electrical protocol for partial reconfiguration is different from that for full reconfiguration. In fact, he said that for partial reconfiguration one shouldn't assert the "/PROGRAM" signal, nor wait for a "/INIT" signal from the FPGA. It should be sufficient to assert the "/CS" and "/RDWR" signals to initiate a partial bitstream download to the FPGA, while asserting the "/PROGRAM" signal would erase the full FPGA configuration (and thus the block that manages the reconfiguration from the FPGA itself). I'm not sure about that. Are you aware of a different protocol that is required when using SelectMap mode for partial reconfiguration instead of full reconfiguration? In particular, do you think that asserting the "/PROGRAM" signal really erases the full FPGA configuration being thus incompatible with partial reconfiguration?? Currently, we only assert the signals "/CS" and "/RDWR", and then, after a couple of garbage bytes, we put "FFFFFFFFAA995566" followed by the rest of the partial bitstream on the FPGA data port. After downloading the bitstream and deasserting "/CS" and "/RDWR" nothing changes, the initial bitstream is still there and -strangely enough- it is (almost always) reset and restarted. Do you have any suggestions (including any hints on bitgen flags) ??? Many, many thanks !! ale PS. When the project will work, all material will be made publicly available.Article: 103480
Felix Bertram wrote:
> I have a problem installing WebPack on Linux. While Xilinx recommends
> RedHat, I would like to use one of the free distributions. I tried
> Fedora Core 5, which I believed is the closest to RedHat I could get.
>
> Unfortunately, install fails, while searching for libstd++.so.5
> Fedora comes with version 6.0.8.
>
> So here are my questions:
> - did you have any success using a free Linux distribution?
> - which distribution did you use?
> - any other hints?
I had a similar problem getting WebPack to run on Linux. Here
is my report to the Home Brew Robotics Club on the problem.
You may want to get the libstd++.so.5 file from a Fedora Core
3 distribution. Hope this helps .....
===============================================================
TO: Home Brew Robotics Club
Silicon Valley Linux Users Group
WHAT: This note briefly describes how to get the Xilinx FPGA
development tools to work on Linux
To learn FPGA design I followed in the steps of Chris Palmer
of the HBRobotics Club and ordered a Digilent "Spartan-3 Board"
for $99. You can order one at http://www.digilentinc.com/
Download the Xilinx free WebPACK 8.1i development software
from the Xilinx web site. You have to register, but it is not
too intrusive. The download is almost 900MB. Xilinx provides
an IDE that looks like a C and Tcl/Tk wrapper around a bunch
of command line tools. Instead of trying to keep up with the
latest kernels and libraries, Xilinx just puts every library
and executable it needs into the download and makes the tool
completely self-contained. They missed libXm.so.3 and I had
to copy it from a Fedora Core 3 system. (They built the IDE
on Red Hat Enterprise Edition 3). For the record, I use
Mandriva 2006 but it does not seem to matter too much which
distribution you use.
The key to getting the Xilinx tools to work on Linux is to
follow the directions at http://gentoo-wiki.com/HOWTO_Xilinx
This page tells where to download, and how to install the
parallel port drivers for the JTAG programming cable that
comes with the kit.
As root, install the software with "sh WebPACK_81i_SFD.sh".
Run the software as root and select HELP->Software_Updates
to get the latest updates from the Xilinx web site.
The quick start is in Xilinx/doc/usenglish/books/docs/qst.pdf.
Open this with xpdf or evince and follow the directions to
create, build, and download a four bit counter. I made a
typo error when editing the design and the tools wouldn't
let me proceed until I fixed the error.
I am just learning Verilog / VHDL but I'd be happy to help
if you want help getting to your first download of an FPGA
circuit.
Article: 103481mailmekaran wrote: > Dear all, I am implementing FLOATING point FIR filter with LATTICE > structure. > For this project i want 32bit Floating Point ADDER and > MULTIPLIER in VHDL. > Please tell me how and from where i can get the VHDL code for the > same. What is the gain in floating point in a FIR ? Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 103482
There is a (in the spec for cardbus) well documented method for extending the res delay, to get enough time for fpga initialisation. Read more detailled. One pin should be tied low, and one can hold recognition proces long enough.Article: 103483
Rich Grise wrote: <snip> > What should I do? I've looked on the Xilinx site, in their "answers database", > and I've searched both groups by google, and haven't seen anything addressing > this particular situation. Are you by any chance missing a ModelSim installation? If you want to simulate your design, you must install the appropriate version of ModelSim because (AFAIK) Xilinx ISE relies on the ModelSim for all simulations, including the "Generate Expected Simulation Results". Hope this helps, ignore if the problem is more complex. ;) - R.Article: 103484
In the Sp3 full datasheet p56/206 there's some notes numbered (3) and (4). They are not to be found below table 31. Is this supposed to be that way? http://direct.xilinx.com/bvdocs/publications/ds099.pdfArticle: 103485
mailmekaran wrote: > Dear all, I am implementing FLOATING point FIR filter with LATTICE > structure. > For this project i want 32bit Floating Point ADDER and > MULTIPLIER in VHDL. > Please tell me how and from where i can get the VHDL code for the > same. > THAKING YOU ALL. > > Shivkaran Ravidas Not to sound rude or anything, but you have a gmail address; try a google search. I found two synthesizable packages on the 1st page of hits.Article: 103486
Ayon kay Nial Stewart: > "water7" <krbyxtrm@gmail.com> wrote in message > news:1149029612.426459.236830@g10g2000cwb.googlegroups.com... > > hi, what is the difference for designing a PCI card for a desktop > > motherboard and with a Single Board Computer(SBC)? should a PCI card > > designed for Desktop PC work on SBC's? > > -k- > > > Yes, as long as you can physically plug it in and it matches the > interface voltage. > > Most SBCs I've seen come in PC104+ format. I've used an adaptor > in one project that allows a standard form PCI card to be > plugged in, I've also developed a PC104+ board that an SBC > plugged on to. > > > > Nial. hi, is the SBC's edge connector(male) works the same as Desktop PC PCI Slots, i mean if i make a male-to-male pci adaptor to plug a generic pci device(male) to SBC? -k-Article: 103487
"radarman" <jshamlet@gmail.com> wrote in message news:1148596758.728200.68060@y43g2000cwc.googlegroups.com... > I've been eyeing the Altium Livedesigner evaluation boards as a > potentially cheap way to get a reasonably powerful FPGA board to play > with. Either the Altera or Xilinx board seem to have decent size parts, > and plenty of accessories - especially for $99 > > http://www.altium.com/Community/LiveDesignEvaluationBoards/ > > The problem is that neither have a configuration memory - which is > understandable given the target audience. > > I'm curious if anyone owns one, and has looked to see if the necessary > configuration pins are brought out anywhere. The schematic for the > Xilinx version shows that all but the din and init_b signals should be > available at either resistors or LED's. Not sure what the red lines > mean in the schematic. They could be direct vias to either ground or > VCC, or test points. > > Has anyone attempted to add a configuration PROM to either of these > boards? > > Thanks! You can use the Tony Burch expansion modules - config prom etc via the user headers I haven't tried this myself. Altium gives a link to Tony's products via third party plugin io modules http://www.altium.com/Community/LiveDesignEvaluationBoards/ Interesting to see that the next version of altium designer is going to need a 3d graphics card http://www.altium.com/Evaluate/DEMOcenter/AltiumDesignerNewFeatures/HardwareAcceleratedGraphicsEngine/ Note that the graphics engine requires a graphics card that supports DirectX® 9.0c and Shader Model 3.0. Work isn't renewing our altium licenses , switching to Eagle instead for pcbs. Does anyone have or know of pin constraints / ucf files for both xilinx and altera live design boards ?Article: 103488
hi all, few days a go I updated my ISE8, now I have ISE Foundation 8.03i and the problem is when I want to perform a multi place an route, it falls and I get an error : "Process "Place & Route" failed" as a simple solution, I performed a simple place and route, after if my constraints are not met, I change the cost table manually. my question is : is it a bug in the service pack 3? also, Is there another way to this automaically ? thanks in advance. NezhateArticle: 103489
sorry I want to say : Multi Pass Place and Route. sorry again!Article: 103490
water7 wrote: > i mean if i make a male-to-male pci adaptor to plug a generic pci > device(male) to SBC? Mostly. Will probably work if a one/two PCI devices are present with a little care. Consider that you may violate several of the design considerations regarding termination and timing right off the bat with the additional trace lengths and addtitional reflections for the adapter connectors. Thankfully there is some margin in most PCI designs at 25/33mhz. Some don't ... IE devices on extender cards makes the system unstable for certain motherboards and configurations.Article: 103491
"Jim" <cairosearch@gmail.com> wrote: >Take a look at opalkelly.com. They have very elegant boards and >excelent abstraction of the USB link (Verilog and VHDL on the board >side and C++,Java and Python on Windows and Linux). Check the >FrontPanel user's manual. Thanks. That's the sort of thing that I'd probably use once I'd understood USB, and needed to design a USB interface plus programmable logic into (say) in-house test equipment. It's a bit expensive for self-teaching, though. I note that Xilinx can sell a board with a 500K-gate FPGA and a huge bunch of peripherals (and configuration via USB) for just $149: http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-SK-US So I'd hoped that an FPGA starter-kit type of board that was pared down to USB could be obtained from somebody for under $150. I guess I'll look at the schematics of the Xilinx starter kit, and see if it can be rewired to also pass the USB data stream directly to generic-I/O on the FPGA. -- Dave FarranceArticle: 103492
Hi
I have a problem when synthesizing my implementation.
I am implementing simple controller for sorting two arrays
X={1,3,5,7,9}, Y={2,4,6,8,10}.Two arrays are initially stored in dual
port BRAM, RAMB16_S9_S9.
My goal is to perform this in less than 15 cycles.
To do this, "load-compare-store" for one element need to be done in one
cycle.
My intention was "read port from A" and "write to port B" in a parallel
and pipelined way.
What I did was, as shown below
Everything is synchronous, except the "address" setting.
Behavioral simulation is okay, but mapper (ISE) complains (also shown
below) that every logic is trimmed.
Does anyone design this way ?
or anyone has this experience?
or maybe problem is somewhere else.
thankyou in advance for comment and suggestion.
------------------------------------------------------------------------------------
--------------------------------
-- Asynchronous address setting
Address_port_A <= AddressX when State = State_LoadX else
AddressX+'1' when State =
State_Compare_StoreX and x<=y else
...
Address_port_A <= AddressY when State = State_LoadY else
AddressY+'1' when State =
State_Compare_StoreY and x > y else
...
-- Synchronous implementation
process(reset, clock)
begin
if (reset='1') then
Current_State <= Initial_State; -- Current State
AdressX <= (othesrs => '0');
AdressY <= (othesrs => '0');
elsif clock'event and clock='1' then
case Current_State is
......
when State_LoadX =>
read_X <= '1'; -- we_portA=0 -- read
....
when State_LoadY =>
read_Y <= '1'; -- we_portB=0 -- read
....
when State_Compare_StoreX
if x <= y then
Data_to_portB <= Smaller_value; -- write "Smaller_value" to
port B
read_X <= '1'; -- read from port
A
AdressX <= AddressX+'1';
else
Data_to_portB <= Smaller_value; -- write "Smaller_value" to
port B
read_Y <= '1'; -- read from port
A
AdressY <= AddressY+'1';
....
------------------------------------------------------------------------------------
--------------------------------
------------------------------------------------------------------------------------
-- Mapping Report
------------------------------------------------------------------------------------
Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network U1/ROC has no load.
WARNING:MapLib:701 - Signal clk connected to top level port clk has
been
removed.
WARNING:MapLib:41 - All members of TNM group "clk" have been optimized
out of
the design.
WARNING:MapLib:50 - The period specification "TS_clk" has been
discarded because
the group "clk" has been optimized away.
Section 4 - Removed Logic Summary
---------------------------------
oadless block "R1/LocalMem" () removed.
The signal "R1/addrMemA<9>" is loadless and has been removed.
Loadless block "R1/addrMemA_9" (FF) removed.
The signal "R1/Result<9>" is loadless and has been removed.
Loadless block "R1/Node_Top_Result<9>_xor11" (ROM) removed.
The signal "R1/Node_Top_Result<7>_cyo" is loadless and has been
removed.
Loadless block "R1/Node_Top_Result<7>cy11" (ROM) removed.
The signal "R1/addrMemA<6>" is loadless and has been removed.
Loadless block "R1/addrMemA_6" (FF) removed.
The signal "R1/Result<6>" is loadless and has been removed.
Loadless block "R1/Node_Top_Result<6>_xor11" (ROM) removed.
The signal "R1/Node_Top_Result<4>_cyo" is loadless and has
been removed.
Loadless block "R1/Node_Top_Result<4>cy1" (ROM) removed.
The signal "R1/addrMemA<4>" is loadless and has been
removed.
.......................
.......................
Article: 103493The ?Vccaux and Vin numbers were added to that table in revision 1.6 of the DC and Switching Characteristics datasheet (1.5 didn't have those entries) but the notes didn't make it into the table and the Revision History didn't mention the changes to that table. It sounds like a simple goof-up by the maintainers of the document as if something got only partly done on that section of the datasheet. I'd suggest you get clarification from Xilinx directly. <pbdelete@spamnuke.ludd.luthdelete.se.invalid> wrote in message news:44821e09$0$490$cc7c7865@news.luth.se... > In the Sp3 full datasheet p56/206 there's some notes numbered (3) and (4). > They are not to be found below table 31. Is this supposed to be that way? > > http://direct.xilinx.com/bvdocs/publications/ds099.pdf >Article: 103494
On Sat, 03 Jun 2006 18:32:21 +0000, Bob Smith wrote: > Felix Bertram wrote: >> I have a problem installing WebPack on Linux. While Xilinx recommends >> RedHat, I would like to use one of the free distributions. I tried >> Fedora Core 5, which I believed is the closest to RedHat I could get. >> >> Unfortunately, install fails, while searching for libstd++.so.5 >> Fedora comes with version 6.0.8. >> >> So here are my questions: >> - did you have any success using a free Linux distribution? >> - which distribution did you use? >> - any other hints? > > I had a similar problem getting WebPack to run on Linux. Here > is my report to the Home Brew Robotics Club on the problem. > You may want to get the libstd++.so.5 file from a Fedora Core > 3 distribution. Hope this helps ..... There is no reason to get libstd++.so.5 from FC3, it's in the FC5 compatibility libraries.Article: 103495
"John_H" <johnhandwork@mail.com> wrote in message news:dmBgg.2794$oa1.2742@news02.roc.ny... > The ?Vccaux and Vin numbers were added to that table in revision 1.6 of > the The ? above was the delta symbol. oops.Article: 103496
Dave Farrance schrieb: > "Jim" <cairosearch@gmail.com> wrote: > > >Take a look at opalkelly.com. They have very elegant boards and > >excelent abstraction of the USB link (Verilog and VHDL on the board > >side and C++,Java and Python on Windows and Linux). Check the > >FrontPanel user's manual. > > Thanks. That's the sort of thing that I'd probably use once I'd > understood USB, and needed to design a USB interface plus programmable > logic into (say) in-house test equipment. It's a bit expensive for > self-teaching, though. > > I note that Xilinx can sell a board with a 500K-gate FPGA and a huge > bunch of peripherals (and configuration via USB) for just $149: > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-SK-US > > So I'd hoped that an FPGA starter-kit type of board that was pared down > to USB could be obtained from somebody for under $150. > > I guess I'll look at the schematics of the Xilinx starter kit, and see > if it can be rewired to also pass the USB data stream directly to > generic-I/O on the FPGA. > > -- > Dave Farrance the USB chip on the Xilinx s3e starterboard is the same as on the opalkelly board I think, so just rewrite the usb eeprom and use the xilinx s3e board as usb devel board - only drawback you need to re-create that parts of the schematic that xilinx censored out from the digilent design eg the wiring of the usb controller - but with an beep-tester it should not take longer than a few hours AnttiArticle: 103497
Nevermind - I discovered the ISE 7.1i webpack doesn't support coregen (even though the program gets installed). I have since downloaded the 8.1i webpack, which does allow coregen. -Seth radarman wrote: > Looks like I have a few more hurdles before getting started with my > Spartan 3e board. This time, I seem to be having trouble generating > models with Core Generator. > > I am using the Xilinx ISE 7.1i webpack - not sure if that makes a > difference of not. > > Although I'm not sure if it applies to 7.1i, I read that 8.1i has > problems with spaces in the path names, so I made sure to install ISE > to a path with no spaces. (C:\MyData\Xilinx\ISE_71i). The Core > Generator project is likewise stored in C:\MyData\Xilinx\Coregen. So > far, I can do simple builds in pure VHDL with good results (I can even > program the bitstream into the target board with impact) > > However, trying to create models in coregen results in an exception > error for some (I don't ever see the customization screen) and for > others, like the FIFO model I need, I get all the way through the > process, only to see this: > > Customizing IP... > Finished Customizing. > Generating IP... > ERROR:coreutil - IO error when creating files for XST synthesis! > ERROR:coreutil - Failure to generate output products > Finished Generating. > > And some actually seem to work. I can create a distributed memory model > perfectly fine: > Generating IP... > Generating Implementation files. > Generating the VHDL wrapper. > Generating the VHDL instantiation template. > Generating the SYM file. > Generating ISE symbol file... > Generating NGC file. > Finished Generating. > Successfully generated dist_mem. > Customizing IP... > Finished Customizing. > > I can also create DCM models as well. I haven't tried everything, but > it seems kind of hit&miss. > > Any clues? I need a FIFO model for a serial transciever I am porting > over from an Altera design. The FIFO is a single clock, 8-bit wide, 512 > locations deep, model with almost full & almost empty. > > For reference, I have ISE 7.1i (webpack) with SP4 installed, and IP > update 3. I have tried both versions of Fifo Generator installed (2.1 > and 2.2) and both produce the same errors. > > Thanks (again) > -SethArticle: 103498
Let me just explain what you functionally can do in a BRAM: Read synchronously: all inputs (address and control) must be stable before the clock edge, data output appears after the clock edge. Write synchronously: all inputs (address, data, and control) must be stable before the clock edge. Even though you are writing, you are also reading. The data output appears after the clock edge: As a config. option that data output is either the "old" data at the addressed location, or it is the "new" data that you are just writing. (Read-before-write or write-before-read). You can also leave the outputs unaffected by the write operation. I think the first option, read-before write, is the most interesting one. It lets you build shift registers in BRAMs, something that Altera touts as an important feature. Xilinx has had it for many years... Obviously, you cannot do a read-modify-write on the same clock edge. Every operation is synchronous. The two ports have independent clocks, addresses, data and controls, they only share the common data storage array. Now you can figure out whether your design is inherently possible. Peter Alfke, Xilinx Applications ===================Article: 103499
"Antti" <Antti.Lukats@xilant.com> wrote: >the USB chip on the Xilinx s3e starterboard is the same as on the >opalkelly board I think, >so just rewrite the usb eeprom and use the xilinx s3e board as usb >devel board - only drawback >you need to re-create that parts of the schematic that xilinx censored >out from the digilent design >eg the wiring of the usb controller - but with an beep-tester it should >not take longer than a few hours Thanks for that. It would have to be the USB interface on the censored page. Is the usb eeprom reprogrammable on-board? -- Dave Farrance
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