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"rnbrady" <rnbrady@gmail.com> wrote in message
news:1151584650.998970.110720@j72g2000cwa.googlegroups.com...
> Hi folks
>
> So, to tell whether my code is synthesizable, I have to do the
> following:
>
> 1. Select a specific chip
> 2. Run the synthesis
> 3. Bring the mapped VHDL netlist file into ModelSim
> 4. Bring vendor specific files into ModelSim because they are required
> by mapped file.
> 5. simulate for that chip.
> Is there another way?
If your code is not synthesizable, you'll get stuck in the middle of stage
2. So steps 3-5 are not necessary to tell whether your code is
synthesizable. Did I miss something?
Generally, if code is synthesizable for one chip it is synthesizable for
any. Of course there will be exceptions to this, and the quality of the
synthesis results will vary from device to device, but generally it's good
or it's not.
Cheers,
-Ben-
Article: 104526
Hi,
For functional verification u don't need to generate the
mapped VHDL code.You can do it with your HDL code.If you would like to
verify the timing you can do the steps you suggested.
subin
rnbrady wrote:
> Hi folks
>
> I'm working with Synplify Pro (8.5.1) and I'm trying to test whether
> VHDL code is synthesizable. How can I do this without selecting a
> specific vendor or chip? Is it possible? I thought there might be some
> concept of a generic target, but can't find anything of the sort.
>
> In particular, I want to get the mapped VHDL file from Synplify and
> bring it back into ModelSim for simulation and functional verification.
> So, to tell whether my code is synthesizable, I have to do the
> following:
>
> 1. Select a specific chip
> 2. Run the synthesis
> 3. Bring the mapped VHDL netlist file into ModelSim
> 4. Bring vendor specific files into ModelSim because they are required
> by mapped file.
> 5. simulate for that chip.
>
> Is there another way?
>
> Thanks in advance,
> Richard
Article: 104527Hi I am using Ken Chapman's UART cores described in xapp223.pdf from Xilinx. I am having mapping errors. Has anyone worked on this?? Thanks, VivekArticle: 104528
I came across the Xilinx application xapp223 for the implementation of
the UART cores. I have been trying various implementations of UART
transmitter cores and I am trying to implement this macro on a Xilinx
Virtex-II Pro 7 FPGA FF672 board. Now, I am using a 100 MHz clock,
which gets divided by 162 to provide the exact clock for a baud rate of
38,400. I have also declared the uart_tx as a black box as per the
README file. However, the design has a lot of errors during the mapping
stage and I am not able to figure out the errors as I am not able to
open the .EDN file. The sample errors I faced are:
ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on FDRE symbol
"U1/$I1"
(output signal=U1/A<3>).
ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on XORCY symbol
"U1/$I10"
(output signal=U1/SUM_A2).
ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on LUT4 symbol
"U1/$I105"
(output signal=U1/$Net00113_).
ERROR:Map:6 - Bad format for RLOC constraint " R6C0.S0" on FD symbol
"U1/$I106"
(output signal=U1/TX_RUN).
ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on FD symbol
"U1/$I107"
(output signal=U1/TX_START).
ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on LUT4 symbol
"U1/$I108"
(output signal=U1/$Net00151_).
ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on MUXCY symbol
"U1/$I11"
(output signal=U1/CY_A2).
My ucf file for the top module is very simple:
NET clk LOC= D13;
NET tx_rs232 LOC=AC6;
NET wrn LOC=E7;
NET bfull LOC=D6;
My top file declaration:
entity rs232_test_top is
port(
clk : in std_logic;
wrn : in std_logic;
bfull : out std_logic;
tx_rs232 : out std_logic);
end rs232_test_top;
I am guessing that the component uart_tx is not being
compiled/synthesized by Xilinx ISE. Please let me know if there are any
solutions.
Thank you,
Vivek
Article: 104529Thanks guys.Article: 104530
Weng Tianxiang wrote: > Hi, > I read some books describing that preservation of patent ideas through > a notary is valid in the law. > > Yesterday we put all patent materials into a large envelop and went to > a notary to seal it. A lawyer in the notary put notary stamps on all > papers and sealed the envelop properly with stamps too. What surprised > us is there is no date!!! There are no date stamps like a register > letter that must have a date stamp on the envelop. There is no receipt > neither. > > What does It prove? What I need is a date a patent law court admits. > But here there is no date. What is wrong? What should I do next? And you're sure they don't dispose it in the bin as soon as you leave ? A patent has to be processed, definitely not deposited. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 104531
Only one restriction comes to mind: DDR logic (two clocks or both edges of one clock) will only synthesize to targets that have DDR resources (usually IO registers). Arrays will (with the appropriate restrictions) synthesize to ram on devices that support it, or to registers on targets that don't, but they will always synthesize, regardless of the target. Andy Ben Jones wrote: > > Generally, if code is synthesizable for one chip it is synthesizable for > any. Of course there will be exceptions to this, and the quality of the > synthesis results will vary from device to device, but generally it's good > or it's not.Article: 104532
run map with -ir (ignore RLOCs)
or if you use ISE, change map propreties by unchecking "use RLOC...."
Aurash
Vivek Menon wrote:
>I came across the Xilinx application xapp223 for the implementation of
>the UART cores. I have been trying various implementations of UART
>transmitter cores and I am trying to implement this macro on a Xilinx
>Virtex-II Pro 7 FPGA FF672 board. Now, I am using a 100 MHz clock,
>which gets divided by 162 to provide the exact clock for a baud rate of
>38,400. I have also declared the uart_tx as a black box as per the
>README file. However, the design has a lot of errors during the mapping
>stage and I am not able to figure out the errors as I am not able to
>open the .EDN file. The sample errors I faced are:
>
>ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on FDRE symbol
>"U1/$I1"
> (output signal=U1/A<3>).
>ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on XORCY symbol
>"U1/$I10"
> (output signal=U1/SUM_A2).
>ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on LUT4 symbol
>"U1/$I105"
> (output signal=U1/$Net00113_).
>ERROR:Map:6 - Bad format for RLOC constraint " R6C0.S0" on FD symbol
>"U1/$I106"
> (output signal=U1/TX_RUN).
>ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on FD symbol
>"U1/$I107"
> (output signal=U1/TX_START).
>ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on LUT4 symbol
>"U1/$I108"
> (output signal=U1/$Net00151_).
>ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on MUXCY symbol
>"U1/$I11"
> (output signal=U1/CY_A2).
>
>My ucf file for the top module is very simple:
>NET clk LOC= D13;
>NET tx_rs232 LOC=AC6;
>NET wrn LOC=E7;
>NET bfull LOC=D6;
>
>My top file declaration:
>entity rs232_test_top is
>port(
> clk : in std_logic;
> wrn : in std_logic;
> bfull : out std_logic;
> tx_rs232 : out std_logic);
>end rs232_test_top;
>
>I am guessing that the component uart_tx is not being
>compiled/synthesized by Xilinx ISE. Please let me know if there are any
>solutions.
>Thank you,
>Vivek
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 104533tester wrote: > Hi i'm using the Xilinx GSRD design. > > Now i try to connect a simple IP core to the reference design. > The problem is that i can not connect my IP to the OPB or PLB bus. The 2 > PLB Bus controllers supports only 1 Master and 1 Slave and they are > alread connected. > > The connection over the OPB does not work because they use a DCR2OPB > bridge. May be the way over the DCR is a solution? How can i manage this > connection. Are there some examples? You should switch over to the new MPMC2 based design which supports what you are looking for http://www.xilinx.com/mpmc2 Ed McGettigan -- Xilinx Inc.Article: 104534
Hi Rene, No, we didn't dispose it in a bin. We will ask for invoice next week. Thank you. WengArticle: 104535
Hi, I am not able to download the Picoblaze bundle from Xilinx site. The ifulcrum questionnaire crashes on me. Any suggestions?? Thanks, VivekArticle: 104536
"rajeev" <shuklrajeev@gmail.com> wrote in message news:1151562326.692337.229940@p79g2000cwp.googlegroups.com... > Hi everyone, > I have a few doubts that are not being addressed in fpga groups(at > least i could not find the one ) though it is very common in DSP design > using FPGAs. > > 1. In many a communication receiver systems a resampler (NCO based) is > required. The output of the resampler is fed to other logics. Can NCO > output be used to drive the portion of the design ? as is sayed that in > FPGA clock derived from (combinational/sequential) logics should be > avoided and whenever a rate change is required use enable signal > instead. But this approach requires the whole design to be run at the > highest clock consuming much more power.What could be the power > efficent method of doing the same. > Most common example is a CIC filter used for large rate change (Not by > integer factor but rather rate change is driven by a NCO) where input > is at much higher rate while the output is at lower rate. > > 2. If at all NCO is used for clocking the design that is required to > run at much slower speed what care should be the taken for NCO master > clock driving NCO , to NCO output clock ? (I feel higher the ratio > lower the jitter will be). > > 3. Can NCO clock be further used to drive a DCM to produce a high freq > clock that can be used for serial MAC fir (for efficient fpga fabric > usage.) > > regards. > rajeev shukla. "DCM" suggests Xilinx, so... The NCO output can be fed to a BUFGMUX to drive other logic, no problem. The reason the clock enables are suggested in many designs is to keep the clock domains between the full speed and lower speed portions of the circuit in the same clock domain, eliminating problems with crossing imprecisely aligned clocks. If you need to communicate between the NCO (or other logic driven by the master clock) and logic driven by the NCO's clock, you need to worry about crossing time domains. Higher clocks for the NCO (or DDS) produce less jitter, certainly. Often jitter at this level doesn't matter in circuits; only when crossing to or from the analog realm (such as an ethernet PHY) is jitter critical. The DCM should have troubles if fed a clock with high jitter. There are specific jitter specs included for the DCM input in the DC & Switching Characteristics for your device. It's tough to establish a lock in a delay line based architecture when the clock is always way too early or way too late. If you need a "clean" clock, consider an A/D to generate a true DDS sinewave or, better yet, use a clock chip such as the IDT5V9885 to clean up the NCO-generated jitter. You can get a more expensive zero-delay buffer style of jitter cleanup with an ICS part.Article: 104537
Some times using a different web browser works. if you are using IE switch to mozilla or visa versa Vivek Menon wrote: > Hi, > I am not able to download the Picoblaze bundle from Xilinx site. The > ifulcrum questionnaire crashes on me. > Any suggestions?? > Thanks, > VivekArticle: 104538
Eric, I am in the same boat. The workaround I found was to replace one of the plb_m1s1 cores with the standard plb_v34. So far this seems to have worked but I haven't finished the testing yet... MPMC2 approach Ed mentioned would probably be a more natural approach but I didn't want to mess with replacing the memory controller as I wasn't sure it was fully compatible with the GSRD design... /Mikhail "tester" <test@test.de> wrote in message news:e808lk$dae$1@nntp.aioe.org... > Hi i'm using the Xilinx GSRD design. > > Now i try to connect a simple IP core to the reference design. > The problem is that i can not connect my IP to the OPB or PLB bus. The 2 > PLB Bus controllers supports only 1 Master and 1 Slave and they are > alread connected. > > The connection over the OPB does not work because they use a DCR2OPB > bridge. May be the way over the DCR is a solution? How can i manage this > connection. Are there some examples? > > EricArticle: 104539
The browser switch does not help... Thanks, Vivek dscolson@rcn.com wrote: > Some times using a different web browser works. > if you are using IE switch to mozilla or visa versa > > > Vivek Menon wrote: > > Hi, > > I am not able to download the Picoblaze bundle from Xilinx site. The > > ifulcrum questionnaire crashes on me. > > Any suggestions?? > > Thanks, > > VivekArticle: 104540
No that does not solve the problem. However, Ken asked me to use the macros provided with picoblaze and now the ifulcrum/xapps questionnaire which keeps crashing. Hence I am not able to download the UART core which comes with the Picoblaze bundle. Thanks, Vivek Aurelian Lazarut wrote: > run map with -ir (ignore RLOCs) > or if you use ISE, change map propreties by unchecking "use RLOC...." > Aurash > > Vivek Menon wrote: > > >I came across the Xilinx application xapp223 for the implementation of > >the UART cores. I have been trying various implementations of UART > >transmitter cores and I am trying to implement this macro on a Xilinx > >Virtex-II Pro 7 FPGA FF672 board. Now, I am using a 100 MHz clock, > >which gets divided by 162 to provide the exact clock for a baud rate of > >38,400. I have also declared the uart_tx as a black box as per the > >README file. However, the design has a lot of errors during the mapping > >stage and I am not able to figure out the errors as I am not able to > >open the .EDN file. The sample errors I faced are: > > > >ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on FDRE symbol > >"U1/$I1" > > (output signal=U1/A<3>). > >ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on XORCY symbol > >"U1/$I10" > > (output signal=U1/SUM_A2). > >ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on LUT4 symbol > >"U1/$I105" > > (output signal=U1/$Net00113_). > >ERROR:Map:6 - Bad format for RLOC constraint " R6C0.S0" on FD symbol > >"U1/$I106" > > (output signal=U1/TX_RUN). > >ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on FD symbol > >"U1/$I107" > > (output signal=U1/TX_START). > >ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on LUT4 symbol > >"U1/$I108" > > (output signal=U1/$Net00151_). > >ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on MUXCY symbol > >"U1/$I11" > > (output signal=U1/CY_A2). > > > >My ucf file for the top module is very simple: > >NET clk LOC= D13; > >NET tx_rs232 LOC=AC6; > >NET wrn LOC=E7; > >NET bfull LOC=D6; > > > >My top file declaration: > >entity rs232_test_top is > >port( > > clk : in std_logic; > > wrn : in std_logic; > > bfull : out std_logic; > > tx_rs232 : out std_logic); > >end rs232_test_top; > > > >I am guessing that the component uart_tx is not being > >compiled/synthesized by Xilinx ISE. Please let me know if there are any > >solutions. > >Thank you, > >Vivek > > > > > > > > > -- > __ > / /\/\ Aurelian Lazarut > \ \ / System Verification Engineer > / / \ Xilinx Ireland > \_\/\/ > > phone: 353 01 4032639 > fax: 353 01 4640324Article: 104541
I am not able to download xapp627.zip from the archives section of Xilinx. Suggestions??? Thanks, Vivek Vivek Menon wrote: > The browser switch does not help... > Thanks, > Vivek > > dscolson@rcn.com wrote: > > Some times using a different web browser works. > > if you are using IE switch to mozilla or visa versa > > > > > > Vivek Menon wrote: > > > Hi, > > > I am not able to download the Picoblaze bundle from Xilinx site. The > > > ifulcrum questionnaire crashes on me. > > > Any suggestions?? > > > Thanks, > > > VivekArticle: 104542
Vivek Menon wrote: > I am not able to download xapp627.zip from the archives section of > Xilinx. The Xilinx website is notorious for simply falling down at random times. Try again another day. -aArticle: 104543
Hi all, I know this has been discussed on the NG before, but it seems like every time it is discussed someone hijacks the post and we end up with no answers. But this will be the last one. I promise ;) I need two identical boards with Xilinx and Altera parts on them for some "fun" at home. I found this page on the net http://www.altium.com/forms/evaluation.aspx Which is this board, I assume: http://www.altium.com/files/livedesign/Live_design_features.pdf $250 for 2 boards plus the download cable sounds nice, but i wonder if there is a catch? * do the boards work with chip vendor software (ISE & Quartus) flows? what about NIOS II and EDK? * does the programming cable work with vendor supplied programmers? * what is that 30-day license thingy they mention on their site? is the board bricked after 30 days?? * someone mentioned these lack program flash, is that true? do i have to re-program boards every time i turn them on? * same cable for both boards? can i remove the cable while the board is on, so i can program the other board? * and so on... to summarize, can I buy these boards instead of ordering a "Starter kit" board from Xilinx and a "NIOS II" board from Altera? what would i be missing? regards, -BurnsArticle: 104544
burn.sir@gmail.com wrote: > $250 for 2 boards plus the download cable sounds nice, but i wonder if > there is a catch? I belive that the basic purpose of these boards is to offer a platform for Altium Designer (software) evaluation. So, if you are an interested company, you buy a couple of these cheapos and recive a 30-day Designer Licence for your engineers to play with it. Then they are supposed to be thrilled and then you buy them NanoBoards and pay for Designer licences (not cheapos). But on the other hand, the NanoBoard isn't that much better, so you should be able to similar designs with the eval board... > * do the boards work with chip vendor software (ISE & Quartus) flows? > what about NIOS II and EDK? > * does the programming cable work with vendor supplied programmers? Not sure 'bout that... I belive all the programming is done via JTAG, if that means anything to you... Maybe you could resolder the cable to work with different programmers if it doesn't by default? > * what is that 30-day license thingy they mention on their site? is the > board bricked after 30 days?? That would be the Altium Designer licence. > * someone mentioned these lack program flash, is that true? do i have > to re-program boards every time i turn them on? AFAIK, the supplied FPGA's are RAM-based, so you would have to "reburn" your whole design anyway... The purpose of these boards is to do live design, I belive. Not sure 'bout flash, though. This is all I know, hope this helps a bit. Regards, - R.Article: 104545
Aurelian Lazarut wrote:
> anyway I synthesized your original code with ISE8.2 and works fine for me.
Aurelian,
Thanks for trying. So the conclusion is that in 8.1 some bug is triggered, but
not in 8.2.
I'll try again in a few weeks when hopefully Webpack 8.2 is available.
Actually the reason that I tried 8.2 is that there were problems with 7.1.
The 8051 ran perfectly until interrupts were used. Then there is some intermittent
and very unpredictable behavior, mostly spontaneous resets of the 8051.
But very difficult to isolate.
Hopefully 8.2 also doesn't have that problem either.
Thanks again,
Sietse
Article: 104546"Andi" <00andi@web.de> wrote in message news:ee9c94c.6@webx.sUN8CHnE... > Is it possible to use other tool than xst for edk synthesis? I haven't tried it, but I am sure one should be able to use Synplify... /MikhailArticle: 104547
rajeev wrote: > Hi everyone, > I have a few doubts that are not being addressed in fpga groups(at > least i could not find the one ) though it is very common in DSP design > using FPGAs. > > 1. In many a communication receiver systems a resampler (NCO based) is > required. The output of the resampler is fed to other logics. Can NCO > output be used to drive the portion of the design ? as is sayed that in > FPGA clock derived from (combinational/sequential) logics should be > avoided and whenever a rate change is required use enable signal > instead. But this approach requires the whole design to be run at the > highest clock consuming much more power.What could be the power > efficent method of doing the same. > Most common example is a CIC filter used for large rate change (Not by > integer factor but rather rate change is driven by a NCO) where input > is at much higher rate while the output is at lower rate. > > 2. If at all NCO is used for clocking the design that is required to > run at much slower speed what care should be the taken for NCO master > clock driving NCO , to NCO output clock ? (I feel higher the ratio > lower the jitter will be). > > 3. Can NCO clock be further used to drive a DCM to produce a high freq > clock that can be used for serial MAC fir (for efficient fpga fabric > usage.) > > regards. > rajeev shukla. > The NCO isn't a sample rate changer, it, along with a mixer will move your signal to base-band where you can then low pass filter it and decimate it to reduce the sample rate to something in line with the bandwidth of your signal after filtering. For large rate changes, a CIC filter does make sense. You'll still need additional filters in most cases to improve the Q of the resulting filter bank. Typically, I use a CIC filter followed by two stages of decimate by 2 FIR filters. Rather than changing the clock rate, it is far easier to use clock enables to flag when good data is present at the decimated rate. This is especially true when you don't know what the output sample rate is going to be because of a programmable bandwidth and decimation ratio. Your downstream design can take advantage of the fact that for a given output sample rate there are N invalid samples between each valid sample. Use those spare clock cycles to reduce the size of the hardware with a combination of bit- or digit-serial computation and sequential computation (in other words trade the spare clock cycles for smaller hardware). Your limitation is the minimum number of clocks per sample, which occurs with the highest output sample rate that you can set the design up for. Many wireless designs have a fairly high minimum decimation ratio, so everything after the CIC filter can be bit serial and might even be shared between multiple channels if the bnadwidth of all the channels is the same. The comb side of the CIC filter can also be made bit serial to save some additional hardware. If there is a fixed integer division in the sample rate, then you can use a divided clock if that makes sense for your design. You should probably avoid an arbitrary non-integer clock divide because getting the data reliably across the clock domain and servo-ing the clock so that you don't have data over or underruns is a rather hard design to get right. If you do need that, then you probably need to be looking at more sophisticated resampling such as a Farrow resampler.Article: 104548
Vivek Menon wrote: > I came across the Xilinx application xapp223 for the implementation of > the UART cores. I have been trying various implementations of UART > transmitter cores and I am trying to implement this macro on a Xilinx > Virtex-II Pro 7 FPGA FF672 board. Now, I am using a 100 MHz clock, > which gets divided by 162 to provide the exact clock for a baud rate of > 38,400. I have also declared the uart_tx as a black box as per the > README file. However, the design has a lot of errors during the mapping > stage and I am not able to figure out the errors as I am not able to > open the .EDN file. The sample errors I faced are: > > ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on FDRE symbol > "U1/$I1" > (output signal=U1/A<3>). > ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on XORCY symbol > "U1/$I10" > (output signal=U1/SUM_A2). > ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on LUT4 symbol > "U1/$I105" > (output signal=U1/$Net00113_). > ERROR:Map:6 - Bad format for RLOC constraint " R6C0.S0" on FD symbol > "U1/$I106" > (output signal=U1/TX_RUN). > ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on FD symbol > "U1/$I107" > (output signal=U1/TX_START). > ERROR:Map:6 - Bad format for RLOC constraint "R6C0.S0" on LUT4 symbol > "U1/$I108" > (output signal=U1/$Net00151_). > ERROR:Map:6 - Bad format for RLOC constraint "R0C0.S1" on MUXCY symbol > "U1/$I11" > (output signal=U1/CY_A2). > > My ucf file for the top module is very simple: > NET clk LOC= D13; > NET tx_rs232 LOC=AC6; > NET wrn LOC=E7; > NET bfull LOC=D6; > > My top file declaration: > entity rs232_test_top is > port( > clk : in std_logic; > wrn : in std_logic; > bfull : out std_logic; > tx_rs232 : out std_logic); > end rs232_test_top; > > I am guessing that the component uart_tx is not being > compiled/synthesized by Xilinx ISE. Please let me know if there are any > solutions. > Thank you, > Vivek > The problem is actually a lot simpler than that. The design macro is apparently for Virtex1 or spartanII devices; the RLOC placement constraints are not the right style for the Virtex2 devices. If you have access to the source code, you need to either remove the RLOCs altogether and hope that it meets timing without them (it probably will), or change the RLOCs to the RLOC=XnYm style used in the Virtex2 and later devices (different layout grid). You can read about the RLOCs in the libraries guide, which is linked to from the XST/ISE project manager.Article: 104549
Aurelian Lazarut wrote: > run map with -ir (ignore RLOCs) > or if you use ISE, change map propreties by unchecking "use RLOC...." > Aurash > I don't believe that will work. I think the RLOCs are still parsed with that switch set, in which case it will error out with the same complaint.
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