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Threads Starting Feb 2008

128637: 08/02/01: Josue P. J. de Freitas: Gemac on ML402
128645: 08/02/01: LilacSkin: Xilinx timming analysis
    128647: 08/02/01: austin: Re: Xilinx timming analysis
    128648: 08/02/01: Symon: Re: Xilinx timming analysis
128650: 08/02/01: M. Hamed: Keeping Xilinx tool from Optimizing out Debugging signals
    128652: 08/02/01: austin: Re: Keeping Xilinx tool from Optimizing out Debugging signals
    128655: 08/02/01: M. Hamed: Re: Keeping Xilinx tool from Optimizing out Debugging signals
128662: 08/02/01: huangjie: spartan3a support DVI ?
    128666: 08/02/02: austin: Re: spartan3a support DVI ?
    128673: 08/02/02: huangjie: Re: spartan3a support DVI ?
    128674: 08/02/03: Antti: Re: spartan3a support DVI ?
128663: 08/02/02: Xesium: Loading from Compact Flash on ML310...
    128698: 08/02/04: Ed McGettigan: Re: Loading from Compact Flash on ML310...
        129604: 08/02/28: Ed McGettigan: Re: Loading from Compact Flash on ML310...
    129564: 08/02/27: Xesium: Re: Loading from Compact Flash on ML310...
128667: 08/02/02: Xin Xiao: Internal signal names in ModelSim
    128669: 08/02/02: KJ: Re: Internal signal names in ModelSim
    128670: 08/02/02: John Retta: Re: Internal signal names in ModelSim
    128671: 08/02/02: mk: Re: Internal signal names in ModelSim
    128695: 08/02/04: Analog_Guy: Re: Internal signal names in ModelSim
128677: 08/02/03: pallavi: Starting problems with ISE 9.2.04i (WebPack+ServicePack)...unable to
    128678: 08/02/03: Arlet Ottens: Re: Starting problems with ISE 9.2.04i (WebPack+ServicePack)...unable
        128712: 08/02/04: Dwayne Dilbeck: Re: Starting problems with ISE 9.2.04i (WebPack+ServicePack)...unable to set Spartan-3E as target
    128869: 08/02/07: pallavi: Re: Starting problems with ISE 9.2.04i (WebPack+ServicePack)...unable
128679: 08/02/03: FPGA: Scaling data
    128680: 08/02/03: Chris Maryan: Re: Scaling data
    128681: 08/02/03: sudhi: Re: Scaling data
    128694: 08/02/04: RCIngham: Re: Scaling data
    128725: 08/02/05: Anuja: Re: Scaling data
128683: 08/02/03: maverick: Bitstream verification through readback
    128684: 08/02/03: austin: Re: Bitstream verification through readback
    128685: 08/02/03: Jeff Cunningham: Re: Bitstream verification through readback
    128686: 08/02/04: Rob: Re: Bitstream verification through readback
    128721: 08/02/05: Dunstan Power: Re: Bitstream verification through readback
    128739: 08/02/05: <Sky465nm@trline5.org>: Re: Bitstream verification through readback
128688: 08/02/04: Goli: Server configuration for Virtex5
    128717: 08/02/05: Rob: Re: Server configuration for Virtex5
        128719: 08/02/05: <Sky465nm@trline5.org>: Re: Server configuration for Virtex5
    128740: 08/02/05: Goli: Re: Server configuration for Virtex5
128689: 08/02/04: LilacSkin: OFFSET In and hold time
    128690: 08/02/04: John McCaskill: Re: OFFSET In and hold time
128693: 08/02/04: <job@amontec.com>: forcing "Unused IOB Pin -> " from .ucf
128696: 08/02/04: <eli.billauer@gmail.com>: A video tutorial: The Xilinx FPGA Editor
    128702: 08/02/04: Daniel Koethe: Re: A video tutorial: The Xilinx FPGA Editor
    128703: 08/02/04: Dwayne Dilbeck: Re: A video tutorial: The Xilinx FPGA Editor
    128736: 08/02/05: <eli.billauer@gmail.com>: Re: A video tutorial: The Xilinx FPGA Editor
128697: 08/02/04: Klaus Mayer: 4-bit table look-up
    128701: 08/02/04: Klaus Mayer: Re: 4-bit table look-up
        128710: 08/02/04: Eric Smith: Re: 4-bit table look-up
    128705: 08/02/04: Eric Smith: Re: 4-bit table look-up
        128706: 08/02/05: Mark McDougall: Re: 4-bit table look-up
            128708: 08/02/04: DJ Delorie: Re: 4-bit table look-up
        128707: 08/02/04: Ed McGettigan: Re: 4-bit table look-up
            128709: 08/02/04: Eric Smith: Re: 4-bit table look-up
    128711: 08/02/04: Peter Alfke: Re: 4-bit table look-up
128700: 08/02/04: Michael Meeuwisse: Possible CRC error on XC3S400 - now what?
    128704: 08/02/04: <Sky465nm@trline5.org>: Re: Possible CRC error on XC3S400 - now what?
        128730: 08/02/05: Michael Meeuwisse: Re: Possible CRC error on XC3S400 - now what?
            128734: 08/02/05: Michael Meeuwisse: Re: Possible CRC error on XC3S400 - now what?
            128738: 08/02/05: <Sky465nm@trline5.org>: Re: Possible CRC error on XC3S400 - now what?
                128750: 08/02/05: Michael Meeuwisse: Re: Possible CRC error on XC3S400 - now what?
                    128753: 08/02/05: <Sky465nm@trline5.org>: Re: Possible CRC error on XC3S400 - now what?
                        128758: 08/02/05: Michael Meeuwisse: Re: Possible CRC error on XC3S400 - now what?
                            128760: 08/02/06: <Sky465nm@trline5.org>: Re: Possible CRC error on XC3S400 - now what?
                            128795: 08/02/06: Michael Meeuwisse: Re: Possible CRC error on XC3S400 - now what?
                                128796: 08/02/06: <Sky465nm@trline5.org>: Re: Possible CRC error on XC3S400 - now what?
                                    128826: 08/02/07: Michael Meeuwisse: Re: Possible CRC error on XC3S400 - now what?
                                        128840: 08/02/07: <Sky465nm@trline5.org>: Re: Possible CRC error on XC3S400 - now what?
                                        128842: 08/02/07: <Sky465nm@trline5.org>: Re: Possible CRC error on XC3S400 - now what?
                    128759: 08/02/06: Falk Brunner: Re: Possible CRC error on XC3S400 - now what?
                    128769: 08/02/06: Thorsten Trenz: Re: Possible CRC error on XC3S400 - now what?
    128715: 08/02/05: Thorsten Trenz: Re: Possible CRC error on XC3S400 - now what?
    128728: 08/02/05: Gabor: Re: Possible CRC error on XC3S400 - now what?
    128752: 08/02/05: Gabor: Re: Possible CRC error on XC3S400 - now what?
    128783: 08/02/06: Brian Davis: Re: Possible CRC error on XC3S400 - now what?
    128841: 08/02/07: AugustoEinsfeldt: Re: Possible CRC error on XC3S400 - now what?
128714: 08/02/05: Marco T.: Minimum Oscillator Frequency
    128722: 08/02/05: Gabor: Re: Minimum Oscillator Frequency
    128723: 08/02/05: Dunstan Power: Re: Minimum Oscillator Frequency
        128735: 08/02/05: Symon: Re: Minimum Oscillator Frequency
    128765: 08/02/05: Marco T.: Re: Minimum Oscillator Frequency
    128773: 08/02/06: AugustoEinsfeldt: Re: Minimum Oscillator Frequency
    128774: 08/02/06: AugustoEinsfeldt: Re: Minimum Oscillator Frequency
    128781: 08/02/06: PFC: Re: Minimum Oscillator Frequency
128716: 08/02/05: LilacSkin: A way to limit the data path delay
    128727: 08/02/05: Dunstan Power: Re: A way to limit the data path delay
    128731: 08/02/05: LilacSkin: Re: A way to limit the data path delay
128718: 08/02/05: <giorgos.puiklis@gmail.com>: MG Leonardo Synthesis Options
    128746: 08/02/05: Mike Treseler: Re: MG Leonardo Synthesis Options
128720: 08/02/05: <hilo_pupu@hotmail.com>: How to optimize my design area to fit?
    128724: 08/02/05: Gabor: Re: How to optimize my design area to fit?
    128726: 08/02/05: <filter001@desinformation.de>: Re: How to optimize my design area to fit?
    128729: 08/02/05: Dunstan Power: Re: How to optimize my design area to fit?
    128732: 08/02/05: Chris Maryan: Re: How to optimize my design area to fit?
    128743: 08/02/05: John Retta: Re: How to optimize my design area to fit?
    128797: 08/02/06: Kevin Neilson: Re: How to optimize my design area to fit?
128733: 08/02/05: <markmcmahon@hotmail.com>: GCLK overmapped
    128749: 08/02/05: Dwayne Dilbeck: Re: GCLK overmapped
128737: 08/02/05: <robquigley@gmail.com>: New leonardo spectrum version has license errors
    128747: 08/02/05: Mike Treseler: Re: New leonardo spectrum version has license errors
128742: 08/02/05: Gerry: Sythesisable subset of VHDL
    128745: 08/02/05: RCIngham: Re: Sythesisable subset of VHDL
    128846: 08/02/07: David Spencer: Re: Sythesisable subset of VHDL
128744: 08/02/05: FPGA: Modelsim Warning
    128748: 08/02/05: Mike Treseler: Re: Modelsim Warning
        128755: 08/02/05: Mike Treseler: Re: Modelsim Warning
    128751: 08/02/05: FPGA: Re: Modelsim Warning
    128756: 08/02/05: FPGA: Re: Modelsim Warning
    128863: 08/02/07: Dave Pollum: Re: Modelsim Warning
128754: 08/02/05: FPGA: simulator options
    128757: 08/02/05: Mike Treseler: Re: simulator options
128762: 08/02/05: <muthusnv@gmail.com>: ML505 with Petalinux
    129075: 08/02/14: John Williams: Re: ML505 with Petalinux
    129195: 08/02/18: <muthusnv@gmail.com>: Re: ML505 with Petalinux
128763: 08/02/05: <jcr_alr@xplornet.com>: Problems with GDB in EDK 9.2
    128766: 08/02/06: Markus: Re: Problems with GDB in EDK 9.2
    128832: 08/02/07: <jcr_alr@xplornet.com>: Re: Problems with GDB in EDK 9.2
128767: 08/02/06: xenix: OPB timer Microblaze
    128780: 08/02/06: Alan Nishioka: Re: OPB timer Microblaze
    128825: 08/02/07: xenix: Re: OPB timer Microblaze
128768: 08/02/06: Lars: 1-Wire and Dallas DS1WM in Spartan
    128791: 08/02/06: Frank Buss: Re: 1-Wire and Dallas DS1WM in Spartan
    128803: 08/02/06: Ray Andraka: Re: 1-Wire and Dallas DS1WM in Spartan
128770: 08/02/06: Paul Boven: Simulator error 607
    128819: 08/02/07: Paul Boven: Re: Simulator error 607
128771: 08/02/06: Gerry: Simple Memory Read problem, help appreciated
    128772: 08/02/06: Gerry: Re: Simple Memory Read problem, help appreciated
        128775: 08/02/06: Gerry: Re: Simple Memory Read problem, help appreciated
            128776: 08/02/06: KJ: Re: Simple Memory Read problem, help appreciated
                128779: 08/02/06: Gerry: Re: Simple Memory Read problem, help appreciated
                    128782: 08/02/06: KJ: Re: Simple Memory Read problem, help appreciated
                    128790: 08/02/06: Gerry: Re: Simple Memory Read problem, help appreciated
                        128792: 08/02/06: John Retta: Re: Simple Memory Read problem, help appreciated
                            128793: 08/02/06: Gerry: Re: Simple Memory Read problem, help appreciated
            128828: 08/02/07: Martin Thompson: Re: Simple Memory Read problem, help appreciated
                128830: 08/02/07: Gerry: Re: Simple Memory Read problem, help appreciated
        128787: 08/02/06: Peter Alfke: Re: Simple Memory Read problem, help appreciated
128777: 08/02/07: Tony Burch: Single Top FPGA Tips
    128784: 08/02/06: Falk Brunner: Re: Single Top FPGA Tips
        128800: 08/02/07: Tony Burch: Re: Single Top FPGA Tips
            128801: 08/02/06: John Retta: Re: Single Top FPGA Tips
                128838: 08/02/07: John Retta: Re: Single Top FPGA Tips
    128821: 08/02/07: want.a.friendlier.world@gmail.com: Re: Single Top FPGA Tips
        128916: 08/02/10: Tony Burch: Re: Single Top FPGA Tips
    128827: 08/02/07: KJ: Re: Single Top FPGA Tips
    128848: 08/02/07: KJ: Re: Single Top FPGA Tips
128785: 08/02/06: kyprianos: Partial Reconfiguration of Virtex-5: ISE and EAPR?
    128789: 08/02/06: austin: Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?
        128836: 08/02/07: austin: Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?
        128837: 08/02/07: austin: Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?
    128802: 08/02/06: <shack19@gmail.com>: Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?
    128835: 08/02/07: kyprianos: Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?
    128859: 08/02/07: shack19@gmail.com: Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?
    128864: 08/02/07: kyprianos: Re: Partial Reconfiguration of Virtex-5: ISE and EAPR?
128788: 08/02/06: <hemulliken@aol.com>: Virtex5 not for SONET or SDH
    128794: 08/02/06: austin: Re: Virtex5 not for SONET or SDH
    128822: 08/02/07: Goli: Re: Virtex5 not for SONET or SDH
        128839: 08/02/07: austin: Virtex 5 and SONET/SDH
128798: 08/02/06: FPGA: function/process to generate sine and cosine wave
    128799: 08/02/06: FPGA: Re: function/process to generate sine and cosine wave
    128804: 08/02/06: Jeff Cunningham: Re: function/process to generate sine and cosine wave
    128806: 08/02/06: Anuja: Re: function/process to generate sine and cosine wave
    128807: 08/02/06: FPGA: Re: function/process to generate sine and cosine wave
    128808: 08/02/06: Ray Andraka: Re: function/process to generate sine and cosine wave
        128813: 08/02/07: Ray Andraka: Re: function/process to generate sine and cosine wave
        128902: 08/02/09: Nicolas Matringe: Re: function/process to generate sine and cosine wave
            128907: 08/02/09: Brian Drummond: Re: function/process to generate sine and cosine wave
    128809: 08/02/06: FPGA: Re: function/process to generate sine and cosine wave
    128814: 08/02/07: comp.arch.fpga: Re: function/process to generate sine and cosine wave
    128823: 08/02/07: John: Re: function/process to generate sine and cosine wave
    128871: 08/02/08: Tricky: Re: function/process to generate sine and cosine wave
    128880: 08/02/08: FPGA: Re: function/process to generate sine and cosine wave
    128903: 08/02/09: comp.arch.fpga: Re: function/process to generate sine and cosine wave
    128906: 08/02/09: FPGA: Re: function/process to generate sine and cosine wave
128810: 08/02/06: <fbv999@gmail.com>: beleive
    128817: 08/02/07: <want.a.friendlier.world@gmail.com>: Re: beleive
        128818: 08/02/07: <MikeShepherd564@btinternet.com>: Re: beleive
    128820: 08/02/07: want.a.friendlier.world@gmail.com: Re: beleive
    128850: 08/02/07: Eric Smith: Re: beleive
        128857: 08/02/07: Ray Andraka: Re: beleive
    128873: 08/02/08: Rob: Re: beleive
128815: 08/02/07: H G: Shutdown parts of core logic on FPGA
    128816: 08/02/07: Falk Brunner: Re: Shutdown parts of core logic on FPGA
128824: 08/02/07: =?ISO-8859-1?Q?GaLaKtIkUs(tm)?=: ML410 and documentation on ALi M1535D+
    128853: 08/02/07: Peter Ryser: Re: ML410 and documentation on ALi M1535D+
    128855: 08/02/07: =?ISO-8859-1?Q?GaLaKtIkUs(tm)?=: Re: ML410 and documentation on ALi M1535D+
128829: 08/02/07: taco: Prom alternatives for xilinx
    128833: 08/02/07: Gabor: Re: Prom alternatives for xilinx
        128870: 08/02/08: taco: Re: Prom alternatives for xilinx
    128834: 08/02/07: Antti: Re: Prom alternatives for xilinx
    128913: 08/02/09: Walter: Re: Prom alternatives for xilinx
        128915: 08/02/09: Antti: Re: Prom alternatives for xilinx
128831: 08/02/07: maverick: Marking Flase paths for Timing Ignore + Virtex 2 Pro support
    128844: 08/02/07: Symon: Re: Marking Flase paths for Timing Ignore + Virtex 2 Pro support
    128845: 08/02/07: JuanC: Re: Marking Flase paths for Timing Ignore + Virtex 2 Pro support
    128931: 08/02/11: Andreas Ehliar: Re: Marking Flase paths for Timing Ignore + Virtex 2 Pro support
128843: 08/02/07: <hilo_pupu@hotmail.com>: What does "Continuous Sample times are not allowed" mean in SysGen
128847: 08/02/07: <Sky465nm@trline5.org>: I/O mode to use for USB ..?
    128849: 08/02/07: Antti: Re: I/O mode to use for USB ..?
        128851: 08/02/07: <Sky465nm@trline5.org>: Re: I/O mode to use for USB ..?
            128852: 08/02/07: austin: Re: I/O mode to use for USB ..?
                128856: 08/02/07: <Sky465nm@trline5.org>: Re: I/O mode to use for USB ..?
                    128866: 08/02/08: Mark McDougall: Re: I/O mode to use for USB ..?
                        128867: 08/02/08: <Sky465nm@trline5.org>: Re: I/O mode to use for USB ..?
        128868: 08/02/07: Antti: Re: I/O mode to use for USB ..?
128858: 08/02/07: Gerry: Weired Distributed Memory behaviour
    128860: 08/02/07: Mike Treseler: Re: Weired Distributed Memory behaviour
    128861: 08/02/07: Peter Alfke: Re: Weired Distributed Memory behaviour
        128882: 08/02/08: Gerry: Re: Weired Distributed Memory behaviour
            128887: 08/02/08: Symon: Re: Weired Distributed Memory behaviour
128862: 08/02/07: Michael Meeuwisse: impact bug or wrong interpretation of xsvf layout?
    128865: 08/02/07: mmihai: Re: impact bug or wrong interpretation of xsvf layout?
        128884: 08/02/08: Michael Meeuwisse: Re: impact bug or wrong interpretation of xsvf layout?
            128893: 08/02/08: Michael Meeuwisse: Re: impact bug or wrong interpretation of xsvf layout?
            128895: 08/02/08: Uwe Bonnes: Re: impact bug or wrong interpretation of xsvf layout?
            128917: 08/02/10: Kolja Waschk: Re: impact bug or wrong interpretation of xsvf layout?
        128894: 08/02/08: mmihai: Re: impact bug or wrong interpretation of xsvf layout?
128872: 08/02/08: <hilo_pupu@hotmail.com>: How to get Map Repoprt after System Generator postmap estimation
128874: 08/02/08: Alfreeeeed: Looking for a development board
    128877: 08/02/08: Symon: Re: Looking for a development board
        128881: 08/02/08: Symon: Re: Looking for a development board
            128886: 08/02/08: Symon: Re: Looking for a development board
                128892: 08/02/08: Michael Meeuwisse: Re: Looking for a development board
    128879: 08/02/08: Alfreeeeed: Re: Looking for a development board
    128883: 08/02/08: Alfreeeeed: Re: Looking for a development board
    128899: 08/02/09: John Adair: Re: Looking for a development board
    128910: 08/02/09: Alfreeeeed: Re: Looking for a development board
128875: 08/02/08: Nial Stewart: Strange "Style guide" requirements...
    128890: 08/02/08: Mike Treseler: Re: Strange "Style guide" requirements...
    128911: 08/02/09: jtw: Re: Strange "Style guide" requirements...
    128918: 08/02/10: Jonathan Bromley: Re: Strange "Style guide" requirements...
        128919: 08/02/10: Mike Treseler: Re: Strange "Style guide" requirements...
            128920: 08/02/10: Mike Treseler: Re: Strange "Style guide" requirements...
            128921: 08/02/10: Jonathan Bromley: Re: Strange "Style guide" requirements...
                129219: 08/02/19: Nial Stewart: Re: Strange "Style guide" requirements...
        129217: 08/02/19: Nial Stewart: Re: Strange "Style guide" requirements...
        129226: 08/02/19: KJ: Re: Strange "Style guide" requirements...
    128924: 08/02/11: Mark McDougall: Re: Strange "Style guide" requirements...
        128929: 08/02/10: Mike Treseler: Re: Strange "Style guide" requirements...
128876: 08/02/08: <hilo_pupu@hotmail.com>: Problem in assignment of pins in PACE
128878: 08/02/08: Clemens: Timing Constraint not met
    128889: 08/02/08: Mike Treseler: Re: Timing Constraint not met
        128898: 08/02/08: morphiend: Re: Timing Constraint not met
        128926: 08/02/10: <chrisdekoh@gmail.com>: Re: Timing Constraint not met
        129012: 08/02/12: M. Hamed: Re: Timing Constraint not met
        129016: 08/02/12: morphiend: Re: Timing Constraint not met
128885: 08/02/08: Clemens: Question to VHDL code fragment
    128888: 08/02/08: KJ: Re: Question to VHDL code fragment
128891: 08/02/08: vijayant.rutgers@gmail.com: multidimensional array
128896: 08/02/08: DJ Delorie: My first verilog/cpld project
    128897: 08/02/08: Tommy Thorn: Re: My first verilog/cpld project
    128900: 08/02/09: Arlet: Re: My first verilog/cpld project
        128912: 08/02/09: DJ Delorie: Re: My first verilog/cpld project
    128904: 08/02/09: <MikeShepherd564@btinternet.com>: Re: My first verilog/cpld project
    128905: 08/02/09: nospam: Re: My first verilog/cpld project
        128914: 08/02/09: DJ Delorie: Re: My first verilog/cpld project
    128998: 08/02/12: Jon Elson: Re: My first verilog/cpld project
        129000: 08/02/12: John_H: Re: My first verilog/cpld project
        129004: 08/02/13: Jim Granville: Re: My first verilog/cpld project
        129008: 08/02/12: DJ Delorie: Re: My first verilog/cpld project
            129022: 08/02/12: Dwayne Dilbeck: Re: My first verilog/cpld project
                129057: 08/02/13: nospam: Re: My first verilog/cpld project
                    129116: 08/02/14: Dwayne Dilbeck: Re: My first verilog/cpld project
            129058: 08/02/13: Jon Elson: Re: My first verilog/cpld project
                129064: 08/02/13: Arlet Ottens: Re: My first verilog/cpld project
128901: 08/02/09: Antti: ANN CPLD add-on module for Nintendo DS game console
    128908: 08/02/09: Symon: Re: ANN CPLD add-on module for Nintendo DS game console
    128909: 08/02/09: Antti: Re: ANN CPLD add-on module for Nintendo DS game console
128922: 08/02/10: <kian.zarrin@gmail.com>: loading unisim in modelsim problem while testin xilinx ipcore
    128923: 08/02/10: Mike Treseler: Re: loading unisim in modelsim problem while testin xilinx ipcore
    128933: 08/02/11: bvkrock: Re: loading unisim in modelsim problem while testin xilinx ipcore
    128993: 08/02/12: <deltabravosingh@gmail.com>: Re: loading unisim in modelsim problem while testin xilinx ipcore
    129863: 08/03/07: <kian.zarrin@gmail.com>: Re: loading unisim in modelsim problem while testin xilinx ipcore
128925: 08/02/10: <chrisdekoh@gmail.com>: microblaze firmware + UART handshaking blues
    128927: 08/02/10: GMM50: Re: microblaze firmware + UART handshaking blues
        128935: 08/02/11: David Brown: Re: microblaze firmware + UART handshaking blues
            129135: 08/02/15: Dave: Re: microblaze firmware + UART handshaking blues
                129144: 08/02/15: <MikeShepherd564@btinternet.com>: Re: microblaze firmware + UART handshaking blues
        129068: 08/02/13: Alex Freed: Re: microblaze firmware + UART handshaking blues
            129089: 08/02/14: David Brown: Re: microblaze firmware + UART handshaking blues
    128954: 08/02/11: <chrisdekoh@gmail.com>: Re: microblaze firmware + UART handshaking blues
    128961: 08/02/11: GMM50: Re: microblaze firmware + UART handshaking blues
    128979: 08/02/12: Dave Pollum: Re: microblaze firmware + UART handshaking blues
    129014: 08/02/12: <chrisdekoh@gmail.com>: Re: microblaze firmware + UART handshaking blues
    129033: 08/02/13: GMM50: Re: microblaze firmware + UART handshaking blues
    129070: 08/02/13: <chrisdekoh@gmail.com>: Re: microblaze firmware + UART handshaking blues
    129134: 08/02/15: werty: Re: microblaze firmware + UART handshaking blues
128928: 08/02/10: <anas_waris@hotmail.com>: Downloading codes to FPGA development Board
    128930: 08/02/11: <Sky465nm@trline5.org>: Re: Downloading codes to FPGA development Board
    128932: 08/02/10: <hilo_pupu@hotmail.com>: Re: Downloading codes to FPGA development Board
    128942: 08/02/11: pallavi: Re: Downloading codes to FPGA development Board
128934: 08/02/11: Symon: FYI. Free Verilog cores from MIT.
    128955: 08/02/11: emeb: Re: FYI. Free Verilog cores from MIT.
128936: 08/02/11: Jean-sébastien LEROY: RC340E board to sell
128937: 08/02/11: Clemens: Critical Path analysis
    128939: 08/02/11: Symon: Re: Critical Path analysis
    128994: 08/02/12: <deltabravosingh@gmail.com>: Re: Critical Path analysis
128938: 08/02/11: LilacSkin: Unsigned to signed vector.
    128940: 08/02/11: Symon: Re: Unsigned to signed vector.
    128943: 08/02/11: comp.arch.fpga: Re: Unsigned to signed vector.
        128945: 08/02/11: Jonathan Bromley: Re: Unsigned to signed vector.
            128947: 08/02/11: Jonathan Bromley: Re: Unsigned to signed vector.
                128952: 08/02/11: Jonathan Bromley: Re: Unsigned to signed vector.
                128976: 08/02/12: RCIngham: Re: Unsigned to signed vector.
    128944: 08/02/11: LilacSkin: Re: Unsigned to signed vector.
    128946: 08/02/11: LilacSkin: Re: Unsigned to signed vector.
    128948: 08/02/11: LilacSkin: Re: Unsigned to signed vector.
128941: 08/02/11: ratemonotonic: FSL version compatability with Microblaze version
128949: 08/02/11: <michel.talon@gmail.com>: Virtex5 DCM lower limit
    128950: 08/02/11: Antti: Re: Virtex5 DCM lower limit
    128957: 08/02/11: Mike Treseler: Re: Virtex5 DCM lower limit
    128969: 08/02/11: m: Re: Virtex5 DCM lower limit
    128972: 08/02/12: <michel.talon@gmail.com>: Re: Virtex5 DCM lower limit
    128992: 08/02/12: <deltabravosingh@gmail.com>: Re: Virtex5 DCM lower limit
        129200: 08/02/18: Mike Treseler: Re: Virtex5 DCM lower limit
    129158: 08/02/15: beeraka@gmail.com: Re: Virtex5 DCM lower limit
    129192: 08/02/18: <michel.talon@gmail.com>: Re: Virtex5 DCM lower limit
128951: 08/02/11: <paragon.john@gmail.com>: ModelSim versus Active-HDL....redux
    128953: 08/02/11: Alfreeeeed: Re: ModelSim versus Active-HDL....redux
    128959: 08/02/11: Duane Clark: Re: ModelSim versus Active-HDL....redux
        128975: 08/02/12: RCIngham: Re: ModelSim versus Active-HDL....redux
        128996: 08/02/12: Duane Clark: Re: ModelSim versus Active-HDL....redux
            129311: 08/02/20: Ray Andraka: Re: ModelSim versus Active-HDL....redux
        129309: 08/02/20: Ray Andraka: Re: ModelSim versus Active-HDL....redux
    128967: 08/02/11: nezhate: Re: ModelSim versus Active-HDL....redux
        128971: 08/02/12: Matthew Hicks: Re: ModelSim versus Active-HDL....redux
    129018: 08/02/12: <bobster.thelobster@yahoo.co.nz>: Re: ModelSim versus Active-HDL....redux
    129023: 08/02/12: Thomas Stanka: Re: ModelSim versus Active-HDL....redux
128956: 08/02/11: jon: XC5VLX85-2FFG1153C
    128980: 08/02/12: jon: Re: XC5VLX85-2FFG1153C
128958: 08/02/11: blisca: Xilinx ISE and XP home,possible?
    128962: 08/02/11: John_H: Re: Xilinx ISE and XP home,possible?
        129151: 08/02/15: blisca: Re: Xilinx ISE and XP home,possible?
128960: 08/02/11: Dave: how to implement this...
    128963: 08/02/12: Symon: Re: how to implement this...
    128964: 08/02/11: John_H: Re: how to implement this...
    128965: 08/02/12: Jim Granville: Re: how to implement this...
    128970: 08/02/12: backhus: Re: how to implement this...
        128973: 08/02/12: comp.arch.fpga: Re: how to implement this...
            129026: 08/02/13: backhus: Re: how to implement this...
        129140: 08/02/15: Nir Dahan: Re: how to implement this...
        129147: 08/02/15: John_H: Re: how to implement this...
        129161: 08/02/16: Nir Dahan: Re: how to implement this...
    129025: 08/02/12: glen herrmannsfeldt: Re: how to implement this...
128966: 08/02/11: nezhate: Reed solomon IP core
    128968: 08/02/12: jtw: Re: Reed solomon IP core
    128974: 08/02/12: nezhate: Re: Reed solomon IP core
128977: 08/02/12: Pasacco: Partial reconfiguration reference design?
128978: 08/02/12: Rob: Vitrex5 JTAG capture and debug
    128983: 08/02/12: Rob: Re: Vitrex5 JTAG capture and debug
128981: 08/02/13: Nick: '1' or '0' when I/O pin is pulled up
    129009: 08/02/12: Jonathan Bromley: Re: '1' or '0' when I/O pin is pulled up
        129021: 08/02/13: Nick: Re: '1' or '0' when I/O pin is pulled up
            129024: 08/02/13: backhus: Re: '1' or '0' when I/O pin is pulled up
128982: 08/02/12: Vagant: Does PC-FPGA communication requires a driver?
    128989: 08/02/12: John_H: Re: Does PC-FPGA communication requires a driver?
    128990: 08/02/12: Vagant: Re: Does PC-FPGA communication requires a driver?
        129013: 08/02/13: Matthew Hicks: Re: Does PC-FPGA communication requires a driver?
    128991: 08/02/12: <deltabravosingh@gmail.com>: Re: Does PC-FPGA communication requires a driver?
    129005: 08/02/12: Ben Jackson: Re: Does PC-FPGA communication requires a driver?
128984: 08/02/12: Jean-sébastien LEROY: XiRisc softcore processor
    128985: 08/02/12: Antti: Re: XiRisc softcore processor
    128986: 08/02/12: Uncle Noah: Re: XiRisc softcore processor
        129027: 08/02/13: Jean-sébastien LEROY: Re: XiRisc softcore processor
            129330: 08/02/21: Jean-sébastien LEROY: Re: XiRisc softcore processor
    128987: 08/02/12: Uncle Noah: Re: XiRisc softcore processor
    128988: 08/02/12: Uncle Noah: Re: XiRisc softcore processor
    129035: 08/02/13: Uncle Noah: Re: XiRisc softcore processor
128995: 08/02/12: morphiend: Virtex4FX over-voltage
    128997: 08/02/12: austin: Re: Virtex4FX over-voltage
    128999: 08/02/12: Andy Botterill: Re: Virtex4FX over-voltage
    129001: 08/02/12: John_H: Re: Virtex4FX over-voltage
    129003: 08/02/12: morphiend: Re: Virtex4FX over-voltage
129002: 08/02/12: MM: Redundant Ethernet connection
    129007: 08/02/12: MM: Re: Redundant Ethernet connection
129006: 08/02/12: everphilski@gmail.com: Newbie looking for guidance
    129010: 08/02/13: <MikeShepherd564@btinternet.com>: Re: Newbie looking for guidance
    129011: 08/02/12: MM: Re: Newbie looking for guidance
    129015: 08/02/13: Gavin Scott: Re: Newbie looking for guidance
        129028: 08/02/13: Martin Thompson: Re: Newbie looking for guidance
        129046: 08/02/13: Jonathan Bromley: Re: Newbie looking for guidance
        129061: 08/02/13: Gavin Scott: Re: Newbie looking for guidance
    129031: 08/02/13: Rob: Re: Newbie looking for guidance
        129063: 08/02/14: Jim Granville: Re: Newbie looking for guidance
    129039: 08/02/13: everphilski@gmail.com: Re: Newbie looking for guidance
    129040: 08/02/13: everphilski@gmail.com: Re: Newbie looking for guidance
129017: 08/02/12: anas_waris: Spartan 3A starter kit
    129019: 08/02/12: Eric Crabill: Re: Spartan 3A starter kit
    129020: 08/02/13: Gavin Scott: Re: Spartan 3A starter kit
129029: 08/02/13: Bathala: mb-g++ compilation error with EDK 8.2.02i
129030: 08/02/13: Thorsten Kiefer: floating point arithmetic in vhdl
    129037: 08/02/13: Patrick Dubois: Re: floating point arithmetic in vhdl
129032: 08/02/13: C-M, Chang: setup time not met in Quartus
    129034: 08/02/13: KJ: Re: setup time not met in Quartus
        129076: 08/02/13: Mike Treseler: Re: setup time not met in Quartus
    129047: 08/02/13: C-M, Chang: Re: setup time not met in Quartus
    129077: 08/02/13: Peter Alfke: Re: setup time not met in Quartus
    129095: 08/02/14: KJ: Re: setup time not met in Quartus
129036: 08/02/13: Mike Silva: When are FPGAs the right choice?
    129041: 08/02/13: chestnut: Re: When are FPGAs the right choice?
    129042: 08/02/13: Symon: Re: When are FPGAs the right choice?
        129051: 08/02/13: Symon: Re: When are FPGAs the right choice?
    129043: 08/02/13: Mike Harrison: Re: When are FPGAs the right choice?
        129324: 08/02/20: Ray Andraka: Re: When are FPGAs the right choice?
    129050: 08/02/13: Mike Silva: Re: When are FPGAs the right choice?
    129055: 08/02/14: Jim Granville: Re: When are FPGAs the right choice?
    129059: 08/02/13: Jon Elson: Re: When are FPGAs the right choice?
        129065: 08/02/13: Gavin Scott: Re: When are FPGAs the right choice?
            129079: 08/02/14: <Sky465nm@trline5.org>: Re: When are FPGAs the right choice?
        129067: 08/02/14: Jim Granville: Re: When are FPGAs the right choice?
    129060: 08/02/13: <Sky465nm@trline5.org>: Re: When are FPGAs the right choice?
    129062: 08/02/13: Eric Smith: Re: When are FPGAs the right choice?
    129066: 08/02/13: Mike Silva: Re: When are FPGAs the right choice?
129038: 08/02/13: tullio: Xilinx GTP_DUAL: wizard or code ?
    129132: 08/02/15: <muthusnv@gmail.com>: Re: Xilinx GTP_DUAL: wizard or code ?
129044: 08/02/13: chestnut: HELP on PLL and DCM
    129045: 08/02/13: Symon: Re: HELP on PLL and DCM
    129048: 08/02/13: austin: Re: HELP on PLL and DCM
129049: 08/02/13: Grumps: State machine outputs and tri-state
    129052: 08/02/13: RCIngham: Re: State machine outputs and tri-state
        129054: 08/02/13: Grumps: Re: State machine outputs and tri-state
            129085: 08/02/14: Grumps: Re: State machine outputs and tri-state
        129071: 08/02/13: <bobster.thelobster@yahoo.co.nz>: Re: State machine outputs and tri-state
        129072: 08/02/13: <bobster.thelobster@yahoo.co.nz>: Re: State machine outputs and tri-state
    129087: 08/02/14: backhus: Re: State machine outputs and tri-state
        129088: 08/02/14: Grumps: Re: State machine outputs and tri-state
            129090: 08/02/14: Grumps: Re: State machine outputs and tri-state
129053: 08/02/13: Symon: OT. Posting with Outlook Express?
129056: 08/02/13: L-C: Is a FPGA the solution ?
    129093: 08/02/14: RCIngham: Re: Is a FPGA the solution ?
        129107: 08/02/14: Mike Harrison: Re: Is a FPGA the solution ?
    129099: 08/02/14: Martin Thompson: Re: Is a FPGA the solution ?
    129323: 08/02/20: Ray Andraka: Re: Is a FPGA the solution ?
129069: 08/02/13: Peter Alfke: Virtex-5 User Guide "Lite"
    129073: 08/02/13: <bobster.thelobster@yahoo.co.nz>: Re: Virtex-5 User Guide "Lite"
    129074: 08/02/14: Symon: Re: Virtex-5 User Guide "Lite"
129078: 08/02/13: RobJ: Virtex-4 input pad failures
    129091: 08/02/14: Symon: Re: Virtex-4 input pad failures
        129096: 08/02/14: AugustoEinsfeldt: Re: Virtex-4 input pad failures
            129109: 08/02/14: RobJ: Re: Virtex-4 input pad failures
        129106: 08/02/14: RobJ: Re: Virtex-4 input pad failures
    129112: 08/02/14: John_H: Re: Virtex-4 input pad failures
        129125: 08/02/14: RobJ: Re: Virtex-4 input pad failures
    129119: 08/02/14: Jon Elson: Re: Virtex-4 input pad failures
        129124: 08/02/15: Jim Granville: Re: Virtex-4 input pad failures
129080: 08/02/13: Vijayan: Erratic Behavior of Virtex 4 FPGA
    129081: 08/02/13: mh: Re: Erratic Behavior of Virtex 4 FPGA
    129086: 08/02/14: Grumps: Re: Erratic Behavior of Virtex 4 FPGA
    129136: 08/02/15: Dunstan Power: Re: Erratic Behavior of Virtex 4 FPGA
129082: 08/02/13: <rabbiaqamar@yahoo.com>: i need ur help
    129131: 08/02/15: <muthusnv@gmail.com>: Re: i need ur help
129083: 08/02/13: <rabbiaqamar@yahoo.com>: i need fpga board with 10 Gig interface and pcie interface
    129084: 08/02/14: Allan Herriman: Re: i need fpga board with 10 Gig interface and pcie interface
        129092: 08/02/14: Symon: Re: i need fpga board with 10 Gig interface and pcie interface
            129101: 08/02/15: Allan Herriman: Re: i need fpga board with 10 Gig interface and pcie interface
        129265: 08/02/19: Ron Huizen: Re: i need fpga board with 10 Gig interface and pcie interface
129094: 08/02/14: rossalbi: signal generation in VHDL on FPGA.... Check my code please
    129098: 08/02/14: Brian Drummond: Re: signal generation in VHDL on FPGA.... Check my code please
    129103: 08/02/14: RCIngham: Re: signal generation in VHDL on FPGA.... Check my code please
    129113: 08/02/14: PatC: Re: signal generation in VHDL on FPGA.... Check my code please
    129130: 08/02/15: Rob: Re: signal generation in VHDL on FPGA.... Check my code please
    129154: 08/02/15: Rehman: Re: signal generation in VHDL on FPGA.... Check my code please
129097: 08/02/14: Frank Buss: Cyclone flash configuration data
    129242: 08/02/19: Mike Treseler: Re: Cyclone flash configuration data
        129245: 08/02/19: <MikeShepherd564@btinternet.com>: Re: Cyclone flash configuration data
        129258: 08/02/19: Frank Buss: Re: Cyclone flash configuration data
            129259: 08/02/19: Mike Treseler: Re: Cyclone flash configuration data
129100: 08/02/14: Marco T.: Rom Implementation in a CPLD
    129102: 08/02/14: Frank Buss: Re: Rom Implementation in a CPLD
    129108: 08/02/14: Mike Harrison: Re: Rom Implementation in a CPLD
    129115: 08/02/15: Jim Granville: Re: Rom Implementation in a CPLD
129104: 08/02/14: Philip Potter: Microblaze 7.0 on V2pro?
    129110: 08/02/14: Alan Nishioka: Re: Microblaze 7.0 on V2pro?
    129111: 08/02/14: austin: Re: Microblaze 7.0 on V2pro?
        129114: 08/02/14: Philip Potter: Re: Microblaze 7.0 on V2pro?
            129117: 08/02/14: austin: Re: Microblaze 7.0 on V2pro?
                129127: 08/02/15: Markus: Re: Microblaze 7.0 on V2pro?
                    129137: 08/02/15: austin: Re: Microblaze 7.0 on V2pro?
    129142: 08/02/15: austin: Re: Microblaze 7.0 on V2pro?
        129150: 08/02/15: Philip Potter: Re: Microblaze 7.0 on V2pro?
129105: 08/02/14: <giorgos.puiklis@gmail.com>: Reprogramming Proms,before the fpga boots from them (Avnet
129118: 08/02/14: =?ISO-8859-1?Q?J=FCrgen_B=F6hm?=: Spartan 3 configuration download error
    129120: 08/02/14: Dwayne Dilbeck: Re: Spartan 3 configuration download error
        129122: 08/02/14: =?ISO-8859-1?Q?J=FCrgen_B=F6hm?=: Re: Spartan 3 configuration download error
            129126: 08/02/14: Dwayne Dilbeck: Re: Spartan 3 configuration download error
                129128: 08/02/15: =?ISO-8859-1?Q?J=FCrgen_B=F6hm?=: Re: Spartan 3 configuration download error
    129121: 08/02/14: Frank Buss: Re: Spartan 3 configuration download error
    129123: 08/02/14: Peter Alfke: Re: Spartan 3 configuration download error
    129133: 08/02/15: Brian Davis: Re: Spartan 3 configuration download error
129129: 08/02/15: maxascent: Virtex 4 package layout
    129138: 08/02/15: austin: Re: Virtex 4 package layout
        129143: 08/02/15: <MikeShepherd564@btinternet.com>: Re: Virtex 4 package layout
            129148: 08/02/15: <MikeShepherd564@btinternet.com>: Re: Virtex 4 package layout
            129149: 08/02/15: Symon: Re: Virtex 4 package layout
                129153: 08/02/15: austin: Re: Virtex 4 package layout
                    129190: 08/02/18: maxascent: Re: Virtex 4 package layout
                        129193: 08/02/18: maxascent: Re: Virtex 4 package layout
        129145: 08/02/15: Peter Alfke: Re: Virtex 4 package layout
    129249: 08/02/19: austin: Re: Virtex 4 package layout
        129250: 08/02/19: maxascent: Re: Virtex 4 package layout
            129252: 08/02/19: austin: Re: Virtex 4 package layout
        129266: 08/02/19: Gabor: Re: Virtex 4 package layout
129139: 08/02/15: FPGA: distorted sine wave
    129146: 08/02/15: John_H: Re: distorted sine wave
        129155: 08/02/15: none: Re: distorted sine wave
        129156: 08/02/15: Dwayne Dilbeck: Re: distorted sine wave
    129152: 08/02/15: FPGA: Re: distorted sine wave
    129157: 08/02/15: John_H: Re: distorted sine wave
    129174: 08/02/17: FPGA: Re: distorted sine wave
129141: 08/02/15: wallge: PC configuration for fastest compiles (synthesis, place and route,
    129175: 08/02/17: CM: Re: PC configuration for fastest compiles (synthesis, place and
129159: 08/02/16: Steve: Ballpark PLB frequency
    129160: 08/02/16: Antti: Re: Ballpark PLB frequency
    129162: 08/02/16: Steve: Re: Ballpark PLB frequency
    129163: 08/02/16: Joseph Samson: Re: Ballpark PLB frequency
    129176: 08/02/17: Jeff Cunningham: Re: Ballpark PLB frequency
        129201: 08/02/18: Jeff Cunningham: Re: Ballpark PLB frequency
            129209: 08/02/19: Jim Granville: Re: Ballpark PLB frequency
            129267: 08/02/19: Jeff Cunningham: Re: Ballpark PLB frequency
                129286: 08/02/20: Andreas Ehliar: Re: Ballpark PLB frequency
                129290: 08/02/20: Jeff Cunningham: Re: Ballpark PLB frequency
    129185: 08/02/17: Ben Jackson: Re: Ballpark PLB frequency
    129194: 08/02/18: Guru: Re: Ballpark PLB frequency
    129203: 08/02/18: Antti: Re: Ballpark PLB frequency
    129224: 08/02/19: Guru: Re: Ballpark PLB frequency
    129281: 08/02/19: Antti: Re: Ballpark PLB frequency
    129294: 08/02/20: Antti: Re: Ballpark PLB frequency
129164: 08/02/16: Bob Smith: Linux and the Digilent Basys ?
    129181: 08/02/17: Michael Trim: Re: Linux and the Digilent Basys ?
    129189: 08/02/18: Andreas Ehliar: Re: Linux and the Digilent Basys ?
        129212: 08/02/18: Bob Smith: Re: Linux and the Digilent Basys ?
            129424: 08/02/23: <sky465nm@trline5.org>: Re: Linux and the Digilent Basys ?
129165: 08/02/16: <fcdup8k@yahoo.com>: Synthesis-Place-Route benchmark for i386-32bit
    129168: 08/02/17: Daniel Koethe: Re: Synthesis-Place-Route benchmark for i386-32bit
    129280: 08/02/19: Patrick Dubois: Re: Synthesis-Place-Route benchmark for i386-32bit
129166: 08/02/16: <veriqiang@gmail.com>: Over utilization of FPGA resources
    129167: 08/02/17: Frank Buss: Re: Over utilization of FPGA resources
        129171: 08/02/17: Symon: Re: Over utilization of FPGA resources
    129186: 08/02/17: Ben Jackson: Re: Over utilization of FPGA resources
129169: 08/02/17: Narendra Sisodiya: Video Over RF - using bluetooth and Xilinx Video Starter Kit
    129172: 08/02/17: Jonathan Bromley: Re: Video Over RF - using bluetooth and Xilinx Video Starter Kit
    129173: 08/02/17: Narendra Sisodiya: Re: Video Over RF - using bluetooth and Xilinx Video Starter Kit
    129405: 08/02/22: Narendra Sisodiya: Re: Video Over RF - using bluetooth and Xilinx Video Starter Kit
129170: 08/02/17: Antti: Embedded in Nurnberg
129177: 08/02/17: Peter Alfke: Antti needs a job
    129179: 08/02/17: Jonathan Bromley: Re: Antti needs a job
    129180: 08/02/17: BobW: Re: Antti needs a job
        129183: 08/02/18: Rob: Re: Antti needs a job
            129184: 08/02/17: BobW: Re: Antti needs a job
        129291: 08/02/20: Thomas Reinemann: Re: Antti needs a job
    129182: 08/02/17: Peter Alfke: Re: Antti needs a job
    129198: 08/02/18: <job@amontec.com>: Re: Antti needs a job
    129202: 08/02/18: Antti: Re: Antti needs a job
    129293: 08/02/20: Antti: Re: Antti needs a job
129187: 08/02/17: krunal: Interface on board ADC to Spartan 3E startkit
    129188: 08/02/18: Frank Buss: Re: Interface on board ADC to Spartan 3E startkit
129191: 08/02/18: Antti: MicroBlaze simulator, software ownership rights for SALE
    129303: 08/02/20: Dwayne Dilbeck: Re: MicroBlaze simulator, software ownership rights for SALE
        129315: 08/02/21: Jim Granville: Re: MicroBlaze simulator, software ownership rights for SALE
    129307: 08/02/20: Antti: Re: MicroBlaze simulator, software ownership rights for SALE
129196: 08/02/18: Julien Lochen: Define the primary clock with XST in VHDL
    129197: 08/02/18: KJ: Re: Define the primary clock with XST in VHDL
    129206: 08/02/18: Mike Treseler: Re: Define the primary clock with XST in VHDL
129199: 08/02/18: morphiend: V4FX100 PowerPC PLB issues (and EDK 9.2)
    129204: 08/02/18: Antti: Re: V4FX100 PowerPC PLB issues (and EDK 9.2)
    129205: 08/02/18: morphiend: Re: V4FX100 PowerPC PLB issues (and EDK 9.2)
    129261: 08/02/19: Ben Jackson: Re: V4FX100 PowerPC PLB issues (and EDK 9.2)
129207: 08/02/18: Jan Pech: Re: Ballpark PLB frequency
    129208: 08/02/18: Antti: Re: Ballpark PLB frequency
    129223: 08/02/19: Guru: Re: Ballpark PLB frequency
129210: 08/02/18: bigyellow: TCL testcase in Modelsim.
    129211: 08/02/18: Mike Treseler: Re: TCL testcase in Modelsim.
        129214: 08/02/18: Mike Treseler: Re: TCL testcase in Modelsim.
    129213: 08/02/18: bigyellow: Re: TCL testcase in Modelsim.
    129344: 08/02/21: Paul Uiterlinden: Re: TCL testcase in Modelsim.
    130668: 08/03/29: <jeffery_dong@hotmail.com>: Re: TCL testcase in Modelsim.
129215: 08/02/18: rickman: Using Lattice ispLEVER with VHDL libraries
    129253: 08/02/19: Colin Hankins: Re: Using Lattice ispLEVER with VHDL libraries
        129301: 08/02/20: Colin Hankins: Re: Using Lattice ispLEVER with VHDL libraries
            129312: 08/02/21: Jim Granville: Re: Using Lattice ispLEVER with VHDL libraries
        129350: 08/02/21: Mike Treseler: Re: Using Lattice ispLEVER with VHDL libraries
            129392: 08/02/22: Mike Treseler: Re: Using Lattice ispLEVER with VHDL libraries
                129472: 08/02/25: Mike Treseler: Re: Using Lattice ispLEVER with VHDL libraries
    129295: 08/02/20: rickman: Re: Using Lattice ispLEVER with VHDL libraries
    129305: 08/02/20: rickman: Re: Using Lattice ispLEVER with VHDL libraries
    129385: 08/02/22: rickman: Re: Using Lattice ispLEVER with VHDL libraries
    129468: 08/02/25: <troy.scott@latticesemi.com>: Re: Using Lattice ispLEVER with VHDL libraries
    129477: 08/02/25: rickman: Re: Using Lattice ispLEVER with VHDL libraries
129216: 08/02/19: Nial Stewart: Efficient division algorithm?
    129218: 08/02/19: Uwe Bonnes: Re: Efficient division algorithm?
        129231: 08/02/19: Nial Stewart: Re: Efficient division algorithm?
    129228: 08/02/19: KJ: Re: Efficient division algorithm?
        129232: 08/02/19: Nial Stewart: Re: Efficient division algorithm?
            129240: 08/02/19: Mike Treseler: Re: Efficient division algorithm?
                129256: 08/02/19: Mike Treseler: Re: Efficient division algorithm?
        129246: 08/02/19: KJ: Re: Efficient division algorithm?
        129247: 08/02/19: KJ: Re: Efficient division algorithm?
        129269: 08/02/19: Alain: Re: Efficient division algorithm?
        129271: 08/02/19: Tommy Thorn: Re: Efficient division algorithm?
    129230: 08/02/19: Mike Treseler: Re: Efficient division algorithm?
        129248: 08/02/19: KJ: Re: Efficient division algorithm?
            129254: 08/02/19: Mike Treseler: Re: Efficient division algorithm?
    129277: 08/02/19: Ray Andraka: Re: Efficient division algorithm?
        129333: 08/02/21: Nial Stewart: Re: Efficient division algorithm?
            129337: 08/02/21: Nial Stewart: Further Thoughts...
                129338: 08/02/21: <MikeShepherd564@btinternet.com>: Re: Further Thoughts...
                    129452: 08/02/25: Nial Stewart: Re: Further Thoughts...
    129304: 08/02/20: Kevin Neilson: Re: Efficient division algorithm?
        129308: 08/02/20: Ray Andraka: Re: Efficient division algorithm?
129220: 08/02/19: Dolphin: MIG and Spartan3 for a 112 bit DQ bus (7chips x16)
    129317: 08/02/20: Nico Coesel: Re: MIG and Spartan3 for a 112 bit DQ bus (7chips x16)
129221: 08/02/19: Alfreeeeed: FPGA Programming solution
    129222: 08/02/19: mh: Re: FPGA Programming solution
    129225: 08/02/19: <MikeShepherd564@btinternet.com>: Re: FPGA Programming solution
        129229: 08/02/19: <MikeShepherd564@btinternet.com>: Re: FPGA Programming solution
            129237: 08/02/19: <MikeShepherd564@btinternet.com>: Re: FPGA Programming solution
        129241: 08/02/19: Tim (one of many): Re: FPGA Programming solution
            129243: 08/02/19: <MikeShepherd564@btinternet.com>: Re: FPGA Programming solution
                129264: 08/02/19: Jon Elson: Re: FPGA Programming solution
                129274: 08/02/19: <MikeShepherd564@btinternet.com>: Re: FPGA Programming solution
                    129283: 08/02/20: <MikeShepherd564@btinternet.com>: Re: FPGA Programming solution
                        129288: 08/02/20: <MikeShepherd564@btinternet.com>: Re: FPGA Programming solution
                            129316: 08/02/20: <MikeShepherd564@btinternet.com>: Re: FPGA Programming solution
                        129310: 08/02/20: Jon Elson: Re: FPGA Programming solution
                            129318: 08/02/21: Jim Granville: Re: FPGA Programming solution
                                129402: 08/02/22: Jon Elson: Re: FPGA Programming solution
            129292: 08/02/20: Antti: Re: FPGA Programming solution
            129296: 08/02/20: emeb: Re: FPGA Programming solution
            129298: 08/02/20: emeb: Re: FPGA Programming solution
            129299: 08/02/20: Antti: Re: FPGA Programming solution
    129227: 08/02/19: Alfreeeeed: Re: FPGA Programming solution
    129234: 08/02/19: Alfreeeeed: Re: FPGA Programming solution
    129235: 08/02/19: comp.arch.fpga: Re: FPGA Programming solution
    129238: 08/02/19: John_H: Re: FPGA Programming solution
    129251: 08/02/19: Alfreeeeed: Re: FPGA Programming solution
    129262: 08/02/19: Bryan: Re: FPGA Programming solution
    129263: 08/02/19: Jon Elson: Re: FPGA Programming solution
    129273: 08/02/19: <langwadt@ieee.org>: Re: FPGA Programming solution
    129276: 08/02/19: <langwadt@ieee.org>: Re: FPGA Programming solution
    129285: 08/02/20: Alfreeeeed: Re: FPGA Programming solution
    129287: 08/02/20: Antti: Re: FPGA Programming solution
    129320: 08/02/20: <langwadt@ieee.org>: Re: FPGA Programming solution
129233: 08/02/19: Narendra Sisodiya: Which Linux Distro to use for Xilinx tools
    129236: 08/02/19: <paragon.john@gmail.com>: Re: Which Linux Distro to use for Xilinx tools
        129331: 08/02/21: Jean-sébastien LEROY: Re: Which Linux Distro to use for Xilinx tools
            129521: 08/02/27: John Williams: Re: Which Linux Distro to use for Xilinx tools
    129239: 08/02/19: morphiend: Re: Which Linux Distro to use for Xilinx tools
    129244: 08/02/19: Narendra Sisodiya: Re: Which Linux Distro to use for Xilinx tools
    129255: 08/02/19: <Sky465nm@trline5.org>: Re: Which Linux Distro to use for Xilinx tools
        129270: 08/02/19: <Sky465nm@trline5.org>: Re: Which Linux Distro to use for Xilinx tools
    129268: 08/02/19: Narendra Sisodiya: Re: Which Linux Distro to use for Xilinx tools
    129272: 08/02/19: Tom Curran: Re: Which Linux Distro to use for Xilinx tools
    129275: 08/02/20: John Williams: Re: Which Linux Distro to use for Xilinx tools
    129278: 08/02/19: Narendra Sisodiya: Re: Which Linux Distro to use for Xilinx tools
    129279: 08/02/19: Narendra Sisodiya: Re: Which Linux Distro to use for Xilinx tools
    129289: 08/02/20: Paul Boven: Re: Which Linux Distro to use for Xilinx tools
    129314: 08/02/20: Eric Smith: Re: Which Linux Distro to use for Xilinx tools
129257: 08/02/19: <michel.talon@gmail.com>: Virtex5 BUFR min frequency
    129260: 08/02/19: austin: Re: Virtex5 BUFR min frequency
129282: 08/02/20: MAx: scanf problem in EDk 9.1i (Microbaze)
129284: 08/02/20: Jan Pech: Re: scanf problem in EDk 9.1i (Microbaze)
    129328: 08/02/20: MAx: Re: scanf problem in EDk 9.1i (Microbaze)
        129433: 08/02/23: PFC: Re: scanf problem in EDk 9.1i (Microbaze)
    129372: 08/02/22: Jon Beniston: Re: scanf problem in EDk 9.1i (Microbaze)
    129448: 08/02/24: MAx: Re: scanf problem in EDk 9.1i (Microbaze)
129297: 08/02/20: jasonL: From ASIC RTL to FPGA, what are the things I should take care of?
    129300: 08/02/20: <info2@rayed.de>: Re: From ASIC RTL to FPGA, what are the things I should take care of?
    129302: 08/02/20: Dwayne Dilbeck: Re: From ASIC RTL to FPGA, what are the things I should take care of?
    129313: 08/02/20: Ralf Hildebrandt: Re: From ASIC RTL to FPGA, what are the things I should take care
    129410: 08/02/22: jasonL: Re: From ASIC RTL to FPGA, what are the things I should take care of?
129306: 08/02/20: <longbrmb@gmail.com>: Post PAR simulation is successful but still fails on the board
    129386: 08/02/22: <longbrmb@gmail.com>: Re: Post PAR simulation is successful but still fails on the board
129319: 08/02/20: radarman: Interrupt Handler page missing in from software platform settings in
    129498: 08/02/26: <MadhuPankaj11@gmail.com>: Re: Interrupt Handler page missing in from software platform settings
129321: 08/02/20: MM: V4FX: LVCMOS25 vs LVCMOS33 output buffer
    129322: 08/02/21: Symon: Re: LVCMOS25 vs LVCMOS33 output buffer
    129327: 08/02/20: austin: Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer
        129342: 08/02/21: MM: Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer
        129367: 08/02/21: BobW: Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer
            129382: 08/02/22: austin: Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer
                129403: 08/02/22: BobW: Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer
                    129409: 08/02/22: austin: Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer
                    129411: 08/02/22: austin: Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer
                    129412: 08/02/22: austin: Re: V4FX: LVCMOS25 vs LVCMOS33 output buffer
129329: 08/02/20: Goli: ADPCM IP Core
129332: 08/02/21: <cuga.smonster@gmail.com>: System generator hardware co-simulation interface
129334: 08/02/21: <puneetjamrani@gmail.com>: Reconfiguration (on the fly) using SPARTAN 3A
    129345: 08/02/21: austin: Re: Reconfiguration (on the fly) using SPARTAN 3A
        129349: 08/02/21: austin: Re: Reconfiguration (on the fly) using SPARTAN 3A
            129352: 08/02/21: austin: Re: Reconfiguration (on the fly) using SPARTAN 3A
                129375: 08/02/22: Andreas Ehliar: Re: Reconfiguration (on the fly) using SPARTAN 3A
                129378: 08/02/22: John_H: Re: Reconfiguration (on the fly) using SPARTAN 3A
                129383: 08/02/22: austin: Re: Reconfiguration (on the fly) using SPARTAN 3A
                    129387: 08/02/22: austin: Re: ICAP in SPARTAN 3A
                        129393: 08/02/22: austin: Re: ICAP in SPARTAN 3A
    129346: 08/02/21: Antti: Re: Reconfiguration (on the fly) using SPARTAN 3A
    129351: 08/02/21: Antti: Re: Reconfiguration (on the fly) using SPARTAN 3A
    129368: 08/02/22: <puneetjamrani@gmail.com>: Re: Reconfiguration (on the fly) using SPARTAN 3A
    129369: 08/02/22: <puneetjamrani@gmail.com>: Re: Reconfiguration (on the fly) using SPARTAN 3A
    129370: 08/02/22: Antti: Re: Reconfiguration (on the fly) using SPARTAN 3A
    129376: 08/02/22: vladitx: Re: Reconfiguration (on the fly) using SPARTAN 3A
    129384: 08/02/22: Antti: Re: Reconfiguration (on the fly) using SPARTAN 3A
    129389: 08/02/22: Antti: Re: ICAP in SPARTAN 3A
    129390: 08/02/22: Peter Alfke: Re: Reconfiguration (on the fly) using SPARTAN 3A
    129391: 08/02/22: Antti: Re: Reconfiguration (on the fly) using SPARTAN 3A
    129394: 08/02/22: Peter Alfke: Re: Reconfiguration (on the fly) using SPARTAN 3A
    129396: 08/02/22: Antti: Re: Reconfiguration (on the fly) using SPARTAN 3A
    129420: 08/02/22: Antti: Re: Reconfiguration (on the fly) using SPARTAN 3A
    129422: 08/02/23: <puneetjamrani@gmail.com>: Re: Reconfiguration (on the fly) using SPARTAN 3A
129335: 08/02/21: tmpstr: which IOSTANDARD to use for IO-bank in Spartan-3
    129339: 08/02/21: austin: Re: which IOSTANDARD to use for IO-bank in Spartan-3
    129371: 08/02/22: tmpstr: Re: which IOSTANDARD to use for IO-bank in Spartan-3
129336: 08/02/21: <auguste.chindji@googlemail.com>: Software Defined Radio auf Xilinx Virtex 4
    129340: 08/02/21: <info2@rayed.de>: Re: Software Defined Radio auf Xilinx Virtex 4
    129341: 08/02/21: austin: Re: Software Defined Radio auf Xilinx Virtex 4
        129364: 08/02/21: Ray Andraka: Re: Software Defined Radio auf Xilinx Virtex 4
    129343: 08/02/21: Peter Alfke: Re: Software Defined Radio auf Xilinx Virtex 4
        129347: 08/02/21: <MikeShepherd564@btinternet.com>: Re: Software Defined Radio auf Xilinx Virtex 4
            129358: 08/02/21: Dwayne Dilbeck: Re: Software Defined Radio auf Xilinx Virtex 4
        129357: 08/02/21: Kevin Neilson: Re: Software Defined Radio auf Xilinx Virtex 4
    129359: 08/02/21: John_H: Re: Software Defined Radio auf Xilinx Virtex 4
    129733: 08/03/04: <jetmarc@hotmail.com>: Re: Software Defined Radio auf Xilinx Virtex 4
129354: 08/02/21: Clemens Blank: Interview questions
    129356: 08/02/21: Clemens Blank: Re: Interview questions
        129361: 08/02/21: Kevin Neilson: Re: Interview questions
        129398: 08/02/22: jack.harvard@googlemail.com: Re: Interview questions
            129419: 08/02/22: jtw: Re: Interview questions
        129399: 08/02/22: jack.harvard@googlemail.com: Re: Interview questions
    129362: 08/02/21: John_H: Re: Interview questions
        129366: 08/02/21: <muthusnv@gmail.com>: Re: Interview questions
        129380: 08/02/22: Nir Dahan: Re: Interview questions
    129381: 08/02/22: Jon Beniston: Re: Interview questions
    129401: 08/02/22: Nico Coesel: Re: Interview questions
        129406: 08/02/22: Symon: Re: Interview questions
            129423: 08/02/23: Nico Coesel: Re: Interview questions
                129487: 08/02/26: Philip Potter: Re: Interview questions
                    129489: 08/02/26: Symon: Re: Interview questions
                        129491: 08/02/26: <MikeShepherd564@btinternet.com>: Re: Interview questions
                        129496: 08/02/26: Philip Potter: Re: Interview questions
                            129519: 08/02/27: Symon: Re: Interview questions
                                129543: 08/02/27: Philip Potter: Re: Interview questions
                                    129545: 08/02/27: Mike Lewis: Re: Interview questions
                                        129547: 08/02/27: Falk Brunner: Re: Interview questions
        129504: 08/02/26: checo: Re: Interview questions
    129508: 08/02/26: Gabor: Re: Interview questions
129360: 08/02/22: Stef: How to use xilinx specific features from Modelsim Designer 6.3a VHDL
    129363: 08/02/21: Mike Treseler: Re: How to use xilinx specific features from Modelsim Designer 6.3a
        129377: 08/02/22: Stef: Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL
            129404: 08/02/22: Mike Treseler: Re: How to use xilinx specific features from Modelsim Designer 6.3a
                129414: 08/02/23: Stef: Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL
                    129415: 08/02/22: Mike Treseler: Re: How to use xilinx specific features from Modelsim Designer 6.3a
                        129434: 08/02/23: Stef: Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL
                            129435: 08/02/23: Mike Treseler: Re: How to use xilinx specific features from Modelsim Designer 6.3a
                                129454: 08/02/25: Stef: Re: How to use xilinx specific features from Modelsim Designer 6.3a VHDL
129373: 08/02/22: auguste.chindji@googlemail.com: Software Defined Radio on Xilinx Virtex 4
    129388: 08/02/22: austin: Re: Software Defined Radio on Xilinx Virtex 4
    129455: 08/02/25: Bart Fox: Re: Software Defined Radio on Xilinx Virtex 4
129379: 08/02/22: Antti: Xilinx self-termination
    129416: 08/02/22: leevv: Re: Xilinx self-termination
        129418: 08/02/23: Tim (one of many): Re: Xilinx self-termination
            129512: 08/02/26: <lb.edc@telenet.be>: Re: Xilinx self-termination
129395: 08/02/22: Antti: Actel FPGA programming using libero 8.1 generated SVF files
    129397: 08/02/22: Antti: Re: Actel FPGA programming using libero 8.1 generated SVF files
129407: 08/02/22: Fei Liu: newbie seeking help to use xilinx spart-3a starter kit
    129408: 08/02/22: Frank Buss: Re: newbie seeking help to use xilinx spart-3a starter kit
        129413: 08/02/22: Fei Liu: Re: newbie seeking help to use xilinx spart-3a starter kit
129417: 08/02/22: Fei Liu: Problem with PINs XC3S700A-4FG484
    129444: 08/02/24: jkljljklk: Re: Problem with PINs XC3S700A-4FG484
    129445: 08/02/24: jkljljklk: Re: Problem with PINs XC3S700A-4FG484
        129446: 08/02/24: Fei Liu: Re: Problem with PINs XC3S700A-4FG484
            129476: 08/02/25: Fei Liu: Re: Problem with PINs XC3S700A-4FG484
                129479: 08/02/25: Dwayne Dilbeck: Re: Problem with PINs XC3S700A-4FG484
                    129499: 08/02/26: Fei Liu: Re: Problem with PINs XC3S700A-4FG484
        129464: 08/02/25: jkljljklk: Re: Problem with PINs XC3S700A-4FG484
129421: 08/02/23: Bob Smith: Xilinx DCM for frequency synthesis -- newbie question
    129427: 08/02/23: morphiend: Re: Xilinx DCM for frequency synthesis -- newbie question
        129431: 08/02/23: Bob Smith: Re: Xilinx DCM for frequency synthesis -- newbie question
            129432: 08/02/23: PatC: Re: Xilinx DCM for frequency synthesis -- newbie question
    129437: 08/02/23: JK: Re: Xilinx DCM for frequency synthesis -- newbie question
        129438: 08/02/24: Bob Smith: Re: Xilinx DCM for frequency synthesis -- newbie question
            129442: 08/02/24: Bob Smith: Re: Xilinx DCM for frequency synthesis -- newbie question
            129443: 08/02/24: PatC: Re: Xilinx DCM for frequency synthesis -- newbie question
        129439: 08/02/24: mng: Re: Xilinx DCM for frequency synthesis -- newbie question
        129453: 08/02/25: Rob: Re: Xilinx DCM for frequency synthesis -- newbie question
        129480: 08/02/25: mng: Re: Xilinx DCM for frequency synthesis -- newbie question
        129692: 08/03/03: <samonestopva@gmail.com>: Re: Xilinx DCM for frequency synthesis -- newbie question
    129483: 08/02/25: Bob Smith: Re: Xilinx DCM for frequency synthesis -- newbie question
        129507: 08/02/26: John LeVieux: Re: Xilinx DCM for frequency synthesis -- newbie question
            129523: 08/02/26: Bob Smith: Re: Xilinx DCM for frequency synthesis -- newbie question
        129525: 08/02/26: JK: Re: Xilinx DCM for frequency synthesis -- newbie question
        129681: 08/03/03: <samonestopva@gmail.com>: Re: Xilinx DCM for frequency synthesis -- newbie question
        129687: 08/03/03: JK: Re: Xilinx DCM for frequency synthesis -- newbie question
129425: 08/02/23: maverick: FPGA Editor Tutorial based on examples
    129426: 08/02/23: Frank Buss: Re: FPGA Editor Tutorial based on examples
    129428: 08/02/23: <MikeShepherd564@btinternet.com>: Re: FPGA Editor Tutorial based on examples
        129429: 08/02/23: Frank Buss: Re: FPGA Editor Tutorial based on examples
        129436: 08/02/24: <sky465nm@trline5.org>: Re: FPGA Editor Tutorial based on examples
129430: 08/02/23: PatC: Planahead IP export
    129474: 08/02/25: <brian.jackson@xilinx.com>: Re: Planahead IP export
        129766: 08/03/04: PatC: Re: Planahead IP export
129440: 08/02/24: saran: canny edge detection
    129441: 08/02/24: Jonathan Bromley: Re: canny edge detection
129447: 08/02/24: <chrisdekoh@gmail.com>: more microblaze firmware blues. tool chain version problem?
    129449: 08/02/24: Antti: Re: more microblaze firmware blues. tool chain version problem?
129450: 08/02/25: <raullim7@hotmail.com>: XEM3010
129451: 08/02/25: <hilo_pupu@hotmail.com>: Command to unzip hardware cosim files
129456: 08/02/25: EngineerEDGE: Online Engineering Calculator Tool for Electronic Engineers - FREE to
    129458: 08/02/25: <MikeShepherd564@btinternet.com>: Re: Online Engineering Calculator Tool for Electronic Engineers - FREE to use
129457: 08/02/25: Martin Schoeberl: The Java processor JOP is now GPL
129459: 08/02/25: FPGA: Seed Values
    129465: 08/02/25: Jim Lewis: Re: Seed Values
    129469: 08/02/25: FPGA: Re: Seed Values
    129470: 08/02/25: FPGA: Re: Seed Values
    129471: 08/02/25: FPGA: Re: Seed Values
        129473: 08/02/25: Mike Treseler: Re: Seed Values
        129497: 08/02/26: Jim Lewis: Re: Seed Values
            129503: 08/02/26: Mike Treseler: Re: Seed Values
    129490: 08/02/26: FPGA: Re: Seed Values
    129502: 08/02/26: FPGA: Re: Seed Values
129460: 08/02/25: Sylvain Munaut <SomeOne@SomeDomain.com>: Picoblaze enhencement and assembler
    129462: 08/02/25: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Picoblaze enhencement and assembler
    129485: 08/02/26: Andrew Greensted: Re: Picoblaze enhencement and assembler
        129492: 08/02/26: Paul Urbanus: Re: Picoblaze enhencement and assembler
    129529: 08/02/27: Jim Granville: Re: Picoblaze enhencement and assembler
        129555: 08/02/27: Nico Coesel: Re: Picoblaze enhencement and assembler
            129599: 08/02/28: Nico Coesel: Re: Picoblaze enhencement and assembler
            129600: 08/02/28: Mark: Re: Picoblaze enhencement and assembler
            129612: 08/02/29: Gerhard Hoffmann: Re: Picoblaze enhencement and assembler
    129548: 08/02/27: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Picoblaze enhencement and assembler
    129549: 08/02/27: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Picoblaze enhencement and assembler
    129550: 08/02/27: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Picoblaze enhencement and assembler
    129558: 08/02/27: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Picoblaze enhencement and assembler
    129605: 08/02/28: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Picoblaze enhencement and assembler
    129618: 08/02/28: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Picoblaze enhencement and assembler
    129630: 08/02/29: rickman: Re: Picoblaze enhencement and assembler
129461: 08/02/25: grant0920: About John Williams' ICAP driver?
    129520: 08/02/27: John Williams: Re: About John Williams' ICAP driver?
    129922: 08/03/10: grant0920: Re: About John Williams' ICAP driver?
129463: 08/02/25: aravind: Xilinx parallel cable 4 clone
    129466: 08/02/25: John_H: Re: Xilinx parallel cable 4 clone
    129467: 08/02/25: Antti: Re: Xilinx parallel cable 4 clone
    129478: 08/02/25: John Adair: Re: Xilinx parallel cable 4 clone
129475: 08/02/25: y_mh: sFPDP IP Core
129481: 08/02/25: FPGA: Synthesis of functions in Quartus
    129493: 08/02/26: RCIngham: Re: Synthesis of functions in Quartus
    129500: 08/02/26: Mike Treseler: Re: Synthesis of functions in Quartus
    129501: 08/02/26: FPGA: Re: Synthesis of functions in Quartus
129482: 08/02/25: =?GB2312?B?ybW5zw==?=: Does Altera has some analogous file like XDL of Xilinx?
    129511: 08/02/26: George: Re: Does Altera has some analogous file like XDL of Xilinx?
    129526: 08/02/26: <antti.tyrvainen@luukku.com>: Re: Does Altera has some analogous file like XDL of Xilinx?
    129541: 08/02/27: George: Re: Does Altera has some analogous file like XDL of Xilinx?
129484: 08/02/26: <hilo_pupu@hotmail.com>: Hardware Cosim no output
129486: 08/02/26: <kundanmit@gmail.com>: Using ICAP in s3a to reconfigure
    129510: 08/02/26: Bryan: Re: Using ICAP in s3a to reconfigure
129488: 08/02/26: Andreas Ehliar: Typical jitter of high frequency oscillators?
    129495: 08/02/26: austin: Re: Typical jitter of high frequency oscillators?
        129505: 08/02/26: Symon: Re: Typical jitter of high frequency oscillators?
            129509: 08/02/26: austin: Re: Typical jitter of high frequency oscillators?
        129524: 08/02/27: Andreas Ehliar: Re: Typical jitter of high frequency oscillators?
    129522: 08/02/26: John Larkin: Re: Typical jitter of high frequency oscillators?
129494: 08/02/26: Dolphin: set_input_delay min and max (timequest)
    129513: 08/02/26: Gianluigi: Re: set_input_delay min and max (timequest)
129506: 08/02/26: Brad Smallridge: ModelSim Natural arg value is negative
    129532: 08/02/27: Jonathan Bromley: Re: ModelSim Natural arg value is negative
        129635: 08/02/29: Brad Smallridge: Re: ModelSim Natural arg value is negative
            129636: 08/02/29: Jonathan Bromley: Re: ModelSim Natural arg value is negative
129514: 08/02/26: sdf: Convert some table into combinatorial circuit + optimization
    129515: 08/02/26: Dwayne Dilbeck: Re: Convert some table into combinatorial circuit + optimization
        129516: 08/02/26: Dwayne Dilbeck: Re: Convert some table into combinatorial circuit + optimization
        129518: 08/02/26: Dwayne Dilbeck: Re: Convert some table into combinatorial circuit + optimization
        129528: 08/02/27: Jim Granville: Re: Convert some table into combinatorial circuit + optimization
    129517: 08/02/26: sdf: Re: Convert some table into combinatorial circuit + optimization
    129968: 08/03/11: glen herrmannsfeldt: Re: Convert some table into combinatorial circuit + optimization
    129986: 08/03/12: Kolja Sulimma: Re: Convert some table into combinatorial circuit + optimization
129527: 08/02/26: Tom: Preventing optimization in cross clock domain logic
    129551: 08/02/27: rickman: Re: Preventing optimization in cross clock domain logic
    129574: 08/02/27: Tom: Re: Preventing optimization in cross clock domain logic
    129575: 08/02/27: rickman: Re: Preventing optimization in cross clock domain logic
    129578: 08/02/27: Tom: Re: Preventing optimization in cross clock domain logic
    129611: 08/02/29: Symon: Re: Preventing optimization in cross clock domain logic
    129613: 08/02/28: Tom: Re: Preventing optimization in cross clock domain logic
129530: 08/02/27: Pablo: OPB_MDM as UART in a PowerPC design
129531: 08/02/27: Stef: Viewing RTL schematic in Xilinx ISE
    129538: 08/02/27: <randallchaas@sbcglobal.net>: Re: Viewing RTL schematic in Xilinx ISE
        129540: 08/02/27: Stef: Re: Viewing RTL schematic in Xilinx ISE
129533: 08/02/27: <harisrini@gmail.com>: How to connect FPGA to a ASIC Board?
    129534: 08/02/27: Antti: Re: How to connect FPGA to a ASIC Board?
        129535: 08/02/27: Jonathan Bromley: Re: How to connect FPGA to a ASIC Board?
            129542: 08/02/27: Tim (one of many): Re: How to connect FPGA to a ASIC Board?
                129565: 08/02/27: Eric Smith: Re: How to connect FPGA to a ASIC Board?
            129589: 08/02/28: mk: Re: How to connect FPGA to a ASIC Board?
    129536: 08/02/27: Antti: Re: How to connect FPGA to a ASIC Board?
    129623: 08/02/29: comp.arch.fpga: Re: How to connect FPGA to a ASIC Board?
    129767: 08/03/05: <harisrini@gmail.com>: Re: How to connect FPGA to a ASIC Board?
129537: 08/02/27: kislo: SPI indirect programming using spartan 3e
    129539: 08/02/27: Antti: Re: SPI indirect programming using spartan 3e
    129552: 08/02/27: Bryan: Re: SPI indirect programming using spartan 3e
    129553: 08/02/27: Antti: Re: SPI indirect programming using spartan 3e
129544: 08/02/27: Antti: Tomorrow at Embeded in Nurnberg: Portable XSVF player demo
129546: 08/02/27: <thomasrt2008@gmail.com>: Xilinx's microblaze hangs when a timer interrupt occurs after a
    129556: 08/02/27: Jacob Schaffner: Re: Xilinx's microblaze hangs when a timer interrupt occurs after a
        129688: 08/03/03: Göran Bilski: Re: Xilinx's microblaze hangs when a timer interrupt occurs after a "rand()" instruction.
            129725: 08/03/04: Göran Bilski: Re: Xilinx's microblaze hangs when a timer interrupt occurs after a "rand()" instruction.
                130066: 08/03/14: Göran Bilski: Re: Xilinx's microblaze hangs when a timer interrupt occurs after a "rand()" instruction.
    129584: 08/02/27: <Remy.thomas.38@gmail.com>: Re: Xilinx's microblaze hangs when a timer interrupt occurs after a
    129704: 08/03/03: =?ISO-8859-1?Q?R=E9my?=: Re: Xilinx's microblaze hangs when a timer interrupt occurs after a
129554: 08/02/27: Jeff Cunningham: Why must a V4 be configured within 10 minutes of power up?
    129557: 08/02/27: Symon: Re: Why must a V4 be configured within 10 minutes of power up?
    129566: 08/02/27: austin: Re: Why must a V4 be configured within 10 minutes of power up?
        129571: 08/02/27: MM: Re: Why must a V4 be configured within 10 minutes of power up?
            129598: 08/02/28: austin: Re: Why must a V4 be configured within 10 minutes of power up?
                129602: 08/02/28: MM: Re: Why must a V4 be configured within 10 minutes of power up?
129559: 08/02/27: Xesium: ICAP attached to Microblaze on Virtex 2-pro..
    129637: 08/02/29: kyprianos: Re: ICAP attached to Microblaze on Virtex 2-pro..
    129638: 08/02/29: kyprianos: Re: ICAP attached to Microblaze on Virtex 2-pro..
    129648: 08/03/01: Xesium: Re: ICAP attached to Microblaze on Virtex 2-pro..
    129671: 08/03/02: kyprianos: Re: ICAP attached to Microblaze on Virtex 2-pro..
    129904: 08/03/08: Xesium: Re: ICAP attached to Microblaze on Virtex 2-pro..
    157083: 14/09/27: Ablaz7: Re: ICAP attached to Microblaze on Virtex 2-pro..
129560: 08/02/27: Jim Thompson: Re: ADC to FPGA Interface Webcast
    129567: 08/02/28: <sky465nm@trline5.org>: Re: ADC to FPGA Interface Webcast
        129568: 08/02/27: Dwayne Dilbeck: Re: ADC to FPGA Interface Webcast
129561: 08/02/27: <martstev@gmail.com>: Quicksim/modelsim
    129562: 08/02/27: Jonathan Bromley: Re: Quicksim/modelsim
129569: 08/02/27: chakra: Bus2IP_WR/RDCE XIO_Out/in32 EDK 9.1
    129698: 08/03/03: chakra: Re: Bus2IP_WR/RDCE XIO_Out/in32 EDK 9.1
129570: 08/02/27: Rajeev: Using dma_sg_v2_01_a component with plb_ipif
129572: 08/02/27: bjzhangwn@gmail.com: sd card slave interface
    129576: 08/02/28: <MikeShepherd564@btinternet.com>: Re: sd card slave interface
    129757: 08/03/04: bjzhangwn@gmail.com: Re: sd card slave interface
129573: 08/02/27: bjzhangwn@gmail.com: sd card slave interface
    129583: 08/02/27: Antti: Re: sd card slave interface
129577: 08/02/27: <etorkild@gmail.com>: Making changes to custom IP in EDK
    129582: 08/02/27: chakra: Re: Making changes to custom IP in EDK
    129591: 08/02/28: Jeff Cunningham: Re: Making changes to custom IP in EDK
    129592: 08/02/28: Guy Eschemann: Re: Making changes to custom IP in EDK
    129603: 08/02/28: Skogul: Re: Making changes to custom IP in EDK
    129634: 08/02/29: <benradu@gmail.com>: Re: Making changes to custom IP in EDK
    129847: 08/03/06: Skogul: Re: Making changes to custom IP in EDK
    129970: 08/03/11: <markmcmahon@hotmail.com>: Re: Making changes to custom IP in EDK
    129973: 08/03/11: Alan Nishioka: Re: Making changes to custom IP in EDK
129579: 08/02/27: FPGA: DSP newbie
129580: 08/02/27: FPGA: DSP newbie
    129581: 08/02/27: FPGA: Re: DSP newbie
        129586: 08/02/28: RCIngham: Re: DSP newbie
    129587: 08/02/28: Tricky: Re: DSP newbie
    129593: 08/02/28: FPGA: Re: DSP newbie
    129596: 08/02/28: Dave: Re: DSP newbie
    129597: 08/02/28: FPGA: Re: DSP newbie
    129601: 08/02/28: FPGA: Re: DSP newbie
129585: 08/02/28: <moogyd@yahoo.co.uk>: DCM Simulation : Input Clock Cycle Jitter
    129588: 08/02/28: Symon: Re: DCM Simulation : Input Clock Cycle Jitter
    129590: 08/02/28: <job@amontec.com>: Re: DCM Simulation : Input Clock Cycle Jitter
129594: 08/02/28: Vagant: Software for FPGA-based PC scope
    129610: 08/02/29: <sky465nm@trline5.org>: Re: Software for FPGA-based PC scope
        129614: 08/02/29: <MikeShepherd564@btinternet.com>: Re: Software for FPGA-based PC scope
        129615: 08/02/29: <MikeShepherd564@btinternet.com>: Re: Software for FPGA-based PC scope
            129654: 08/03/02: <MikeShepherd564@btinternet.com>: Re: Software for FPGA-based PC scope
                129655: 08/03/02: Nico Coesel: Re: Software for FPGA-based PC scope
                129659: 08/03/02: Mike Treseler: Re: Software for FPGA-based PC scope
                    129664: 08/03/02: <MikeShepherd564@btinternet.com>: Re: Software for FPGA-based PC scope
                        129666: 08/03/02: Mike Treseler: Re: Software for FPGA-based PC scope
                129663: 08/03/02: Jeff Cunningham: Re: Software for FPGA-based PC scope
                    129665: 08/03/02: Nico Coesel: Re: Software for FPGA-based PC scope
                        129676: 08/03/03: Jeff Cunningham: Re: Software for FPGA-based PC scope
    129646: 08/03/01: lm317t: Re: Software for FPGA-based PC scope
    129657: 08/03/02: lm317t: Re: Software for FPGA-based PC scope
    129660: 08/03/02: lm317t: Re: Software for FPGA-based PC scope
    129669: 08/03/02: lm317t: Re: Software for FPGA-based PC scope
    129672: 08/03/02: m: Re: Software for FPGA-based PC scope
    129694: 08/03/03: <Itandian@gmail.com>: Re: Software for FPGA-based PC scope
129606: 08/02/28: Sylvain Munaut <SomeOne@SomeDomain.com>: Re: Picoblaze enhencement and assembler
129607: 08/02/28: LM: What demokit and VHDL compiler pair to buy
    129608: 08/02/28: Dwayne Dilbeck: Re: What demokit and VHDL compiler pair to buy
129609: 08/02/28: LM: Re: What demokit and VHDL compiler pair to buy
129616: 08/02/28: Goli: Is there any way to disable JTAG for Sptantan3AN
    129617: 08/02/28: Antti: Re: Is there any way to disable JTAG for Sptantan3AN
    129619: 08/02/29: <job@amontec.com>: Re: Is there any way to disable JTAG for Sptantan3AN
        129727: 08/03/04: Martin Thompson: Re: Is there any way to disable JTAG for Sptantan3AN
    129621: 08/02/29: waltherz: Re: Is there any way to disable JTAG for Sptantan3AN
    129622: 08/02/29: Antti: Re: Is there any way to disable JTAG for Sptantan3AN
    129673: 08/03/02: Goli: Re: Is there any way to disable JTAG for Sptantan3AN
    129678: 08/03/02: Antti: Re: Is there any way to disable JTAG for Sptantan3AN
    129684: 08/03/03: Bert: Re: Is there any way to disable JTAG for Sptantan3AN
    129685: 08/03/03: Antti: Re: Is there any way to disable JTAG for Sptantan3AN
    129777: 08/03/05: Gabor: Re: Is there any way to disable JTAG for Sptantan3AN
129620: 08/02/29: Jean-sébastien LEROY: DSP Ip Core
    129653: 08/03/02: MM: Re: DSP Ip Core
129624: 08/02/29: FPGA: real to signed
    129627: 08/02/29: Mike Treseler: Re: real to signed
    129628: 08/02/29: Tricky: Re: real to signed
    129629: 08/02/29: Tricky: Re: real to signed
    129632: 08/02/29: FPGA: Re: real to signed
    129633: 08/02/29: FPGA: Re: real to signed
    129677: 08/03/02: Thomas Stanka: Re: real to signed
    129682: 08/03/03: Tricky: Re: real to signed
    129738: 08/03/04: FPGA: Re: real to signed
129625: 08/02/29: Marc Reinig: Need info on systolic arrays in actual use
    129626: 08/02/29: Kolja Sulimma: Re: Need info on systolic arrays in actual use
        129631: 08/02/29: Marc Reinig: Re: Need info on systolic arrays in actual use
            129647: 08/03/01: Marc Reinig: Re: Need info on systolic arrays in actual use
        129641: 08/03/01: Kolja Sulimma: Re: Need info on systolic arrays in actual use
    129965: 08/03/11: glen herrmannsfeldt: Re: Need info on systolic arrays in actual use
        129969: 08/03/11: Steven Guccione: Re: Need info on systolic arrays in actual use
    129983: 08/03/12: Florian Stock: Re: Need info on systolic arrays in actual use


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