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>Jon, > >OK, I was WRONG. I am not often WRONG, but, I can be WRONG, and I have >been WRONG in the past. > >NC is no connect. We don't use those pins, and they are not connected >internally in V4, and V5. > >Sorry for any confusion. > >Austin > Ok thanks for clearing that up. JonArticle: 129251
On Feb 19, 12:31 pm, MikeShepherd...@btinternet.com wrote: > >With Xilinx FPGAs, the fastest solution with a micro is usually one of > >the SPI modes. And a fast micro, of course. A little PAL or another FPGA > >will be at least as fast. Maybe this is also true for Altera. > > Let's race your SPI solution against my hand-optimised assembler!! :) > > I have to warn you that my method transfers at a peak rate of one > configuration bit every 375ns (three instruction cycles) and an > average of about one bit every 420ns over each 512-byte block from the > flash device. (There's a delay in requesting each block which would > apply to any method). > > If you use SPI, you'll first need to read the flash data into your > processor. With byte-wide flash, you have an advantage there and may > overtake me (although you'll use a lot more processor lines). With > serial flash, it will take longer to read the data to your processor > (unless you use another SPI controller for that) than it takes me to > send it on the direct connection between my flash memory and the FPGA > by just toggling the clocks. > > With parallel flash memory, you could still use direct connection. > This would waste all but one bit in each flash word, but that may not > be significant if the flash memory is much larger than the FPGA > configuration. > > Mike Ok , so here we are. We are evaluating between using a 16Mb PROM that you can use for Multi-boot ( USD $16) or doing it with a processor that would read all the programs from different Flash memories. In case we use the last one , I will evaluate wether use SPI or hand- optimised Assembler code. What do you think of that?Article: 129252
Jon, No problem. I was initially too conservative as there was something I recalled in the back of my mind for V4. That turned out to be not an issue. Just wanted to be sure I didn't say anything that would lead to a bad pcb layout! AustinArticle: 129253
Did you include the use clause in your library package files that require dependancies? You can either reference the user defined library itself or just do: use work.my_package; The error messages related to library not found is probably due to the library not being successfully compiled in the first place. Colin "rickman" <gnuarm@gmail.com> wrote in message news:284755cf-f23b-4979-9ecd-25d229fde921@e23g2000prf.googlegroups.com... >I am trying to pick up the Lattice ispLEVER tool and am having a bit > of trouble with it in regards to libraries. I have several files for > the various libraries I have written for my VHDL. In order to use > them, they have to be compiled in the correct order since some use > definitions from the others. I can't seem to figure out how to tell > ispLEVER what order to compile the files. It has a way to telling the > tool that a given file *is* a library, but that seems to be where it > stops. I can't order the files in the project and it doesn't seem to > actually understand that the libraries exist in the VHDL. I get > several error message all related to libraries not found or > identifiers not declared that should have been in the library files. > > I have looked through every piece of documentation I can find and they > all pretty much gloss over the idea of user defined libraries. Is > this something so simple I have missed it? >Article: 129254
KJ wrote:
>> A binary search multiply-subtract is possible with dsp blocks.
>>
> That's one that I've always wanted to try just to see how well it
> does, but haven't had the need to do so of late.
Yes, that one's on my white board too.
> One would expect it
> to get high throughput, low logic usage and probably be the best in
> today's world of nearly free DSP block multipliers in FPGAs.
It would be a good use for hardware multipliers
that often left unwired.
> Any benchmark data?
Well it couldn't do any better than log2(quotient) ticks
with one multiplier. Hmmm.. could divide that time 2**m for
m multipliers and parallel searches...
-- Mike Treseler
Article: 129255Narendra Sisodiya <narendra.sisodiya@gmail.com> wrote: >Hi, >I Love Linux, but currently i have to boot in XP because of xilinx >toolset (ISE, EDK, sysgen Matlab, chipscope etc) >May any body tell me , Any Linux Distro (other then commercial , like >redhat, i cann't buy) which will work perfectly with all >components(ISE, EDK, sysgen Matlab, chipscope etc). >I am using Fedora 7 and face problem with cable drivers and many such >things, >Is any body working perfectly with this any Linux Distro, ??? You can use www.FreeBSD.org ,any software that is stuck with ms-win can be handled with www.WineHQ.org ,or be run under vmware or qemu. Freebsd also use libusb asfair.Article: 129256
KJ wrote:
>> Quartus will infer lpm_divide from from int or signed /.
>>
> Doing so though will result in lpm_divide being parameterized with 0
> latency which will result in the largest logic lump and the slowest
> clock cycle performance. Depending on the application it might be
> better to instantiate the lpm_divide and not have it inferred from
> "/".
Thanks for the clarifications.
I might also try using "/"
with pipeline registers
and turn on synthesis register retiming.
-- Mike Treseler
Article: 129257Hi all, I've a question about BUFR primitives. I read in the datasheet that BUFR can distribute their output clock on clock regions, and have the availability to divide the input clock frequency by an integer (between 1 and 8). But, after reading AC specifications, I could not found the minimum frequency of the BUFR output clock ( when divider is equal to 8). So if anyone could help me ? Thanks by advance, Best regards, Michel.Article: 129258
Mike Treseler wrote: > Not completely as the RBF format is proprietary and sometimes > those 'bits at the beginning' move around with software > and device versions. It can be made to work, but you must > keep an eye on it. Looks like it doesn't work. The bits at the beginning are important. But if I convert it to a pof file first, and then to a rpd file, the content of the flash is the same when as when I flash it with a jic file and it works. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 129259
Frank Buss wrote:
> Looks like it doesn't work. The bits at the beginning are important. But if
> I convert it to a pof file first, and then to a rpd file, the content of
> the flash is the same when as when I flash it with a jic file and it works.
>
Thanks for the clarification.
I was confusing RBF with
a modified RBF used *only* by an Altera flash IP.
-- Mike Treseler
Article: 129260Michel, DC. There is no lower limit on frequency for this resource. AustinArticle: 129261
On 2008-02-18, morphiend <morphiend@gmail.com> wrote: > Anyone ever run into an issue where the PowerPC can write to entities > on its DPLB, but cannot read from them? > > I've added chipscope to the PLB and everything looks right from the > control lines. I singled-stepped the first read instruction on the > PowerPC and after stepping that instruction the PPC goes off into 'la- > la' land. I've seen that. If a PLB read doesn't complete, the PPC locks up pretty solidly. At least one case was a host bus access via a plb_temac (the indirection to the host bus may be important because it's slow or buggy or may be a red herring). The problem I saw didn't happen every time, and could be dramatically reduced with minute timing changes to the PLB accesses. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 129262
The Xilinx Platform Flash with Revisioning is a great, simple way to do this. With a parallel interface, it's very fast, and it comes with JTAG in-system capability. A lower cost alternative is Master SPI MultiBoot, which is available on the Spartan-3A series of FPGAs. Spartan-3E supports MultiBoot through parallel flash or Platform Flash. Spartan-3A can also do it with SPI flash and can support as many images as your flash will hold. See the Master SPI Mode and Reconfiguration and MultiBoot chapters in UG332 http://www.xilinx.com/support/documentation/user_guides/ug332.pdf One restriction with SPI is that the first configuration always takes place at address 0. So, you may have to have a "Selector" bitstream that takes user input to decide whether to redirect to Application A or Application B. You can see a simple example of this for the Spartan-3A Starter Kit on the Avnet Design Resource Center (sorry for the long URL) https://www.em.avnet.com/common/filetree/0,2740,RID%253D0%2526CID%253D44394%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526LID%253D32232%2526PVW%253D%2526PNT%253D%2526BID%253DDF2%2526CTP%253DSTA,00.html Bryan Alfreeeeed wrote: > On Feb 19, 12:31 pm, MikeShepherd...@btinternet.com wrote: > > >With Xilinx FPGAs, the fastest solution with a micro is usually one of > > >the SPI modes. And a fast micro, of course. A little PAL or another FPGA > > >will be at least as fast. Maybe this is also true for Altera. > > > > Let's race your SPI solution against my hand-optimised assembler!! :) > > > > I have to warn you that my method transfers at a peak rate of one > > configuration bit every 375ns (three instruction cycles) and an > > average of about one bit every 420ns over each 512-byte block from the > > flash device. (There's a delay in requesting each block which would > > apply to any method). > > > > If you use SPI, you'll first need to read the flash data into your > > processor. With byte-wide flash, you have an advantage there and may > > overtake me (although you'll use a lot more processor lines). With > > serial flash, it will take longer to read the data to your processor > > (unless you use another SPI controller for that) than it takes me to > > send it on the direct connection between my flash memory and the FPGA > > by just toggling the clocks. > > > > With parallel flash memory, you could still use direct connection. > > This would waste all but one bit in each flash word, but that may not > > be significant if the flash memory is much larger than the FPGA > > configuration. > > > > Mike > > Ok , so here we are. We are evaluating between using a 16Mb PROM that > you can use for Multi-boot ( USD $16) or doing it with a processor > that would read all the programs from different Flash memories. In > case we use the last one , I will evaluate wether use SPI or hand- > optimised Assembler code. > > What do you think of that?Article: 129263
Alfreeeeed wrote: > Greetings , I am trying to implement a solution for an FPGA that needs > to be configured with two different programs because the whole system > will operate in two different modes. Basically what I need is a device > that contains two programs and depending on the user will program one > of each. The pinout will be the same because it is a digital filter. > One thing that came to my mind is putting a PIC that would emulate a > PROM and would retrieve the corresponding program from a FLASH > memory. Another scheme is to use one of the really cheap SST serial proms that is twice the size you need, and rig a select bit to the logic that instructs the PROm where to start reading from. These chips are not drop-in replacements for the standard download PROMs, but they are SO cheap that it pays for the extra components required. JonArticle: 129264
Alfreeeeed wrote: > Ok , so here we are. We are evaluating between using a 16Mb PROM that > you can use for Multi-boot ( USD $16) or doing it with a processor > that would read all the programs from different Flash memories. In > case we use the last one , I will evaluate wether use SPI or hand- > optimised Assembler code. I have a scheme that I have worked out to use the SST25VF010-20-4C-SAE chip, $0.98 in 100 piece quantity, that's a 1 MBit serial flash. They have several larger versions, like the 8 MBit one is ~$3.00 ! I use a pair of LVQ CMOS logic chips to send the correct instruction to the chip to prepare it to read from the beginning. It would require adding one additional chip to extend the number of programmable bits so you could select the starting location within the PROM to select the desired program. This requires no CPU whatsoever, and the 2 or 3 logic chips are tiny SSOP parts costing no more than $0.25 each. The SPROM can keep up with the Xilinx master-mode configuration clock, so you don't need to provide a special clock for it. JonArticle: 129265
I expect that the poster may mean using four 3.125 GHz SerDes to implement 10 GigE (10GBASE-CX4 or -KX4), which is much more common these days. What he fails to mention is the form factor desired - we have a Stratix II GX AMC module which can do 4x PCI Express and 10 GigE (4 x 3.125), as there are 8 SerDes lanes from the Stratix II GX to the AMC connector, as well as another 4 out the front panel. See http://www.bittware.com/products/boards/prod_desc.cfm?ProdShrtName=GXAM for a description. ----------- Ron Huizen BittWare "Allan Herriman" <allanherriman@hotmail.com> wrote in message news:jrn7r35qmmm8roblphmc11b6sv19is6hbm@4ax.com... > On Wed, 13 Feb 2008 22:14:03 -0800 (PST), rabbiaqamar@yahoo.com wrote: > >>hi all, for my application i need a fpga board which has PCI express >>interface and 10 Gig ethernet or fibre channel interface. plz tell me >>if there is any board. > >>one more thing startix II GX PCI Express development board of Altera >>has10 Gig interface or not > > If it's the development board I'm thinking of, it doesn't do 10Gb/s. > The onboard StratixIIGX SERDES only works to about 6Gb/s. You could > do 4G Fibrechannel or 1G Ethernet using the SFP sockets supplied. > > > It's not too hard to roll your own 10Gb/s board though, but you'll > need to use external SERDES parts if you want it to work. See AMCC, > Vitesse, etc. > A couple of years ago I would have said that XFP was the only 10Gb/s > serial interface to use; now I would consider SFP+, as SFP+ will > probably be much cheaper than XFP over the lifetime of products > currently being designed. > > Regards, > AllanArticle: 129266
On Feb 19, 11:18 am, austin <aus...@xilinx.com> wrote: > Jon, > > OK, I was WRONG. I am not often WRONG, but, I can be WRONG, and I have > been WRONG in the past. > > NC is no connect. We don't use those pins, and they are not connected > internally in V4, and V5. > > Sorry for any confusion. > > Austin In my experience, NC means no internal connection. DNU means "do not use" or "make no external connection." There are many examples of this in JEDEC standard memories for instance. I would like to add that Xilinx does a pretty good job of making the package footprint compatible across the parts that use it. This gets even better in the V5 series where the smaller parts just leave out entire banks instead of a spattering of pins within banks. This helps to maintain I/O functionality when going to a larger device. In the old devices, the additional I/O's separating the same pins of the package can cause excessive pin-to-pin timing when upgrading to a larger device. As one who works with board-level products, I've seen a number of headaches involved with making the FPGA size a customer option. With some vendors it was almost impossible to find a DDR memory pinout that works across the device range of a given package. Regards, GaborArticle: 129267
Guru wrote: >> Ales, >> I'm still on 9.1. What bus diversity is changed in 9.2? >> -Jeff > > DCR and OPB is gone. > > Guru DCR bus is gone? WTF? I have a bunch of DCR peripherals - I cannot use those in 9.2 or beyond??? -JeffArticle: 129268
On Feb 19, 10:49 pm, Sky46...@trline5.org wrote: > Narendra Sisodiya <narendra.sisod...@gmail.com> wrote: > >Hi, > >I Love Linux, but currently i have to boot in XP because of xilinx > >toolset (ISE, EDK, sysgen Matlab, chipscope etc) > >May any body tell me , Any Linux Distro (other then commercial , like > >redhat, i cann't buy) which will work perfectly with all > >components(ISE, EDK, sysgen Matlab, chipscope etc). > >I am using Fedora 7 and face problem with cable drivers and many such > >things, > >Is any body working perfectly with this any Linux Distro, ??? > > You can usewww.FreeBSD.org,any software that is stuck with ms-win can be > handled withwww.WineHQ.org,or be run under vmware or qemu. > Freebsd also use libusb asfair. Using Vmware,, or any virtualization technique to install windows on top of Linux is not a good solution,, --as it will take a hell lot of time of compile,,, I have already tried,,wine,, but i does not work perfectly,, i will not suggest wine or vmware,,or quem in context of xilinx tools, I will try with Debian,Article: 129269
Hi all, Take a look at http://www.xilinx.com/support/documentation/user_guides/ug073.pdf On page 61, it describes two different algorithms. I've implement the first one without DSP block. It can perform a division of N bits in N cycles. It runs quite fast; on Spartan-3A-5, 100MHz for 32 bits (200MHz for 8 bits). Best regards.Article: 129270
Narendra Sisodiya <narendra.sisodiya@gmail.com> wrote: >On Feb 19, 10:49 pm, Sky46...@trline5.org wrote: >> Narendra Sisodiya <narendra.sisod...@gmail.com> wrote: >> >Hi, >> >I Love Linux, but currently i have to boot in XP because of xilinx >> >toolset (ISE, EDK, sysgen Matlab, chipscope etc) >> >May any body tell me , Any Linux Distro (other then commercial , like >> >redhat, i cann't buy) which will work perfectly with all >> >components(ISE, EDK, sysgen Matlab, chipscope etc). >> >I am using Fedora 7 and face problem with cable drivers and many such >> >things, >> >Is any body working perfectly with this any Linux Distro, ??? >> >> You can usewww.FreeBSD.org,any software that is stuck with ms-win can be >> handled withwww.WineHQ.org,or be run under vmware or qemu. >> Freebsd also use libusb asfair. >Using Vmware,, or any virtualization technique to install windows on >top of Linux is not a good solution,, --as it will take a hell lot of >time of compile,,, >I have already tried,,wine,, but i does not work perfectly,, i will >not suggest wine or vmware,,or quem in context of xilinx tools, >I will try with Debian, The newer virtualization technqiues like Xen etc.. runs at near native execution speed. It's not perfect, but it can solve the task. Another approach is a dedicated ms-win box wich is remote controlled via VNC or RDP.Article: 129271
On Feb 19, 7:57 am, KJ <kkjenni...@sbcglobal.net> wrote: > On Feb 19, 9:43 am, Mike Treseler <mike_trese...@comcast.net> wrote: > > Quartus will infer lpm_divide from from int or signed /. > > Doing so though will result in lpm_divide being parameterized with 0 > latency which will result in the largest logic lump and the slowest > clock cycle performance. Depending on the application it might be > better to instantiate the lpm_divide and not have it inferred from > "/". It doesn't have to be. If you explicitly delay the result, it will infer pipeline stages (I haven't tried it for divide, but other lpm works this way) . Eg. res3 <= a / b; res2 <= res3; res1 <= res2; final_result <= res1; You get the idea. TommyArticle: 129272
"Narendra Sisodiya" <narendra.sisodiya@gmail.com> wrote in message news:4a11eeee-c31f-4f2c-8f7b-10abce080ac2@s8g2000prg.googlegroups.com: > Hi, > I Love Linux, but currently i have to boot in XP because of xilinx > toolset (ISE, EDK, sysgen Matlab, chipscope etc) > May any body tell me , Any Linux Distro (other then commercial , like > redhat, i cann't buy) which will work perfectly with all > components(ISE, EDK, sysgen Matlab, chipscope etc). > I am using Fedora 7 and face problem with cable drivers and many such > things, > Is any body working perfectly with this any Linux Distro, ??? I have had reasonable success with the ISE and EDK 9.x tools installed on Fedora and CentOS. I have also very briefly tried Kubuntu 7.? and OpenSuse 10.2. I gave up on OpenSuse due to time constraints. I would avoid using the tools in a virtual environment (VMware, etc.) if you also need to use the parallel or USB programming cable. It is a known issue, for VMware at least, that the Xilinx USB programmer does not work reliably with the Xilinx drivers installed within a virtual machine. This is true for both the Xilinx supplied proprietary driver (IF you can manage to even get it to install!) and the open-source user-space driver mentioned previously. --TomArticle: 129273
On 19 Feb., 16:31, MikeShepherd...@btinternet.com wrote: > >With Xilinx FPGAs, the fastest solution with a micro is usually one of > >the SPI modes. And a fast micro, of course. A little PAL or another FPGA > >will be at least as fast. Maybe this is also true for Altera. > > Let's race your SPI solution against my hand-optimised assembler!! :) > > I have to warn you that my method transfers at a peak rate of one > configuration bit every 375ns (three instruction cycles) and an > average of about one bit every 420ns over each 512-byte block from the > flash device. (There's a delay in requesting each block which would > apply to any method). > > If you use SPI, you'll first need to read the flash data into your > processor. With byte-wide flash, you have an advantage there and may > overtake me (although you'll use a lot more processor lines). With > serial flash, it will take longer to read the data to your processor > (unless you use another SPI controller for that) than it takes me to > send it on the direct connection between my flash memory and the FPGA > by just toggling the clocks. > > With parallel flash memory, you could still use direct connection. > This would waste all but one bit in each flash word, but that may not > be significant if the flash memory is much larger than the FPGA > configuration. > > Mike how about wiring the prom clock to a pin that can be used as a timer output, at startup you can use the pin as io and bitbang the prom the usual way to pick the right starting address and give it the right read commands, after that enable the pin as a timer output and run as fast as the timer will go... -LasseArticle: 129274
>how about wiring the prom clock to a pin that can be used as a timer >output, at startup you >can use the pin as io and bitbang the prom the usual way to pick the >right starting address >and give it the right read commands, after that enable the pin as a >timer output and run as >fast as the timer will go... Maybe that would work in some cases. The number of clocks would need to be well-defined (to match exactly the size of a data block). The micro would then need to discard the CRC which follows the data. (It needn't check it as the FPGA will check the CRC on the whole of the configuration). In my case, the clock to the flash memory must be set before the clock to the FPGA (although they can be cleared at the same time), so a single signal won't work. Mike
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