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Hi, how are you. I am a university student from china. Now I am doing a project which will implement SAS with FPGAs on Xilinx Virtex 4 ML405 board. But before I am a software designer and never do IC design before ,so this project is very difficult for me.But this project is my graduate design.Without this project , I even canot graduate. So it is very important to me.I see you have done this project in Google groups forum. So could I make friends with you ,and exchange some technique about SAS with FPGAs.I hope you can help me and give me some guidances about this project, I will be very grateful to you.You can contact with me using email.My email is westspeed@163.com .Thank you very much. Yours sincerely TonyArticle: 127901
<snip> >. With the XP device, once > the flash is reprogrammed by the system via JTAG, I believe it has to > be told to reboot the SRAM from the flash which I don't have a simple > way of doing. I may have to share a incoming board pin between a > board disable control and the PROGRAM_N control.. if this is what is > required to reboot the device. > > Anyone here know for sure that toggling the PROGRAM_N pin is needed > and sufficient to reload the SRAM from the Flash? > Yes, it is neded and sufficient. I'm working with an XP device based board as we speak. Best regards, MakiArticle: 127902
Hi John, Just to point out that when using two FFs to mitigate metastability, the constraints file should include something (e.g. MAXDELAY) to make sure the signal delay between the two FFs is somewhat less than the default, which is the period of the FFs' clock. The P&R tools may not do this otherwise. Cheers, Syms.Article: 127903
Hi, I need to know is it possible to add multiple ucf files in an ISE project? I tried to do this by splitting the original ucf file into two and added it into a project. The tool compiles only one file and assigns default IOs to the the rest of the pins mentioned in the second part of the ucf. Any comments...........any tool settings I am not aware of......... Thanks in advance -farhanArticle: 127904
Thank for info Joe, > This product is on Spartan 3E 1600, but the original work was using the > 1200. Pixel Velocity using a Spartan - are you entering a low cost market? > > > The problem with this particular Spartan3E package is that banks 1 and > > 3 have just enough pins (except for calibration loop) for 32Mx16 DDR, > > but MIG does not want to use them (it forces clocks to bank 0 and 2). > > Which clocks do you mean - a master oscillator input? MIG wants that on > bank 0 or 2 because those have the global clock inputs. Bank 3's LHCLK > local clocks will only supply the left hand side of the chip. The global > clocks supply the entire chip. I suppose that you could generate a > design that had the pinouts that you like in Bank 3, then investigate > modding the code to use a LHCLK input. In the design that MIG1.5 > generated, LHCLK1 was unused. A master oscillator input is in bank 2 (GCLK0). I do not trust HCLKs. I was referring to DDR differential clock which should be in bank1 as other DDR signals. My problem is actually MIG methodology - how to build a custom design? > > If I follow MIG guidelines then I loose another bank - it should be > > connected to 2.5V. > > There are lots of oscillators available; there is probably one that > supports the standard that you want for bank 0 or 2. Input clock is not a problem, but If I put other DDR pins there, then the bank should be 2.5V powered. Cheers, AlesArticle: 127905
>On Jan 8, 8:03 am, "MJ Pearson" <mjp...@york.ac.uk> wrote: >> >Hi, >> >> >Gabor is right, As an addendum to his comment, I think that some >> >cameras from "Basler" use DVAL as pixel framing signal. It is used >> >when the user want to output some selected region from CCD of camera. >> >If you are getting two pulses of DVAL, check your camera whether it is >> >operating in single or dual tap mode and what is the region of >> >interest in camera setting. >> >> >Hope this helps, >> >> >/MH >> >> Thanks, >> >> My camera operates in 2-taps interleaved mode. It operates as a line scan >> camera, a single row value for each column of the sensor array is >> calculated and read out. Therefore I don't think the ROI will come into >> it, but I'm not sure what the taps refer to or their definition, and >> haven't had any luck in finding out...? > >The term "taps" come from the CCD world, where video comes out as >a serial analog stream from the sensor. In larger sensors, the >array was read out with more than one analog shift register or CCD >where a CCD might read out a quadrant or half of the sensor array. >Each of these output streams is called a "tap" and would be digitized >independently to provide the necessary readout bandwidth. > >In some older cameras, the framegrabber would need to re-assemble >the multiple taps into an image, possibly getting data in a different >order for each tap. One example of this is a four quadrant CCD read >out at the four corners of the array. When shifting out the data, >you would get the four corner pixels first and scan through in >raster fashion toward the final central pixels. In this case you >have all combinations of left-to-right, right-to-left, top-to-bottom, >and bottom-to-top scanning. Modern cameras might use similar CCD >devices, but generally re-order the data within the camera electronics >so the output looks like a simple raster. > >Interleaved tap order usually refers to odd / even pixels coming >out of two taps of the camera. In this case each tap services >every other pixel of the entire image, so the resultant image >is formed by merging (interleaving) the two taps to form a >single raster. > >For Camera Link, the number of "taps" usually refers to the number >of digitized pixels sent on each Camera Link pixel clock, regardless >of the organization of the sensor. The same camera may operate >in 1, 2, or 4 tap modes for example using Medium camera link and >8, 16, or 32 bits per clock. > >You may find more information in the technical manual of your camera. >These are usually available from the vendor's website and have more >detailed information that the user manual that ships with the camera. > >HTH, >Gabor > Thanks Gabor. I managed to get my head round this... While LVAL is high, a full line (in my case) is delivered by the camera - 1536 values. With a higher precision option the values are 10 bit - but everything from the camera is sent as 16bit data. The line is divided up into 2 DVAL pulses. On the first pulse the pixels 1-768 are read out, the second 769-1536. If however a lower precision is chosen, the values are 8 bit. In this case DVAL is the same as LVAL. On each clock pulse, 16 of the RxOut channels are used to describe 2 pixels, so thats 2 pixels read out on each clock pulse. Thanks very much for your help, my systems *appears* to be working. Hope the above info is of use to others. Regards Marc.Article: 127906
On Jan 10, 8:00 am, "MJ Pearson" <mjp...@york.ac.uk> wrote: > >On Jan 8, 8:03 am, "MJ Pearson" <mjp...@york.ac.uk> wrote: > >> >Hi, > > >> >Gabor is right, As an addendum to his comment, I think that some > >> >cameras from "Basler" use DVAL as pixel framing signal. It is used > >> >when the user want to output some selected region from CCD of camera. > >> >If you are getting two pulses of DVAL, check your camera whether it > is > >> >operating in single or dual tap mode and what is the region of > >> >interest in camera setting. > > >> >Hope this helps, > > >> >/MH > > >> Thanks, > > >> My camera operates in 2-taps interleaved mode. It operates as a line > scan > >> camera, a single row value for each column of the sensor array is > >> calculated and read out. Therefore I don't think the ROI will come > into > >> it, but I'm not sure what the taps refer to or their definition, and > >> haven't had any luck in finding out...? > > >The term "taps" come from the CCD world, where video comes out as > >a serial analog stream from the sensor. In larger sensors, the > >array was read out with more than one analog shift register or CCD > >where a CCD might read out a quadrant or half of the sensor array. > >Each of these output streams is called a "tap" and would be digitized > >independently to provide the necessary readout bandwidth. > > >In some older cameras, the framegrabber would need to re-assemble > >the multiple taps into an image, possibly getting data in a different > >order for each tap. One example of this is a four quadrant CCD read > >out at the four corners of the array. When shifting out the data, > >you would get the four corner pixels first and scan through in > >raster fashion toward the final central pixels. In this case you > >have all combinations of left-to-right, right-to-left, top-to-bottom, > >and bottom-to-top scanning. Modern cameras might use similar CCD > >devices, but generally re-order the data within the camera electronics > >so the output looks like a simple raster. > > >Interleaved tap order usually refers to odd / even pixels coming > >out of two taps of the camera. In this case each tap services > >every other pixel of the entire image, so the resultant image > >is formed by merging (interleaving) the two taps to form a > >single raster. > > >For Camera Link, the number of "taps" usually refers to the number > >of digitized pixels sent on each Camera Link pixel clock, regardless > >of the organization of the sensor. The same camera may operate > >in 1, 2, or 4 tap modes for example using Medium camera link and > >8, 16, or 32 bits per clock. > > >You may find more information in the technical manual of your camera. > >These are usually available from the vendor's website and have more > >detailed information that the user manual that ships with the camera. > > >HTH, > >Gabor > > Thanks Gabor. > > I managed to get my head round this... While LVAL is high, a full line (in > my case) is delivered by the camera - 1536 values. With a higher precision > option the values are 10 bit - but everything from the camera is sent as > 16bit data. The line is divided up into 2 DVAL pulses. On the first pulse > the pixels 1-768 are read out, the second 769-1536. > > If however a lower precision is chosen, the values are 8 bit. In this case > DVAL is the same as LVAL. On each clock pulse, 16 of the RxOut channels are > used to describe 2 pixels, so thats 2 pixels read out on each clock pulse. > > Thanks very much for your help, my systems *appears* to be working. Hope > the above info is of use to others. > > Regards > > Marc. It may be more useful if you mention the model of camera you're using :) Regards, GaborArticle: 127907
On Wed, 9 Jan 2008 09:50:37 -0800 (PST), koltes@fmi.uni-passau.de wrote: >> Do you want information about the board, or the chips? >> Xilinx Virtex-II can be programmed by Xilinx Webpack I assume. >> Maybe you could use the chips to decode the board connections. > >I'm primarly looking for information about the board. I guess, the >FPGAs are part of a JTAG chain, but I'm not even sure how to access >the JTAG subsystem, since there are lots of connectors and jumper >banks on the board. There is also a single small push button device on >the board, maybe some sort of reset? > >Despite this I have no idea what the two large chips are supposed to >do which can be seen at the bottom of the page. Fujitsu may be able to help ... these are possibly SPARC CPUs? - BrianArticle: 127908
On Wed, 09 Jan 2008 14:22:05 GMT, "KJ" <kkjennings@sbcglobal.net> wrote: [snip] >> >> The other point of my post was that because everyone has heard of >> metastability and that it's usually easy to deal with - just add flip >> flops and some timing slack - it gets taken into account in designs >> and doesn't actually cause a lot of bugs. >I think you're overestimating new designers ability to properly add these >flops based on postings in this and other newsgroups even when the poster >seems to have knowledge of metastability. I wasn't talking about new designers or Usenet posters, I was talking about a large group of experienced designers at Agilent. They wouldn't have been employed there if they didn't have a basic grasp of fundamentals such as designing for metastability. I apologise for not making it clear I wasn't talking about noobs. [snip] AllanArticle: 127909
On Jan 10, 4:23 pm, maverick <sheikh.m.far...@gmail.com> wrote: > Hi, > I need to know is it possible to add multiple ucf files in an ISE > project? I tried to do this by splitting the original ucf file into > two and added it into a project. The tool compiles only one file and > assigns default IOs to the the rest of the pins mentioned in the > second part of the ucf. Any comments...........any tool settings I am > not aware of......... > > Thanks in advance > > -farhan Hi, Farhan, ISE right now does not support multiple ucf files. But I think it is going to be supported form ISE10.1 that is what I had heard, am not sure though. -- GoliArticle: 127910
On Jan 9, 10:23 pm, Ben Jackson <b...@ben.com> wrote: > On 2008-01-10, ghel...@lycos.com <ghel...@lycos.com> wrote: > > > To re-configure the part, you (most likely) need to send a > > configuration command which will use both edges. > > Ah yes, I hadn't considered the mode registers. > > -- > Ben Jackson AD7GD > <b...@ben.com>http://www.ben.com/ While the mode registers are different, no command requires both edges. "Commands" are all captured on the rising edge of the clock and use only the control and address lines. Only the data is double-rate. My main reason for using single-data-rate parts is the simplicity of the wiring for the LVCMOS signals vs. SSTL. In small designs (1 32-bit SDR vs. 1 16-bit DDR) the pin savings for data can be lost in the additional Vref and control pins, especially on Xilinx parts that require all Vref pins in a bank to be tied together. I imagine if you started with a controller intended for DDR memory and only treat the data as SDR, you could get it to work. But as I mentioned before, your write data needs to set up to both edges of the clock in order for the read data to have extended setup time. If you slow the clock sufficiently, you may as well run the data DDR anyway. And you still need to generate DQS on a quadrature clock. So you would only save a DLL or DCM if you generated the clocks by dividing down some higher frequency. By the way, did you look into mobile DDR parts? I believe these are intended to run at low frequencies in order to save power and don't require SSTL interfacing. Regards, GaborArticle: 127911
Goli <togoli@gmail.com> wrote: > On Jan 10, 4:23 pm, maverick <sheikh.m.far...@gmail.com> wrote: > > Hi, > > I need to know is it possible to add multiple ucf files in an ISE > > project? I tried to do this by splitting the original ucf file into > > two and added it into a project. The tool compiles only one file and > > assigns default IOs to the the rest of the pins mentioned in the > > second part of the ucf. Any comments...........any tool settings I am > > not aware of......... > > > > Thanks in advance > > > > -farhan > Hi, > Farhan, > ISE right now does not support multiple ucf files. But I think it is > going to be supported form ISE10.1 that is what I had heard, am not > sure though. This single UCF is hard to handle. I construct the Pin Constraints by a script out of the layout. Then i have to add all timing constrainst by hand. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 127912
On Jan 9, 10:17=A0pm, "Brad Smallridge" <bradsmallri...@dslextreme.com> wrote: > I answered your code on the comp.vhdl group. > I think what you don't understand is that > if your dout statement is outside your clk block, > you will get what Xilinx calls an unregistered output. > > For some reason, Xilinx decided that unregistered RAM > is distributed, that is, it is made up indivivdual > registers scatered throughout the fabric. > > If the output is registered, on the other hand, > then ISE will drop your RAM into BRAM or Block RAM, > which is much more abundant in most Xilinx parts, > and also you will not task the synthesis tool to > scatter and then route your RAM, which is very time > consuming. > > Try this for more memory models:http://toolbox.xilinx.com/docsan/3_1i/data= /fise/xst/chap02/xst02013.htm > > Brad Smallridge > AiVision I had thought that the requirement for inferring BRAM was: 1) Either register the read address, or the read data output 2) register the write into the ram signal/variable So that not registering the "dout" signal would be OK, as long as the read address signal was registered.Article: 127913
On Jan 9, 9:54=A0pm, "Brad Smallridge" <bradsmallri...@dslextreme.com> wrote: > I am getting 'width mismatch' warning on the > char_slv assignement and text garbage after > synthesis on this code that ran fine on ISE 7.1 > > Does any one have an idea of what's wrong? > > Thanks much, > Brad Smallridge > AIVision > > type text_type is array(0 to 2047) of character; > constant text : text_type :=3D > " =A0 Bling 003 =A0 AiVision =A0 =A0Pat. 5,768,421 " & > . . . > " =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0" ; > > signal char_slv =A0: std_logic_vector(6 downto 0); > > begin > > text_proc: process(clk) > variable char_val : character; > variable char_pos : integer; > begin > =A0if(clk'event and clk=3D'1') then > =A0if(en=3D'1') then > =A0 =A0char_val :=3D text(to_integer(unsigned(text_index))); > =A0 =A0char_pos :=3D character'pos(char_val); > =A0 =A0char_slv <=3D std_logic_vector(to_unsigned(char_pos, char_slv'lengt= h)); > =A0end if; > =A0end if; > =A0end process; Maybe make char_pos an integer range 0 to 127? I don't think that explains garbage results, though...Article: 127914
On Thu, 10 Jan 2008 03:23:51 -0800 (PST), maverick <sheikh.m.farhan@gmail.com> wrote: >Hi, >I need to know is it possible to add multiple ucf files in an ISE >project? I tried to do this by splitting the original ucf file into >two and added it into a project. The tool compiles only one file and >assigns default IOs to the the rest of the pins mentioned in the >second part of the ucf. Any comments...........any tool settings I am >not aware of......... If you script (makefile, shell script, dos batch file, etc.) your build instead of using ISE, it becomes trivial to concatenate a number of UCFs into a single file and pass that to the tools. Regards, AllanArticle: 127915
Symon wrote:
> I thought from the OP's post that he means that this 'input' has already
> been sampled in the system clock domain, although it's not clear. If that is
> the case, assuming setup and hold are met, this is a metastability problem.
> If metastable signals only ever go to one place it's not a problem. That's
> how the input resampler works.
Yes. The synthesis tools assume input synchronization.
When synchronization fails all bets are off.
This thread points out the importance of being able
to distinguish structures intended to *be* synchronizers
from structures that assume such synchronization.
I beginning to think I should code synchronizers as
separate entities/modules. This would simplify constraints
and make it easier to check for register duplication.
> p.s. FYI
> http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Problems/asp06/PDF/8175.pdf
> this FF is immune. (Actually, of course it isn't, but it's interesting to
> see why it doesn't work.)
Funny. I'm wiping the coffee off my monitor ;)
These inventions always move the problem around
but never solve it.
-- Mike Treseler
Article: 127916On Thu, 10 Jan 2008 07:54:22 -0800, Mike Treseler <mike_treseler@comcast.net> wrote: >> p.s. FYI >> http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Problems/asp06/PDF/8175.pdf >> this FF is immune. (Actually, of course it isn't, but it's interesting to >> see why it doesn't work.) > >Funny. I'm wiping the coffee off my monitor ;) >These inventions always move the problem around >but never solve it. What I don't understand is how these patents get written. Doesn't the person who comes up with this invention look at the timing waveform at the bottom of fig.1 and say "what happens if this input goes to the input of the xor [on fig.3]?"Article: 127917
On Jan 10, 5:20 am, "Maki" <veselic...@eunet.yu> wrote: > <snip> > > >. With the XP device, once > > the flash is reprogrammed by the system via JTAG, I believe it has to > > be told to reboot the SRAM from the flash which I don't have a simple > > way of doing. I may have to share a incoming board pin between a > > board disable control and the PROGRAM_N control.. if this is what is > > required to reboot the device. > > > Anyone here know for sure that toggling the PROGRAM_N pin is needed > > and sufficient to reload the SRAM from the Flash? > > Yes, it is neded and sufficient. I'm working with an XP device based board > as we speak. > > Best regards, > Maki Thanks. I guess I am just a bit unsure, not having worked with these parts before. The board disable signal is high for disable. In that state my board should be non-functional in all ways. When the board is to be used or programmed, that line will be low. If I invert the disable signal and use it to drive PROGRAM_N, it will hold the XP in program mode when the board is disabled. Will this cause any problems? I know these parts are similar to the Xilinx parts and they would sit in the initialize state clearing memory continuously until PROGRAM_N is released. I can't find any info on what happens with the Lattice parts. They do list the power consumption in initialization which is around 100 mA combined and over twice as high as in "Standby". But they don't define exactly either of these measurements. I assume the initialization current is about the same while holding the PROGRAM_N pin low as it is after you release it until the DONE pin goes high. I also assume the Standby power is a configured part with no activity. I'll see what their support says. They seem to be pretty good at getting back in a day or so.Article: 127918
On Jan 9, 7:17=A0pm, "Brad Smallridge" <bradsmallri...@dslextreme.com> wrote: > > For some reason, Xilinx decided that unregistered RAM > is distributed, that is, it is made up indivivdual > registers scatered throughout the fabric. > Let me give a better explanation: Xilinx BlockRAMs are synchronous blocks. "Nothing happens without a clock". That means, the data output of a read operation appears at the RAM output as a result of the same clock edge that registered the address and the Enables. This is what happens in the "latched" option. There is also a "registered" option, where the output data only appears as a result of the subsequent clock edge, internally pipelined. It's the usual trade-off between performance and latency. When the designer specifies combinatorial RAM read operation (without a clock), the synthesis tool has no choice, it can only select the distributed LUT-RAM function, since the BlockRAM inherently cannot possibly perform a combinatorial read. Specifying combinatorial vs clocked read operation has a big impact on the design implementation... Peter AlfkeArticle: 127919
Hi All , I new to FPGA development tools from xilinx. I am following an application note number XAPP924 to use EPC module to inteface SMSC91C111 with a microblaze ( the application note is for PPC I have replaced it with uBlaze). This doesnt work I can only read lower bytes of the registers in SMSC , that too not for all registers? Has any one else encountered same problem? BR rateArticle: 127920
"Antti" <Antti.Lukats@googlemail.com> wrote in message news:c052dfab-e332-4842-9283-cd691a34f928@i72g2000hsd.googlegroups.com... > Hi > > it seems that Xilinx has promised to publisch (finally!) the > programming APIs for > cable IV and platform USB cable. > > this is not official but the universal scan last version includes > notes that they add support for Cable IV and platform USB in JANUARY > 2008; after Xilinx publishes the docs. > > so it can be derived that Xilinx has made promises to publish the APIs > in 2007 > > hm, maybe they already online at xilinx.com ? > > any more info anyone? > > Antti Lukats Antti, I found this post very surprising as I have worked with the engineering group that designs the cables. They have always had a stead-fast and adamant position regarding releasing the API (which is not to). After reading this post I inquired and just heard back. As expected, there are no immediate plans to release. It is also my understanding that further discussions regarding this will not happen any time soon. Sorry. -DavidArticle: 127921
mk wrote:
> What I don't understand is how these patents get written.
Many organizations like to collect patents
as as bargaining chips in legal disputes.
An engineer might come up with the original idea,
but lawyers do the technical writing and interpretations.
Some end up obeying the laws of physics. Some don't.
> Doesn't the
> person who comes up with this invention look at the timing waveform at
> the bottom of fig.1 and say "what happens if this input goes to the
> input of the xor [on fig.3]?"
Apparently not in this case.
-- Mike Treseler
Article: 127922maverick <sheikh.m.farhan@gmail.com> wrote: >Hi, >I need to know is it possible to add multiple ucf files in an ISE >project? I tried to do this by splitting the original ucf file into >two and added it into a project. The tool compiles only one file and >assigns default IOs to the the rest of the pins mentioned in the >second part of the ucf. Any comments...........any tool settings I am >not aware of......... Isn't it possible to include other UCF files? -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 127923
If you are looking to buy components I have a friend works in class-ic and she will give you a good priceArticle: 127924
Switching to Precision certainly did the trick. I've also alerted Lattice about the issue with Synplify and they've been very responsive. So hopefully it will soon be resolved. Although, I think I might just stick with Precision. "Maki" <veselic123@eunet.yu> wrote in message news:fm0imd$pe$1@aioe.org... > >I am unable to infer a True Dual Port RAM in ispLEVER using VHDL. I'm >> targetting the Lattice ECP2M using Synplify. Even the provided example >> located in >> isptools7_0\examples\fpga\latticexp2\memory\inferencing\true_dual_port\vhdl\true_dual_port.vhd >> does not synthesize successfully. Has anyone else had any better luck at >> this? > > It works fine with Precision. I too had the same problem with Synplify ver > 8.1 IIRC. It appears that template is all wrong for Synplify. Try another > one from Sunplify user guide... > > Happy inferencing :) > >> >> Thanks, >> Colin > > Maki. > >
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