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Messages from 128225

Article: 128225
Subject: Re: Xilinx ISE9.2 iMPACT manual
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Fri, 18 Jan 2008 08:20:37 -0800
Links: << >>  << T >>  << A >>

>> Is there a complete manual for iMPACT
>> ISE9.2 ?  Can't find it.
>>
>> Brad Smallridge
>> AiVision
>
> In the new software manuals (.pdf) I only see a link to iMPACT help,
> not a manual.  It's online in some fancy Java format.
>
> http://toolbox.xilinx.com/docsan/xilinx92/help/iseguide/mergedProjects/plugin_imp/plugin_imp.htm
>

Is that it?
Seems a little skimpy. And doesn't have screen shots.

Brad Smallridge





Article: 128226
Subject: Re: How is FIFO implemented in FPGA and ASIC?
From: "Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk>
Date: Fri, 18 Jan 2008 16:22:59 -0000
Links: << >>  << T >>  << A >>
> Hi Glen,
> My favourite FPGA FIFO design is described in XAPP291. The counters' storage elements are part of 
> the dual port RAM. "Their advantage is in using only one clock load."
> Cheers, Syms.


Pah, I'll beat that for elegance and simplicity....


process(clk,rst)
begin
    one_bit_fifo <= '0';
elsif(rising_edge(clk)) then
    if(load_fifo = '1') then
        one_bit_fifo <= one_bit_fifo_input;
    end if;
end if;
end process;

fifo_output <= one_bit_fifo;



:-)

It _is_ Friday afternoon!


Nial 



Article: 128227
Subject: Re: Where has Xilnet gone?
From: nico@puntnl.niks (Nico Coesel)
Date: Fri, 18 Jan 2008 17:14:45 GMT
Links: << >>  << T >>  << A >>
radarman <jshamlet@gmail.com> wrote:

>On Jan 14, 12:38 pm, Siva Velusamy <siva.velus...@xilinx.com> wrote:
>> ratemonotonic wrote:
>> > Hi all ,
>>
>> > I am new to xilinx tool and currently I am working with a project
>> > constructed using EDK 7.1. I am using EDK 9.2.
>>
>> > In this old project Xilnet is used for a webserver demo talking to an
>> > external MAC/PHY chip (SMSC 91C111).
>>
>> > Where can I get this library ?
>>
>> xilnet was deprecated for the last few releases. It is still there in
>> 9.2, but will go away in 10.1.
>>
>> The preferred solution is to use lwIP.
>>
>> /Siva
>
>lwip is not an adequate replacement for xilnet in all cases. First,
>lwip requires some form of OS kernel and timers, while xilnet can be
>used in stand-alone applications. As a result, xilnet is more suitable
>for smaller projects where code space is a constraint. However,
>reading the license for the code, it appears that you can keep using
>it even though it is deprecated, you will just need to turn it into a
>user library.

You could also use uIP. AFAIK this is lwip's little brother.
-- 
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

Article: 128228
Subject: Re: Using PECL inputs and PLL's in ProASIC Plus.
From: "RCIngham" <robert.ingham@gmail.com>
Date: Fri, 18 Jan 2008 11:15:09 -0600
Links: << >>  << T >>  << A >>
>Hello,
>   I am trying to use the PECL inputs of a ProASIC Plus APA075 device,
>independently of the PLL blocks.  The two PECL inputs (one on each
>side of this device) can be used independently of the PLL by assigning
>the GLPE or GLPEMIB macros, which use a global line each.  But I'm
>also using both PLL blocks on the device, although I only require one
>output from each it seems that I have to assign a global resource to
>both of the PLL outputs.  This is a problem since there are only 4
>globals available, so the PLL's use them all and I don't have any
>spare for the PECL inputs.  Can anyone advise whether it is possible
>to have both PLL's and both PECL inputs available at the same time?
>   Mark Lesha
>
I tried to do something similar on a previous project, and the Libero
fitter would not let me. If I remember correctly, it is an architectural
limitation.



Article: 128229
Subject: Re: Two's complement Coregen gone?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 18 Jan 2008 10:34:45 -0800
Links: << >>  << T >>  << A >>
Marty Ryba wrote:

>     I'm a systems engineer and not the direct FPGA guy, but I'm fairly 
> involved in the implementation of my DSP algorithm on our Virtex-II 
> platform. Our current code uses the 2's complement block IP core. Today, 
> when I went searching on the Xilinx site to refresh my memory on how it 
> works (we did the initial coding 3+ years ago), I couldn't find it anywhere! 
> Did it get replaced by something else, or should I just use the numeric 
> package to convert to that format?

Yes, ieee.numeric_std.unsigned would do the job.

           -- Mike Treseler

Article: 128230
Subject: Fuzzy Fixed Point Calculating
From: gvark <tsepkovsky@yandex.ru>
Date: Fri, 18 Jan 2008 10:38:45 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello!
 Prompt please how it is possible to create fuzzy system Sugeno
(ANFIS) with use fixed point calculations?
Realisation on FPGA is planned further. Probably there is a
literature
where about it it is possible to read?
In advance thanks!

Article: 128231
Subject: Re: ?FIR on GPU,CPU, FPGA, ASIC
From: Gabor <gabor@alacron.com>
Date: Fri, 18 Jan 2008 10:55:37 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 18, 9:39 am, Karl <karl.polyt...@googlemail.com> wrote:
> Hi,
> I am looking for a paper that compare the achieved performance from
> implementing general a N taps FIR filter on CPU, GPU, FPGA and ASIC
>
> i googled not much in return
>
> thanks

I would think that if anyone has this information it might be BDTI.  I
know
they have at least done benchmarks for DSP's ...

Article: 128232
Subject: Re: How is FIFO implemented in FPGA and ASIC?
From: "jack.harvard@googlemail.com" <jack.harvard@googlemail.com>
Date: Fri, 18 Jan 2008 11:12:03 -0800 (PST)
Links: << >>  << T >>  << A >>
> FIFOs get more complex than that. They can have different clocks for
> read and write, they can be large and require a dual port memory
> block, etc.

I reckon the question was about asynchronous FIFOs and possibly more
on the ASIC side, the Full and Empty signals need some care.

Article: 128233
Subject: Re: Fuzzy Fixed Point Calculating
From: austin <austin@xilinx.com>
Date: Fri, 18 Jan 2008 11:14:47 -0800
Links: << >>  << T >>  << A >>
http://www.google.com/search?hl=en&q=fuzzy+logic+fpga&btnG=Google+Search

33,800 hits ...

Looks like you have some reading to do.

Austin

Article: 128234
Subject: Re: How is FIFO implemented in FPGA and ASIC?
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 18 Jan 2008 11:42:28 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 18, 11:12=A0am, "jack.harv...@googlemail.com"
<jack.harv...@googlemail.com> wrote:
> > FIFOs get more complex than that. They can have different clocks for
> > read and write, they can be large and require a dual port memory
> > block, etc.
>
> I reckon the question was about asynchronous FIFOs and possibly more
> on the ASIC side, the Full and Empty signals need some care.

Let me throw in my usual tutorial:
If you have a dual-ported RAM, designing a synchronous (single-clock)
FIFO is trivial.
Designing an asynchronous (two independent clocks) FIFO faces the
tricky issue of detecting Full and Empty. That means detecting the
identity of two counters, which is best done with Gray-coded counters
(which in turn makes it difficult to perform arithmetic on them).

The leading edges of Full and Empty are unproblematic, since they are
generated by the "proper" clock (Empty is generated by a read
operation, and only the read side is interested in the Empty signal)
The VERY TRICKY issues are the trailing edges of Full and Empty, since
they are caused by the "wrong" clock, and thus require
synchronization, and face the UGLY issue of metastability. Enough
problems to give you some grey hair...
Peter Alfke


Article: 128235
Subject: Re: Fuzzy Fixed Point Calculating
From: austin <austin@xilinx.com>
Date: Fri, 18 Jan 2008 11:54:53 -0800
Links: << >>  << T >>  << A >>
http://www.google.com/search?as_q=fuzzy+system+Sugeno&hl=en&suggon=0&num=10&btnG=Google+Search&as_epq=&as_oq=fpga&as_eq=&lr=&cr=&as_ft=i&as_filetype=&as_qdr=all&as_nlo=&as_nhi=&as_occt=any&as_dt=i&as_sitesearch=&as_rights=&safe=images

OK, 1,290 hits.  Still a lot of reading.

Austin

Article: 128236
Subject: Re: How is FIFO implemented in FPGA and ASIC?
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Fri, 18 Jan 2008 21:33:53 +0100
Links: << >>  << T >>  << A >>
Peter Alfke schrieb:

> synchronization, and face the UGLY issue of metastability. Enough
> problems to give you some grey hair...

So it looks like you designed quite a lot of those nasty FIFOs . . .

SCNR
Falk

Article: 128237
Subject: Re: How is FIFO implemented in FPGA and ASIC?
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 18 Jan 2008 13:59:34 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 18, 12:33=A0pm, Falk Brunner <Falk.Brun...@gmx.de> wrote:
> Peter Alfke schrieb:
>
> > synchronization, and face the UGLY issue of metastability. Enough
> > problems to give you some grey hair...
>
> So it looks like you designed quite a lot of those nasty FIFOs . . .
>
> SCNR
> Falk
Yes, grey hair, but (still) lots of it !
Today is my 20th anniversary at Xilinx.
It has been a very good experience, in every respect...
Peter

Article: 128238
Subject: Re: How is FIFO implemented in FPGA and ASIC?
From: "jack.harvard@googlemail.com" <jack.harvard@googlemail.com>
Date: Fri, 18 Jan 2008 14:21:49 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 18, 7:42=A0pm, Peter Alfke <pe...@xilinx.com> wrote:
> On Jan 18, 11:12=A0am, "jack.harv...@googlemail.com"
>
> <jack.harv...@googlemail.com> wrote:
> > > FIFOs get more complex than that. They can have different clocks for
> > > read and write, they can be large and require a dual port memory
> > > block, etc.
>
> > I reckon the question was about asynchronous FIFOs and possibly more
> > on the ASIC side, the Full and Empty signals need some care.
>
> Let me throw in my usual tutorial:
> If you have a dual-ported RAM, designing a synchronous (single-clock)
> FIFO is trivial.
> Designing an asynchronous (two independent clocks) FIFO faces the
> tricky issue of detecting Full and Empty. That means detecting the
> identity of two counters, which is best done with Gray-coded counters
> (which in turn makes it difficult to perform arithmetic on them).
>
> The leading edges of Full and Empty are unproblematic, since they are
> generated by the "proper" clock (Empty is generated by a read
> operation, and only the read side is interested in the Empty signal)
> The VERY TRICKY issues are the trailing edges of Full and Empty, since
> they are caused by the "wrong" clock, and thus require
> synchronization, and face the UGLY issue of metastability. Enough
> problems to give you some grey hair...
> Peter Alfke

Asynchronous FIFO implementation is also explained in Steve Kilts'
Advanced FPGA Design book, although not in great details.

Article: 128239
Subject: Re: How is FIFO implemented in FPGA and ASIC?
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Fri, 18 Jan 2008 23:43:31 +0100
Links: << >>  << T >>  << A >>
Peter Alfke schrieb:

> Today is my 20th anniversary at Xilinx.

Congratulations!

Regards
Falk

Article: 128240
Subject: Source of accurate frequency
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 18 Jan 2008 14:49:46 -0800 (PST)
Links: << >>  << T >>  << A >>
This is slightly off-topic:
I have mentioned before that I am in the process of designing (and
manufacturing in limited volume) a clock-generator box (1 Hz to 1.5
GHz in 1 Hz increments). We debated some jitter issues...
It's tough to get a very accurate reference xtal (2 ppm should be
possible, 20 ppm is easy)
I might include a simple calibration mechanism (any reasonable amount
of logic is free in the Virtex-5 FPGA), but from where do I get a very
accurate reference frequency input of any value ?

Decades ago, the major TV stations kept the color subcarrier very
accurate (much better than 0.01 ppm), but that service has ben
abandoned. WWV needs a short-wave receiver, or at least a good
selective amplifier.
I am asking this smart group for some creative ideas. GPS ?
I indicate the frequency on a 9-digit display, so it would be
desirable to be able to guarantee better than 1 ppm (after calibration
for at least a few days. Temperature drift is not a big issue in a lab
instrument...)
Peter Alfke

Article: 128241
Subject: Re: Source of accurate frequency
From: MikeShepherd564@btinternet.com
Date: Fri, 18 Jan 2008 23:24:55 +0000
Links: << >>  << T >>  << A >>
>Decades ago, the major TV stations kept the color subcarrier very
>accurate (much better than 0.01 ppm), but that service has ben
>abandoned...

Some radio carriers are maintained to very high accuracy for use as a
frequency reference.  E.g. the BBC long wave transmission (previously
200kHz, now 198kHz) is controlled by a rubidium clock.  The audio
modulation is AM but there is also a low-bandwidth phase modulation
used to broadcast data to electricity meters (for control of overnight
load-shedding).  I don't know if that phase modulation would be a
problem for your application.

I'd guess that the signal is useable over all of western Europe. I
recall that when I stayed about 200km east of Moscow, I had forgotten
how to set my radio-controlled alarm clock to run only from the
internal crystal, but in the morning it had set itself from the 60kHz
transmitter in the UK.

Perhaps there is something similar in the USA.

http://en.wikipedia.org/wiki/Droitwich_transmitting_station
http://en.wikipedia.org/wiki/Radio_teleswitch

Mike

Article: 128242
Subject: Re: Source of accurate frequency
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Fri, 18 Jan 2008 23:27:08 +0000
Links: << >>  << T >>  << A >>
On Fri, 18 Jan 2008 14:49:46 -0800 (PST), 
Peter Alfke <peter@xilinx.com> wrote:


>I might include a simple calibration mechanism (any reasonable amount
>of logic is free in the Virtex-5 FPGA), but from where do I get a very
>accurate reference frequency input of any value ?

I don't know what happens in the USA, but here in the UK we have
a timecode broadcast service (MSF) that provides a very stable
60kHz carrier, modulated with some timecode stuff that keeps
clocks up-to-date.  Because the frequency is so low, coverage
is excellent and receivers very simple.  If you're happy to
do the calibration over many hours, that might be all you need.
An A-D converter and synchronous demodulation sounds like an
afternoon's work for you guys - you could use it as a demo
of a high-resolution delta-sigma A/D...  only a ferrite-rod
antenna needed.  Add a temperature sensor near your oscillator
and then you could, over time, calibrate its temperature 
coefficient, enabling you to keep it very accurate even if
you lose the time code signal.

I can easily imagine such a thing being subverted by nearby
CRT monitors or other sources of spurious-ness with components
close to 60kHz.  I still carry the scars of attempts to build 
readers for the TIRIS RF-ID tags, which worked at around 130kHz
and were pretty much inductively coupled.  That frequency was 
nicely at the second harmonic of the line scan rate of VGA 
monitors, which made the whole thing fail horribly if it 
was within a couple of yards of any cheap-and-nasty monitor.

Still, you could use synchronous demodulation to establish
a *very* narrow receiver bandwidth.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 128243
Subject: Re: Source of accurate frequency
From: gavin@allegro.com (Gavin Scott)
Date: Fri, 18 Jan 2008 23:49:36 -0000
Links: << >>  << T >>  << A >>
Jonathan Bromley <jonathan.bromley@mycompany.com> wrote:
> On Fri, 18 Jan 2008 14:49:46 -0800 (PST), 
> Peter Alfke <peter@xilinx.com> wrote:


> >I might include a simple calibration mechanism (any reasonable amount
> >of logic is free in the Virtex-5 FPGA), but from where do I get a very
> >accurate reference frequency input of any value ?

> I don't know what happens in the USA, but here in the UK we have
> a timecode broadcast service (MSF) that provides a very stable
> 60kHz carrier, modulated with some timecode stuff that keeps
> clocks up-to-date.

In the US the same service comes from WWVB in colorado:

   http://tf.nist.gov/stations/wwvb.htm

and clock devices that use it as a time reference are fairly common,
though these typically only preform a time sync once a day (typically
at night when propagation is better).  In fact I'm wearing a Casio
watch that's both solar powered and gets the time nightly from WWVB
so I never have to think about it and I always have sub-second accurate
time on my wrist.

But I think GPS is generally the right solution for this problem these
days.  There's a whole sub-genre of the GPS community (and devices from
manufacturers) that only care about when rather than where.  Once you
get out of the consumer stuff, receivers that output a very accurate
1 pps (pulse per second) are common, and you can get any level of 
exotic time keeping beyond this that you have the money to pay for :-)

G.

Article: 128244
Subject: Re: Source of accurate frequency
From: John McCaskill <jhmccaskill@gmail.com>
Date: Fri, 18 Jan 2008 15:51:11 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 18, 4:49 pm, Peter Alfke <pe...@xilinx.com> wrote:
> This is slightly off-topic:
> I have mentioned before that I am in the process of designing (and
> manufacturing in limited volume) a clock-generator box (1 Hz to 1.5
> GHz in 1 Hz increments). We debated some jitter issues...
> It's tough to get a very accurate reference xtal (2 ppm should be
> possible, 20 ppm is easy)
> I might include a simple calibration mechanism (any reasonable amount
> of logic is free in the Virtex-5 FPGA), but from where do I get a very
> accurate reference frequency input of any value ?
>
> Decades ago, the major TV stations kept the color subcarrier very
> accurate (much better than 0.01 ppm), but that service has ben
> abandoned. WWV needs a short-wave receiver, or at least a good
> selective amplifier.
> I am asking this smart group for some creative ideas. GPS ?
> I indicate the frequency on a 9-digit display, so it would be
> desirable to be able to guarantee better than 1 ppm (after calibration
> for at least a few days. Temperature drift is not a big issue in a lab
> instrument...)
> Peter Alfke

You can get reference clocks that are locked to GPS.  Here are a few
links:

http://ngn.symmetricom.com/products/primary_reference_sources/index.asp
http://www.trimble.com/tmg_thunderbolt.shtml
http://cgi.ebay.com/Thunderbolt-GPS-Disciplined-Clock-Trimble-Precise-clock_W0QQitemZ300191164048QQihZ020QQcategoryZ25399QQssPageNameZWDVWQQrdZ1QQcmdZViewItem


If you want to Google for more, search on "primary reference clock" or
"telcom primary base reference".

It is pretty common to find them with a 10MHz reference clock output,
IRIG time code, and a one PPS signal.  They discipline an internal
oscillator to the GPS clock, which is locked to an atomic clock. 10
MHz is also a common reference clock for frequency generators.



Regards,

John McCaskill
www.FasterTechnology.com

Article: 128245
Subject: Re: Source of accurate frequency
From: "comp.arch.fpga" <ksulimma@googlemail.com>
Date: Fri, 18 Jan 2008 16:05:10 -0800 (PST)
Links: << >>  << T >>  << A >>
On 18 Jan., 23:49, Peter Alfke <pe...@xilinx.com> wrote:
> This is slightly off-topic:
> I have mentioned before that I am in the process of designing (and
> manufacturing in limited volume) a clock-generator box (1 Hz to 1.5
> GHz in 1 Hz increments). We debated some jitter issues...
> It's tough to get a very accurate reference xtal (2 ppm should be
> possible, 20 ppm is easy)

Peter,

for our time to digital converters we use temperature compensated
oscillators  (TCXOs) with 1 ppm.
We pay a premium because we have custom frequencies cut for us, but
for standard frequencies
in higher quantities the price should be below 10$.
These devices are available from many manucatures in 7mm x 5mm SMD.

I recently saw a new TCXO that only has 100ppb temperature drift.

Below that you need OCXOs. The packages of these are a bit larger,
they are more expensive
and draw quite a lot of current (500mW to 5W). But you can get them
down to 5ppb.

Another option is to lock the clock to GPS. There are boxed solutions
for that available.

Have fun,

Kolja
www.cronologic.de



Article: 128246
Subject: Re: Source of accurate frequency
From: John_H <newsgroup@johnhandwork.com>
Date: Fri, 18 Jan 2008 17:13:07 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 18, 2:49=A0pm, Peter Alfke <pe...@xilinx.com> wrote:
> This is slightly off-topic:
> I have mentioned before that I am in the process of designing (and
> manufacturing in limited volume) a clock-generator box (1 Hz to 1.5
> GHz in 1 Hz increments). We debated some jitter issues...
> It's tough to get a very accurate reference xtal (2 ppm should be
> possible, 20 ppm is easy)
> I might include a simple calibration mechanism (any reasonable amount
> of logic is free in the Virtex-5 FPGA), but from where do I get a very
> accurate reference frequency input of any value ?
>
> Decades ago, the major TV stations kept the color subcarrier very
> accurate (much better than 0.01 ppm), but that service has ben
> abandoned. WWV needs a short-wave receiver, or at least a good
> selective amplifier.
> I am asking this smart group for some creative ideas. GPS ?
> I indicate the frequency on a 9-digit display, so it would be
> desirable to be able to guarantee better than 1 ppm (after calibration
> for at least a few days. Temperature drift is not a big issue in a lab
> instrument...)
> Peter Alfke

(I wish I didn't have to use google groups to access from work...)

Peter,

Your own austin has quite a background in stable timing so he can
probably provide some good lunchtime conversation.  The specs I've
seen on GPS timing references give 1 pulse per second outputs accurate
to within 100 ns.  Perhaps this accuracy is better than those many
years ago when I was actively looking at the specs but it gives you an
idea of the accuracies you'd need to work with.  GPS-trained frequency
sources use clean local oscillators to smooth out the uncertainty and
provide good accuracy under signal dropout conditions.  For very high
accuracy phase stuff, the Allan variance can come into play (again,
seek guidance from austin).

It may be that for measurement accuracy, the low Allan variance isn't
a necessity; I don't have an appreciation for the scale of the
problem, only the problem itself.  Heck - even rubidium oscillators
have close-in phase noise issues that are averaged out with external
help.  Just this week I've been demodulating jitter and watching cheap
oscillators changing frequencies on a whim, changing from one
relatively stable value to the next.

The jitter generator I produced a decade ago went with a small OCXO
from www.mti-milliren.com that had nice close-in phase noise
characteristics within a reasonably small package but it was still a
$50 instrumentation solution.

Both a GPS reference and an OCXO will probably be a chunk of the
device cost and consume more power than you'd want for batteries.

A quick discussion with an apps engineer from someplace like MTI might
get you more precise information that from the lovely engineers that
frequent this group.

Let us know when we can order one of your devices!
- John_H

Article: 128247
Subject: Re: How is FIFO implemented in FPGA and ASIC?
From: ghelbig@lycos.com
Date: Fri, 18 Jan 2008 17:49:29 -0800 (PST)
Links: << >>  << T >>  << A >>
On Jan 18, 11:42 am, Peter Alfke <pe...@xilinx.com> wrote:
> On Jan 18, 11:12 am, "jack.harv...@googlemail.com"
>
> <jack.harv...@googlemail.com> wrote:
> > > FIFOs get more complex than that. They can have different clocks for
> > > read and write, they can be large and require a dual port memory
> > > block, etc.
>
> > I reckon the question was about asynchronous FIFOs and possibly more
> > on the ASIC side, the Full and Empty signals need some care.
>
> Let me throw in my usual tutorial:
> If you have a dual-ported RAM, designing a synchronous (single-clock)
> FIFO is trivial.
> Designing an asynchronous (two independent clocks) FIFO faces the
> tricky issue of detecting Full and Empty. That means detecting the
> identity of two counters, which is best done with Gray-coded counters
> (which in turn makes it difficult to perform arithmetic on them).
>
> The leading edges of Full and Empty are unproblematic, since they are
> generated by the "proper" clock (Empty is generated by a read
> operation, and only the read side is interested in the Empty signal)
> The VERY TRICKY issues are the trailing edges of Full and Empty, since
> they are caused by the "wrong" clock, and thus require
> synchronization, and face the UGLY issue of metastability. Enough
> problems to give you some grey hair...
> Peter Alfke

Or just use "coregen".  The FIFO's generated by it work pretty darn
well.  ;)

G.

Article: 128248
Subject: Re: SRL16x2 in Virtex5
From: Ben Jackson <ben@ben.com>
Date: Fri, 18 Jan 2008 20:02:47 -0600
Links: << >>  << T >>  << A >>
On 2008-01-18, winscatt@googlemail.com <winscatt@googlemail.com> wrote:
>
> Does anyone know how to create them in one slice?

It might happen automatically when your design gets larger and packing
is needed for space.

-- 
Ben Jackson AD7GD
<ben@ben.com>
http://www.ben.com/

Article: 128249
Subject: Re: Source of accurate frequency
From: "Marty Ryba" <martin.ryba.nospam@verizon.net>
Date: Sat, 19 Jan 2008 04:02:10 GMT
Links: << >>  << T >>  << A >>

"Peter Alfke" <peter@xilinx.com> wrote in message 
news:76bcd2dd-330e-47c8-9813-00fea9a4d6d1@v67g2000hse.googlegroups.com...
> Decades ago, the major TV stations kept the color subcarrier very
> accurate (much better than 0.01 ppm), but that service has ben
> abandoned. WWV needs a short-wave receiver, or at least a good
> selective amplifier.
> I am asking this smart group for some creative ideas. GPS ?
> I indicate the frequency on a 9-digit display, so it would be
> desirable to be able to guarantee better than 1 ppm (after calibration
> for at least a few days. Temperature drift is not a big issue in a lab
> instrument...)

Other posters have mentioned the excellent GPS-based solutions available, 
and/or WWV(B) options. Here are two others:
1) The TV carriers are still often dead-on in frequency, as they are now 
locked to GPS.
2) The Loran-C system (100 kHz pulses) is being recapitalized with precise 
(GPS-locked) references as a backup to GPS against potential jamming.

I've been very happy with my Symmetricom frequency references; for a 
small/cheap solution, SigNav is now selling a GPS receiver based on the old 
Motorola Oncore series (interface compatible) that provides a precise 10MHz 
output. Trimble also sells something called the Micro-T with similar 
capability. Both I believe are in the ~$200 range for an OEM, but prices 
have been dropping. When locked to GPS, these jobbies can give you better 
than 10 ppb accuracy.

Marty 





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