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Hi all, In UG192 Xilinx proposes to use a MAX6043 Reference IC as a supply for the System Monitor section. But I couldn't take the System Monitor into operation, because the REF- Voltage reached only 2.0 V, although the supply current was roughly 7mA and therefore lower than the maximum value of 10m amps from the MAX6043. I solved this issue by replacing the MAX6043 by a MAX6033 (same package, lower precision, higher source current of 10 mA). Do you have any idea what's going wrong? EdArticle: 128126
The Quartus II handbook says that its Incremental compilation feature has the ability to iterate rapidly during the design and debugging stages. What exactly does this mean? Is this feature similar to Partial Reconfiguration offered by Xilinx?Article: 128127
Hi I have a very basic question. I have a design that has a clk and reset input. I know that I have to connect the clk and the reset inputs to the corresponding pins of the FPGA. But how can i now assert a reset signal for 8ns to my design to initialise some values? I dont think that I have a reset button ;). can I specify this maybe somehow in the UCF file? thanks for help! JeyArticle: 128128
"jey" <jey_1453@hotmail.com> wrote in message news:fml0qo$qnd$1@aioe.org... > Hi > > I have a very basic question. I have a design that has a clk and reset > input. I know that I have to connect the clk and the reset inputs to > the corresponding pins of the FPGA. But how can i now assert a reset > signal for 8ns to my design to initialise some values? I dont think that I > have a reset button ;). can I specify this maybe somehow in the UCF file? > > thanks for help! > Jey Hi Jey, No, you can't set this in the UCF. However, in most FPGAs, the state of the design is set to a known state on configuration, usually in the source code. At other times, you must have an input somewhere to initiate reset, correct? Also, I suggest this link. http://www.xilinx.com/support/documentation/white_papers/wp272.pdf HTH., Syms. p.s. It looks like the Xilinx techxclusives have been resurrected as white papers.Article: 128129
On Jan 16, 8:19=A0am, Anuja <thakkar.an...@gmail.com> wrote: > The Quartus II handbook says that its Incremental compilation feature > has the ability to iterate rapidly during the design and debugging > stages. What exactly does this mean? It means that your build times using Quartus will be quicker because it won't redo things that haven't changed. So instead of a 20 minute build, maybe it takes only 2. > Is this feature similar to Partial Reconfiguration offered by Xilinx? They are entirely different things. KJArticle: 128130
"jey" <jey_1453@hotmail.com> wrote in message news:fml3mi$3p0$1@aioe.org... >> No, you can't set this in the UCF. However, in most FPGAs, the state of >> the design is set to a known state on configuration, usually in the >> source code. At other times, you must have an input somewhere to initiate >> reset, correct? >> > > Thanks for your comments Symon. I have a design where a reset signal is > required for lets say some clock cycles to initialise the status of my > design. So I wonder how this can be done easy? Having an own reset module > is probably also a little bit akward, isnt it? > > cheers! Hi Jey, Does this reset only happen once? I.e. at configuration time? Cheers, Syms.Article: 128131
> No, you can't set this in the UCF. However, in most FPGAs, the state of the > design is set to a known state on configuration, usually in the source code. > At other times, you must have an input somewhere to initiate reset, correct? > Thanks for your comments Symon. I have a design where a reset signal is required for lets say some clock cycles to initialise the status of my design. So I wonder how this can be done easy? Having an own reset module is probably also a little bit akward, isnt it? cheers!Article: 128132
On Jan 16, 9:17 am, jey <jey_1...@hotmail.com> wrote: > > No, you can't set this in the UCF. However, in most FPGAs, the state of the > > design is set to a known state on configuration, usually in the source code. > > At other times, you must have an input somewhere to initiate reset, correct? > > Thanks for your comments Symon. I have a design where a reset signal is > required for lets say some clock cycles to initialise the status of my > design. So I wonder how this can be done easy? Having an own reset > module is probably also a little bit akward, isnt it? > > cheers! Jey; You could use a separate chip to reset the FPGA, such as a one-shot or a voltage supervisor that has a reset push button input. HTH -Dave PollumArticle: 128133
> You could use a separate chip to reset the FPGA, such as a one-shot or > a voltage supervisor that has a reset push button input. > HTH Thanks Dave, was some sort of hoping that there is any simpler way as that I could do it without an additonal hardware source. It there a way to do that with Chipscope? Maybe with a VIO core? Cheers,Article: 128134
In article <febb5ed1-1a6e-4298-9891-15e31dda1a77 @f47g2000hsd.googlegroups.com>, ksulimma@googlemail.com says... > I do not think that you need multipliers at all. > For a circular hough transform you process each point of your input > (possibly preprocessed for gradients, whatever) and draw a circle in > an output histogram. That's different approach. I'll need to think about it. My implementation uses gradients. That's why I'm not drawing circles. When I detect an edge, because I have a gradient in this point, I know in which direction is the center located. So I'm not drawing a circel. I suppouse formula (2) was missleading, I used it to suggest CORDIC approach. Still, I'll think about your approach, perhaps it's really good one for me as well, altough it reminds me of CORDIC because of many iterations involved. Good idea!Article: 128135
Yes! The tech-X's were scrubbed, and polished, and the more useful ones will re-appear in the coming months as white papers. If someone REALLY wants an old tech-X, email me, as we have retrieved the tape, and placed the old web pages on an internal server as a means of supporting folks.... (I know, it isn't like this shouldn't have been done in the first place, well, let us just say 'a lesson learned." Austin Symon wrote: > "jey" <jey_1453@hotmail.com> wrote in message news:fml0qo$qnd$1@aioe.org... >> Hi >> >> I have a very basic question. I have a design that has a clk and reset >> input. I know that I have to connect the clk and the reset inputs to >> the corresponding pins of the FPGA. But how can i now assert a reset >> signal for 8ns to my design to initialise some values? I dont think that I >> have a reset button ;). can I specify this maybe somehow in the UCF file? >> >> thanks for help! >> Jey > > Hi Jey, > > No, you can't set this in the UCF. However, in most FPGAs, the state of the > design is set to a known state on configuration, usually in the source code. > At other times, you must have an input somewhere to initiate reset, correct? > > Also, I suggest this link. > > http://www.xilinx.com/support/documentation/white_papers/wp272.pdf > > HTH., Syms. > > p.s. It looks like the Xilinx techxclusives have been resurrected as white > papers. > >Article: 128136
On Jan 16, 10:04=A0am, jey <jey_1...@hotmail.com> wrote: > > You could use a separate chip to reset the FPGA, such as a one-shot or > > a voltage supervisor that has a reset push button input. > > HTH > > Thanks Dave, was some sort of hoping that there is any simpler way as > that I could do it without an additonal hardware source. It there a way > to do that with Chipscope? Maybe with a VIO core? > > Cheers, Why not use a counter? The counter gets set to 0 at configuration, and counts up after that until it gets to whatever value you choose. The reset signal can be keyed from the count value. I usually like using an on-board power-on-reset chip, but if you can't do that, this is another way.Article: 128137
In article <slrnforhdc.857.ehliar-nospam@sabor.isy.liu.se>, ehliar- nospam@isy.liu.se says... > On 2008-01-15, Frater <mfraterBEZ@VELIKIHgmail.SLoVAcom> wrote: > > I could rewrite (1) like this: > > (2) > > x = R*cos(fi) > > y = R*sin(fi) > > How many values can fi take? For example, if you only need > 1024 values between 0 and 2*pi you can just use blockrams > in the FPGA to calculate cos(fi) and sin(fi) (e.g. you can > fit 1024 18-bit values into a single blockram in a Virtex-2) 'fi' is uknown to me, I can compute it with 'gx' & 'gy', since they are vector coordinates. So it would be: atan2(gy,gx).Article: 128138
In order not to spam, I'd like to thank everyone for your replies. It makes me feel good to see people who are interested to help with their knowledge. I'm still looking forward to all your replies, this is not the end :)Article: 128139
On 14 Jan., 22:24, lm317t <lm3...@gmail.com> wrote: > On Jan 14, 1:53 pm, filter...@desinformation.de wrote:> On 14 Jan., 19:02,= lm317t <lm3...@gmail.com> > > > > DSP is more for the "procedural" Software= Engineer. > > FPGA is more for the "parallel" Hardware/Logic design engineer. > > > And yes, you may get much more MACs(Multiplyaccumulate/second)/dollar > > in a FPGA, but at higher development effort. You dont't write a > > procedural signal processing routine then, you design a parallel > > running logic circuit and also need to care about timing. Although > > utilizing a modern DSP may also get difficult and you have to care > > much about pipelining. > > With the performance per dollar gains, there must be a way to use some > of this > parallelism in a higher level way that would be useful in DSP > applications. You may start a new Company and get into the Reconfigurable Computing / Reconfigurable Processor Array Market. Right now it misses broader acceptance, maybe also because the radical new "paradigm". Programming under this new "paradigm" is so different from how the average engineer has been taught (all his life) to solve technical problems. And it's not the "hierarchical/centralized" way of procedural thinking inherent to most of us. > > And with a DSP you get lot's of IP already on chip like DMA > > Controller, SDRAM interface etc. > > With a FPGA you need to do much more than reading the DMA doc and > > setting up it's registers to have a SDRAM/DMA interface making use of > > the FPGA's power, although there may be also some IP. > > How about the ones at opencores.org, I have only used one of their > cores, but it did its job. Yes, but as long the IP is not device specific (optimized) enough, it's feasibility may be questionable. > > I guess dedicated DSP chips will specialize to niches where they are > > surrounded by application specific mixed signal (like A/D) and > > specialized circuits (like FLASH) to give a low cost system on chip > > solution. > > FPGA's with DSP capabilities will take over the high performance more > > general purpose DSP maket like for example video processing when the > > extra effort in development pays off or IP and development tools > > enables it. > > I guess it really boils down to development tools and IP > availability. > There is just all this parallelism availible in an FPGA. =A0It would be > interesting to be able to use it. > I guess its just easier to buy a blackfin and use some of the free > libraries. Guess the easy way still is what DSP's about (today). And if you think about a software tool that would assist/automate the job of mapping some signal processing routine to a FPGA you'll encounter some difficulties, likely to get less significant with time and available computing power / software. runtime A already complicated C-Compiler for a DSP will be i guess at least 100 times faster than compiling some DSP code into a netlist, feeding this into vendor specific FPGA P&R tool and then checking/examining timing results and eventual adaptive iterating. Debugging/simulating showing similar difficulties as you'd have to do it with a general purpose logic simulators possibly using more computing power than a specific DSP simulator. algorithms / computing power High level DSP programming with FPGA targets is still missing widely accepted suitable languages, software algorithms and computing power and - most important - enough people willing to aim their work at this. And some minor Problem is that you are bound to the vendor's proprietary P&R tools and you'd need to embed them in that tool. For simpler DSP tasks and the "hardcore engineer" DSP with FPGA is already a everyday business.Article: 128140
jey wrote:
>
> Thanks for your comments Symon. I have a design where a reset signal is
> required for lets say some clock cycles to initialise the status of my
> design. So I wonder how this can be done easy? Having an own reset
> module is probably also a little bit akward, isnt it?
>
> cheers!
signal reset_shifter: std_logic_vector(5 downto 0) := "00000";
signal synchronous_reset: std_logic;
...
process(clk)
begin
if rising_edge(clk) then
reset_shifter <= reset_shifter(4 downto 0) & '1';
end if;
end process;
synchronous_reset <= not reset_shifter(4);
-- Better yet, replace the '1' above with the "locked" output signal of
the DLL that's generating the clock.
-Jeff
Article: 128141On Jan 16, 6:23 am, Dick <leeyei...@gmail.com> wrote: > Hi all, > > I'm a new guy in fpga. I need to implement a GMSK in altera fpga. I > plan to design a gaussian filter but I don't know how to do it. Can i > implement the gaussian filter by using FIR filter (with the function > of dsp builder)? > > Has anyone done this before? > If so, do you have any method to complete this task? I am really > struggling! I have only just started to learn the FPGA. > > Thank you. > > Dick Actually I did not use dsp builder but it is an FIR filter in fact. I did something like it for image processing purpose. I used usual adders and multipliers and a shift register so that at each shift I was getting a filter output(of course with delay). I don't have so much information about other tools. But someone will be helping you I guess. Enes.Article: 128142
On Jan 16, 7:14 am, bi...@wavenet.at wrote: > Hi all, > > In UG192 Xilinx proposes to use a MAX6043 Reference IC as a supply for > the System Monitor section. > But I couldn't take the System Monitor into operation, because the REF- > Voltage reached only 2.0 V, > although the supply current was roughly 7mA and therefore lower than > the maximum value of 10m amps from the MAX6043. > > I solved this issue by replacing the MAX6043 by a MAX6033 (same > package, lower precision, higher source current of 10 mA). > > Do you have any idea what's going wrong? > > Ed Did you look at the MAX6043 datasheet spec for input voltage? The 2.5V version requires 4.5V minimum input and the 3.3V version needs a minimum of 5.3V in... The MAX6033 dropout voltage is much lower, 2.7V min for 2.5V out.Article: 128143
On 16 Jan., 17:34, Gabor <ga...@alacron.com> wrote: > On Jan 16, 7:14 am, bi...@wavenet.at wrote: > > > Hi all, > > > In UG192 Xilinx proposes to use a MAX6043 Reference IC as a supply for > > the System Monitor section. > > But I couldn't take the System Monitor into operation, because the REF- > > Voltage reached only 2.0 V, > > although the supply current was roughly 7mA and therefore lower than > > the maximum value of 10m amps from the MAX6043. > > > I solved this issue by replacing the MAX6043 by a MAX6033 (same > > package, lower precision, higher source current of 10 mA). > > > Do you have any idea what's going wrong? > > > Ed > > Did you look at the MAX6043 datasheet spec for input voltage? The > 2.5V version requires 4.5V minimum input and the > 3.3V version needs a minimum of 5.3V in... > > The MAX6033 dropout voltage is much lower, 2.7V min for 2.5V out. Thank you for the hint, you solved my problem; After an optimization step I had overseen that I had replaced a +5.0V Voltage by 3.3 Volts. Thanks EdArticle: 128144
On Jan 16, 7:04 am, jey <jey_1...@hotmail.com> wrote: > > You could use a separate chip to reset the FPGA, such as a one-shot or > > a voltage supervisor that has a reset push button input. > > HTH > > Thanks Dave, was some sort of hoping that there is any simpler way as > that I could do it without an additonal hardware source. It there a way > to do that with Chipscope? Maybe with a VIO core? > > Cheers, I have seen a number of designs where unpredictable operation (particularly FPGA's not loading reliably) was traced to a sloppy reset circuit. You should use a reset circuit external to the FPGA. There are many makers of suitable devices, they are often listed as 'microprocessor supervisors'. They are typically in the half-dollar price range, and make it easy to generate a proper reset. G.Article: 128145
I am using Xilinx ISE 9.02. When I invoke the Timing Analyzer, go to "Analyze" on the pull-down menu, and then further select "Against User Specified Paths ... by Defining Endpoints" the tool just hangs - infinite loop. I had used this before but this problem suddenly emerged. Also, the other functions of Timing Analyzer work - just this one single function hangs. Has anyone else experienced this?Article: 128146
G. How one starts the configuration process is a different problem that how the device after configuration, starts up. The first problem is often caused by people "not trusting" the internal Power On Reset circuits in the FPGA: bad. We spend an immense amount of time making sure the POR circuits work under all sequences, and all ramps from 2us to 50ms. Mess with this, and then you have to do all the engineering for three power supplies to make it work at least as well as we already did. Not a smart move. Why would anyone want to re-invent this wheel? After the product has loaded the configuration, and has completed the start-up sequence, then everything is in a known state, so a reset isn't even required (it is implicit in the starting values you placed in the registers in your VHDL or verilog code, and was part of the loaded bitstream). If at some time later, you want to return to a 'known good state', which we will call "reset" for no better reason than it describes the action you want to take, then the applications note (or the old Tech X) details all kinds of ways to do this, that work. AustinArticle: 128147
On 16 Jan., 05:23, Dick <leeyei...@gmail.com> wrote: > Hi all, > > I'm a new guy in fpga. I need to implement a GMSK in altera fpga. I > plan to design a gaussian filter but I don't know how to do it. The nice property of the gauss function is, that if you fold more or less any function with itself multiple times the result converges to a gauss function. Therefore you can build a gauss filter by cascading multiple simple filters. For exampel four consecutive boxcar filters provide a good aproximation to a gauss filter. If you use a CIC-implementation of the boxcar you end up with an extremely efficient implementation. (No multipliers, four adders) Kolja SulimmaArticle: 128148
On 16 Jan., 16:16, Frater <mfraterREM...@BIGgmail.LETTERScom> wrote: > In article <febb5ed1-1a6e-4298-9891-15e31dda1a77 > @f47g2000hsd.googlegroups.com>, ksuli...@googlemail.com says... > > > I do not think that you need multipliers at all. > > For a circular hough transform you process each point of your input > > (possibly preprocessed for gradients, whatever) and draw a circle in > > an output histogram. > > That's different approach. I'll need to think about it. > > My implementation uses gradients. That's why I'm not drawing circles. > When I detect an edge, because I have a gradient in this point, I know > in which direction is the center located. So I'm not drawing a circel. > I suppouse formula (2) was missleading, I used it to suggest CORDIC > approach. > > Still, I'll think about your approach, perhaps it's really good one for > me as well, altough it reminds me of CORDIC because of many iterations > involved. Also, you can still use the gradient to draw only 2/8th of the circle. Note that drawing full circles provides a better immunity against different types of noise in the image. It will however definitely be slower than drawing only a single point. Note also that depending on resolution, occupancy and FPGA size it might be benefitial to implement a many-to-one approach instead of a one-to-many approach. To do this you implement a portion of the target bitmap in internal memory. For each block ram you have a processing element that can decide whether the input results in a hit in that RAM. Than you stream the input bitmap through your hardware. This results in linear extermal memory accesses and should therefore reach a higher throughput. I believe that you can do two pixels per hit BRAM per clock cycle for each BRAM that has a hit. Kolja SulimmaArticle: 128149
We are using a number of these boards but do not have the documentation for them and need to make some changes. Any information on where we could get the userguide would be welcomed. We've tried contacting a number of different vendors, etc. with no luck The markings on the board Insight VIRTEX-E REFERENCE BOARD PART # :_________ REV-B SERIAL # : __________ Both the part # and Serial # are blank It uses a Virtex XCV600E FPGA
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