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"Paul" <Paul@yahoo.co.uk> wrote in message news:fm5u18$jkp$1@aioe.org... > > > Waiting for core to be armed, slow or stopped clock Hi Paul, That's the problem. The clock is slow or stopped. HTH., Syms. p.s. Unrelated, but you should use numeric_std. http://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf Also, use rising_edge(clock), it's (marginally) better in simulation, but mostly it's less typing. ;-)Article: 127951
>It may be more useful if you mention the model of camera you're >using :) > >Regards, >Gabor > Agreed! SICK IVP Ranger C.Article: 127952
On 2008-01-11, Gary Pace <abc@xyz.com> wrote: > > Altera Quartus 2 7.2SP1 > EP2C50 design, about "70% full" > > Last year's rig : > AMD Athlon 64 X2 4800+ System, total compile time 13 minutes > > This year's rig : > Intel Core Quad 6600+ system, total compile time 10 minutes The Q6600 is multiplier locked, but at the bottom of the availabe front side bus speed. As a result, it's easy to overclock, and people have gotten 3GHz fairly easily. It'd be interesting to see how much effect that has on the build. If you want to go "legit" at those clock speeds there are Q6800 procs... -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 127953
On 2008-01-11, Goli <togoli@gmail.com> wrote: > > I have a particular SFP device, whose SCK signal (I2C clock) is > connected in this fashion. And this is causing the I2C state machine > inside the SFP device to go in freeze state. I can only get around > this problem by jack out jack in of SFP. You can probably unwedge it by sending enough SCK signals to be sure you're out of the current "byte" (so 8) and then sending STOP (maybe it will take multiple stops as well). That's a theory I've been meaning to test myself... -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 127954
Hi everybody, As Altera claims that Stratix III engineering samples are available today for some customers who subcribed to the early avaibility program, I am very interested in the 1st feedback from people who get already this chip (in term of avaibility, performance, power consumption...). Thx in advance for your answers.Article: 127955
Hi to all, I am confused about one thing that if I want to use LVDS in VirtexE, should I feed the Vcco of the desired bank with 2.5 V. Is it applicable if I feed the bank by 3.3 V? What about playing with the termination resistors? I couldn't find a satisfactory answer through searching but only XAPP232 Appendix A was a bit helping. Thanks in advance. EnesArticle: 127956
>...I want to use LVDS in VirtexE...2.5V...3.3V... The was a discussion in this group in December 2007: "Using LVDS_25 with 3.3V Vcco".Article: 127957
First of all, sorry for my English. What I want is: variable int : integer range 0 to 64:=0; begin process begin int := int + 1; end process; And the values: 0 1 2 3 4... 64 0 1 2 3 4 5.... But the real case is that : 0 1 2 3 4 ... 64 64 64 64 64 64 64 My best Regards PabloArticle: 127958
"Michael Laajanen" <michael_laajanen@yahoo.com> wrote in message news:5uoh19F1id6lfU1@mid.individual.net... > Why not just concatenate the files? > > /michael > Hi Michael, For the same reason that I don't concatenate all my VHDL files into one big whopper. HTH., Syms.Article: 127959
> That's the problem. The clock is slow or stopped. Hm yeah, maybe I have forgotten the clk then completly? I thought through the net connection to clk_BUFG of clk the clock connecntion is established? For simulation I used this code: process begin CLK <= '1'; wait for 10 ns; CLK <= '0'; wait for 10 ns; end process; But this is not sythesizable VHDL code, so I wonder how to generate a clk signal there? I am a little bit lost now, sorry! PaulArticle: 127960
On Fri, 11 Jan 2008 05:22:48 -0800 (PST),
Pablo <pbantunez@gmail.com> wrote:
hi Pablo
>variable int : integer range 0 to 64:=0;
>begin
>process
> begin
>int := int + 1;
>end process;
>
>
>And the values: 0 1 2 3 4... 64 0 1 2 3 4 5....
You want wrap-around at some upper limit.
> But the real case is that : 0 1 2 3 4 ... 64 64 64 64 64 64 64
Really? That seems strange. You should get a runtime error when
you try to increment from 64 to 65, because 65 is outside the range of
the variable.
You can easily do it...
if int < LIMIT then
int := int + 1;
else
int := 0;
end if;
However, if your limit is "all ones" in a binary number
(e.g. 31, 63, 127, 255) it may be simpler to use UNSIGNED
data instead of integer data. UNSIGNED values are a
vector of std_logic bits, and arithmetic will wrap around
from (2**N)-1 to 0.
You may get more help on comp.lang.vhdl.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 127961hi, i need to 100BASET connection with a PC using xilinx spatan-3E board and lan83c185 chip.i need a bare system just to send some predefined UDP packets without using a Soft processor . if any one have some app notes on lan83c185 is helpful. thanks dilanArticle: 127962
Hi We are looking for an FPGA evaluation board to get a simple RISC processor running. It should have at least 32K slices and I was thinking of buying a Xilinx Virtex board. As synthesis tool we would like to use XST 9.2. Anyone has got a hint where I could get here a good and cheap board ;). We are using it at university so also some deals for students would come into question! many thanks, pArticle: 127963
> We are looking for an FPGA evaluation board with > 32K slices. http://www.xilinx.com/products/boards/ml410/index.html This sounds not too bad, according to http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex4/product_table.htm this FPGA XC4VFX60 has got 56,880 logic cells. Should be fine for our purposes I assume. Costs around 3000$, any other products in this price range?Article: 127964
Hello, I am interested in looking at the resource utilization of a design I am working on broken down based on the RTL hierarchy of the design. I am using a Virtex-II Pro part. I have seen in the past where you can do this using Floorplanner, however when I attempt to use Floorplanner on my design I get the following error.... "The design contains macros with RPM grid coordinates which are not supported by Floorplanner" After digging a little in Xilinx's Answer Database, I don't believe that there is a way around this based on this answer.... http://www.xilinx.com/support/answers/19355.htm Specifically, this line.... NOTE: These solutions will not work if any of the cores have hardware multipliers because the RPM_GRID system must be used with multipliers. I use hardware multipliers in my design. Does anybody have any ideas as to how I could get my design in floorplanner, or another option for viewing the broken down resource utilization? Thanks for all the help. Regards, JohnArticle: 127965
On Jan 11, 8:56 am, Paul <P...@yahoo.co.uk> wrote: > > That's the problem. The clock is slow or stopped. > > Hm yeah, maybe I have forgotten the clk then completly? I thought > through the net connection to clk_BUFG of clk the clock connecntion > is established? > > For simulation I used this code: > > process > begin > CLK <= '1'; wait for 10 ns; > CLK <= '0'; wait for 10 ns; > end process; > > But this is not sythesizable VHDL code, so I wonder how to generate a > clk signal there? > > I am a little bit lost now, sorry! > > Paul That's probably your problem right there. I don't use the ISE GUI at all - I run everything from the command line, so I can't help with that. I manually instantiate the ICON and ILA modules within my design and copy the *.edn files into my build directory. Your ILA needs a clock signal to sample the state of the trigger ports. Are you using an eval board? Doesn't it have an oscillator on it?Article: 127966
> That's probably your problem right there. I don't use the ISE GUI at > all - I run everything from the command line, so I can't help with > that. I manually instantiate the ICON and ILA modules within my > design and copy the *.edn files into my build directory. > > Your ILA needs a clock signal to sample the state of the trigger > ports. Are you using an eval board? Doesn't it have an oscillator on > it? Alright, I use the core inserter for this task but at the end of day both should work properly. When I select the net for the clock I can use either clk_BYFGP with Base Type BUFGP or clk with base type port. If I try using BUFGP nothing happens as stated in my first post. If I use clk and run synthesis I get the following error message: NgdBuild:924 - input pad net 'clk' is driving non-buffer primitives Although a very basic question, but where is the input port for my clk coming from. DO I need to write my own oszilator? Or does the FPGA automatically detect the clk signal and know what to do? Cheers,Article: 127967
On Jan 11, 9:20 am, Paul <P...@yahoo.co.uk> wrote: <snip> > > Your ILA needs a clock signal to sample the state of the trigger > > ports. Are you using an eval board? Doesn't it have an oscillator on > > it? > > Alright, I use the core inserter for this task but at the end of day > both should work properly. When I select the net for the clock I can > use either clk_BYFGP with Base Type BUFGP or clk with base type port. > If I try using BUFGP nothing happens as stated in my first post. If I > use clk and run synthesis I get the following error message: > > NgdBuild:924 - input pad net 'clk' is driving non-buffer primitives > > Although a very basic question, but where is the input port for my clk > coming from. DO I need to write my own oszilator? Or does the FPGA > automatically detect the clk signal and know what to do? > > Cheers, The FPGA does not automatically detect the clock, and you do not really want to try to generate an oscillator internal to the FPGA in most cases. What board are you using? It should have one or more oscillators on it that go to the FPGA. The documentation should tell you what pin each clock signal goes to. You use the UCF file to associate the pins with the signal names in top level of your FPGA design. Choose one of the available clocks, buffer it with a BUFG, and use the output of the BUFG as the clock signal to your logic. Regards, John McCaskill www.FasterTechnology.comArticle: 127968
On Jan 11, 7:02=A0am, paragon.j...@gmail.com wrote: > Hello, > > I am interested in looking at the resource utilization of a design I > am working on broken down based on the RTL hierarchy of the design. =A0I > am using a Virtex-II Pro part. =A0I have seen in the past where you can > do this using Floorplanner, however when I attempt to use Floorplanner > on my design I get the following error.... > > "The design contains macros with RPM grid coordinates which are not > supported by Floorplanner" > > After digging a little in Xilinx's Answer Database, I don't believe > that there is a way around this based on this answer.... > > http://www.xilinx.com/support/answers/19355.htm > > Specifically, this line.... > NOTE: These solutions will not work if any of the cores have hardware > multipliers because the RPM_GRID system must be used with multipliers. > > I use hardware multipliers in my design. > > Does anybody have any ideas as to how I could get my design in > floorplanner, or another option for viewing the broken down resource > utilization? > > Thanks for all the help. > > Regards, > John I use a program called Adept for this. http://home.comcast.net/~jimwu88/tools/adept/Article: 127969
Hi, I'm a new synplify pro user. This tool seems to be much powerfull than XST for apply timing constraints. But there is something I don't understand : in the synplify pro report, I can see all my timing constraints, and design meets timing requirements. After that, using Synplify pro interface, I launch ISE Place & Route.. When P&R finishs, I look at the report, and I can see all my timing constraints, but for the most importants, I can read : N/A. ISE tells me it can't apply my constraints.. I will understand if it tells me timing were not met, but why can't it apply them ? is there a problem between synplify pro and ISE ? why synplify can't pass my constraints to ISE ? Thank you by advance, Best regards, Michel.Article: 127970
Goli, What is the Vcco doing on the bank? Can you post a scope picture for me? Trace 1 = Vcco, Trace 2 = IO pin. Or, send the .jpg picture of the scope shot to me directly (email is good). Since every IO pin has an intrinsic diode to Vcco from the IO pin (it is the diode that is part of the pmos pullup stack) as Vcco comes up, the IO pin will be pulling down through the forward biased IO diode to ground. Other than that, the IO is tristate all through the power ON (any sequence),cleanout, and configure until DONE goes high, when your design then decides what to do with the pin. If the IO pin goes low AFTER DONE, then it is under your control (you are doing this). So, where in this sequence is the pin pulling low? AustinArticle: 127971
Philipp, Have you contacted the Xilinx University Program? We give away devices for classes and students, all you need to do is buy the boards. $299 http://www.digilentinc.com/Products/Detail.cfm?Nav1=Products&Nav2=Programmable&Prod=XUPV2P XUP: http://www.xilinx.com/univ/index.htm We also have many other university boards that we may recommend, Austin Philipp wrote: > Hi > > We are looking for an FPGA evaluation board > to get a simple RISC processor running. It > should have at least 32K slices and I was thinking > of buying a Xilinx Virtex board. As synthesis tool > we would like to use XST 9.2. Anyone has got a hint > where I could get here a good and cheap board ;). We > are using it at university so also some deals for students > would come into question! > > many thanks, > pArticle: 127972
On Jan 10, 10:58=A0pm, Enes ERDIN <eneser...@yahoo.com> wrote: > Thank you for your answers. Sorry I have to be more precise. I am > trying to implement the SpaceWire protocol. Unfortunately I have to > use this link through a parallel cable for testing purposes (test > setup is in that way and the cable is about 4 meters wihich includes > also some D-sub connectors on it) So I am trying at such frequency. By > the way when I implement two links on the same board and interconnect > them they operate quite well but when I connect two different boards > the link crashes. > > > What constitutes a glitch? > > Actually I have no idea as I said signal levels seem good when I > observe in ossciloscope. Dagnabbit. "When I look through oscilloscope I see a good signal however on Chipscope I see glitches." What the heck are you observing that makes you think your link isn't working? I repeat: What constitites a "glitch" in your problem statement? > > How are you sourcing the clock and data? =A0(using DDR flops, output reg= isters, combinatorial outputs) > > Receiver clock is implemented through combinatorial logic (Data Strobe > encoding). Transmitter clock is output registered. So the tx clock frequency is actually half the bit rate and the clock and data are both registered outputs from the same system clock? Did you verify these registers in the IOBs? > > What edge are you using to clock the input data? > > For the receiver I use double edge If your clock and data are both generated from the same master clock (as opposed to the TX clock generated from the falling edge and TX data generated from the rising edge of that master clock) then your timing constraints need to make sure there's a slightly negative hold time to avoid a hold violation. Your UCF information from the other post doesn't specify the timing constraints I asked about. > > Do you have input timing constraints? > > I have written the input constraints to the ucf file. Please communicate these timing constraints for the Receive clock and data. > > Are you using a DCM? =A0If so, are you specifying SYSTEM_SYNCHRONOUS or = SOURCE_SYNCHRONOUS? > > I am not using a DCM Thanks for that info. > And an attached question : will it be a matter if I use VirtexE board > supplied with (the bank is supplied) 3.3 V and Virtex4 is supplied > with 2.5 V? > > Thanks for your invaluable help. The Virtex-E is specified for 2.5V drive. I expect your pad report tells you 2.5V Vcco is expected for that bank. It's not too much of an issue for the output LVDS, however, since the output networks are used to generate proper LVDS signal levels. You *are* using the recommended transmit termination scheme in the Virtex-E Functional Description "Design Considerations" section, aren't you? These values are ideally tweaked to give a different voltage swing but slightly overdriving your LVDS with a slightly higher common mode voltage is probably okay. Next time please design with the Vcco that the tools and data sheets recommend. In the end, I wouldn't be surprised if your entire problem boils down to setup/hold violations at your input registers. Are you using DDR input registers or implementing two registers that don't end up in the IOB? - John_HArticle: 127973
On Jan 11, 10:49 am, Barry <barry...@gmail.com> wrote: > On Jan 11, 7:02 am, paragon.j...@gmail.com wrote: > > > > > Hello, > > > I am interested in looking at the resource utilization of a design I > > am working on broken down based on the RTL hierarchy of the design. I > > am using a Virtex-II Pro part. I have seen in the past where you can > > do this using Floorplanner, however when I attempt to use Floorplanner > > on my design I get the following error.... > > > "The design contains macros with RPM grid coordinates which are not > > supported by Floorplanner" > > > After digging a little in Xilinx's Answer Database, I don't believe > > that there is a way around this based on this answer.... > > >http://www.xilinx.com/support/answers/19355.htm > > > Specifically, this line.... > > NOTE: These solutions will not work if any of the cores have hardware > > multipliers because the RPM_GRID system must be used with multipliers. > > > I use hardware multipliers in my design. > > > Does anybody have any ideas as to how I could get my design in > > floorplanner, or another option for viewing the broken down resource > > utilization? > > > Thanks for all the help. > > > Regards, > > John > > I use a program called Adept for this.http://home.comcast.net/~jimwu88/tools/adept/ Thank looks promising, except I am using ISE 8.2 and it looks like Adept only supports 9.1 and 9.2. Any other ideas? Thanks.Article: 127974
> But the real case is that : 0 1 2 3 4 ... 64 64 64 64 64 64 64
You can easily do it...
if int < LIMIT then
int := int + 1;
else
int := 0;
end if;
Shouldn't this be:
if int < LIMIT then
int := int + 1;
else
int := LIMIT ;
end if;
BTW, I used something very similar to age items in a queue.
Regards,
G.
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