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On Jan 10, 12:11 pm, rickman <gnu...@gmail.com> wrote: > On Jan 10, 5:20 am, "Maki" <veselic...@eunet.yu> wrote: > > > > > <snip> > > > >. With the XP device, once > > > the flash is reprogrammed by the system via JTAG, I believe it has to > > > be told to reboot the SRAM from the flash which I don't have a simple > > > way of doing. I may have to share a incoming board pin between a > > > board disable control and the PROGRAM_N control.. if this is what is > > > required to reboot the device. > > > > Anyone here know for sure that toggling the PROGRAM_N pin is needed > > > and sufficient to reload the SRAM from the Flash? > > > Yes, it is neded and sufficient. I'm working with an XP device based board > > as we speak. > > > Best regards, > > Maki > > Thanks. I guess I am just a bit unsure, not having worked with these > parts before. The board disable signal is high for disable. In that > state my board should be non-functional in all ways. When the board > is to be used or programmed, that line will be low. If I invert the > disable signal and use it to drive PROGRAM_N, it will hold the XP in > program mode when the board is disabled. Will this cause any > problems? I know these parts are similar to the Xilinx parts and they > would sit in the initialize state clearing memory continuously until > PROGRAM_N is released. I can't find any info on what happens with the > Lattice parts. They do list the power consumption in initialization > which is around 100 mA combined and over twice as high as in > "Standby". But they don't define exactly either of these > measurements. I assume the initialization current is about the same > while holding the PROGRAM_N pin low as it is after you release it > until the DONE pin goes high. I also assume the Standby power is a > configured part with no activity. > > I'll see what their support says. They seem to be pretty good at > getting back in a day or so. I'd be very surprised if the parts drew as much power while PROGRAM_N is held low as they do while initializing until DONE goes high. The main reason for the extra current is the internal flash memory reading. Also be aware that the pullups may be active on some pins until the part is programmed. I know this is the case for ECP parts, and that the "weak" pullup current is higher in these parts than in the Xilinx parts I've used in the past.Article: 127926
Thuy Pham <thuyp@xilinx.com> wrote: >If you are looking to buy components I have a friend works in class-ic >and she will give you a good price Are you saying this on behalf of Xilinx?Article: 127927
Hi
I have a simple VHDL counter modul that I wanna debug with Chipscope 7.1
on a Virtex II board:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity top is
port
(
clk : in std_logic := ‘0’;
cnt : out std_logic_vector(3 downto 0)
);
end top;
architecture behave of top is
signal counter : std_logic_vector(31 downto 0) := (others => ‘0’);
begin
process(clk)
begin
if ( clk’event and clk = ‘1’ ) then
counter <= counter + 1;
end if;
end process;
cnt <= counter(31 downto 28);
end behave;
I synthesize this module with XST 7.1 and then I generate an ICON with
Chipscope Generator. The I generate an ILA with TRIG0 where the trigger
width is 8, match type: extended and the number of match units is 1.
Features like Enable Trigger Sequences, Storage Qualification and tigger
output port have been disabled. Data depth is 512 samples and the data
width is 16 bits whereas Data is not same as trigger!
Then I add a new chipscope.cdc source to my ISE project and double click
it to start the Chipscope Core Inserter. JTAG Clock BUFG Insertion is
enabled. In the Net connections I connect clk_BUFG to the clock signal,
trigger signals are then the lower 8 bits of the counter, i.e.
counter[7..0] and the data signals are the lower 16 bits of the counter,
i.e. counter[15..0]. In the process properties I tell XST to use the
JTAG clock as FPGA Start-Up clock.I start then the Implemeent design
process and i can see that Chipscope starts the inserterlauncher.
I just get one warning:
Timing:2666 - Constraint ignored: Path "TS_U_D_path" TIG;
I use then the Chipscope Analyser to download the generated bit file on
the FPGA. The analyzer tells me that one 1 core unit was found in the
JTAG device Chain. I click then Trigger Immediate so some data should be
returned immerdiatelly. Unfortunately I can just see a device 1 Unit 0:
Waiting for core to be armed, slow or stopped clock in the status and in
the waveform it tells me "waiting for upload". After 2 Minutes I hit the
stop button and it says: ERROR - device 1 Unit 0: Upload command failed
- no new data.
Anyone an idea where the problem could be? Would be very thankful for
some feedback
Article: 127928On Jan 10, 2:13=A0pm, "Colin Hankins" <Colin.Hank...@touit.com> wrote: > Switching to Precision certainly did the trick. I've also alerted Lattice > about the issue with Synplify and they've been very responsive. So hopeful= ly > it will soon be resolved. Although, I think I might just stick with > Precision. > > > > "Maki" <veselic...@eunet.yu> wrote in messagenews:fm0imd$pe$1@aioe.org... > > >I am unable to infer a True Dual Port RAM in ispLEVER using VHDL. I'm > >> targetting the Lattice ECP2M using Synplify. Even the provided example > >> located in > >> isptools7_0\examples\fpga\latticexp2\memory\inferencing\true_dual_port\= vhdl=AD\true_dual_port.vhd > >> does not synthesize successfully. Has anyone else had any better luck a= t > >> this? > > > It works fine with Precision. I too had the same problem with Synplify v= er > > 8.1 IIRC. It appears that template is all wrong for Synplify. Try anothe= r > > one from Sunplify user guide... > > > Happy inferencing =A0:) > > >> Thanks, > >> Colin > > > Maki.- Hide quoted text - > > - Show quoted text - How does everyont simulate True Dual Ports with VHDL? I've got synplicity working fine with simple behavioral code but it has two seperate processes accessing the same memory array (one for port A, another for port B). My simulator can't handle this situation. Do you need to work around this problem by writing a seperate, non- synthesizable version of the dual port just for simulation? Just curious... PeteArticle: 127929
Paul wrote: > Hi > > I have a simple VHDL counter modul that I wanna debug with Chipscope 7.1 > on a Virtex II board: > > ... > I use then the Chipscope Analyser to download the generated bit file on > the FPGA. The analyzer tells me that one 1 core unit was found in the > JTAG device Chain. I click then Trigger Immediate so some data should be > returned immerdiatelly. Unfortunately I can just see a device 1 Unit 0: > Waiting for core to be armed, slow or stopped clock in the status and in > the waveform it tells me "waiting for upload". After 2 Minutes I hit the > stop button and it says: ERROR - device 1 Unit 0: Upload command failed > - no new data. > > Anyone an idea where the problem could be? Would be very thankful for > some feedback Do you have a clock, and what is the frequency? Have you checked that the outputs are running? That is a big counter, so even at 50MHz, cnt[0] should be toggling once every 5 seconds or so (if I didn't mess up my quick calculations). Even if you don't have an oscilloscope, you can see that with a plain voltmeter.Article: 127930
Hi, I am trying to connect a Virtex4 and a VirtexE FPGA by LVDS signals. When I look through oscilloscope I see a good signal however on Chipscope I see glitches. I am trynig to operate at about 1 MHz. For VirtexE side there is a 100 ohm termination resistor between differential lines at the receiver and there are 160 ohms and a 140 ohm at the transmitter sides and the connecting cable is matched 100 ohm cable (although it is a very short cable at about 25 cm = 10 inches). For Virtex4 I use Diff_term attribute at the receiver that's all. What can be the problem about this situation. I am stuck. Thanks in advance. Enes.Article: 127931
<snip> >Do you need to work around this problem by writing a seperate, non- >synthesizable version of the dual port just for simulation? > >Just curious... > >Pete IIRC I used template for dpram with shared variables for XST and for simulation. But this template for Precision is strange... Best regards, Maki.Article: 127932
On Jan 10, 11:36=A0am, MikeShepherd...@btinternet.com wrote: > Thuy Pham <th...@xilinx.com> wrote: > >If you are looking to buy components I have a friend works in class-ic > >and she will give you a good price > > Are you saying this on behalf of Xilinx? I checked this out: Thuy Pham is indeed a Xilinx employee here in San Jose, and he used his Xilinx e-mail address on this newsgroup - I am sure for the first and last time :-( He has a friend who works at a company called class-ic.com They seem to have a big inventory of integrated circuits. I told Thuy to be more careful in the future. When anybody sends an e- mail from a Xilinx address into a public newsgroup, he is inevitably considered some kind of a Xilinx spokesman, even if in rality he is not (and neither am I). I have straddled this precarious situation thousands of times, but he had never done it before. So this was his innocent private communication, just trying to be helpful. Peter Alfke, XilinxArticle: 127933
Anybody heard of a recent benchmark comparing both Intel and AMD high- end processors regarding their Place-and-Route (PAR) performance? All I can find is a 2005 intervention here stating that AMD exceeded Intel, probably due to Intel's huge pipeline which is not suited for non-homogeneous processing such as PAR: http://www.fpga-faq.com/archives/89325.html#89336 With Intel apparently taking the lead for general purpose processing with its 45nm technology, is such statement still true? I'm basically looking for the best workstation honest money can buy to run Xilinx's PAR tool. Any suggestions? Thanks.Article: 127934
On Jan 10, 1:14=A0pm, Enes ERDIN <eneser...@yahoo.com> wrote: > Hi, > Enes, this is not an answer but a question: Why do you plan to use LVDS for a short 1 MHz connection? Any single-ended (non-differential) standard would do this "hands- down". I do not see any inherent problem with LVDS, but why use two pins when one pin is enough? Peter Alfke, Xilinx Applications > I am trying to connect a Virtex4 and a VirtexE FPGA by LVDS signals. > When I look through oscilloscope I see a good signal however on > Chipscope I see glitches. I am trynig to operate at about 1 MHz. For > VirtexE side there is a 100 ohm termination resistor between > differential lines at the receiver and there are 160 ohms and a 140 > ohm at the transmitter sides and the connecting cable is matched 100 > ohm cable (although it is a very short cable at about 25 cm =3D 10 > inches). For Virtex4 I use Diff_term attribute at the receiver that's > all. What can be the problem about this situation. I am stuck. > > Thanks in advance. > > Enes.Article: 127935
Hello, I am interested in looking at the breakdown of resource utilization for a design I have done in a Virtex-II Pro (in ISE 8.2), broken down on based on the design hierarchy. I've seen in the past that you can do this using Floorplanner, however when I attempt to, I get the following message... "Design contains macros with RPM grid coordinates which are not supported by Floorplanner." I've looked into the error and based on the following Xilinx Answer [I realize it is 6.2 but I assume the essence still applies] (http:// www.xilinx.com/support/answers/19355.htm), I believe that I can't get around it because of the following line (I use hardware multipliers)... NOTE: These solutions will not work if any of the cores have hardware multipliers because the RPM_GRID system must be used with multipliers. So therefore.... Does anybody know a way to either: a) use Floorplanner on my design, or b) get the information I am interested in from another Xilinx tool? Thanks in advance for all your help! Regards, JohnArticle: 127936
Louis wrote: > Anybody heard of a recent benchmark comparing both Intel and AMD high- > end processors regarding their Place-and-Route (PAR) performance? All > I can find is a 2005 intervention here stating that AMD exceeded > Intel, probably due to Intel's huge pipeline which is not suited for > non-homogeneous processing such as PAR: > > http://www.fpga-faq.com/archives/89325.html#89336 > > With Intel apparently taking the lead for general purpose processing > with its 45nm technology, is such statement still true? I'm basically > looking for the best workstation honest money can buy to run Xilinx's > PAR tool. Any suggestions? Thanks. I think you'll find that Intel's Core 2 generation does a lot better than previous one, because they have better memory latency and shorter pipelines than the P4, which just plain sucked. I don't have a recent benchmark, but I can tell you what I've seen in the past (early 2006 timeframe): - multicore doesn't matter (unless you try to do other things while running.) Most current FPGA tools are still single-threaded. - cache size matters more than anything. Going from a 512K to a 1024K cache cut the synthesis time by two-thirds. Intel probably has an advantage here, because they have shared caches; remember to only count the cache available to a single core. - memory size and memory latency matters too. Get lots of fast RAM. - the OS will manage memory better if it's a 64 bit OS. Running on a 64-bit Linux seemed to run about 20-25% faster than 32-bit WinXP. -hpaArticle: 127937
On Jan 9, 11:28=A0am, Peter Alfke <pe...@xilinx.com> wrote: > Glen, > I have been thinking about this for decades, but I now consider it > hopeless. > If you believe the results of my statistical measurements, then you > realize that the capture window for a metastable delay of more than 2 > ns is not picoseconds, but a fraction of a femtosecond. > There is no way to keep the circuitry stable within such a narrow > timing window. And if you could, how do you derive any quantitative > data from it? > I remain convinced that the randomly asynchronous testing approach is > the only one that gives us reliable results. > Peter Alfke > Let me give some quantitative information: At a 300 MHz clock rate and roughly 50 MHz data rate, the Virtex-2Pro flip-flop exhibits an extra delay of 1.5 ns once every second. What is the metastable capture window? The data changes once every 10 ns ( 50 MHz has a 20 ns period, with 2 changes per period) Within a second, the 300 MHz oscillator puts 300 million transitions into this half period, and only one of them causes a metastable delay of 1.5 ns 10 ns divided by 300 million =3D 0.03 femtosecond =3D 33 times 10 exp -18 seconds. In other words, the capture window is extremely small... Peter AlfkeArticle: 127938
Goli is correct. "Goli" <togoli@gmail.com> wrote in message news:110b87e9-a130-444a-9d9f-3a06654d7c6e@l1g2000hsa.googlegroups.com... > > ISE right now does not support multiple ucf files. But I think it is > going to be supported form ISE10.1 that is what I had heard, am not > sure though. > > -- > GoliArticle: 127939
Enes ERDIN wrote: > Hi, > > I am trying to connect a Virtex4 and a VirtexE FPGA by LVDS signals. > When I look through oscilloscope I see a good signal however on > Chipscope I see glitches. I am trynig to operate at about 1 MHz. For > VirtexE side there is a 100 ohm termination resistor between > differential lines at the receiver and there are 160 ohms and a 140 > ohm at the transmitter sides and the connecting cable is matched 100 > ohm cable (although it is a very short cable at about 25 cm = 10 > inches). For Virtex4 I use Diff_term attribute at the receiver that's > all. What can be the problem about this situation. I am stuck. > > Thanks in advance. > > Enes. What constitutes a glitch? How are you sourcing the clock and data? (using DDR flops, output registers, combinatorial outputs) What edge are you using to clock the input data? Do you have input timing constraints? Are you using a DCM? If so, are you specifying SYSTEM_SYNCHRONOUS or SOURCE_SYNCHRONOUS? I have a feeling the signal integrity is good, just an issue of system-level implementation. - John_HArticle: 127940
"Louis" <louis.dupont@gmail.com> wrote in message news:c04a5301-f9fc-4031-ade1-70f8050785ee@q39g2000hsf.googlegroups.com... > Anybody heard of a recent benchmark comparing both Intel and AMD high- > end processors regarding their Place-and-Route (PAR) performance? All > I can find is a 2005 intervention here stating that AMD exceeded > Intel, probably due to Intel's huge pipeline which is not suited for > non-homogeneous processing such as PAR: > > http://www.fpga-faq.com/archives/89325.html#89336 > > With Intel apparently taking the lead for general purpose processing > with its 45nm technology, is such statement still true? I'm basically > looking for the best workstation honest money can buy to run Xilinx's > PAR tool. Any suggestions? Thanks. I can only give one example : Altera Quartus 2 7.2SP1 EP2C50 design, about "70% full" Last year's rig : AMD Athlon 64 X2 4800+ System, total compile time 13 minutes This year's rig : Intel Core Quad 6600+ system, total compile time 10 minutes Both systems have 4GB DDR2 RAM at max speeds (CPU max speed for AMD, P35 northbridge max speed for Intel) Both systems using WD Raptor drives Both systems using /3GB switch in boot.ini The difference is almost entirely in the placement. Quartus has a multi-processor option, and reports an average of 1.5 processors out of a maximum of 2 for the AMD, and 1.7 out of a maximum of 4 for the Intel I wonder how the AMD Phenom quad core doo-dah would perform ? I am assuming it accesses main memory via a dedicated 128-bit port like the dual core one. I think the Intel goes via the northbridge, and uses "interleaved dual channel" (meaning what I don't know). Sounds like a better channel to main memory.Article: 127941
On 10 Jan., 19:26, "davide" <dav...@xilinx.com> wrote: > "Antti" <Antti.Luk...@googlemail.com> wrote in message > > news:c052dfab-e332-4842-9283-cd691a34f928@i72g2000hsd.googlegroups.com... > > > > > > > Hi > > > it seems that Xilinx has promised to publisch (finally!) the > > programming APIs for > > cable IV and platform USB cable. > > > this is not official but the universal scan last version includes > > notes that they add support for Cable IV and platform USB in JANUARY > > 2008; after Xilinx publishes the docs. > > > so it can be derived that Xilinx has made promises to publish the APIs > > in 2007 > > > hm, maybe they already online at xilinx.com ? > > > any more info anyone? > > > Antti Lukats > > Antti, > > I found this post very surprising as I have worked with the engineering > group that designs the cables. =A0They have always had a stead-fast and > adamant position regarding releasing the API (which is not to). =A0After > reading this post I inquired and just heard back. =A0As expected, there ar= e no > immediate plans to release. =A0It is also my understanding that further > discussions regarding this will not happen any time soon. =A0Sorry. > > -David- Zitierten Text ausblenden - > > - Zitierten Text anzeigen - hm this means that the company who makes "universal scan" tool was just lying or had false information! :( too bad. they claimed to add support for cableIV/USB in jan 2008, __AFTER__ xilinx release of the API AnttiArticle: 127942
Hi, I have a design which has Virtex5 LX30T. On a particular IO, I have a external pull up of 4.7K, which connects to another device. I notice that at powerup that IO is driven down for 30msec before it gets tristated (and hence assumes state of logic high because of external pull up) I have filed the webcase for the same and awaiting the response. Does anyone has encountered any such problem. This behavior makes the board design little tricky, because unintentional toggling on the IOs may cause some devices on board to behave abnormally during powerup and may lead to potential problems. I have a particular SFP device, whose SCK signal (I2C clock) is connected in this fashion. And this is causing the I2C state machine inside the SFP device to go in freeze state. I can only get around this problem by jack out jack in of SFP. -- Goli PS: I am not following any voltage sequencing, my VCCAux and VCCint is derived from LDO using VCCIO (which is 3.3 Volts)Article: 127943
westspeed@gmail.com wrote: > Hi, how are you. I am a university student from china. Now I am doing > a project which will implement SAS with FPGAs on Xilinx Virtex 4 ML405 > board. What is SAS? The one I know of is statistical software, but that would be hard to do in an FPGA. > But before I am a software designer and never do IC design > before ,so this project is very difficult for me. You don't need to do IC design, but doing logic design helps. In the olden days, that was done by wiring up 7400 series TTL gates. That still might be the best way to learn about logic design. You might find a book on using TTL logic and try to think like a logic designer. The thought process is somewhat different from software design. -- glenArticle: 127944
Hi, maverick wrote: > Hi, > I need to know is it possible to add multiple ucf files in an ISE > project? I tried to do this by splitting the original ucf file into > two and added it into a project. The tool compiles only one file and > assigns default IOs to the the rest of the pins mentioned in the > second part of the ucf. Any comments...........any tool settings I am > not aware of......... > > Thanks in advance > > -farhan Why not just concatenate the files? /michaelArticle: 127945
On 10 Jan., 10:18, westsp...@gmail.com wrote: > Hi, how are you. I am a university student from china. Now I am doing > a project which will implement SAS with FPGAs on Xilinx Virtex 4 ML405 > board. But before I am a software designer and never do IC design > before ,so this project is very difficult for me.But this project is > my graduate design.Without this project , I even canot graduate. So it > is very important to me.I see you have done this project in Google > groups forum. So could I make friends with you ,and exchange some > technique about SAS with FPGAs.I hope you can help me and give me some > guidances about this project, I will be very grateful to you.You can > contact with me using email.My email is westsp...@163.com .Thank you > very much. > Yours sincerely > Tony SAS IP (Serially Attached SCSI) IP-Cores cost > 50 KUSD and are not available for free. your university can not ask you to implement SAS on ML405 as part of the study. you will not be able todo it. if that is needed to graduate, you will not graduate, too bad . AnttiArticle: 127946
On Thu, 10 Jan 2008 22:33:33 -0800, glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: >westspeed@gmail.com wrote: > >> Hi, how are you. I am a university student from china. Now I am doing >> a project which will implement SAS with FPGAs on Xilinx Virtex 4 ML405 >> board. > >What is SAS? The one I know of is statistical software, but >that would be hard to do in an FPGA. Probably Serial Attached SCSI which is SCSI over SATA. He probably needs to implement SAS controller logic as doing the SATA PHY does require IC design. Do Virtex 4s have working SATA phys on them? Actually any fpgas with working SATA phys? Most have PCIE but I'm not sure about SATA.Article: 127947
On 11 Jan., 07:37, mk <kal*@dspia.*comdelete> wrote: > On Thu, 10 Jan 2008 22:33:33 -0800, glen herrmannsfeldt > > <g...@ugcs.caltech.edu> wrote: > >westsp...@gmail.com wrote: > > >> Hi, how are you. I am a university student from china. Now I am doing > >> a project which will implement SAS with FPGAs on Xilinx Virtex 4 ML405 > >> board. > > >What is SAS? =A0The one I know of is statistical software, but > >that would be hard to do in an FPGA. > > Probably Serial Attached SCSI which is SCSI over SATA. He probably > needs to implement SAS controller logic as doing the SATA PHY does > require IC design. Do Virtex 4s have working SATA phys on them? > Actually any fpgas with working SATA phys? Most have PCIE but I'm not > sure about SATA. some sort of SATA is possible with V2P, V4 but full SATA support is only available with V5 as the V4,V2P have some compliance issues with SATA physical specs. AnttiArticle: 127948
Thank you for your answers. Sorry I have to be more precise. I am trying to implement the SpaceWire protocol. Unfortunately I have to use this link through a parallel cable for testing purposes (test setup is in that way and the cable is about 4 meters wihich includes also some D-sub connectors on it) So I am trying at such frequency. By the way when I implement two links on the same board and interconnect them they operate quite well but when I connect two different boards the link crashes. > What constitutes a glitch? Actually I have no idea as I said signal levels seem good when I observe in ossciloscope. > How are you sourcing the clock and data? (using DDR flops, output registers, combinatorial outputs) Receiver clock is implemented through combinatorial logic (Data Strobe encoding). Transmitter clock is output registered. > What edge are you using to clock the input data? For the receiver I use double edge > Do you have input timing constraints? I have written the input constraints to the ucf file. > Are you using a DCM? If so, are you specifying SYSTEM_SYNCHRONOUS or SOURCE_SYNCHRONOUS? I am not using a DCM And an attached question : will it be a matter if I use VirtexE board supplied with (the bank is supplied) 3.3 V and Virtex4 is supplied with 2.5 V? Thanks for your invaluable help.Article: 127949
On 11 Ocak, 08:58, Enes ERDIN <eneser...@yahoo.com> wrote:
> Thank you for your answers. Sorry I have to be more precise. I am
> trying to implement the SpaceWire protocol. Unfortunately I have to
> use this link through a parallel cable for testing purposes (test
> setup is in that way and the cable is about 4 meters wihich includes
> also some D-sub connectors on it) So I am trying at such frequency. By
> the way when I implement two links on the same board and interconnect
> them they operate quite well but when I connect two different boards
> the link crashes.
>
> > What constitutes a glitch?
>
> Actually I have no idea as I said signal levels seem good when I
> observe in ossciloscope.
>
> > How are you sourcing the clock and data? (using DDR flops, output registers, combinatorial outputs)
>
> Receiver clock is implemented through combinatorial logic (Data Strobe
> encoding). Transmitter clock is output registered.
>
> > What edge are you using to clock the input data?
>
> For the receiver I use double edge
>
> > Do you have input timing constraints?
>
> I have written the input constraints to the ucf file.
>
> > Are you using a DCM? If so, are you specifying SYSTEM_SYNCHRONOUS or SOURCE_SYNCHRONOUS?
>
> I am not using a DCM
>
> And an attached question : will it be a matter if I use VirtexE board
> supplied with (the bank is supplied) 3.3 V and Virtex4 is supplied
> with 2.5 V?
>
> Thanks for your invaluable help.
I also felt the need for writing the instantiation of the input and
output buffers. Thanks.
===The instantiation for VirtexE bank is driven by 3.3 V ===
IBUF_LVDS_L1_DIN_P :IBUF_LVDS port map (I => L1_DIN_P, O =>
L1_DIN_int);
IBUF_LVDS_L1_DIN_N :IBUF_LVDS port map (I => L1_DIN_N, O => open);
IBUF_LVDS_L1_SIN_P :IBUF_LVDS port map (I => L1_SIN_P, O =>
L1_SIN_int);
IBUF_LVDS_L1_SIN_N :IBUF_LVDS port map (I => L1_SIN_N, O => open);
OBUF_LVDS_L1_DOUT_P : OBUF_LVDS port map (I=>L1_DOUT_int,
O=>L1_DOUT_P);
L1_DOUT_inv: INV port map (I=>L1_DOUT_int, O=>L1_DOUT_N_int); --
negative side
OBUF_LVDS_L1_DOUT_N : OBUF_LVDS port map (I=>L1_DOUT_N_int,
O=>L1_DOUT_N);
OBUF_LVDS_L1_SOUT_P : OBUF_LVDS port map (I=>L1_SOUT_int,
O=>L1_SOUT_P);
L1_SOUT_inv: INV port map (I=>L1_SOUT_int, O=>L1_SOUT_N_int); --
negative side
OBUF_LVDS_L1_SOUT_N : OBUF_LVDS port map (I=>L1_SOUT_N_int,
O=>L1_SOUT_N);
The UCF file:
NET L1_DIN_P IOSTANDARD=LVDS;
NET L1_DIN_N IOSTANDARD=LVDS;
NET "L1_DIN_P" LOC = "P33";
NET "L1_DIN_N" LOC = "P34";
NET L1_SIN_P IOSTANDARD=LVDS;
NET L1_SIN_N IOSTANDARD=LVDS;
NET "L1_SIN_P" LOC = "P35";
NET "L1_SIN_N" LOC = "P36";
NET L1_DOUT_P IOSTANDARD=LVDS;
NET L1_DOUT_N IOSTANDARD=LVDS;
NET "L1_DOUT_P" LOC = "P52";
NET "L1_DOUT_N" LOC = "P53";
NET L1_SOUT_P IOSTANDARD=LVDS;
NET L1_SOUT_N IOSTANDARD=LVDS;
NET "L1_SOUT_P" LOC = "P38";
NET "L1_SOUT_N" LOC = "P39";
=======For Virtex4:=========
IBUFDS_L1_DIN : IBUFDS
generic map (
CAPACITANCE => "NORMAL", -- "LOW", "NORMAL",
"DONT_CARE" (Virtex-4 only)
DIFF_TERM => TRUE, -- Differential Termination (Virtex-4,
Spartan-3E/3A)----FALSE idi eskiden
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input
delay for buffer, "0"-"16" (Spartan-3E/3A only)
IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay
for input register, "AUTO", "0"-"8" (Spartan-3E/3A only)
IOSTANDARD => "DEFAULT")
port map (
O => L1_DIN, -- Clock buffer output
I => L1_DIN_P, -- Diff_p clock buffer input (connect directly
to top-level port)
IB => L1_DIN_N -- Diff_n clock buffer input (connect directly to
top-level port)
);
--link1 sin
IBUFDS_L1_SIN : IBUFDS
generic map (
CAPACITANCE => "NORMAL", -- "LOW", "NORMAL",
"DONT_CARE" (Virtex-4 only)
DIFF_TERM => TRUE, -- Differential Termination (Virtex-4,
Spartan-3E/3A)-----------
IBUF_DELAY_VALUE => "0", -- Specify the amount of added input
delay for buffer, "0"-"16" (Spartan-3E/3A only)
IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay
for input register, "AUTO", "0"-"8" (Spartan-3E/3A only)
IOSTANDARD => "DEFAULT")
port map (
O => L1_SIN, -- Clock buffer output
I => L1_SIN_P, -- Diff_p clock buffer input (connect directly
to top-level port)
IB => L1_SIN_N -- Diff_n clock buffer input (connect directly to
top-level port)
);
---------------------------------------------
----------------------------------------------
--link1 dout
OBUFDS_L1_DOUT : OBUFDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => L1_DOUT_P, -- Diff_p output (connect directly to top-
level port)
OB => L1_DOUT_N, -- Diff_n output (connect directly to top-
level port)
I => L1_DOUT -- Buffer input
);
--link1 sout
OBUFDS_L1_SOUT : OBUFDS
generic map (
IOSTANDARD => "DEFAULT")
port map (
O => L1_SOUT_P, -- Diff_p output (connect directly to top-
level port)
OB => L1_SOUT_N, -- Diff_n output (connect directly to top-
level port)
I => L1_SOUT -- Buffer input
);
The UCF :
NET "L1_DIN_N" LOC = "Y18" | IOSTANDARD = LVDS_25 ;
NET "L1_DIN_P" LOC = "AA18" | IOSTANDARD = LVDS_25 ;
NET "L1_DOUT_N" LOC = "Y21" | IOSTANDARD = LVDS_25 ;
NET "L1_DOUT_P" LOC = "Y20" | IOSTANDARD = LVDS_25 ;
NET "L1_SIN_N" LOC = "W19" | IOSTANDARD = LVDS_25 ;
NET "L1_SIN_P" LOC = "Y19" | IOSTANDARD = LVDS_25 ;
NET "L1_SOUT_N" LOC = "W24" | IOSTANDARD = LVDS_25 ;
NET "L1_SOUT_P" LOC = "W23" | IOSTANDARD = LVDS_25 ;
What if I use LVDS_25_DCI instead?
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