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On Dec 26, 12:42 am, Alain <no_spa2...@yahoo.fr> wrote: > Hi all, > > Does anybody knows where are the web page of "TechXclusives" subject. > It seems they've disappeared from Xilinx website. > > Thanks. And there used to be a nice summary page for different categories of app-notes that is now gone. More improvements to the Xilinx web site for us. John P.Article: 127451
Before you get too far in suspecting the FPGA, take a look at your board. Is it capable of handling whatever post-configuration current surge your bitstreams generate? Since your bitstreams are failing when you add functionality, I would immediately suspect the added current draw from that functionality is causing a voltage drop on the core voltage rail. A sufficient voltage drop can cause the FPGA to lose its configuration. - Nathan On Dec 26, 8:38 am, maverick <sheikh.m.far...@gmail.com> wrote: > Hi, > I have a custom made FPGA board with Spartan xc3s1000 -4 fg456 on it. > There is this strange behaviour of different bitstreams that made me > to turn on the verify option while configuring the FPGA. It was quite > disappointing that the verification for different bitstreams fail. The > FPGA does get programmed successfully but does not pass the > verification phase. I have started suspecting the FPGA part on my > board. There are some ISE projects whose generated bitstreams work > fine on the board but if I add some functionality in these projects, > the FPGA stops responding or start misbehaving. Is there anyway I can > verify the complete FPGA for its LUTs, static ram cells etc which hold > the configuration bits? > In case if some LUTs or ram cells are faulty, is there any way I can > know the locations of these faulty cells so that I can try mapping my > design on the working area? > > Regards > SMFArticle: 127452
On Dec 26, 7:31=A0am, johnp <johnp3+nos...@probo.com> wrote: > On Dec 26, 12:42 am, Alain <no_spa2...@yahoo.fr> wrote: As you noticed, the website is under de-struction and (hopefully) con- struction. You may also have noticed that TechXclusives had been almost dormant for the past year. We intend to remedy this situation, and come up with a different but similar method of publishing short technical notes, publicly readable. Austin, Ken Chapman, and I are very interested in breathing new life into this project. Give us a few weeks... Peter Alfke > > Hi all, > > > Does anybody knows where are the web page of "TechXclusives" subject. > > It seems they've disappeared from Xilinx website. > > > Thanks. > > And there used to be a nice summary page for different categories of > app-notes that is now gone. =A0More improvements to the Xilinx web site > for us. > > John P.Article: 127453
krc.1987@gmail.com wrote: > 1. what is the use of core generators? I use them only for PLLs for which there is no HDL template. > 2. What are xilix primitives and cores? If I use synthesis, the primitives are irrelevant. > 3. what is the adv of using core generators over std. vhdl files? None, if working vhdl code is available or I know how to write it. The biggest *dis*advantage is that the simulation model is a primitive netlist instead of human-readable synthesis code. -- Mike TreselerArticle: 127454
maverick <sheikh.m.farhan@gmail.com> wrote: >Hi, >I have a custom made FPGA board with Spartan xc3s1000 -4 fg456 on it. >There is this strange behaviour of different bitstreams that made me >to turn on the verify option while configuring the FPGA. It was quite >disappointing that the verification for different bitstreams fail. The >FPGA does get programmed successfully but does not pass the >verification phase. I have started suspecting the FPGA part on my >board. There are some ISE projects whose generated bitstreams work >fine on the board but if I add some functionality in these projects, >the FPGA stops responding or start misbehaving. Is there anyway I can >verify the complete FPGA for its LUTs, static ram cells etc which hold >the configuration bits? >In case if some LUTs or ram cells are faulty, is there any way I can >know the locations of these faulty cells so that I can try mapping my >design on the working area? The bitstreams contain CRC32 checks. If these fail, the FPGA won't be programmed. I've had similar problems when I started using FPGAs and it always turned out to be a constraint problem (assuming your board is build adhering to Xilinx's design guides). It is more likely that your contraints are wrong of absent. There is a way to check for unconstrained paths; use google groups to find past messages on that topic in this newgroup. It is possible to make verification maps that skip memory elements (Xilinx has appnotes on that subject). -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 127455
Hi All, Thx for your all replies...I appreciated. Meanwhile I hve solved all this by purchasing a simple CF reader in $5. Sachin On Dec 14, 4:14 am, self <pete.dud...@comcast.net> wrote: > On Dec 13, 2:55 pm, PatC <p...@patocarr.com> wrote: > > > > > Ed McGettigan wrote: > > > sachin wrote: > > >> HI everyone, > > > >> I have purchased ML505 virtex5 based kit for PCIe testing. It has one > > >> pre-loaded compact flash with some in-built testing environment. My > > >> uses is PCIe testing which this compact flash doesn't have the testing > > >> utility nor Xilinx having any utility for the same. I have contacted > > >> Xilinx but didn't get any proper answer. > > >> As per user guide it requires external CF reader for copying .ace file > > >> to compact flash after executing using core gen for PCIe. Does any > > >> body know how to read/write compact flash on-board(ML505), any utility > > >> to copy any file to compact flash, anybody having?? I don't have CF > > >> reader. I want to copy generated .ace file to CF using on-board ML505. > > >> Your early reply is highly appreciated. > > > > Sorry, but what you are asking for (to write to the CF Card while it is > > > plugged into the ML505 board through PCI Express) is not a standard design. > > > It is possible to access the CF Card from the FPGA and there is an EDK > > > design using MicroBlaze and SystemACE peripheral that is available in > > > the online ML505 reference designs > > >http://www.xilinx.com/products/boards/ml505/reference_designs.htm > > > > You will save yourself a lot of time and effort by going down to your > > > local electronics store and picking up a CompactFlash Card Reader/Writer. > > > This should be with the $5-10 range. > > > > Also, there is a PCIe reference design available for the ML505 here: > > >http://www.xilinx.com/products/boards/ml505/pcie.htm > > > The bitfiles are included with the board and the documentation on the > > > above page provides the instructions for setting the configuration > > > control switches to get the example design loaded. > > > > Ed McGettigan > > > -- > > > Xilinx Inc. > > > I'd add that this bitfile can be loaded through JTAG, bypassing the CF > > card method altogether. In the JTAG chain you should see 5 components > > IIRC, being one of the the Virtex5. After programming the completer > > example application onto it and rebooting, the host PC now sees a > > virtual memory on the PCIe bus, which can be accessed by ie. Pcitree > > software. > > I took this example application as a starting point and modified it to > > change it into a requester app. One bit of advice, use the PCIe core > > Plus instead of the hard core. It's much easier to interface with, from > > an end-user point of view. Unless you need multiple virtual channels and > > extreme flexibility, core Plus is the way to go. > > > HTH, > > -P@- Hide quoted text - > > > - Show quoted text - > > All advise above is good. > > On our project we have been talking to the ML506 (same board with > sx50t) using linux. Linux is nice for bringing up pci and pcie cards > because utilities like lspci and scanpci are built into the OS. Also > drivers are easy to write that make the pci(e) hardware accessible to > C programming.Article: 127456
Hi all i have a series of questions regarding the XST capabilities (read: incapabilities). It all started when i had completed this nice multi-port register file code that used MxN BRAMs for an M-read-port, N-write-port register file. I have designed it based on a publication by Mazen Saghir: "A Configurable Multi-Ported Register File Architecture for Soft Processor Cores". The behavior of the design (did two versions: one with the VHDL code generated by an ANSI C 300-line program and one using generates using certain preprocessing for enabling the proper output multiplexers) is inferred properly by both XST 7.1 (patch 4) and 9.2 (unpatched) when i try to synthesize it as a top-level module. So this works. The problems arise when it is included in a bigger design. XST is infamous (in off-the-record talk with my colleagues) pressumably for not using solid graph-based databases in its core (CDFGs?); but this is a macroscopic deduction. Xilinx people correct if i'm wrong and actually you donnot rely too much on "templates" but really perform decomposition to an intermediate representation form at elaboration time. What is really strange is that some MxN cases work in the bigger design (my soft microprocessor) and some don't (no, i have not surpassed limitations in physical resources). Certain BRAMs are actually removed from the microprocessor design. And here are the questions: 1) WHY does the synthesis for some combinations of read/write ports (it is fundamental parameter of my microprocessor) and some don't? 2) is it possible to disable all optimizations (except maybe boolean optimizations) that lead to net eliminations? I'm looking for something close to the "-wysiwyg yes" and "-noreduce yes" options that are available to CPLDs. But i guess such option is not there. 3) is it possible to generate a technology-targeted netlist for synthesis and not for either functional (UNISIM) or timing simulation (SIMPRIMS) in either (preferrably) VHDL or Verilog? I would like to integrate a black-box module in my final design that is deep within the design hierarchy. I have posted some of the questions to the Xilinx forums, but no answers yet. Are the answering people all situated in the States (and are kind of sleeping at this moment)? Hope for answers Kind regards Nikolaos KavvadiasArticle: 127457
On Wed, 26 Dec 2007 07:06:39 -0800 (PST), John Adair <g1@enterpoint.co.uk> wrote: >The big advantage of using the core generator is to get a logic >function that is difficult to infer in a language like VHDL or >difficult to attain the required performance. Or which is easy to infer in a language like VHDL, but for which the synthesis tools don't support particularly well. A recent case here was a 256-element lookup table, inferred as a constant array initialised via a function call (which called other functions to create the data, and others to manipulate it into fixed point format, round it, etc) A bit convoluted but too fast to see in Modelsim.. ISE 7.1 inferred three BlockRams where one would do; Webpack 9.2 improved on that (to two BlockRams). But the interesting thing was the execution time. 544 seconds on ISE 7.1; yes, over nine minutes. There is something n^2 in its handling of initialisation functions. I added an assert for each value calculated; just to reassure me it was doing something. The first few "flashed" past at several per second; by the end, each value gnerated as taking over five seconds. A 512 element LUT "just for a laugh" took almost exactly four times as long. But surely, given years of continuous improvement, Webpack 9.2 can't take 9 minutes to do this? No it can't; it takes over twice as long. Amazing. (I ended up copying the "init" generics from the post-synth netlist and instantiating the BRAMS) - BrianArticle: 127458
On Thu, 27 Dec 2007 01:52:32 -0800 (PST), Uncle Noah <nkavv@skiathos.physics.auth.gr> wrote: >Hi all > >i have a series of questions regarding the XST capabilities (read: >incapabilities). > >3) is it possible to generate a technology-targeted netlist for >synthesis and not for either functional (UNISIM) or timing simulation >(SIMPRIMS) in either (preferrably) VHDL or Verilog? I would like to >integrate a black-box module in my final design that is deep within >the design hierarchy. Black boxing is relatively easy and seems to work. Synthesise the module on its own - the only change to the normal flow I am aware of is that you MUST turn OFF insertion of IOBs for the module's external connections; obviously you want to connect them internally in the top level design. Make sure the resulting .ngc file is available to NGDbuild at the "translate" stage; either in the main project directory or somewhere in the cores search path (see "Translate/Properties" if using the GUI) http://www.xilinx.com/support/answers/11701.htm Instantiate the module in the top level design and add a "box type" attribute set to "black_box" (for syntax see e.g. http://www.xilinx.com/support/answers/9838.htm After synthesis, check the synthesis report; your module should appear as a black box (or primitive component). Then when you run"Translate", NGDbuild should pick up the module's .ngc file and combine the two. NOTE - this avoids synthesis optimisations; it is still possible for MAP to perform trimming... I have typically used this approach to place complex RPMs in the top level of a design. Hope this helps. - BrianArticle: 127459
Meanwhile, you can use the wayback machine... http://web.archive.org/web/20070426050239/http://www.xilinx.com/xlnx/xweb/xil_tx_home.jsp HTH., Syms.Article: 127460
Hi Brian thanks for your answer. A question: > Instantiate the module in the top level design and add a "box type" > attribute set to "black_box" (for syntax see e.g.http://www.xilinx.com/support/answers/9838.htm > After synthesis, check the synthesis report; your module should appear > as a black box (or primitive component). Actually, the black-box module is deep in the hierarchy. The hierarchy is something like: level0: /top-level level1: /top-level/foo level2: /top-level/foo/bar bar is the black-box module. Does your answer apply for this case too? Nikolaos KavvadiasArticle: 127461
Hi and something else. Is it possible to get timing analysis report for a final design which is assembled by: - the design containing a black-box deep within the hierarchy - the black box in some format (EDIF, VHDL netlist or even NGC) I mean is it possible to run final timing analysis (e.g. after par) for the entire design (with the black-box included as proper). Kind regards Nikolaos KavvadiasArticle: 127462
Hello, I am an FPGA designer and I need to get more general knowledge in the field of video and image processing. Are there any courses that you can recommend? thanks and best regards, KarelArticle: 127463
Thanks all for your answers (and interresing to know that this project is still alive) and the useful links ! Alain.Article: 127464
In article <ec27dbd7-ae0f-4581-8772-459bf66990d8@v4g2000hsf.googlegroups.com>,
Uncle Noah <nkavv@skiathos.physics.auth.gr> writes:
|>
|> 1) WHY does the synthesis for some combinations of read/write ports
|> (it is fundamental parameter of my microprocessor) and some don't?
xst has a quite good log output during synthesis. It precisely describes what it
synthesises at which line, and what gets eliminated for what reason. That may
give a clue about the reasons. At least for me, xst was always right and I caused
the problem...
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 127465TechXclusives fell into disrepair because there was no organization behind it. It totally depended on the individual authors to submit something, and the rest of Xilinx, even Marketing, seemed desinterested and hands-off. Enthusiasm without support and feedback only lasts so long, like a few years in this case... It seems like there will be some support in the future. Peter Alfke On Dec 27, 7:49=A0am, Alain <no_spa2...@yahoo.fr> wrote: > Thanks all for your answers (and interresing to know that this project > is still alive) and the useful links ! > > Alain.Article: 127466
On 27 dec, 10:52, Uncle Noah <nk...@skiathos.physics.auth.gr> wrote: > Hi all > > i have a series of questions regarding the XST capabilities (read: > incapabilities). > > It all started when i had completed this nice multi-port register file > code that used MxN BRAMs for an M-read-port, N-write-port register > file. I have designed it based on a publication by Mazen Saghir: "A > Configurable Multi-Ported Register File Architecture for Soft > Processor Cores". > > The behavior of the design (did two versions: one with the VHDL code > generated by an ANSI C 300-line program and one using generates using > certain preprocessing for enabling the proper output multiplexers) is > inferred properly by both XST 7.1 (patch 4) and 9.2 (unpatched) when i > try to synthesize it as a top-level module. So this works. > > The problems arise when it is included in a bigger design. XST is > infamous (in off-the-record talk with my colleagues) pressumably for > not using solid graph-based databases in its core (CDFGs?); but this > is a macroscopic deduction. Xilinx people correct if i'm wrong and > actually you donnot rely too much on "templates" but really perform > decomposition to an intermediate representation form at elaboration > time. > > What is really strange is that some MxN cases work in the bigger > design (my soft microprocessor) and some don't (no, i have not > surpassed limitations in physical resources). Certain BRAMs are > actually removed from the microprocessor design. > > And here are the questions: > > 1) WHY does the synthesis for some combinations of read/write ports > (it is fundamental parameter of my microprocessor) and some don't? > > 2) is it possible to disable all optimizations (except maybe boolean > optimizations) that lead to net eliminations? I'm looking for > something close to the "-wysiwyg yes" and "-noreduce yes" options that > are available to CPLDs. But i guess such option is not there. > > 3) is it possible to generate a technology-targeted netlist for > synthesis and not for either functional (UNISIM) or timing simulation > (SIMPRIMS) in either (preferrably) VHDL or Verilog? I would like to > integrate a black-box module in my final design that is deep within > the design hierarchy. > > I have posted some of the questions to the Xilinx forums, but no > answers yet. Are the answering people all situated in the States (and > are kind of sleeping at this moment)? > > Hope for answers > > Kind regards > Nikolaos Kavvadias yes, i agree ... i had the same feeling and behavior on some of my inference designs ... usually i could fix it by rewriting some pieces of the code (and thus not fulfilling the template) to get it to synthesize the logic i wanted ... although i must say it has improved a lot, nowadays i only get it when i try to do something with RAMB's... kind regards, TimArticle: 127467
Uncle Noah wrote:
> The behavior of the design (did two versions: one with the VHDL code
> generated by an ANSI C 300-line program and one using generates using
> certain preprocessing for enabling the proper output multiplexers) is
> inferred properly by both XST 7.1 (patch 4) and 9.2 (unpatched) when i
> try to synthesize it as a top-level module. So this works.
Is your objective a hardware description
for synthesis or or a netlist generator?
> 1) WHY does the synthesis for some combinations of read/write ports
> (it is fundamental parameter of my microprocessor) and some don't?
Maybe some of the dimensions line up cleanly
with the block ram structures while others don't.
> 2) is it possible to disable all optimizations (except maybe boolean
> optimizations) that lead to net eliminations? I'm looking for
> something close to the "-wysiwyg yes" and "-noreduce yes" options that
> are available to CPLDs. But i guess such option is not there.
Maybe synthesis would do a better job if you gave it the whole problem.
Do you prefer to generate the netlist yourself?
I can only guess what synthesis will do with very simple designs.
Consider writing a clean hdl description using block ram
templates and muxes and compare results with the present design.
Some related examples:
http://home.comcast.net/~mike_treseler/sync_fifo.vhd
http://home.comcast.net/~mike_treseler/stack.vhd
> 3) is it possible to generate a technology-targeted netlist for
> synthesis and not for either functional (UNISIM) or timing simulation
> (SIMPRIMS) in either (preferrably) VHDL or Verilog? I would like to
> integrate a black-box module in my final design that is deep within
> the design hierarchy.
Consider a code template rather than a black box.
This gives synthesis some flexibility.
The main advantage to clean synthesis code is that the
synthesis and simulation models are the same thing.
> I have posted some of the questions to the Xilinx forums, but no
> answers yet. Are the answering people all situated in the States (and
> are kind of sleeping at this moment)?
No. Having a hot toddy at the holiday party ;)
-- Mike Treseler
Article: 127468Dolphin wrote: > I am an FPGA designer and I need to get more general knowledge in the > field of video and image processing. > Are there any courses that you can recommend? http://www.google.com/search?q=image+processing+tutorialArticle: 127469
Using a black boxed component with ISE should be as simple as pointing the tools at the macro file (ngc etc.) and having the associate component declaration in your VHDL module above that level. You may find some useful information in our TechiTip http://www.enterpoint.co.uk/techitips/Previous_TechiTips/techitips_increment_synth.html. It's a little dated now but generally still applicable to the ISE tools. John Adair Enterpoint Ltd. Home of Drigmorn1. The Low Cost FPGA Development Board. On 27 Dec, 12:33, Uncle Noah <nk...@skiathos.physics.auth.gr> wrote: > Hi > > and something else. Is it possible to get timing analysis report for a > final design which is assembled by: > > - the design containing a black-box deep within the hierarchy > - the black box in some format (EDIF, VHDL netlist or even NGC) > > I mean is it possible to run final timing analysis (e.g. after par) > for the entire design (with the black-box included as proper). > > Kind regards > Nikolaos KavvadiasArticle: 127470
Brian Drummond wrote: > On Wed, 26 Dec 2007 07:06:39 -0800 (PST), John Adair > <g1@enterpoint.co.uk> wrote: > >> The big advantage of using the core generator is to get a logic >> function that is difficult to infer in a language like VHDL or >> difficult to attain the required performance. > > Or which is easy to infer in a language like VHDL, but for which the > synthesis tools don't support particularly well. > > A recent case here was a 256-element lookup table, inferred as a > constant array initialised via a function call (which called other > functions to create the data, and others to manipulate it into fixed > point format, round it, etc) A bit convoluted but too fast to see in > Modelsim.. For that kind of a task, I prefer to write C code that directly generates a VHDL package file with a constant array. I find it a lot easier to code and debug (and change), and the level of C knowledge required is not very high.Article: 127471
I installed Centos (linux) 5.1, Xilinx Webpack 9.2i.04, and EDK 9.2.02. However, when i launch 'xpsgui', I see a bunch of warning messages in my shell-window: QPainter::begin: Cannot paint null pixmap QPainter::setPen: Will be reset by begin() QPainter::begin: Cannot paint null pixmap QPainter::setWorldMatrix: Will be reset by begin() QPainter::setWorldMatrix: Will be reset by begin() QPainter::setPen: Will be reset by begin() QPainter::setFont: Will be reset by begin() QPainter::setWorldMatrix: Will be reset by begin() QPainter::setWorldMatrix: Will be reset by begin() QPainter::setFont: Will be reset by begin() QPainter::setWorldMatrix: Will be reset by begin() QPainter::setWorldMatrix: Will be reset by begin() QPainter::setPen: Will be reset by begin() QPainter::setFont: Will be reset by begin() QPainter::setPen: Will be reset by begin() QPainter::setFont: Will be reset by begin() QPainter::setPen: Will be reset by begin() QPainter::setFont: Will be reset by begin() QPainter::setPen: Will be reset by begin() QPainter::setFont: Will be reset by begin() QPainter::setPen: Will be reset by begin() QPainter::setFont: Will be reset by begin() QPainter::setWorldMatrix: Will be reset by begin() QPainter::setWorldMatrix: Will be reset by begin() QPainter::setFont: Will be reset by begin() When the XPS window comes up, the toolbars are missing a bunch of buttons. Sometimes, I can 'mouse over' (move the mouse cursor) over the toolbar, and a text-tip message pops-up. I can still click the invisible buttons, but for some the generated-IPs, the configuration options don't work (the checkboxes that should be there simply aren't in the config window.) This is a problem, because I'm trying to rebuild a petalogix-uclinux distribution from sources, and I need to use XPS to generate a working hardware-platform. (Can't seem to do that under Linux.) I suppose I could do this under a Windows/XP machine, then tar everything over to the Centos 5.1 machine, but I'd really like to get the EDK working on Centos 5.1. The same thing happens on both the 32-bit (x86) and 64-bit (x86_64) Centos 5.1 distributions. Each time, I selected every package to install (including all optional ones.) Any ideas?Article: 127472
root wrote: > I installed Centos (linux) 5.1, Xilinx Webpack 9.2i.04, and EDK 9.2.02. > > However, when i launch 'xpsgui', I see a bunch of warning messages in my Try running just 'xps', rather than 'xpsgui'.Article: 127473
Alain wrote: > Does anybody knows where are the web page of "TechXclusives" subject. > It seems they've disappeared from Xilinx website. John wrote: > And there used to be a nice summary page for different categories of > app-notes that is now gone. More improvements to the Xilinx web site > for us. Peter Alfke wrote: > As you noticed, the website is under de-struction and (hopefully) con- > struction. > You may also have noticed that TechXclusives had been almost dormant > for the past year. > We intend to remedy this situation, and come up with a different but > similar method of publishing short technical notes, publicly readable. > Austin, Ken Chapman, and I are very interested in breathing new life > into this project. Give us a few weeks... Please suggest to your web developers that they should put technical documentation (such as data sheets, user guides, app notes, ZIP files associated with app notes, TechXclusives, etc.) at permanent URLs that don't get shuffled around and lost whenever the marketing people decide that the site should be redesigned. I don't think there's any reason that there can't be a portion of the namespace set aside for permanent URLs for such things, and the fancy point-and-drool web pages can ultimately yield links to the documents at those permanent URLs. Someone well-known in web development (maybe Philip Greenspun?) pointed out years ago that URLs for real documents (not fluff) should not shift around randomly, but should be persistent. There was a paper on it, but I can't find it now. Unfortunately few web developers have taken this to heart. Thanks, EricArticle: 127474
Peter Alfke wrote: > TechXclusives fell into disrepair because there was no organization > behind it. It totally depended on the individual authors to submit > something, OK, but that's no excuse for the web developers to throw the files away. Even if new ones weren't being generated, the old ones should remain available. They contained useful material. Too many people seem to subscribe to the idea that if information is old, it has no value. :-( Eric
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