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Hello everyone ,I am totally new on this group ,and the subject ,sorry if thoses question are alredy answered. I am very , very much interresred in old computers particularly in dec pdp8 and pdp11,and I'd like to 'build' such processors on a spartan 3e starter kit ref :HW-SPAR3E-SK-UNI-G. Before doing a buying mistake,I'd like some informations:My pc is an old windows 98 /machine ,do the provided software work , on those machine?I downloaded the free spartan4k.exe program from xilinx :it seems it works on win98 machines;is it ok?will it work with this board? Thanks very much best regards alain niervezeArticle: 127501
On Sat, 29 Dec 2007 06:40:22 GMT, rsl <rsl@rsl.com> wrote:
>Systemverilog adds multi-dimensional UNpacked-arrays, which VHDL has
>already supported since the dawn of time. Of course, Xilinx XST will
>need to catch up and start supporting Systemverilog. (Altera Quartus
>7.2 is already there!)
>
> logic [7:0][3:0] unpacked_array; // Systemverilog
> logic [7:0][3:0] unpacked_array2; // Systemverilog
> initial unpacked_array = { 8'd1, 8'd2, 8'd3, 8'd4 };
> initial unpacked_array2 = { default: '0 }; // all 0
> integer [3:0] i;
>
>^^^Ok I didn't check that in Modelsim -- someone will correct me if
> that's wrong!
Yeah, a little bit wrong.
By putting both subscripts on the LEFT of the declaration
logic [7:0] [3:0] something;
you are declaring a PACKED two-dimensional array -
OK, and useful, but not what I suspect you mean.
Also, I don't think you can declare a packed array of
any predefined integral type, so "integer [3:0] i"
is illegal.
This looks closer:
logic [7:0] four_bytes [3:0]; // unpacked array of bytes
integer i[3:0]; // unpacked array of integers
And then your assignment-pattern syntax is slightly
wrong too:
> initial unpacked_array2 = { default: '0 }; // all 0
No, you need the assignment pattern syntax with an
apostrophe in front of the opening brace:
initial unpacked_array2 = '{ default: '0 };
Simple braces {} enclose a concatenation, which
is just a way of writing a vector of bits and is
largely unchanged from standard Verilog. Assignment
pattern '{} "learns" its data type from the context,
and can therefore be more intelligent than concatenation
about which part of its contents goes into which part
of the target. For example:
logic [7:0] [1:0] packed_two_bytes;
That declares a 16-bit vector that can also be thought
of as two 8-bit vectors stuck together. Now....
packed_two_bytes = {8'hFF, 4'b1}; // concatenation
packed_two_bytes = '{8'hFF, 4'b1}; // assignment pattern
Oops!!! The first assignment (concatenation) creates
the value 12'b1111_1111_0001 (the concatenation of
8'hFF and 4'b1) and then assigns that to the 16-bit
vector, so we get
packed_two_bytes[1] = 8'h0F
packed_two_bytes[0] = 8'hF1
Betcha that's not what you wanted! The second (assignment
pattern) form knows about the array-of-bytes data type
of "packed_two_bytes" and will assign 8'hFF to packed_two_bytes[1],
and 4'b1 to packed_two_bytes[0].
"default:" syntax is valid in assignment patterns, but
not in concatenations.
Yes, it's confusing :-)
And yes, it's a pity that ISE isn't adopting SystemVerilog
a little more briskly. SV provides structured data for
designers, in the same way that VHDL users have had multi-
dimensional arrays, records and suchlike since forever
(as you correctly say). It also provides a few other
useful goodies like "unique case", and some more radical
enhancements such as interfaces. All these things are
(a) useful, (b) important for well-structured RTL design,
(c) relatively easy for synthesis vendors to implement.
Don't let your synth vendor leave you stuck in the
mediaeval rut of traditional Verilog - put pressure
on them to implement SV design constructs sooner rather
than later!
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 127502On Fri, 28 Dec 2007 15:41:16 GMT, "KJ" <kkjennings@sbcglobal.net> wrote: > >> There are limits to escaping from low-level hardware generation to >> higher level behavioural design creation; but mostly they are not >> inherent in the language, and they are slowly being pushed further back. >> This was partly an experiment to find out how far they have been pushed; >> not very far yet, unfortunately. >> >Keep in mind though that those limits are most likely vendor dependent. >I've used functions that manipulate reals to initialize constant arrays to >produce lookup tables without any problems with vendor A...using vendor X or >Syn, I'm still generating service requests to fix other deficiencies in >their tool that breeze right through with A. Doesn't help you if you're >commited to vendor X, but if you're not, it might. Good to know; I expect the third party ($$$) tools are also better. Meanwhile, I expect we just have to keep up the pressure, via webcases or whatever. This is certainly not the only way in which XST falls behind. - BrianArticle: 127503
try cmpware.com there are free demos (eclipse plugin CELL BE 8 x spu + 1 x spu) commercial product is reported to generate fpga design... On Dec 29, 6:12 am, Koustav <kousta...@gmail.com> wrote: > Hello everybody, > > Does anybody have any idea of a multiprocessor simulator. I have > worked with uniprocessor architecture simulators based on > simplescalar. Please suggest some CMP simulators which are more or > less easy to build in Solaris/Linux machines. I would prefer using a > CMP simulator based on extension of simplescalar but I am open to try > my hands on anything new as well. Thanks in advance. > > KoustavArticle: 127504
"Mir" <irfanfaisalmir@gmail.com> wrote in message news:f32c5128-c4c1-4353-827f-b54f0a4a57ee@v4g2000hsf.googlegroups.com... > > I developed a Spartan-II (xc2s150-5pq208) based card. I also installed > Xilinx Flash (xcf01s) there. Unfortunately when I detect these chips > through JTAG, I found Xilinx Virtex (XCV150) device instead of Spartan- > II (XC2S150). Rest of all is fine.. > It's a known issue with Spartan-II. Simply ignore. It will work just fine. /MikhailArticle: 127505
On Dec 30, 10:50 am, "MM" <mb...@yahoo.com> wrote: > "Mir" <irfanfaisal...@gmail.com> wrote in message > > news:f32c5128-c4c1-4353-827f-b54f0a4a57ee@v4g2000hsf.googlegroups.com... > > > > > I developed a Spartan-II (xc2s150-5pq208) based card. I also installed > > Xilinx Flash (xcf01s) there. Unfortunately when I detect these chips > > through JTAG, I found Xilinx Virtex (XCV150) device instead of Spartan- > > II (XC2S150). Rest of all is fine.. > > It's a known issue with Spartan-II. Simply ignore. It will work just fine. > > /Mikhail Thanks Mikhail, You are right. It is working fine. Actually I am going to develop some commercial product that's why I am conscious about device ID.. I understand from your kind reply that there is only issue in particular Spartan-II chip. Will you suggest me that I should replace Spartan-II chip with new one..? Regards, MirArticle: 127506
My Altera Verilog design is clocked at 50MHz (20ns period). Every 60ns, a data word is read and manipulated by combinational logic to give: one output word which is read after 20ns one output word which is read after 40ns one output word which is read after 60ns The first output is simply a field of the input and so is certainly available on the next clock. The second and third outputs involve integer division by nine. This can take longer than 20ns and so Quartus indicates that the timing constraints are not met. Since the division alone takes more than 20ns, pipelining doesn't help. Even if it did, it seems just a waste of logic to avoid the warning, since the combinational logic actually has enough time to form the result before it's needed. The second and third results are certainly available by 40ns, but I can't see how to indicate to Quartus that that it can allow more than one clock period for these results. (I've found it difficult to do relevant searches either in the Quartus documentation or more widely, because I don't know the standard term to describe this problem). MikeArticle: 127507
> (I've found it difficult to do relevant searches either in the Quartus > documentation or more widely, because I don't know the standard term > to describe this problem). multicycle path? Cheers, JonArticle: 127508
On Dec 30, 4:09=A0am, MikeShepherd...@btinternet.com wrote: > My Altera Verilog design is clocked at 50MHz (20ns period). > > Every 60ns, a data word is read and manipulated by combinational logic > to give: > > =A0 =A0one output word which is read after 20ns > =A0 =A0one output word which is read after 40ns > =A0 =A0one output word which is read after 60ns > > The first output is simply a field of the input and so is certainly > available on the next clock. > > The second and third outputs involve integer division by nine. =A0This > can take longer than 20ns and so Quartus indicates that the timing > constraints are not met. > > Since the division alone takes more than 20ns, pipelining doesn't > help. =A0Even if it did, it seems just a waste of logic to avoid the > warning, since the combinational logic actually has enough time to > form the result before it's needed. > > The second and third results are certainly available by 40ns, but I > can't see how to indicate to Quartus that that it can allow more than > one clock period for these results. > > (I've found it difficult to do relevant searches either in the Quartus > documentation or more widely, because I don't know the standard term > to describe this problem). > > Mike The technical term is multicycle paths. If you are using the classic timing ananlyzer use http://www.altera.com/literature/hb/qts/qts_qii53004.pdf Pgs 8-7 to 8-15 If you are using the TimeQuest Timing Ananlyzer read http://www.altera.com/literature/hb/qts/qts_qii5v3_02.pdf Pgs 6-53 to 6-57. Hope this helps. Subroto Datta Altera Corp.Article: 127509
Many thanks for your replies. MikeArticle: 127510
Hello from Diego Italy Another newbie question I'm using XilinxISE 9.2 on a Spartan3 XC3S1500 I would like to implement a simple dual port ram using the fpga block ram resources. After setting enable pins,active levels and so on i did a TestBenchWaveform Say that i write in RAM-PORT_A locations 0x0,0x1,0x2 the same 8 bit value,say 0x54 Changing some signals i go to read in RAM_PORT_B locations 0x0,0x1,0x2 The result is undefined"UU" It is likely due to my errors.But i dare to ask if the ISE is able to simulate the writing,reading and the content of such a ram? Thanks to everybody and have an Happy new Year Diego Milan,ItalyArticle: 127511
On Sun, 30 Dec 2007 01:10:21 -0800 (PST), Mir <irfanfaisalmir@gmail.com> wrote: >On Dec 30, 10:50 am, "MM" <mb...@yahoo.com> wrote: >> "Mir" <irfanfaisal...@gmail.com> wrote in message >> >> news:f32c5128-c4c1-4353-827f-b54f0a4a57ee@v4g2000hsf.googlegroups.com... >> >> >> >> > I developed a Spartan-II (xc2s150-5pq208) based card. I also installed >> > Xilinx Flash (xcf01s) there. Unfortunately when I detect these chips >> > through JTAG, I found Xilinx Virtex (XCV150) device instead of Spartan- >> > II (XC2S150). Rest of all is fine.. >> >> It's a known issue with Spartan-II. Simply ignore. It will work just fine. >> >> /Mikhail > > > >Thanks Mikhail, > >You are right. It is working fine. Actually I am going to develop some >commercial product that's why I am conscious about device ID.. > >I understand from your kind reply that there is only issue in >particular Spartan-II chip. Will you suggest me that I should replace >Spartan-II chip with new one..? It's not a fault with that particular part. It's also not a bug. There is nothing wrong. The two devices return the same ID, that is all. The Spartan parts are closely related to their Virtex parents, that is all. Regards, AllanArticle: 127512
Hi, I am using Xilinx ISE for PAR (from edf to bit file). and synplify tool for synthesis (to generate edf). Is there some thing like incremental PAR or incremental SYNTH. Please give some reference. Thanks, VittalArticle: 127513
Hi All, Playing with the Spartan 3E Starter Kit reference designs, I've found the following "Exercise" in the "Initial Design - LCD Display Control). Exercise: Implement a hardware state machine which can perform the LCD initialisation sequence. Compare the size of your implementation with the 96 slices required to implement a PicoBlaze processor. Trying to implement a required state machine, I've found an idea which is quite interesting, but may also seem to be crazy: A state machine with "subroutines". The idea is to implement typical, often used state sequences as "subroutines", which may be "called" after pushing the next state to the stack. In the last state of the subrtoutine-sequence the next state is retrieved from the stack. It seems, that this approach may lead to relatively simple implementation of the complex state machines. The sources may be found at "alt.sources" newsgroup as topic "FSM with state stack in VHDL", e.g. available via: http://groups.google.pl/group/alt.sources/browse_thread/thread/4e77d10410e65562/9211c4a79df64ca2 (please switch to the "original message" to be able to save the shar archive containing the sources). There are two implementations provided. One implements the stack in registers, but "return" requires only a single cycle. The another one uses additional clock cycle, to simplify access to the stack, which allows XST to implement the stack in the inferred RAM. The resulting code requires 159 slices in version with stack in inferred RAM, or 189 slices in the version with stack implemented in registers. The code heavily uses VHDL procedures, but synthesizes correctly with XST. I have also a version, where procedures are replaced with M4 macros, so you can generate the "procedure-free" VHDL for less advanced synthesis tools. The code is published as public domain. Maybe someone will find this idea useful? The sources contain also the GHDL testbench: lcd_test_tb.vhd, and the shell script needed to run it. If you are going to run the simulation however, change the definition of the T_CLK from: constant T_CLK : integer := 20; to: constant T_CLK : integer := 2000; Otherwise the simulation will be very loooong, and the resulting file will occupy a lot of space. -- Regards & Happy New Year! Wojciech M. Zabolotny wzab@ise.pw.edu.plArticle: 127514
On Dec 31, 5:59=A0am, vits <vittal.pa...@gmail.com> wrote: > Hi, > I am using Xilinx ISE for PAR (from edf to bit file). and synplify > tool for synthesis (to generate edf). > Is there some thing like incremental PAR or incremental SYNTH. > Please give some reference. > Thanks, > Vittal I know that incremental PAR is possible with Xilinx ISE. The method used is to first go through the entire flow once. Then use the result from this flow as "Guide files" for subsequent flows. You may want to look at the Xilinx documentation for more details. Also take a look at this. http://www.xilinx.com/publications/xcellonline/xcell_48/xc_timing48.htm -Sudheendra KadriArticle: 127515
On Mon, 31 Dec 2007 15:59:49 +0000 (UTC), Wojciech Zabolotny <wzab@ise.pw.edu.pl> wrote: >Trying to implement a required state machine, I've found an idea which is >quite interesting, but may also seem to be crazy: >A state machine with "subroutines". The idea is to implement typical, >often used state sequences as "subroutines", which may be "called" >after pushing the next state to the stack. In the last state of the >subrtoutine-sequence the next state is retrieved from the stack. Interesting, and not at all crazy, but not new either. Something similar was commonly done in the controller state machines used to manage bit-slice microprocessors (vintage 1975-1985 or thereabouts). The AMD 29PL141 family of EPROM-programmable state machines did exactly this. Of course, if you push this idea much further you'll find your "state register" slowly but surely mutating into a "program counter", and the procedures that implement each state's activity will become "instructions", and .... oh, how about that, I seem to have a programmable processor here.... Seriously though... the tradeoffs that give rise to a spectrum of controller organizations, from pure hardware state machine through to pure general purpose processor, are very interesting. For any given problem, there are sure to be many possible styles of solution with different benefits and drawbacks. Even more interesting, for me at least, is the fascinating social spectrum that mirrors this spectrum of design paradigms - with JavaScript programmers somewhere near one end, and soldering-iron users at the other. Thanks -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 127516
>...fascinating social spectrum that mirrors this >spectrum of design paradigms - with JavaScript programmers >somewhere near one end, and soldering-iron users at the other. Jonathan wisely avoids suggesting which social group is uppermost! As he says, the idea is not new. Many such techniques were developed when they were necessary (long before hardware became fast enough and cheap enough to allow a choice). To solve a few specific problems, it doesn't usually make economic sense to invent a new programming language and write a compiler for it. Similarly, it doesn't usually make economic sense to invent a new processor (even a simple one like that described) to save logic elements in a few specific cases. It's fun and heroic, but usually takes too long to be economic. MikeArticle: 127517
Not sure what you are looking for, but there is Cmpware's CMP-DK: http://www.cmpware.com/ -- Steve -- 12/31/07 "Koustav" <koustav79@gmail.com> wrote in message news:1643d9e9-5a43-404c-9c4d-a8149e7e86cd@w56g2000hsf.googlegroups.com... > Hello everybody, > > Does anybody have any idea of a multiprocessor simulator. I have > worked with uniprocessor architecture simulators based on > simplescalar. Please suggest some CMP simulators which are more or > less easy to build in Solaris/Linux machines. I would prefer using a > CMP simulator based on extension of simplescalar but I am open to try > my hands on anything new as well. Thanks in advance. > > Koustav >Article: 127518
Hi I've just received a Sparkfun Spartan 3E Development Board, http://www.sparkfun.com/commerce/product_info.php?products_id=8458 I can use the Xilinx parallel port JTAG cable to program the FPGA but I can't figure out how to program the SPI PROM. This PROM, an Atmel AT45DB), has an SPI interface but does not have a JTAG one. You have to do some magic in the Spartan to add the SPI PROM as part of the JTAG chain. Does anyone know how to do this? How can I use Impact to program an SPI PROM that does not have a JTAG interface? thanks Bob SmithArticle: 127519
Hi Bob, "Bob Smith" <usenet@linuxtoys.org> wrote in message news:f90p45-s3k.ln1@mail.linuxtoys.org... > Hi > > I've just received a Sparkfun Spartan 3E Development Board, > http://www.sparkfun.com/commerce/product_info.php?products_id=8458 > > I can use the Xilinx parallel port JTAG cable to program the FPGA > but I can't figure out how to program the SPI PROM. This PROM, an > Atmel AT45DB), has an SPI interface but does not have a JTAG one. > You have to do some magic in the Spartan to add the SPI PROM as > part of the JTAG chain. > > Does anyone know how to do this? How can I use Impact to program > an SPI PROM that does not have a JTAG interface? > > thanks > Bob Smith Xilinx have a sample project for their S3E starter kit to program an SPI flash chip using a picoblaze processor: http://www.xilinx.com/products/boards/s3estarter/files/s3esk_picoblaze_spi_flash_programmer.pdf http://www.xilinx.com/products/boards/s3estarter/files/s3esk_picoblaze_spi_flash_programmer.zip Targets a "STMicro M25P16 SPI Flash" found on the S3e kit. (Not sure how compatible it is with the AT45DB, but would expect them to be fairly similar) The design itself would be fairly easy to adapt to the Sparkfun board. RedArticle: 127520
Thanks dear memebers for giving such a nice support.. Regards, Mir Allan Herriman wrote: > On Sun, 30 Dec 2007 01:10:21 -0800 (PST), Mir > <irfanfaisalmir@gmail.com> wrote: > > >On Dec 30, 10:50 am, "MM" <mb...@yahoo.com> wrote: > >> "Mir" <irfanfaisal...@gmail.com> wrote in message > >> > >> news:f32c5128-c4c1-4353-827f-b54f0a4a57ee@v4g2000hsf.googlegroups.com... > >> > >> > >> > >> > I developed a Spartan-II (xc2s150-5pq208) based card. I also installed > >> > Xilinx Flash (xcf01s) there. Unfortunately when I detect these chips > >> > through JTAG, I found Xilinx Virtex (XCV150) device instead of Spartan- > >> > II (XC2S150). Rest of all is fine.. > >> > >> It's a known issue with Spartan-II. Simply ignore. It will work just fine. > >> > >> /Mikhail > > > > > > > >Thanks Mikhail, > > > >You are right. It is working fine. Actually I am going to develop some > >commercial product that's why I am conscious about device ID.. > > > >I understand from your kind reply that there is only issue in > >particular Spartan-II chip. Will you suggest me that I should replace > >Spartan-II chip with new one..? > > It's not a fault with that particular part. It's also not a bug. > There is nothing wrong. > > The two devices return the same ID, that is all. The Spartan parts > are closely related to their Virtex parents, that is all. > > Regards, > AllanArticle: 127521
Bob The SPI and JTAG chain can share a header with some switchover of signals, or be entirely seperate as you will see in most of our products. The same 14 way cable(Xilinx pinout) is used for programming. In the IMPACT part of ISE there are seperate menu options for for boundary scan(JTAG) and SPI. When using SPI it is advisable to assert signal Prog_b low (if available) to avoid potential drive conflicts on the SPI. There is supposed to be some JTAG programming of the SPI coming and this I believe works by loading a temporary design into the FPGA to allow access to the SPI I/O and thence waggling appropriately. There is a Xilinx answer on this and when it will become available. A link is on out Darnaw1 product page if you can't find it. John Adair Enterpoint Ltd.- Home of Drigmorn1. The low cost FPGA Starter Board. On 1 Jan, 06:08, Bob Smith <use...@linuxtoys.org> wrote: > Hi > > I've just received a Sparkfun Spartan 3E Development Board,http://www.spar= kfun.com/commerce/product_info.php?products_id=3D8458 > > I can use the Xilinx parallel port JTAG cable to program the FPGA > but I can't figure out how to program the SPI PROM. =A0This PROM, an > Atmel AT45DB), has an SPI interface but does not have a JTAG one. > You have to do some magic in the Spartan to add the SPI PROM as > part of the JTAG chain. > > Does anyone know how to do this? =A0How can I use Impact to program > an SPI PROM that does not have a JTAG interface? > > thanks > Bob SmithArticle: 127522
Bob Smith <usenet@linuxtoys.org> writes: > Does anyone know how to do this? How can I use Impact to program > an SPI PROM that does not have a JTAG interface? You can also do this with some software which will control the JTAG boundry scan register of the FPGA to toggle the pins connectes to the SPI PROM to generate a given programming sequence. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 127523
On Mon, 31 Dec 2007 16:41:09 +0000, Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> wrote: >On Mon, 31 Dec 2007 15:59:49 +0000 (UTC), >Wojciech Zabolotny <wzab@ise.pw.edu.pl> wrote: > > >>Trying to implement a required state machine, I've found an idea which is >>quite interesting, but may also seem to be crazy: >>A state machine with "subroutines". The idea is to implement typical, >>often used state sequences as "subroutines", which may be "called" >>after pushing the next state to the stack. In the last state of the >>subrtoutine-sequence the next state is retrieved from the stack. > >Interesting, and not at all crazy, but not new either. > >Something similar was commonly done in the controller state >machines used to manage bit-slice microprocessors (vintage >1975-1985 or thereabouts). The AMD 29PL141 family of >EPROM-programmable state machines did exactly this. > >Of course, if you push this idea much further you'll find your >"state register" slowly but surely mutating into a "program >counter", and the procedures that implement each state's >activity will become "instructions", and .... oh, how about >that, I seem to have a programmable processor here.... Push the idea one stage further, so that the instructions themselves can suspend to stack and resume operations, and things get even more interesting. Then instructions don't have to be trivial sequential operations, because you don't have to throw away their state and restart them, e.g. to service an interrupt or page fault. "message send" instructions make compilation for OO programming very simple, hiding the details of searching a hierarchy of method tables. Or for example, iterator instructions, e.g. to search an entire array, or other "high level" operations can become a seamless part of the instruction set. (Which may be interesting if you have ever pondered how to integrate something like a hardware search engine or FFT processor into software cleanly). Or an instruction capable of walking a compiler's parse tree, executing whatever code it found at each node, for a halfway house between interpretation and compilation... In 1980s terms, this was called "closing the semantic gap" (between the level at which people could most productively program, and the machine level). Nowadays, of course, there IS no semantic gap, because people are taught to program in C or C++. It makes me shudder to see so many fundamentally unnecessary layers of crud like pure abstract virtual base classes and templates piled on top of the basic simplicity of OO programming. It doesn't even make things more efficient. The above message send, in C++, does result in a lengthy sequential search of the chain of method tables to find the correct method; while the "message send" instruction hits a cache and could usually be out in six cycles, even in a 1980s first-attempt technology demonstrator. And common cases suffered much less penalty. "Send Integer +" can obviously add two integers. But in parallel, it can type check them both; and commence the message send process, and either: commit the sum, or continue the message send process, according to the type check results... We have come such a long way since then. (incidentally there's not much information online about the Linn Rekursiv, or its language Lingo, and much of that is pretty misleading) - BrianArticle: 127524
In Xilinx EDK 9.2.02, when I select the Xilinx Spartan 3A1800 DSP Starter Kit, the base-system-builder doesn't give me the option of adding the SystemACE peripheral to the hardware environment. In a text-editor, I manually examined ./board/Xilinx/boards/Xilinx_S3ADSP1800_RevA/data/Xilinx_S3ADSP1800_RevA_v2_2_0.xbd The interface and I/O declarations related to the SystemACE peripheral are commented out... What's the status of the hardware on the board? Is there a known problem, or is it just untested?
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