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On Dec 1, 6:35 am, shu...@gmail.com wrote: > Hi, > > I am usign the Xilinx xapp058 design to program another device on the > JTAG chain. In this design I download a xsvf file over a serial link > and once it's done, the processor will play the xsvf to configure the > other device. The xsvf file is played successfully. However, the done > pin of the device under configuration doesn't go high and the device > is not starting up. > > If I go to impact and read the status register of that device, I will > get GHIGH = 1 meaning the configuration data is loaded correctly. And > if I do a "verify", the device will then wake up and run. So it looks > like I am lacking some startup instuctions in my xsvf file. > > Anyone has an idea how I can solve it? > > Thanks, > Yan If 'done' is not going high, then the xsvf is NOT getting to the chip properly, which probably means that it's not being "played successfully." Most likely you are missing the post-amble. Time to re-read the documentation. G.Article: 126826
blisca wrote:
> Downloading ip updates 3 does not solve the problem.
does this?
http://home.comcast.net/~mike_treseler/block_ram.vhd
-- Mike Treseler
Article: 126827On Dec 3, 1:20 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > KJ wrote: > > Bottom line right now for the code I right, I'm > > finding Altera way ahead of Xilinx and Synplify so I'm working with X and S > > to get their tools improved so that they too can have less stuff that some > > would consider to be 'not synthesizable'. > > Synplify used to have it over quartus on viewers, > but quartus has caught up. As far as synthesis, > it varies with the design, but I would call > A and S comparable for an altera target. > X needs some focus on advanced synthesis. > For example, I wish they would take this one seriously: > > http://home.comcast.net/~mike_treseler/proc_demo.vhd > http://home.comcast.net/~mike_treseler/proc_demo_ise_bug.pdf > http://home.comcast.net/~mike_treseler/proc_demo_ise_fix.pdf > > It has been hanging fire since ISE 6.1i, > It wouldn't be so bad if I got an error message. > I get synthesis that does not match simulation. > > The suggested "solution" > http://www.xilinx.com/support/answers/18452.htm > is to avoid the legal code that causes the problem. > Note that brand A and S and Modelsim get it right. > > -- Mike Treseler This is an interesting issue. I had to refresh my knowledge of procedures in VHDL. But I don't understand why you say the Xilinx solution to the problem is to "avoid the legal code". They are saying that it will work if you simply pass the variable into the procedure rather then use it as a global variable. To be honest, I find your use of procedures for very simple functions inside of a process to be hard to read. It seems like using parameters instead of a global might even make the code more readable. Is that something you don't want to do?Article: 126828
"Barry" <barry374@gmail.com> wrote in message news:c800e4d7-0d73-4590-afe5-1581e9025327@d4g2000prg.googlegroups.com... > > The driver is a Texas Instruments ADS6244 ADC. Rise time is spec'd > between 50 and 200 psec (from -100mV to +100mV), and my data rate will > be 800Mbps. The device's LVDS drivers have a configurable internal > termination, which I can set to 100 ohm differential if I desire, at > the expense of a little more power dissipation. > Hi Barry, OK, so the signals are fast! But, because you can set the source termination, the design will almost certainly work even with the inaccurate LVDS termination in the FPGA caused by the out of spec. Vcco you're considering. Hell, the FPGA's ~10pF Cpin already screws with the termination enough. I suggest you try simulating to confirm the circuit's operation, however you decide to proceed. HTH., Syms.Article: 126829
I am simulating a system where I use the ISOCM and DSOCM for all code manipulation/data movement to/from the PowerPC. I have verified that the system_init.v file is poulated and pointing the DSOCM_Bram and the ISOCM_Bram. However, once the Power PC comes out of reset I see NO activity at all...on any Power PC interface. The OCM controllers appear to have the correct register initialization values that should enable them coming out of reset. The C code is very simple. I am wondering if I need to put some init sequence to get the Power PC up and running.Article: 126830
rickman wrote:
> This is an interesting issue. I had to refresh my knowledge of
> procedures in VHDL. But I don't understand why you say the Xilinx
> solution to the problem is to "avoid the legal code". They are saying
> that it will work if you simply pass the variable into the procedure
> rather then use it as a global variable.
The declaration is a regular variable.
The name chosen by the original author is indeed unfortunate.
In vhdl, a "global" would be declared shared.
I am not advocating shared variables or
suggesting that anyone support synthesis for them.
The point is that the variable is in scope
for both procedures, and should not require parameters.
That would be a belt and suspenders.
> To be honest, I find your
> use of procedures for very simple functions inside of a process to be
> hard to read.
The point of my code was to demonstrate a complex problem
in as simple a way as I could, and I guess I fell short of that mark.
The procedure update_regs_fix is the way I would
have coded this example:
_______
procedure update_regs_fix is
begin
if incr = '1' and decr = '0'
then
increment;
elsif incr = '0' and decr = '1'
then
decrement;
end if;
end procedure update_regs_fix;
________
This is very easy for me to read.
> It seems like using parameters instead of a global
> might even make the code more readable.
There is no global variable in either example.
Adding parameters where they
are not needed makes the code *harder*
to read not easier.
-- Mike Treseler
Article: 126831Hi I have a very basic question. I have got a Xilinx Virtex-II board with an JTAG interface. I was thinking of using the Xilinx Platform Cable to communicate over the JTAG interface. In the documentation for the Platform cable it says: Platform Cable USB attaches to the USB port on a desktop or laptop PC with an off-the-shelf Hi-Speed USB A-B cable. It derives all operating power from the hub port controller. No external power supply is required. So I wonder if I connect this cable to the JTAG interface of the Xilinx FPGA if then the power supply is also passed to FPGA or if I need there a serperate external power supply? Thanks for some feedback!Article: 126832
I'll let you know to you both Many thanks . It is not the first time that the readers of this NG are helping the newbie that I am. Have a good evening or night wherever you are. DiegoArticle: 126833
Mark McDougall wrote: > > > But only when: > > - decode_field is an alias (signals work ok) > > - the constant CS2_ADDRESS has the MSB set > > - the old std_logic_signed package is used > > ( numeric_std, or just std_logic_unsigned."+" is ok) > > How you found that, I have no idea, but thanks again! > Years of practice!!! ( Plus the divide-and-conquer technique I described earlier ) I've been using XST for 'home projects' since it was released with Webpack 3.1i in 2000, and Synplify since ~1997 at work. XST is great for a free synthesis tool, and Xilinx has improved the language coverage dramatically since its' launch, but XST is far more likely to produce incorrect logic than Synplify. Some of the sneakier issues are the never-ending signed/unsigned bugs, the various logic optimization errors, and the need for a unique index variable name in every 'for' and 'generate' loop. Xilinx normally summarizes these problems in an "XST Known Issues" Answer Record, like 21682, but I haven't seen one of those for 9.x > >Frustrating, because the design differs only from the Altera project in >the memory block instantiations, and the DCM replacing the PLL. > XST 9.1 has some nasty bugs (fixed in 9.2) that cause it to drop pipeline stages near inferred memories, but that doesn't affect instantiations, nor cause wholesale logic removal. BrianArticle: 126834
"Andrew Ganger" <Andrew.Ganger@yahoo.co.uk> wrote in message news:fj1uqt$cdp$1@aioe.org... > Hi > > I have a very basic question. I have got a Xilinx Virtex-II board with > an JTAG interface. I was thinking of using the Xilinx Platform Cable to > communicate over the JTAG interface. In the documentation for the Platform > cable it says: > > Platform Cable USB attaches to the USB port on a desktop or laptop PC with > an off-the-shelf Hi-Speed USB A-B cable. It derives all operating power > from the hub port controller. No external power supply is required. > > So I wonder if I connect this cable to the JTAG interface of the Xilinx > FPGA if then the power supply is also passed to FPGA or if I need there > a serperate external power supply? > Hi Andrew, The 'cable' will be powered, but not your FPGA board. The FPGA board must be independently powered. AFAIK, the JTAG cable monitors the power from the board to determine the JTAG signal voltage levels. Or something like that. But you RTFM, right? ;-) Cheers, Syms.Article: 126835
I wrote: > The article makes mention of a Memec application note on the Flancter, > but the URL is stale and Google doesn't seem to find it. Does anyone > have a copy squirreled away? Several people have sent me copies. Thank you! EricArticle: 126836
Andrew Ganger wrote: > So I wonder if I connect this cable to the JTAG interface of the > Xilinx FPGA if then the power supply is also passed to FPGA or if I > need there > a serperate external power supply? The Xilinx Platform Cable USB does not provide power to the target hardware, if that's what you are asking. You still need a power supply for the target hardware. The Xilinx Platform Cable USB gets its own operating power from USB. It does connect to the target power via the JTAG connector, but it only uses that to establish a voltage reference for the target interface. The early revisions of the Platform Cable USB (DLC9) needed more than 100 mA from the USB port, so they would not work if plugged into an unpowered USB hub. The newer "Low Power" (DLC9LP) and "Pb-free" (DLC9G) revisions use less than 100 mA, so they will work with unpowered hubs (convenient for laptops with few USB ports).Article: 126837
"Martin Thompson" <martin.j.thompson@trw.com> wrote in message
news:uzlwsdss3.fsf@trw.com...
> "KJ" <kkjennings@sbcglobal.net> writes:
>
>> Bottom line right now for the code I right, I'm finding Altera way
>> ahead of Xilinx and Synplify so I'm working with X and S to get
>> their tools improved so that they too can have less stuff that some
>> would consider to be 'not synthesizable'.
>
> Could you give us an example of something Altera can do that Synplify
> can't? (I've always "felt" Synplify to be ahead of the vendor-specific
> tools, but it sounds like that may have changed :-)
>
A few years back my general ranking of tools as to adherance to the standard
was Modelsim, Synplify, Quartus. Now a days, I'd put Quartus way ahead of
Synplify with Modelsim still #1 but Quartus a very close 2nd (again, only in
regards to correctly interpreting the code, not anything else). I haven't
played enough with ISE but the little bit that I have seems to put it close
to but a bit behind Synplify. I say that mainly because the first two bugs
I found in ISE were the exact same two bugs that I had with Synplify...but I
think S has fixed them now.
I didn't take too much time to filter these (sorry, getting late) but
hopefully you can get the gist of what isn't working
Example 0: Time is not synthesizable...even as a constant (I 'think' this
is fixed with Synplify now after I reported it a year or so ago....ISE still
doesn't like this but I'm told that they are considering it)
constant PULSE_HIGH_TIME: time := 1 us;
constant CLOCK_PERIOD: time := 10 ns;
signal My_Counter: natural range 0 to (PULSE_HIGH_TIME / CLOCK_PERIOD);
Example 1. This one is somewhat involved but it has to do with when you have
an enumerated type and try to take the 'pos attribute.
Perusing the log file further, it appears that Synplify can produce either a
note or a warning or the above mentioned error when it encounters usage of
an enumerated type. The line that causes the error is
Line 1324: constant CPU_ROUTER_LOW_INDEX_RANGE: natural :=
t_CPU_ROUTER_COMPONENT_CONNECTIONS'pos(t_CPU_ROUTER_COMPONENT_CONNECTION
S'low);
where 't_CPU_ROUTER_COMPONENT_CONNECTIONS' is defined to be a subtype of
't_CPU_INTERFACES'
Line 1302: subtype t_CPU_ROUTER_COMPONENT_CONNECTIONS is t_CPU_INTERFACES;
and 't_CPU_INTERFACES' is defined to be an enumerated type.
Line 155: type t_CPU_INTERFACES is (rt_Feeder, rt_Track,
rt_SpiIntf,rt_Cam_Cntl, rt_Micr, rt_Trk_Cntl, rt_InkJet, rt_Franker,
rt_Gate,rt_Ports);
The line that causes the error should have returned the position of the
lowest ordered element in the enumerated type. In other words
t_CPU_ROUTER_COMPONENT_CONNECTIONS'pos(t_CPU_ROUTER_COMPONENT_CONNECTION
S'low)
Since 'rt_Feeder' is the lowermost enumeration, this is equivalent to
t_CPU_ROUTER_COMPONENT_CONNECTIONS'pos(rt_Feeder)
And this should be equal to 0
Example 2: Range of a generic can not be used to define the range of a port
The line of code in question is in one of the outputs of an entity
Line 624: Track_Speed_Select: out natural range
ALLOWABLE_TRACK_SPEEDS'range;
where 'ALLOWABLE_TRACK_SPEEDS' is an input generic for that entity and is
defined on line 519
ALLOWABLE_TRACK_SPEEDS: arr_real := (1.0,1.0);
What Synplify should be doing is taking the range of the input generic and
using that to define the range of the output signal 'Track_Speed_Select'.
Example 3:
@E: CD297
:"C:\Designs\ZFpga_EM1_Syn\HDL\ZFpga_Common\Avl_Lexmark_A640_Ink_Jet_Controller\Avl_Lexmark_A640_Ink_Jet_Controller.vhd":724:3:724:11|Width
mismatch, location has width 32, value 1
The offending line of code is
Line 724: RetVal(i) :=
Convert_Track_Speed_To_Sample_Time(Track_Speed(i), Samples_Per_Second);
But 'RetVal' is defined to be an array of time types
(work.pkg_VHD_Common.arr_time) therefore RetVal(i) (the left side of the
line being reported as an error) is of type 'time'.
The function 'Convert_Track_Speed_To_Sample_Time' is a function that returns
type 'time' as well. The error message indicates that the location has a
width of 32 which is not correct, it has a width of 1.
It should be noted that the use of type 'time' in this design is only for
the purposes of computing other constants that then get used to define
ranges of other signals; I'm not trying to synthesize any signals of type
'time'
Example 4: If you define a record type and have some element that is a
vector you can't use the length of that vector to define the range of an
integer. I think it went something like this....
type t_My_Type is record
....
Some_Field: std_ulogic_vector(7 downto 0);
end record;
...
signal My_Counter: natural range 0 to 2**t_My_Type'Some_Field'length - 1
I reported this one a while back, I'm not sure if it's been fixed in
Synplify or not....ISE has this problem (reported to brand X, they are
taking it under advisement).
KJ
Article: 126838
On Dec 3, 3:16 pm, Mike Treseler <mike_trese...@comcast.net> wrote:
> rickman wrote:
> > This is an interesting issue. I had to refresh my knowledge of
> > procedures in VHDL. But I don't understand why you say the Xilinx
> > solution to the problem is to "avoid the legal code". They are saying
> > that it will work if you simply pass the variable into the procedure
> > rather then use it as a global variable.
>
> The declaration is a regular variable.
> The name chosen by the original author is indeed unfortunate.
>
> In vhdl, a "global" would be declared shared.
> I am not advocating shared variables or
> suggesting that anyone support synthesis for them.
>
> The point is that the variable is in scope
> for both procedures, and should not require parameters.
> That would be a belt and suspenders.
Yes, you are right that this is not a "global" variable. But the
point is that the one way you have it coded does not work with XST.
So why is that a real problem? There are at least two way to code it
correctly. This sort of thing (not supporting all valid code styles)
has plagued HDLs since they were invented.
> > To be honest, I find your
> > use of procedures for very simple functions inside of a process to be
> > hard to read.
>
> The point of my code was to demonstrate a complex problem
> in as simple a way as I could, and I guess I fell short of that mark.
>
> The procedure update_regs_fix is the way I would
> have coded this example:
> _______
> procedure update_regs_fix is
> begin
> if incr = '1' and decr = '0'
> then
> increment;
> elsif incr = '0' and decr = '1'
> then
> decrement;
> end if;
> end procedure update_regs_fix;
> ________
>
> This is very easy for me to read.
Yes, the procedure is easy to read. The procedures increment and
decrement are even easier to read. But in context this just seems to
me to spread the code over many more lines than is needed and does
nothing to *improve* the readability of the code. If you had
procedures that were being shared I could see the point of it. But
this is just breaking the code into modules for the sake of having
modules, in my opinion.
I have coded in Forth and this language encourages the use of many
small routines to facilitate correct coding and debugging. Part of
the goal is to write reusable modules. Here I don't see how the
procedures are easier to code or debug and there is no reuse.
> > It seems like using parameters instead of a global
> > might even make the code more readable.
>
> There is no global variable in either example.
> Adding parameters where they
> are not needed makes the code *harder*
> to read not easier.
I don't agree. If a procedure is modifying a parameter, I easily know
exactly what is happening. If it is modifying a variable that is in a
wider scope, I have to look for the variable and figure out which
scope it currently being used. Even better than parameters would be
to not use procedures for such small snippets of code.
architecture RTL of proc_demo is
begin
p_main : process (clk, rst)
variable count_v : unsigned(data'range);
begin
if rst = '1' then
count_v := (others => '0');
elsif rising_edge(clk) then
if incr = '1' then
count_v := count_v + 1;
end if;
if decr = '1' then
count_v := count_v - 1;
end if;
end if;
data <= std_logic_vector(count_v);
end process;
end RTL;
That is the entire architecture without the procedures, 18 lines vs.
40 for a single example of the procedure version. I can use two
copies of the entire architecture for the two cases and it will still
be smaller than the procedure version which uses 50 lines total for
the two cases. But of course everyone sees things differently. If
very small procedures work for you, go for it.
Article: 126839
rickman wrote:
> Yes, you are right that this is not a "global" variable. But the
> point is that the one way you have it coded does not work with XST.
> So why is that a real problem?
The fact that XST does not throw an error.
Instead, it silently creates hardware that doesn't sim
anything like the code.
> There are at least two way to code it
> correctly. This sort of thing (not supporting all valid code styles)
> has plagued HDLs since they were invented.
Not supporting every odd version is fine.
Producing a bad netlist is not.
> If you had
> procedures that were being shared I could see the point of it. But
> this is just breaking the code into modules for the sake of having
> modules, in my opinion.
This is a simplified example with one purpose:
to demonstrate the bug to xilinx.
When I write production
code, I use use procedures for duplicated blocks of code.
I do sometimes like to share a variable between
two procedures.
For example, I might want to share an
input register variable between a collect_data
procedure and a readback procedure
that packs in a status bit. It works fine.
If I make a mistake, it shows up in the sim,
just like any other mistake.
-- Mike Treseler
Article: 126840Hai all, Is there any formula to calculate processor clock cycles per Instructions with given parameters as FPGA implemented processor clock frequency and instruction bytes... pls suggest.. regards, fazalArticle: 126841
Op Mon, 03 Dec 2007 18:27:50 +0100 schreef rickman <gnuarm@gmail.com>: > On Dec 3, 4:14 am, "Boudewijn Dijkstra" <boudew...@indes.com> wrote: >> Op Thu, 29 Nov 2007 15:42:45 +0100 schreef Denkedran Joe >> <denkedran...@googlemail.com>: >> >> > I'm working on a hardware implementation (FPGA) of a lossless >> compression >> > algorithm for a real-time application. The data will be fed in to the >> > system, will then be compressed on-the-fly and then transmitted >> further. >> >> > The average compression ratio is 3:1, so I'm gonna use some FIFOs of a >> > certain size and start reading data out of the FIFO after a fixed >> > startup-time. The readout rate will be 1/3 of the input data rate The >> > size >> > of the FIFOs is determined by the experimental variance of the mean >> > compression ratio. Nonetheless there are possible circumstances in >> which >> > no compression can be achieved. >> >> Given that uncompressible data often resembles noise, you have to ask >> yourself: what would be lost? > > The message! Just because the message "resembles" noise does not mean > it has no information. In fact, just the opposite. If you are compressing reliably transmitted pure binary data, then you are absolutely right. But if there is less information per datum, like in an analog TV signal, something that resembles noise might very well be noise. > Once you have a > message with no redundancy, you have a message with optimum > information content and it will appear exactly like noise. > > Compression takes advantage of the portion of a message that is > predictable based on what you have seen previously in the message. > This is the content that does not look like noise. Once you take > advantage of this and recode to eliminate it, the message looks like > pure noise and is no longer compressible. But it is still a unique > message with information content that you need to convey. > > >> > Since the overall system does not support >> > variable bitrates a faster transmission is no solution here. >> >> > So my idea was to put the question to all of you what to do in case of >> > uncompressibility? Any ideas? >> >> If you can identify the estimated compression beforehand and then split >> the stream into a 'hard' part and an 'easy' part, then you have a way to >> retain the average. > > Doesn't that require sending additional information that is part of > the message? Usually, yes. > On the average, this will add as much, if not more to > the message than you are removing... Possibly. > If you are trying to compress data without loss, you can only compress > the redundant information. If the message has no redundancy, then it > is not compressible and, with *any* coding scheme, will require some > additional bandwidth than if it were not coded at all. > > Think of your message as a binary number of n bits. If you want to > compress it to m bits, you can identify the 2**m most often > transmitted numbers and represent them with m bits. But the remaining > numbers can not be transmitted in m bits at all. If you want to send > those you have to have a flag that says, "do not decode this number". > Now you have to transmit all n or m bits, plus the flag bit. Since > there are 2**n-2**m messages with n+1 bits and 2**m messages with m+1 > bits, I think you will find the total number of bits is not less then > just sending all messages with n bits. But if the messages in the m > bit group are much more frequent, then you can reduce your *average* > number of bits sent. If you can say you will *never* send the numbers > that aren't in the m bit group, then you can compress the message > losslessly in m bits. -- Gemaakt met Opera's revolutionaire e-mailprogramma: http://www.opera.com/mail/Article: 126842
"KJ" <kkjennings@sbcglobal.net> writes: <a lot!> Many thanks for that - interesting stuff! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 126843
Hi, I want to launch Modelsim from within Xilinx EDK. I have the correct versions installed, the ISE recognizes Modelsim correctly. EDK says it cannot find Modelsim, although i have set the following variables in Win XP: %MODELSIM% points to the correct modelsim.ini %MODELTECH% points to the win32 Folder of the installation package %MODEL_TECH% also points to the win32 folder. What is going wrong in the configuration? TimoArticle: 126844
"rickman" <gnuarm@gmail.com> wrote in message
news:58740cd5-a79f-4306-bff9-c274852f2a01@e6g2000prf.googlegroups.com...
> On Nov 30, 5:15 pm, "KJ" <kkjenni...@sbcglobal.net> wrote:
>> "rickman" <gnu...@gmail.com> wrote in message
>>
>> > The examples are far too numerous to list, but here is one.
>> <snip>
>> > To make this unsynthesizable in a way that is sometimes attempted by
>> > newbies...
>>
>> > Example2: process (SysClk, Reset) begin
>> > if (Reset = '1') then
>> > DataOutReg <= (others => '0');
>> > elsif (rising_edge(SysClk) or falling_edge(SysClk)) then
>> > if (SCFG_CMD = '1') THEN
>> > DataOutReg <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
>> > RTS;
>> > end if;
>> > end if;
>> > end process Example2;
>>
>> > You can imagine a register that clocks on both the rising and falling
>> > edge, but you can't build it in an FPGA.
>>
>> But that does not imply that it couldn't be synthesized using two sets of
>> flip flops whose results get combined. You might not find a synthesis
>> tool
>> in 2007 that accepts the above code, but that doesn't mean that there
>> won't
>> be one in 2008 that will. Whether there is such a tool or not depends on
>> how many users scream to brand A and X that they really need this. It
>> can
>> be synthesized, just not how you are focusing on how you think it must be
>> synthesized.
>
> If you can build the second description, I would like to see that. Do
> you know this is possible or are you just speculating? I have never
> seen a good example of a register clocked on both edges done in an
> FPGA.
>
Like I said, your description does not imply that it couldn't be synthesized
using two sets of flops suitably combined. See code below for functionally
equivalent code that implements your example 2 but does so in a way that I'm
sure you can see that it can be synthesized. Note, I'm not suggesting that
writing dual edge flop code is good practice or anything, I'm simply saying
that the code that you presented is synthesizable, since it is functionally
equivalent to the code that I list below which clearly is synthesizable.
That implies that your Example 2 code is just not supported by today's
tools, quite possibly due to the lack of any real demand for support for
such coding....but, like I said in the earlier post, 'not supported' is not
the same as 'not synthesizable'.
KJ
Example2a: process (SysClk, Reset) begin
if (Reset = '1') then
DataOutReg_re <= (others => '0');
elsif rising_edge(SysClk) then
if (SCFG_CMD = '1') THEN
DataOutReg_re <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
RTS;
end if;
end if;
end process Example2a;
Example2b: process (SysClk, Reset) begin
if (Reset = '1') then
DataOutReg_fe <= (others => '0');
elsif falling_edge(SysClk) then
if (SCFG_CMD = '1') THEN
DataOutReg_fe <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
RTS;
end if;
end if;
end process Example2b;
DataOutReg <= DataOutReg_re when (SysClk = '1') else DataOutReg_fe;
Article: 126845"Martin Thompson" <martin.j.thompson@trw.com> wrote in message news:ueje2g5ot.fsf@trw.com... > "KJ" <kkjennings@sbcglobal.net> writes: > <a lot!> KJ also copy/pastes to avoid writing <a lot!>. There are of course other examples but I didn't want to be hammering the suppliers too much in a public forum. KJArticle: 126846
KJ wrote:
> "Martin Thompson" <martin.j.thompson@trw.com> wrote in message
> news:ueje2g5ot.fsf@trw.com...
>> "KJ" <kkjennings@sbcglobal.net> writes:
>> <a lot!>
>
> KJ also copy/pastes to avoid writing <a lot!>. There are of course other
> examples but I didn't want to be hammering the suppliers too much in a
> public forum.
Sometimes they need a nudge.
Thanks for the posting.
I found it informative, and commend you
for taking the time to submit all those bug reports.
Synthesis crosses the newsgroup boundaries,
and I am sometimes conflicted about which groups
are interested in discussing it.
-- Mike Treseler
Article: 126847
Timo Gerber wrote:
> I want to launch Modelsim from within Xilinx EDK.
Click up a shell, bash or cmd.exe
mkdir play
cd play
vcom
If this doesn't give you the vcom usage,
type "exit" to close the shell,
find vcom, and add it's location
to your path and try again.
-- Mike Treseler
Article: 126848Hi, Is there anyone that has XABEL for Sun available, due to some internal mess we have managed to loose our old XABEL installation. It was used with XACT 5.2.1 and Viewlogic powerview which we still have along with licenses for XABEL only the distribution CD is missing. /michaelArticle: 126849
Try www.orangetreetech.com in Oxford.
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