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I just got a Digilent Spartan3E board & tried to load a bit file using webpack 9.2 IMPACT says no USB cable found. Then I tried one of the JTAG3 cables from Digilent. IMPACT can see the cable but detects too many unknown devices. I'm guessing the board is just bad from Digilent. Now I go back & recompile everything for my Avnet Virtex 4 board. Using ISE 7.2 I get the same IMPACT error. Too many unknown devices. This Avnet board was working & I have used it a few dozen times but it seems to be getting flakier and getting harder to program. So my experience is these xilinx fpga boards are not very durable or even working when received. ( Although I am impressed with how fast they are when they do work ) My question is How long does your fpga boards last when subject to repeated configuration attempts ? How long have you used a board before you have to replace it ?Article: 127101
Does anyone know a way to initialize DDR2 memory models from Micron with data....easily? I have 16 DDR2 SDRAM models connected in a 2 Gigabyte SODIMM configuration. The problem I am facing is that our EDK system will eventually populate that memory with data needed during subsequent system operation. Currently I am using C code to write data out to DDR. I am only running simulation right now, so it takes a REALLY long time to get all that data out to RAM before I use it. I know you can make .mem files that you can intitialize the RAM to using mem load commands in ModelSim. However, the crux is, since the RAM is 2GB, you can't specify the Verilog to model all that storage. If you do, ModelSim crashes...and that makes sense. The PC itself only has so much RAM to use. So the RAM model uses some indexing style to save data into the RAM model's internal memory structure. I guess I am asking if there is an easy way to make .mem files to initialize the memory correctly. Hope this makes some sense!Article: 127102
On Tue, 11 Dec 2007 08:34:38 +0100, Frank Buss <fb@frank-buss.de> wrote: >John Larkin wrote: > >> At any decent speed, analog issues (noise, nonlinearity, thd, drift, >> crosstalk) overwhelm math accuracy, and at 14 dac bits we're already >> there. At 32 MHz and healthy swings, the thd limit is the output >> amplifiers, with 50-60 dB tough to hit. But most commercial arbs and >> RF signal generators have ghastly thd specs, like -30 or even -20 dBc. > >I want to generate AES3 and S/PDIF as well, which needs 24 bit resolution. >But for the audio signals the frequency needs only below 20kHz, so I think >I can split this: very good 24 bit, but slow generator with direct sine >calculation from fdlibm and DDS table lookup for faster signals. What do you do with 24-bit data? No dac can keep up with that. JohnArticle: 127103
Brian Davis wrote: > The beauty of this scheme is that it is an exact computation, > not an approximation; I haven't worked out the error terms for > 18x18 or 36x36 multipliers, but I'd expect you could easily > do a computation to twenty-something bits of precision with two > comfortably-fit-in-BRAM sized lookup tables and one complex multiply. > > Their actual implementation with 1970-era TTL took some shortcuts > to conserve hardware, e.g. approximate the fine cosine values as ~1.0 > > [Ref 2] is a great DDS reference that reprints that early paper, > along with summaries of other sine computation methods [Ref 3, Ref 4] Thanks, 24 bit high speed exact sine generation with inexpensive FPGAs would be cool, I've ordered the paper collection. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 127104
I have ordered 2 FPGA board by Digilent - the older S3 and newer S3e boards and a large number of smaller items like USB cables, modules, etc. The latest experience is negative: the S3E board appear to heve the SDRAM broken somehow. Cost me several days of struggle till a frien confirmed that the same tests that fail for me pass on his board. All other items were just fine. No complaints. ereader wrote: > I just got a Digilent Spartan3E board & tried to load a bit file using > webpack 9.2 > IMPACT says no USB cable found. Then I tried one of the JTAG3 > cables from Digilent. IMPACT can see the cable but detects too many > unknown devices. I'm guessing the board is just bad from Digilent. > Now I go back & recompile everything for my Avnet Virtex 4 board. Using > ISE 7.2 I get the same IMPACT error. Too many unknown devices. This > Avnet board was working & I have used it a few dozen times but it seems > to be getting flakier and getting harder to program. > > So my experience is these xilinx fpga boards are not very durable or even > working when received. ( Although I am impressed with how fast they are > when they do work ) > > My question is How long does your fpga boards last when subject to > repeated > configuration attempts ? How long have you used a board before you have to > replace it ? > >Article: 127105
John Larkin wrote: > What do you do with 24-bit data? No dac can keep up with that. There are high end DACs, which gets close to it: http://www.analog.com/en/prod/0,,761_796_AD1852%2C00.html SNR of 114 dB from 20 Hz to 20 kHz means 19 bits accuracy, I think. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 127106
The only time I have seen the "Too many devices" dialog was when I had misconnected the JTAG cable, so I would check their first. I have used serveral Xilinx based boards from Digilent without a single problem outside of incorrect documentation. ---Matthew Hicks > I just got a Digilent Spartan3E board & tried to load a bit file using > webpack 9.2 > IMPACT says no USB cable found. Then I tried one of the JTAG3 > cables from Digilent. IMPACT can see the cable but detects too many > unknown devices. I'm guessing the board is just bad from Digilent. > Now I go back & recompile everything for my Avnet Virtex 4 board. > Using > ISE 7.2 I get the same IMPACT error. Too many unknown devices. This > Avnet board was working & I have used it a few dozen times but it > seems > to be getting flakier and getting harder to program. > So my experience is these xilinx fpga boards are not very durable or > even working when received. ( Although I am impressed with how fast > they are when they do work ) > > My question is How long does your fpga boards last when subject to > repeated > configuration attempts ? How long have you used a board before you > have to > replace it ?Article: 127107
Hi there first of all, i appreciate your bulletins on your newest products. They are interesting indeed. But... size is not everything. I would appreciate either a well-defined prototyping area and certainly an RGB3 or full-RGB DAC interface to a VGA connector (i mostly work on images). Regarding units of measurement... imperial units are fine, i tend to use the units of length/distance in my everyday life, although nobody else does so here (Greece). Since imperial (length) units have been modelled based on human body measures. But i'm mostly fond of Biblical units. Especially cubits (there are ancient Greek, Egyptian, Hebrew variations and so on). I suggest measurements in cubits from now on. Just my 2c Kind regards Nikolaos KavvadiasArticle: 127108
hello I will be trying to [Tri-Mode Embedded EMAC] except EDK tool. Can I implement only by ISE 9.1i tool ? Does anyone have a sample project?Article: 127109
On Dec 11, 8:03 pm, Paul <P...@yahoo.co.uk> wrote: > Hi > > I am using Chipscope 7.1 and I have a VirtexII xc2V6000 with a > Instruction width of 6 bits. I have a design for which I had > automatically generated a JTAG Controller. I can successfully sythesize > the design as well as the JTAG TAP. The problem is just that when I use > ChipScope Pro with to connect to the device it tells me that there are 0 > Core units found in the JTAG device chain. for chipscope connection to the fpga, you need JTAG, but you can use it only when you're sure of working your JTAG controller properly. Also if you need to monitor this controller or any other design, you need to add your demanded signals to chipscope core. if a JTAG port is selected to connect to FPGA that dosn't have any apropriate core on the chip(fpga) then you will receive this report: "There are 0 Core units found in the JTAG device chain." make sure you add and generate your monitoring chipscope core to your design. AHNArticle: 127110
> So my experience is these xilinx fpga boards are not very durable or even > working when received. ( Although I am impressed with how fast they are > when they do work ) > > My question is How long does your fpga boards last when subject to > repeated > configuration attempts ? How long have you used a board before you have to > replace it ? I haven't worked with the boards you mention, but I worked on the ML505 & ML555 from Xilinx. They are very impressive, with lots of peripheral interfaces on board; DDR2, video, audio, you name it. I used it for 6 months to work on our PCIe packet based interface with a virtual FIFO using DDR2, and it proved to be very reliable. Even though it came with ES V5 part, upon request, Xilinx supplied a production part (SX50T) with the distributor loaning us another board on which we re-flowed the V5. No problem re-flowing. These are sturdy, fully functional boards. And very accessible, the 505 was around U$1400. YMMV- -P@Article: 127111
ereader wrote: > Now I go back & recompile everything for my Avnet Virtex 4 board. Using > ISE 7.2 I get the same IMPACT error. Too many unknown devices. I have seen this with older versions of ISE WebPACK, too. I was able to solve it by reducing the transfer speed. With ISE WebPACK 9.2 I never had this problem, old Digilent boards (Sparten 3 and Spartan 3E) are working fine, too. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 127112
My avnet virtex 4 board was working fine with the jtag cable. But over time, it seems to get flaky. Programming would fail. I'd have to power cycle or plug/unplug the cable to get it working again. Now it seems dead. Hope the new board I ordered works better.Article: 127113
>Does anyone know a way to initialize DDR2 memory models from Micron >with data....easily? I have 16 DDR2 SDRAM models connected in a 2 >Gigabyte SODIMM configuration. The problem I am facing is that our >EDK system will eventually populate that memory with data needed >during subsequent system operation. > >Currently I am using C code to write data out to DDR. I am only >running simulation right now, so it takes a REALLY long time to get >all that data out to RAM before I use it. I know you can make .mem >files that you can intitialize the RAM to using mem load commands in >ModelSim. However, the crux is, since the RAM is 2GB, you can't >specify the Verilog to model all that storage. If you do, ModelSim >crashes...and that makes sense. The PC itself only has so much RAM to >use. > >So the RAM model uses some indexing style to save data into the RAM >model's internal memory structure. I guess I am asking if there is an >easy way to make .mem files to initialize the memory correctly. > >Hope this makes some sense! If you post the URL from where you downloaded the models, perhaps someone will know which model you mean and be able to help you... >Article: 127114
First cut of the user manual for Drigmorn1 is now available here http://www.enterpoint.co.uk/component_replacements/Drigmorn1_User_Manual_Issue_1_00.pdf. We are planning an update of this with some more photos and diagrams to clarify bits and pieces in a few weeks. As always anything you think we missed let us know and we will try and get that into the next update. The XC3S500E version has now passed all design tests. XC3S100E version isn't far behind and we are still on target to release to customers this week. John Adair Enterpoint Ltd.Article: 127115
I've tried running pjcli -f xxxx.npl as you mentioned but the problem still remains. The problem seems to be when i swap between behavioural and synthesis/implementation. I think it may be webcase time.Article: 127116
On Dec 12, 11:10 am, mozilla <godzilla...@gmail.com> wrote: > I've tried running pjcli -f xxxx.npl as you mentioned but the problem > still remains. The problem seems to be when i swap between behavioural > and synthesis/implementation. > > I think it may be webcase time. in fact i was wrong it does seem to fix the problem thank you....Article: 127117
rossalbi <rossalbi@hotmail.com> writes:
> Hi people...
>
> I am trying to find a vhdl code for 3x3 sobel algorithm to implement
> on a Spartan 3, FPGA.
>
> I have found many papers on the subject but they are all from a high
> level of abstraction and none include any actual code.
>
> Any help would be greatly appreciated.
>
What's wrong with a high-level of abstraction? Just write code that
does what the high-level abstraction says - it's a fairly simply operator!
How's this:
entity sobel is
port (
top_left_pixel : in integer;
top_middle_pixel : in integer;
top_right_pixel : in integer;
middle_left_pixel : in integer;
middle_right_pixel : in integer;
bottom_left_pixel : in integer;
bottom_middle_pixel : in integer;
bottom_right_pixel : in integer;
sobelx : out integer;
sobely : out integer
);
end entity sobel;
architecture noddy of sobel is
begin -- architecture noddy
sobelx <= (-1*top_left_pixel)+(-2*middle_left_pixel)+(-1*bottom_left_pixel)
+(1*top_right_pixel)+(2*middle_right_pixel)+(1*bottom_right_pixel);
sobely <= (-1*top_left_pixel)+(-2*top_middle_pixel)+(-1*top_right_pixel)
+(1*bottom_left_pixel)+(2*bottom_middle_pixel)+(1*bottom_right_pixel);
end architecture noddy;
Just feed some pixels in in the right order and out pops the 2
Sobel'ed pixels.
Cheers,
Martin
--
martin.j.thompson@trw.com
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Article: 127118On Dec 11, 10:16 pm, Tim P <timmy4th...@gmail.com> wrote: > How about if cleaning up project files does not help? > > I would like to avoid recreating the project due to the size of the > schematic to be redrawn. I have the same symptoms as mentioned in the > first post, except cleaning project files does not solve the problem. > However, when opening the ".ucf" file for my project, Xilinx ISE goes > through a "synthesis" before that file can be opened. This backdoor > synthesis runs fine, but not by activating the synthesize, implement, > or generate prog. file options... > > Any thoughts? I wouldn't think you need to re-draw any schematics, just include the existing ones in the new project. It isn't your source files that are messed up (usually), but the project itself (.ise file). Regards, GaborArticle: 127119
On Tue, 11 Dec 2007 20:10:53 -0800, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >On Tue, 11 Dec 2007 08:34:38 +0100, Frank Buss <fb@frank-buss.de> >wrote: > >>John Larkin wrote: >> >>> At any decent speed, analog issues (noise, nonlinearity, thd, drift, >>> crosstalk) overwhelm math accuracy, and at 14 dac bits we're already >>> there. At 32 MHz and healthy swings, the thd limit is the output >>> amplifiers, with 50-60 dB tough to hit. But most commercial arbs and >>> RF signal generators have ghastly thd specs, like -30 or even -20 dBc. >> >>I want to generate AES3 and S/PDIF as well, which needs 24 bit resolution. >>But for the audio signals the frequency needs only below 20kHz, so I think >>I can split this: very good 24 bit, but slow generator with direct sine >>calculation from fdlibm and DDS table lookup for faster signals. > >What do you do with 24-bit data? No dac can keep up with that. Further processing, normally. Audio signals are ideally recorded with enough headroom to allow mix, EQ, dynamic range adjustment and other processing, without unnecessary compromises in resolution. At the consumption end of the chain, 24 bits is a bit unnecessary, though there are DACs pushing 20 bits. - BrianArticle: 127120
Hi. I am trying to establish a communication between two RocketIO driven Virtex2P FPGAs. I am currently simulating the design running into the following problem: When I set the RocketIO Transmitters (Xilinx GT_CUSTOM) into parallel loopback mode everything is fine (received data = sent data). Whenever I set it into serial loopback mode (or try to communicate with another RocketIO receiver) I seem to receive strange data (which doesn't seem to be connected to sent data in any way). I am completely running out of ideas what I might do wrong, even though I am just a starter with RocketIO. An yes, I did read the RocketIO Users Guide, but I didn't find it very helpful for my problem. tnx alot JohnArticle: 127121
Frank Buss wrote: > ereader wrote: > >> Now I go back & recompile everything for my Avnet Virtex 4 board. Using >> ISE 7.2 I get the same IMPACT error. Too many unknown devices. > > I have seen this with older versions of ISE WebPACK, too. I was able to > solve it by reducing the transfer speed. With ISE WebPACK 9.2 I never had > this problem, old Digilent boards (Sparten 3 and Spartan 3E) are working > fine, too. I think you hit on the problem "ereader" is having. I recall playing with the speed for our own production boards in the past. 24 Mb/s may fail, but 12 Mb/s is golden by my recollection. I've had three development boards with no problems on any of them. I've hauled the one between home and work many times, observing reasonable handling at each location. The performance has been great. I respect and appreciate the work Digilent does and look forward to more purchases down the road. - John_HArticle: 127122
motty wrote: > Does anyone know a way to initialize DDR2 memory models from Micron > with data....easily? [snip] > > [T]he RAM model uses some indexing style to save data into the RAM > model's internal memory structure. I guess I am asking if there is an > easy way to make .mem files to initialize the memory correctly. Look at the MAX_MEM flag. When it is defined, the memory address just comes from addr, so the memory array can be initialized from a file. Otherwise the memory uses an indexing scheme. --- Joe Samson Pixel VelocityArticle: 127123
Hi, I have been developing applications in Xilinx FPGAs using VHDL for the past 3 years for a small company in Virginia. As our designs are getting larger and more complex, the off-the-shelf boards we have been using are proving to be insufficient. I am interested in learning about designing boards myself with FPGAs, ADCs, DACs etc. I am new to board design and am wondering where to start. Any suggestions would be greatly appreciated. Thanks, PoonamArticle: 127124
Yeah, I can't use the MAX_MEM define. It is a 2G SODIMM and ModelSim crashes...obviously due to memory allocation. I have to use the indexing scheme. Looking at the model's Verilog more, I don't even know if it is possible to initialize the memory when it uses that indexing scheme.
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