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On Dec 12, 3:13 pm, Poonam <poonam.mur...@gmail.com> wrote: > Hi, > > I have been developing applications in Xilinx FPGAs using VHDL for the > past 3 years for a small company in Virginia. As our designs are > getting larger and more complex, the off-the-shelf boards we have been > using are proving to be insufficient. I am interested in learning > about designing boards myself with FPGAs, ADCs, DACs etc. I am new to > board design and am wondering where to start. Any suggestions would be > greatly appreciated. > > Thanks, > Poonam Hi Poonam, In my experience it is good design practise to design contigency plans into the board so that mistakes can be rectified easily without having to hack the board around with a scapel. For example, bring some unused IO out to test pads, tie pins high or low via a zero ohm resistor, track the JTAG port to a header. I would never expect a design to be correct on the first spin and if the only changes for the respin are to remove redundant test points etc, you're doing well. Also, I'd avoid BGA packages if at all possible as it is significantly more difficult to design the board, fabricate it, rework faults and rectify design mistakes. I'd also check the website of your FPGA vendor as they usually have lots of information on PCB design. Finally, the PCB design difficulty goes up as the clock frequencies go up. If you are designing something slow with small FPGAs then I'd say have a crack at it and learn as you go. If it's something with lots of high speed logic signals you may be better off going to the experts and paying a third party design house to do the work for you. RobArticle: 127176
On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic <niladri1979@gmail.com> wrote: >Hi All , > >I am new to FPGA development and have learned VHDL using text books. >NOW! that doesn't teach practical aspects! >I am extremely confused with the following discovery - > >Now the confusing part - I have designed an IP which consumes 15 >Block Rams , and when I include the IP in my microblaze system , the >bitstream gets generated! The synthesis report shows that my IP is >using up 15 Block Rams and that microblaze momories are using up 16 >Block Rams! That means that the system is using up 31 Block Rams! > >How is that Possilbe? The final synthesis report probably shows about 190% of the BRAM resources are used. The synthesis output is valid - BUT - will not pass through the implementation tools until you either: redesign to use fewer resources, or: target a bigger FPGA. If you don't want to re-design, low cost boards are available with the Spartan-3 1500. Here's one... http://www.enterpoint.co.uk/moelbryn/raggedstone1.html - BrianArticle: 127177
On Wed, 12 Dec 2007 09:28:29 -0800, "ereader" <rats@myhouse.com> wrote: >Thanks for the tip. > > >"John_H" <newsgroup@johnhandwork.com> wrote in message >news:aef566b7-cc88-4a54-bf07-6fb2e3fc56ca@a35g2000prf.googlegroups.com... >> On Dec 12, 7:32 am, "ereader" <r...@myhouse.com> wrote: >> <snip> >>> >>> How do you reduce the speed ? I don't see any speed selection on the >>> boards >>> or in IMPACT. >> <snip> You said you were using a parallel cable to JTAG interface? A similar thing applies ; the Parallel Cable 4 (and clones) are quite fussy in high speed modes, about the settings on the parallel port, and often don't work at all on laptops. But there is a low speed mode (Parallel Cable 3 compatibility mode) about 200kbits/second. It auto-selects that on my system. At 200kbits/second, things take a while .... but at least they are reliable. - BrianArticle: 127178
On Wed, 12 Dec 2007 22:36:39 -0800 (PST), Josh.OuterSpace@gmail.com wrote: >On Dec 12, 10:47 pm, John Larkin ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> On Wed, 12 Dec 2007 13:45:47 -0800 (PST), Josh.OuterSp...@gmail.com >> wrote: >> >> >How come in the pdf of the vq100 diagram, it shows something with 64 >> >pins. This is odd because the spartan 3e sure doesn't come in a vq64, >> >it comes in a vq100. Maybe they mean the vq100 has 64 pins but that >> >doesn't make sense because the pinout spreadsheet has 100 entries. >> >And how would you divide 100 by 4 to fill up 4 sides of a square >> >chip? You cant do that with 100 unless its a 5 sided chip. >> >> >Thanks. >> >> I couldn't swear to it, but I think that 100 divided by 4 is close to >> 25. >> >> John > >It makes more sense to me to have 5 sides than an odd number of pins >one side Tell that to a 7400. - BrianArticle: 127179
Ed McGettigan wrote: > John Stein wrote: >> [RocketIO] [...] > I have 2 guesses as to what is likely wrong. > > 1) You didn't wait long enough for the MGT PLL and CDR to be fully > functional and if you run it another 10K+ words things might be OK. > > 2) Your special application protocol is not properly aligned as you > either haven't set the 8B10B comma alignment sequences to the values > defined in your protocol (along with the correct initialization > control) or if you have a scrambled protocol you haven't implemented > an aligner in the fabric. I double-checked on every bit regarding the alignment and finally found my (dumb) mistake. One signal for the Phase-alignment was not connected correctly. You can imagine how I felt when finding that out. Once connected the simulation does what I expect it to. Right now the "correct" data is being received after about 50 to 60 clock cycles in the ISE Simulator. (I am aware that this might take a lot longer when being deployed). tnx to all who helped JohnArticle: 127180
On Wed, 12 Dec 2007 14:58:19 -0800 (PST), dteira@gmail.com wrote: >Hello, >I'm having problems with XIlinx ISE 9.1. My design works fine on >behavioral simulation but when I want to implement i, I get an error >in bitgen stage. > >I get a warning message in PAR stage: >"WARNING:Par:289 - The signal GSS/emu_gss/emul_sm/B_haz has no driver. >PAR will not attempt to route this signal. The first stage is to look at the MAP report (rerunning MAP to get a detailed report if necessary) to see if MAP trimmed "B_haz" and if so, why. - BrianArticle: 127181
On 12 Dec., 21:50, John_H <newsgr...@johnhandwork.com> wrote: > On Dec 12, 12:24 pm, kislo <kisl...@student.sdu.dk> wrote: > > > I have a question regarding the T9 pin of the FT256 footprint of the > > spartan 3e .. GCLK0 shares pin with the RDWR_B pin which is a > > configuration pin whitch according to the datasheet (p.97) has to be > > low during configuration .. how is it possible to use GLCK0 as input > > for my primary fpga clock source? (im am using SPI for configuration). > > If you're using SPI for configuration, you should be fine. According > to the Spartan-3 Generation Configuration User Guide > > http://www.xilinx.com/support/documentation/user_guides/ug332.pdf > > the RDWR_B is only used for BPI and Slave Serial modes (table 2-15, > p54 and table 2-16, p. 57). > > Also keep in mind that you can use other GCLK signals as alternatives > to GCLK0. Just because it's "0" doesn't mean it has to be used > first. Note with the BPI mode on page 160 in the User Guide that > many, many GCLK lines are taken up by that configuration mode. > > You should be clean with SPI configuration; do you have functional > results that suggest the data isn't accurate or was it just a matter > of incompletely communicated information in the myriad of guides and > tables that led you to believe you were in trouble? > > Hope the configuration is a breeze, > - John_H Thanks for the confirmation John .. the reason i was in doubt, was that i didnt read that the mode select pins control which pins are reserved during configuration, so i assumed that all configuration pins where reserved during the configuration. KimArticle: 127182
On Dec 13, 6:11 am, Rob <BertyBoos...@googlemail.com> wrote: > On Dec 12, 3:13 pm, Poonam <poonam.mur...@gmail.com> wrote: > > > Hi, > > > I have been developing applications in Xilinx FPGAs using VHDL for the > > past 3 years for a small company in Virginia. As our designs are > > getting larger and more complex, the off-the-shelf boards we have been > > using are proving to be insufficient. I am interested in learning > > about designing boards myself with FPGAs, ADCs, DACs etc. I am new to > > board design and am wondering where to start. Any suggestions would be > > greatly appreciated. > > > Thanks, > > Poonam > > Hi Poonam, > > In my experience it is good design practise to design contigency plans > into the board so that mistakes can be rectified easily without having > to hack the board around with a scapel. For example, bring some unused > IO out to test pads, tie pins high or low via a zero ohm resistor, > track the JTAG port to a header. I would never expect a design to be > correct on the first spin and if the only changes for the respin are > to remove redundant test points etc, you're doing well. > > Also, I'd avoid BGA packages if at all possible as it is significantly > more difficult to design the board, fabricate it, rework faults and > rectify design mistakes. > > I'd also check the website of your FPGA vendor as they usually have > lots of information on PCB design. > > Finally, the PCB design difficulty goes up as the clock frequencies go > up. If you are designing something slow with small FPGAs then I'd say > have a crack at it and learn as you go. If it's something with lots of > high speed logic signals you may be better off going to the experts > and paying a third party design house to do the work for you. > > Rob Thank you, all of you ... PoonamArticle: 127183
I am using the parallel cable III but unfortunately it doesn't work at all on my new Digilent Spartan3E board and has started to quit working on my Avnet Virtex 4 boards. My boards are falling apart despite low (& careful ) usage. Thus my complaint. > But there is a low speed mode (Parallel Cable 3 compatibility mode) > about 200kbits/second. It auto-selects that on my system. At > 200kbits/second, things take a while .... but at least they are > reliable. > > - BrianArticle: 127184
On Dec 13, 12:23 pm, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic
>
> <niladri1...@gmail.com> wrote:
> >Hi All ,
>
> >I am new to FPGA development and have learned VHDL using text books.
> >NOW! that doesn't teach practical aspects!
> >I am extremely confused with the following discovery -
>
> >Now the confusing part - I have designed an IP which consumes 15
> >Block Rams , and when I include the IP in my microblaze system , the
> >bitstream gets generated! The synthesis report shows that my IP is
> >using up 15 Block Rams and that microblaze momories are using up 16
> >Block Rams! That means that the system is using up 31 Block Rams!
>
> >How is that Possilbe?
>
> The final synthesis report probably shows about 190% of the BRAM
> resources are used.
>
> The synthesis output is valid - BUT - will not pass through the
> implementation tools until you either: redesign to use fewer resources,
> or: target a bigger FPGA.
>
> If you don't want to re-design, low cost boards are available with the
> Spartan-3 1500. Here's one...
>
> http://www.enterpoint.co.uk/moelbryn/raggedstone1.html
>
> - Brian
yes it is confusing because I am able to burn the logic and step
through the C code!
The system.mhh is as follows -
#
##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 9.2 Build
EDK_Jm.16
# Tue Dec 11 11:23:35 2007
# Target Board: Memec Spartan-3 3S400LC Development Board Rev 2
# Family: spartan3
# Device: XC3S400
# Package: PQ208
# Speed Grade: -4
# Processor: microblaze_0
# System clock frequency: 50.000000 MHz
# On Chip Memory : 16 KB
#
##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
PORT fpga_0_DIP_Switches_4Bit_GPIO_in_pin =
fpga_0_DIP_Switches_4Bit_GPIO_in, DIR = I, VEC = [0:3]
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ =
50000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
BEGIN microblaze
PARAMETER HW_VER = 7.00.a
PARAMETER INSTANCE = microblaze_0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_AREA_OPTIMIZED = 1
PARAMETER C_FSL_LINKS = 1
PARAMETER C_FAMILY = spartan3
PARAMETER C_INSTANCE = microblaze_0
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_dbg
BUS_INTERFACE SFSL0 = modem_fsl_wrapper_0_to_microblaze_0_0
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE MFSL0 = microblaze_0_to_modem_fsl_wrapper_0_0
PORT RESET = mb_reset
PORT INTERRUPT = microblaze_0_INTERRUPT
END
BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.00.a
PORT PLB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00007FFF
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_cntlr_BRAM_PORT
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00007FFF
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_cntlr_BRAM_PORT
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTB = dlmb_cntlr_BRAM_PORT
BUS_INTERFACE PORTA = ilmb_cntlr_BRAM_PORT
END
BEGIN xps_uartlite
PARAMETER INSTANCE = RS232
PARAMETER HW_VER = 1.00.a
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000
PARAMETER C_BASEADDR = 0x83c12000
PARAMETER C_HIGHADDR = 0x83c121ff
BUS_INTERFACE SPLB = mb_plb
PORT RX = fpga_0_RS232_RX
PORT TX = fpga_0_RS232_TX
END
BEGIN xps_gpio
PARAMETER INSTANCE = DIP_Switches_4Bit
PARAMETER HW_VER = 1.00.a
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_DUAL = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_IS_BIDIR = 0
PARAMETER C_BASEADDR = 0x81400000
PARAMETER C_HIGHADDR = 0x8140ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_in = fpga_0_DIP_Switches_4Bit_GPIO_in
END
BEGIN xps_timer
PARAMETER INSTANCE = timer_counter
PARAMETER HW_VER = 1.00.a
PARAMETER C_ONE_TIMER_ONLY = 1
PARAMETER C_BASEADDR = 0x83c00000
PARAMETER C_HIGHADDR = 0x83c0ffff
BUS_INTERFACE SPLB = mb_plb
PORT Interrupt = timer1
PORT CaptureTrig0 = net_gnd
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_CLKIN_FREQ = 50000000
PARAMETER C_CLKOUT0_FREQ = 50000000
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PORT CLKOUT0 = sys_clk_s
PORT CLKIN = dcm_clk_s
PORT LOCKED = Dcm_all_locked
PORT RST = net_gnd
END
BEGIN mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 1.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
PORT Debug_SYS_Rst = Debug_SYS_Rst
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT Slowest_sync_clk = sys_clk_s
PORT Dcm_locked = Dcm_all_locked
PORT Ext_Reset_In = sys_rst_s
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
END
BEGIN fsl_v20
PARAMETER INSTANCE = modem_fsl_wrapper_0_to_microblaze_0_0
PARAMETER HW_VER = 2.11.a
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = net_gnd
END
BEGIN modem_fsl_wrapper
PARAMETER INSTANCE = modem_fsl_wrapper_0
BUS_INTERFACE MFSL = modem_fsl_wrapper_0_to_microblaze_0_0
BUS_INTERFACE SFSL = microblaze_0_to_modem_fsl_wrapper_0_0
PORT FSL_Clk = sys_clk_s
END
BEGIN fsl_v20
PARAMETER INSTANCE = microblaze_0_to_modem_fsl_wrapper_0_0
PARAMETER HW_VER = 2.11.a
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = net_gnd
END
BEGIN xps_intc
PARAMETER INSTANCE = xps_intc_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x83c14000
PARAMETER C_HIGHADDR = 0x83c141ff
BUS_INTERFACE SPLB = mb_plb
PORT Irq = microblaze_0_INTERRUPT
PORT Intr = timer1
END
BEGIN util_vector_logic
PARAMETER INSTANCE = util_vector_logic_0
PARAMETER HW_VER = 1.00.a
END
The guilty modules are -
1)modem_fsl_wrapper whose device utilisation summary is -
Selected Device : 3s400pq208-4
Number of Slices: 665 out of 3584 18%
Number of Slice Flip Flops: 841 out of 7168 11%
Number of 4 input LUTs: 995 out of 7168 13%
Number used as logic: 923
Number used as Shift registers: 72
Number of IOs: 140
Number of bonded IOBs: 0 out of 141 0%
Number of BRAMs: 15 out of 16 93%
Number of MULT18X18s: 16 out of 16 100%
Number of GCLKs: 6 out of 8 75%
2) Local BRAM -
device utilisatioin -
Device utilization summary:
---------------------------
Selected Device : 3s400pq208-4
Number of Slices: 0 out of 3584 0%
Number of IOs: 206
Number of bonded IOBs: 0 out of 141 0%
Number of BRAMs: 16 out of 16 100%
Thanks for the guidance !
BR
Rate
Article: 127185
On Dec 13, 12:23 pm, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic
>
> <niladri1...@gmail.com> wrote:
> >Hi All ,
>
> >I am new to FPGA development and have learned VHDL using text books.
> >NOW! that doesn't teach practical aspects!
> >I am extremely confused with the following discovery -
>
> >Now the confusing part - I have designed an IP which consumes 15
> >Block Rams , and when I include the IP in my microblaze system , the
> >bitstream gets generated! The synthesis report shows that my IP is
> >using up 15 Block Rams and that microblaze momories are using up 16
> >Block Rams! That means that the system is using up 31 Block Rams!
>
> >How is that Possilbe?
>
> The final synthesis report probably shows about 190% of the BRAM
> resources are used.
>
> The synthesis output is valid - BUT - will not pass through the
> implementation tools until you either: redesign to use fewer resources,
> or: target a bigger FPGA.
>
> If you don't want to re-design, low cost boards are available with the
> Spartan-3 1500. Here's one...
>
> http://www.enterpoint.co.uk/moelbryn/raggedstone1.html
>
> - Brian
On Dec 13, 12:23 pm, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic
>
> <niladri1...@gmail.com> wrote:
> >Hi All ,
>
> >I am new to FPGA development and have learned VHDL using text books.
> >NOW! that doesn't teach practical aspects!
> >I am extremely confused with the following discovery -
>
> >Now the confusing part - I have designed an IP which consumes 15
> >Block Rams , and when I include the IP in my microblaze system , the
> >bitstream gets generated! The synthesis report shows that my IP is
> >using up 15 Block Rams and that microblaze momories are using up 16
> >Block Rams! That means that the system is using up 31 Block Rams!
>
> >How is that Possilbe?
>
> The final synthesis report probably shows about 190% of the BRAM
> resources are used.
>
> The synthesis output is valid - BUT - will not pass through the
> implementation tools until you either: redesign to use fewer resources,
> or: target a bigger FPGA.
>
> If you don't want to re-design, low cost boards are available with the
> Spartan-3 1500. Here's one...
>
> http://www.enterpoint.co.uk/moelbryn/raggedstone1.html
>
> - Brian
yes it is confusing because I am able to burn the logic and step
through the C code!
The system.mhh is as follows -
#
##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 9.2 Build
EDK_Jm.16
# Tue Dec 11 11:23:35 2007
# Target Board: Memec Spartan-3 3S400LC Development Board Rev 2
# Family: spartan3
# Device: XC3S400
# Package: PQ208
# Speed Grade: -4
# Processor: microblaze_0
# System clock frequency: 50.000000 MHz
# On Chip Memory : 16 KB
#
##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = I
PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = O
PORT fpga_0_DIP_Switches_4Bit_GPIO_in_pin =
fpga_0_DIP_Switches_4Bit_GPIO_in, DIR = I, VEC = [0:3]
PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ =
50000000
PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
BEGIN microblaze
PARAMETER HW_VER = 7.00.a
PARAMETER INSTANCE = microblaze_0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_AREA_OPTIMIZED = 1
PARAMETER C_FSL_LINKS = 1
PARAMETER C_FAMILY = spartan3
PARAMETER C_INSTANCE = microblaze_0
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_dbg
BUS_INTERFACE SFSL0 = modem_fsl_wrapper_0_to_microblaze_0_0
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE MFSL0 = microblaze_0_to_modem_fsl_wrapper_0_0
PORT RESET = mb_reset
PORT INTERRUPT = microblaze_0_INTERRUPT
END
BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.00.a
PORT PLB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk_s
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00007FFF
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_cntlr_BRAM_PORT
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 2.10.a
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00007FFF
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_cntlr_BRAM_PORT
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTB = dlmb_cntlr_BRAM_PORT
BUS_INTERFACE PORTA = ilmb_cntlr_BRAM_PORT
END
BEGIN xps_uartlite
PARAMETER INSTANCE = RS232
PARAMETER HW_VER = 1.00.a
PARAMETER C_BAUDRATE = 9600
PARAMETER C_DATA_BITS = 8
PARAMETER C_ODD_PARITY = 0
PARAMETER C_USE_PARITY = 0
PARAMETER C_SPLB_CLK_FREQ_HZ = 50000000
PARAMETER C_BASEADDR = 0x83c12000
PARAMETER C_HIGHADDR = 0x83c121ff
BUS_INTERFACE SPLB = mb_plb
PORT RX = fpga_0_RS232_RX
PORT TX = fpga_0_RS232_TX
END
BEGIN xps_gpio
PARAMETER INSTANCE = DIP_Switches_4Bit
PARAMETER HW_VER = 1.00.a
PARAMETER C_GPIO_WIDTH = 4
PARAMETER C_IS_DUAL = 0
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_IS_BIDIR = 0
PARAMETER C_BASEADDR = 0x81400000
PARAMETER C_HIGHADDR = 0x8140ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_in = fpga_0_DIP_Switches_4Bit_GPIO_in
END
BEGIN xps_timer
PARAMETER INSTANCE = timer_counter
PARAMETER HW_VER = 1.00.a
PARAMETER C_ONE_TIMER_ONLY = 1
PARAMETER C_BASEADDR = 0x83c00000
PARAMETER C_HIGHADDR = 0x83c0ffff
BUS_INTERFACE SPLB = mb_plb
PORT Interrupt = timer1
PORT CaptureTrig0 = net_gnd
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_EXT_RESET_HIGH = 1
PARAMETER C_CLKIN_FREQ = 50000000
PARAMETER C_CLKOUT0_FREQ = 50000000
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PORT CLKOUT0 = sys_clk_s
PORT CLKIN = dcm_clk_s
PORT LOCKED = Dcm_all_locked
PORT RST = net_gnd
END
BEGIN mdm
PARAMETER INSTANCE = debug_module
PARAMETER HW_VER = 1.00.a
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER C_UART_WIDTH = 8
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_dbg
PORT Debug_SYS_Rst = Debug_SYS_Rst
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT Slowest_sync_clk = sys_clk_s
PORT Dcm_locked = Dcm_all_locked
PORT Ext_Reset_In = sys_rst_s
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
END
BEGIN fsl_v20
PARAMETER INSTANCE = modem_fsl_wrapper_0_to_microblaze_0_0
PARAMETER HW_VER = 2.11.a
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = net_gnd
END
BEGIN modem_fsl_wrapper
PARAMETER INSTANCE = modem_fsl_wrapper_0
BUS_INTERFACE MFSL = modem_fsl_wrapper_0_to_microblaze_0_0
BUS_INTERFACE SFSL = microblaze_0_to_modem_fsl_wrapper_0_0
PORT FSL_Clk = sys_clk_s
END
BEGIN fsl_v20
PARAMETER INSTANCE = microblaze_0_to_modem_fsl_wrapper_0_0
PARAMETER HW_VER = 2.11.a
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = net_gnd
END
BEGIN xps_intc
PARAMETER INSTANCE = xps_intc_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x83c14000
PARAMETER C_HIGHADDR = 0x83c141ff
BUS_INTERFACE SPLB = mb_plb
PORT Irq = microblaze_0_INTERRUPT
PORT Intr = timer1
END
BEGIN util_vector_logic
PARAMETER INSTANCE = util_vector_logic_0
PARAMETER HW_VER = 1.00.a
END
The guilty modules are -
1)modem_fsl_wrapper whose device utilisation summary is -
Selected Device : 3s400pq208-4
Number of Slices: 665 out of 3584 18%
Number of Slice Flip Flops: 841 out of 7168 11%
Number of 4 input LUTs: 995 out of 7168 13%
Number used as logic: 923
Number used as Shift registers: 72
Number of IOs: 140
Number of bonded IOBs: 0 out of 141 0%
Number of BRAMs: 15 out of 16 93%
Number of MULT18X18s: 16 out of 16 100%
Number of GCLKs: 6 out of 8 75%
2) Local BRAM -
device utilisatioin -
Device utilization summary:
---------------------------
Selected Device : 3s400pq208-4
Number of Slices: 0 out of 3584 0%
Number of IOs: 206
Number of bonded IOBs: 0 out of 141 0%
Number of BRAMs: 16 out of 16 100%
Thanks for the guidance !
BR
Rate
Article: 127186On Dec 13, 12:23 pm, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic > > <niladri1...@gmail.com> wrote: > >Hi All , > > >I am new to FPGA development and have learned VHDL using text books. > >NOW! that doesn't teach practical aspects! > >I am extremely confused with the following discovery - > > >Now the confusing part - I have designed an IP which consumes 15 > >Block Rams , and when I include the IP in my microblaze system , the > >bitstream gets generated! The synthesis report shows that my IP is > >using up 15 Block Rams and that microblaze momories are using up 16 > >Block Rams! That means that the system is using up 31 Block Rams! > > >How is that Possilbe? > > The final synthesis report probably shows about 190% of the BRAM > resources are used. > > The synthesis output is valid - BUT - will not pass through the > implementation tools until you either: redesign to use fewer resources, > or: target a bigger FPGA. > > If you don't want to re-design, low cost boards are available with the > Spartan-3 1500. Here's one... > > http://www.enterpoint.co.uk/moelbryn/raggedstone1.html > > - Brian spartan 3 400 has 56Kbit distributed RAM is it possible that the synthesizer is using then as block RAMs as well? BR RateArticle: 127187
On Dec 13, 8:13 am, "ereader" <r...@myhouse.com> wrote: > I am using the parallel cable III but unfortunately it doesn't work at all > on my new Digilent Spartan3E board and has started to quit working > on my Avnet Virtex 4 boards. My boards are falling apart despite > low (& careful ) usage. Thus my complaint. Well shoot. It's quite possibly just a voltage issue. The JTAG interface is quite probably a 2.5V interface which isn't very compatible with the LPT port. Before I purchased the much better Xilinx USB Platform Cable (similar in interface to the Parallel IV) I hooked up the VCC of my Parallel-III to 3.3V such that the I/O to the 2.5V JTAG chain was good and the 5V LPT logic was still happy. The buffers in the Parallel-III don't provide good LPT voltages when powered by 2.5V. I highly suggest making the big purchase and getting a Xilinx USB cable. The headaches are significantly fewer! But for the moment, strap VCC for the cable to 3.3V. (and sorry, folks, for the empty response I just accidentally posted)Article: 127188
On Dec 13, 10:16 am, ratemonotonic <niladri1...@gmail.com> wrote: > On Dec 13, 12:23 pm, Brian Drummond <brian_drumm...@btconnect.com> > wrote: > > > > > On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic > > > <niladri1...@gmail.com> wrote: > > >Hi All , > > > >I am new to FPGA development and have learned VHDL using text books. > > >NOW! that doesn't teach practical aspects! > > >I am extremely confused with the following discovery - > > > >Now the confusing part - I have designed an IP which consumes 15 > > >Block Rams , and when I include the IP in my microblaze system , the > > >bitstream gets generated! The synthesis report shows that my IP is > > >using up 15 Block Rams and that microblaze momories are using up 16 > > >Block Rams! That means that the system is using up 31 Block Rams! > > > >How is that Possilbe? > > > The final synthesis report probably shows about 190% of the BRAM > > resources are used. > > > The synthesis output is valid - BUT - will not pass through the > > implementation tools until you either: redesign to use fewer resources, > > or: target a bigger FPGA. > > > If you don't want to re-design, low cost boards are available with the > > Spartan-3 1500. Here's one... > > >http://www.enterpoint.co.uk/moelbryn/raggedstone1.html > > > - Brian > > yes it is confusing because I am able to burn the logic and step > through the C code! > The system.mhh is as follows - > Look at the map report and see what utilization it reports. Many optimizations are performed in the map phase, including removing unconnected/unused resources. It may be that something is not connected the way you meant it to be, and map is removing it. This can happen during development if not all of your signals are connected yet. If that is the case, it may not help your situation of wanting to use more BRAMS than are in the device, but it explains why your design made it through place and route. Regards, John McCaskillArticle: 127189
Paul wrote: > Hi > >> What FPGA you are using? What kind of interfaces are already available >> on your design? How much data do you want to capture? How fast? > > I am using a Xilinx Virtex II XC2V6000 board, and I have a simple > processor running on it. So the simulation in Modelsim is working fine, > and I have to check wether the register content or the memory content > on the FPGA are the same as in the simulation! So either I have a way to > see what is written in the registers in the end or I need a way to have > access to the data written into the RAM. How fast doesnt matter, I just > need to know now for a start, that at the end of the computation I have > the correct result! If there is a processor running, do you already have a uart connection? If not, do you have a couple of pins accessible that you could attach to a uart chip? I like to write a simple monitor that I can access via a uart, that allows me to type simple commands to read/write memory and some important register values. A simple uart monitor program with a couple of commands is very easy to write, and requires very little code. I have also done purely VHDL implementations of a uart monitor, that allows the same kind of reading and writing of data. >> I kind of infer from the way you phrased the question the you don't want >> > to use Chipscope? If that assumption is wrong, and you have a Xilinx >> > FPGA, then how about Chipscope? It does exactly what you are asking >> > about, though it does use the JTAG port. > > Yes I have chipscope and JTAG, so maybe thats then my only chance if > there is no other way to do that! If this is something you only need to do a few times to check that things are working, then I would think chipscope would be by far the easiest. If it were something you wanted to look at repeatedly over a long period of development, it might be worth writing a uart monitor.Article: 127190
If your processor ist allready working in principle and you just want to be sure you can compile GDB for your processor or at least a GDB target. But still you need to get the data out of the chip. As there is no slot for a disc or a usb stick on an fpga, you need some other interface. JTAG is a good solution and there is software available (GDB, ChipScope, GNAT, ...) but in principle any interface that can send data is possible. I am sure many people use RS232 or Ethernet with GDB. Kolja Sulimma > So either I have a way to > see what is written in the registers in the end or I need a way to have > access to the data written into the RAM. How fast doesnt matter, I just > need to know now for a start, that at the end of the computation I have > the correct result! > Yes I have chipscope and JTAG, so maybe thats then my only chance if > there is no other way to do that!Article: 127191
sachin wrote: > HI everyone, > > I have purchased ML505 virtex5 based kit for PCIe testing. It has one > pre-loaded compact flash with some in-built testing environment. My > uses is PCIe testing which this compact flash doesn't have the testing > utility nor Xilinx having any utility for the same. I have contacted > Xilinx but didn't get any proper answer. > As per user guide it requires external CF reader for copying .ace file > to compact flash after executing using core gen for PCIe. Does any > body know how to read/write compact flash on-board(ML505), any utility > to copy any file to compact flash, anybody having?? I don't have CF > reader. I want to copy generated .ace file to CF using on-board ML505. > Your early reply is highly appreciated. Sorry, but what you are asking for (to write to the CF Card while it is plugged into the ML505 board through PCI Express) is not a standard design. It is possible to access the CF Card from the FPGA and there is an EDK design using MicroBlaze and SystemACE peripheral that is available in the online ML505 reference designs http://www.xilinx.com/products/boards/ml505/reference_designs.htm You will save yourself a lot of time and effort by going down to your local electronics store and picking up a CompactFlash Card Reader/Writer. This should be with the $5-10 range. Also, there is a PCIe reference design available for the ML505 here: http://www.xilinx.com/products/boards/ml505/pcie.htm The bitfiles are included with the board and the documentation on the above page provides the instructions for setting the configuration control switches to get the example design loaded. Ed McGettigan -- Xilinx Inc.Article: 127192
motty wrote:
> Does anyone know a way to initialize DDR2 memory models from Micron
> with data....easily? I have 16 DDR2 SDRAM models connected in a 2
> Gigabyte SODIMM configuration. The problem I am facing is that our
> EDK system will eventually populate that memory with data needed
> during subsequent system operation.
>
> Currently I am using C code to write data out to DDR. I am only
> running simulation right now, so it takes a REALLY long time to get
> all that data out to RAM before I use it. I know you can make .mem
> files that you can intitialize the RAM to using mem load commands in
> ModelSim. However, the crux is, since the RAM is 2GB, you can't
> specify the Verilog to model all that storage. If you do, ModelSim
> crashes...and that makes sense. The PC itself only has so much RAM to
> use.
>
> So the RAM model uses some indexing style to save data into the RAM
> model's internal memory structure. I guess I am asking if there is an
> easy way to make .mem files to initialize the memory correctly.
>
> Hope this makes some sense!
I have added my own initialization routines to the Micron SDRAM model
before. I also commented out `FULL_MEM or `MAX_MEM (depending on the
model) so I only had to simulate a subset of the DRAM. I used $readmemh
to read a hex file into the model's storage array ("mem_array" in some
models or "memory" in others). If you are spreading the memory across
many models, that of course becomes more difficult. You could write an
"initial" routine that uses $fscanf to read values from the file and
populate the "memory" array correctly.
I wonder why you are using the model, though. If you are designing a
memory controller you definitely need it. If your controller is already
known to work, you don't want to use the model because it is superslow.
After I designed my memory controller I couldn't tolerate the speed
of it and since I knew it worked, for simulation I replaced the
controller and the memory model with a few lines of code that create an
array, basically like an SRAM. I also used the "bit" type in
SystemVerilog to make the model, because it just uses a single bit to
store one bit in the array (no X or Z). This array is monolithic so
it's easy to initialize with a file. And the simulation is very fast.
There is no timing information in it at all. Maybe that's what you need.
-Kevin
Article: 127193
Does anybody know if XST defines any testable variables when compiling
verilog code?
Some of the compilers or simulators that I'm using have differing
$readmemh() semantics, and I'd like to be able to write something like:
`ifdef INCA
initial $readmemh("memory",configurations,0,15);
`else
`ifdef XST
initial $readmemh("memory",configurations,0,15);
`else
initial $readmemh("memory",configurations);
`endif
`endif
Article: 127194
Brian Davis wrote:
> Kevin Neilson wrote:
>> It's basically a truncated Maclaurin series--probably similar to the
>> way Babbage cranked out sine tables on his Difference Engine. But
>> it is a great idea, and witty because you get the derivatives for free,
>> and apparently no one had used it in a DDS before.
>>
> For high precision sinusoids in FPGA's with multipliers,
> I'd try dusting off the technique from the vintage 1970
> Tierney/Rader/Gold paper [Ref 1] and doing something like :
>
> - Upper two{three} phase bits used for quadrant{octant} folding
>
> - next N phase bits look up a 'coarse' IQ value
> ( coarse phase index, yet precise amplitude )
>
> - next M phase bits look up a 'fine' IQ value
> ( residual rotation )
>
> - complex multiply rotates coarse IQ by fine IQ
>
> Figure six of their paper has a nice graphical summary of
> the technique.
>
> The beauty of this scheme is that it is an exact computation,
> not an approximation; I haven't worked out the error terms for
> 18x18 or 36x36 multipliers,
I like that idea. It takes a little more hardware than the first-order
Taylor (I wrote 'Maclaurin' which isn't exactly accurate). It would
require an extra lookup and also four mults for the complex multiply,
provided you want an output on every cycle. But this is about the same
amount of hardware as required for the 2nd-order Taylor and may be more
accurate. I don't know if I'd call it an exact computation because the
second lookup table it still yields an approximation.
-Kevin
Article: 127195I would do that but my Virtex 4 board doesn't support USB downloading. The USB cable that came with my new digilent board doesn't work at all. I have 3 digilent parallel III cables that are suppose to work at 1.5, 1.8 & 2.5v. Either these things are not tested before shipping or the design is just flat out wrong. Digilent seems to be like those chinese companies that have no idea as to what they are selling & can't provide anyone to answer the most basic question. > I highly suggest making the big purchase and getting a Xilinx USB > cable. The headaches are significantly fewer! But for the moment, > strap VCC for the cable to 3.3V.Article: 127196
On Dec 13, 12:37 pm, "ereader" <r...@myhouse.com> wrote: > I would do that but my Virtex 4 board doesn't support USB downloading. > The USB cable that came with my new digilent board doesn't work at all. > I have 3 digilent parallel III cables that are suppose to work at 1.5, 1.8 & > 2.5v. > Either these things are not tested before shipping or the design is just > flat > out wrong. Digilent seems to be like those chinese companies that have no > idea as to what they are selling & can't provide anyone to answer the most > basic question. Are you on Windows XP? Vista? Ubunto Linux? Are you in the US such that I could send/lend you my Digilent Spartan3E (rev D) board for comparison? I can connect by USB cable without issue. But I'm not messing with Linux issues, I'm just on Windows XP. I'm up in the Portland, OR area and would like to see you having a better experience with the Pullman, Washington company that shares this corner of the US. Your experience should be much better than you appear to be having. Digilent is a small company and doesn't have a support staff large enough to outsource. If email gets you nowhere, perhaps a phone call could. I hooked up an overseas purchaser with the right folks just by placing a phone call to get the right email to the right place. If you'd like to pass along shipping info to take me up on the offer to lend you my board or start up a side conversation, feel free to email me directly. - John_HArticle: 127197
On Dec 12, 10:13 am, Poonam <poonam.mur...@gmail.com> wrote: > Hi, > > I have been developing applications in Xilinx FPGAs using VHDL for the > past 3 years for a small company in Virginia. As our designs are > getting larger and more complex, the off-the-shelf boards we have been > using are proving to be insufficient. I am interested in learning > about designing boards myself with FPGAs, ADCs, DACs etc. I am new to > board design and am wondering where to start. Any suggestions would be > greatly appreciated. > > Thanks, > Poonam Tell us more about the off-the-shelf boards that don't meet your new requirements. Have you looked at Digilent's products? They make Xilinx FPGA starter boards. Perhaps it would be simpler/cheaper to design a daughter board that has ADCs, DACs, whatever, than to design a FPGA board from scratch. -Dave Pollum (Burke, VA)Article: 127198
Hi David, you can't read the ISOCM in Virtex-II Pro. You can only write it and execute from it. - Peter David Hand wrote: > I'm trying to use the Xilinx ISOCM memory in a Virtex-II Pro. I can't > seem to get it to actually write to the ISOCM BRAMs. > > In .mhs file I have: > > BEGIN ppc405 > PARAMETER INSTANCE = ppc405_0 > PARAMETER HW_VER = 2.00.c > PARAMETER C_ISOCM_DCR_BASEADDR = 0b0100000000 > PARAMETER C_DSOCM_DCR_BASEADDR = 0b1000000000 > PARAMETER C_DCR_RESYNC = 2 > BUS_INTERFACE ISOCM = iocm > BUS_INTERFACE DSOCM = docm > PORT BRAMISOCMCLK = sys_clk_s > PORT BRAMDSOCMCLK = sys_clk_s > PORT DCRCLK = sys_clk_s > . > . > . > END > > BEGIN isocm_v10 > PARAMETER INSTANCE = iocm > PARAMETER HW_VER = 2.00.a > PARAMETER C_ISCNTLVALUE = 0x83 // Note ppc_clk_s is 2 times sys_clk_s > PORT ISOCM_Clk = sys_clk_s > PORT sys_rst = sys_bus_reset > END > > BEGIN isbram_if_cntlr > PARAMETER INSTANCE = iocm_cntlr > PARAMETER HW_VER = 3.00.a > PARAMETER C_BASEADDR = 0x01000000 > PARAMETER C_HIGHADDR = 0x01003FFF > BUS_INTERFACE ISOCM = iocm > BUS_INTERFACE DCR_WRITE_PORT = isocm_porta > BUS_INTERFACE INSTRN_READ_PORT = isocm_portb > END > > BEGIN bram_block > PARAMETER INSTANCE = isocm_bram > PARAMETER HW_VER = 1.00.a > BUS_INTERFACE PORTA = isocm_porta > BUS_INTERFACE PORTB = isocm_portb > END > > In .mss I have: > > BEGIN DRIVER > PARAMETER DRIVER_NAME = generic > PARAMETER DRIVER_VER = 1.00.a > PARAMETER HW_INSTANCE = iocm_cntlr > END > > Then in my C code, I do the following: > > // Initialize ISINIT register to starting address. > // This works when I read it back. > mtdcr(0x100, 0x01000000); > > I'm using 0x100 for the DCRN address above since I set the base address > of the IOCM DCR to 0x100 in the MHS, and the offset of the ISINIT from > that base is 0. > > // Write a value to ISFILL register. > mtdcr(0x101, 0xFFFFFFFF); > > The write to the ISFILL works and increments ISINIT as it should. > Reading back the value in ISFILL gives 0xFFFFFFFF as it should, but this > is just the register, not what is in BRAM itself. However, when I go to > read the IOCM memory itself using: > > long *p = (long *) 0x01000000; > long x = *p; > > I still get 0. > > So it seems the like everything is working except the value in ISFILL is > not being transferred to the actual BRAM. What am I missing? Do I need > to create a DCR bus to the IOCM? Do I need to somehow enable DCR writes? > > Any help would be appreciated.Article: 127199
Ed McGettigan wrote: > sachin wrote: >> HI everyone, >> >> I have purchased ML505 virtex5 based kit for PCIe testing. It has one >> pre-loaded compact flash with some in-built testing environment. My >> uses is PCIe testing which this compact flash doesn't have the testing >> utility nor Xilinx having any utility for the same. I have contacted >> Xilinx but didn't get any proper answer. >> As per user guide it requires external CF reader for copying .ace file >> to compact flash after executing using core gen for PCIe. Does any >> body know how to read/write compact flash on-board(ML505), any utility >> to copy any file to compact flash, anybody having?? I don't have CF >> reader. I want to copy generated .ace file to CF using on-board ML505. >> Your early reply is highly appreciated. > > Sorry, but what you are asking for (to write to the CF Card while it is > plugged into the ML505 board through PCI Express) is not a standard design. > It is possible to access the CF Card from the FPGA and there is an EDK > design using MicroBlaze and SystemACE peripheral that is available in > the online ML505 reference designs > http://www.xilinx.com/products/boards/ml505/reference_designs.htm > > You will save yourself a lot of time and effort by going down to your > local electronics store and picking up a CompactFlash Card Reader/Writer. > This should be with the $5-10 range. > > Also, there is a PCIe reference design available for the ML505 here: > http://www.xilinx.com/products/boards/ml505/pcie.htm > The bitfiles are included with the board and the documentation on the > above page provides the instructions for setting the configuration > control switches to get the example design loaded. > > Ed McGettigan > -- > Xilinx Inc. I'd add that this bitfile can be loaded through JTAG, bypassing the CF card method altogether. In the JTAG chain you should see 5 components IIRC, being one of the the Virtex5. After programming the completer example application onto it and rebooting, the host PC now sees a virtual memory on the PCIe bus, which can be accessed by ie. Pcitree software. I took this example application as a starting point and modified it to change it into a requester app. One bit of advice, use the PCIe core Plus instead of the hard core. It's much easier to interface with, from an end-user point of view. Unless you need multiple virtual channels and extreme flexibility, core Plus is the way to go. HTH, -P@
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