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Hello, I want to design a system which includes ADC, digital filter, DAC with dataflow chart like this: audio_signal1->ADC->digital filter->DAC->audio_signal2 digital filter has to be controlled from PC host running Windows through a GUI written in Visual Basic. Which software from Xilinx is more appropriate to design such system - WebPack ISE or EDK?Article: 125326
On 21 Okt., 22:26, Wei Wang <camww...@gmail.com> wrote: > Hi, > > Just wondering what could go wrong when synthesizing memories (i- > cache, d-cache, and write buffer) of microprocessors on fpga Xilinx > Virtex 5? Thanks! > > Wei anything ;)Article: 125327
Neil Steiner schrieb: > I would like to prevent GLOBAL_LOGIC0 and GLOBAL_LOGIC1 nets from > stealing unused slices in a particular region. I don't mind if those or > other nets pass through the region, but the logic within the region must > remain untouched. > > Does anybody know how this might be accomplished? This is under ISE/EDK > 8.1. I'm not presently using the PR flow, and would rather not use it > if there is any alternate way of protecting the slices. > > (I did try defining an AREA_GROUP with attributes PLACE=CLOSED and > MODE=RECONFIG, but that made no difference, either because the tools > think these nets are exempt, or because I'm not using the PR flow.) Can you feed the GLOBAL_LOGIC0 and GLOBAL_LOGIC1 signals via ports (and bus macros) into your module? Probably you have to modify the .edf files, because the synthesis tool introduces some vcc/gnd symbols. -MarkusArticle: 125328
Antonio Pasini wrote: There are several examples to be found on internet. Did you type it in google before asking here? One example is: http://www.xilinx.com/bvdocs/appnotes/xapp616.pdf (title: Huffman coding) taco > Il 21/10/2007 0.44, no_reply ha scritto: >> Hi, >> >> I've been looking at available VHDL/Verilog implementations of huffman >> coders. It appears that all currently available implementations use a >> fixed codebook (e.g. the one specified in the MPEG standard) for >> coding and decoding, and thus are quite trivial (they just look up >> symbols in that fixed codebook). I'm more interested in building a >> huffman codebook from the input data. It appears that this can become >> quite difficult due to the use of changing tree structures, which seem >> quite complicated to do in hardware. Can anyone point me towards >> readily available (read: free) implementations for such an encoder? >> >> Thanks in advance >> Enno >> > > > Check "FPGA Implementation of the Dynamic Huffman Encoder", > Ernest Jamro, Maciej Wielgosz, Kazimierz Wiatr > AGH University of Science and Technology > al. Mickiewicz 30, 30-051, Poland > Academic Computer Center CYFRONET > ul. Nawojki 11, Kraków 30-950, Poland > email: jamro / wiatr@agh.edu.pl > > They "augment" a standard, lookup table huffman encoder with an > histogram unit, then use a microblaze to update the table on the fly. > > To easily implement Huffman in hardware you need a length limited code, > so you can use a fixed width ram table to compress. So you may be > interested in this, also: > > http://en.wikipedia.org/wiki/Package-merge_algorithm > > The links at the bottom are a very good place to start. > > I didn't find any free core, so far. > > > Please share your results!Article: 125329
On Oct 22, 6:22 am, Vagant <vladimir.v.koroste...@rambler.ru> wrote: > Hello, > > I want to design a system which includes ADC, digital filter, DAC with > dataflow chart like this: > > audio_signal1->ADC->digital filter->DAC->audio_signal2 > > digital filter has to be controlled from PC host running Windows > through a GUI written in Visual Basic. > > Which software from Xilinx is more appropriate to design such system - > WebPack ISE or EDK? Hi Vagant, I would use ISE with MACFIR filter core on a OpalKelly XEM3001 board. XEM3001 has a very easy to use USB2.0 interface. Add ons (ADC and DAC) should have parallel bus and easy handshaking to ease FPGA communication. If you are a beginner embedded design is an overkill. Cheers, GuruArticle: 125330
On Sep 30, 4:47 am, Tommy Thorn <tommy.th...@gmail.com> wrote: > > You may use GCC compiler with specially build back-end for your > > processor, that's how it done for Nios II.http://en.wikipedia.org/wiki/GNU_Compiler_Collection#Back_end > > Of course, but that's a lot more work than it sounds. You'll need to > add support for you architecture to binutils. And test it. Not necessarily. If you already have an assembler, you can have gcc stop with assembly output, no binaries involved. And writing a primitive assembler is actually not that bad, once you've seen the code for one to get an idea of how to tackle the problem. > Then write a new backend to GCC. And test it. Yes, that's the part that can't be avoided, except as you observed to the degree to which you can find one for something similar to your processor and use that as a starting point. >GDB also. Only if you want it. There are other ways to debug code too, which do work even if being more primitive. The decision to invest work in getting a debugger going would depend a lot on how much need you expected to have for it. >Finally you need to port a libc, like glibc or newlib. Embedded work does not necessarily involve a standard c library. > For many architectures, writing the softcore implementation is much less work > than writing the software tool chain support. Agreed. When I did it, I had an allegedly working primitive version of gcc already available, which only needed some fixing.Article: 125331
Hi, Does anyone know which algorithm or scheme is used by Quartus to compress FPGA configuration files such as SOF or RBF (raw binary file)? Thanks, JasonArticle: 125332
On Oct 21, 1:26 pm, Wei Wang <camww...@gmail.com> wrote: > Hi, > > Just wondering what could go wrong when synthesizing memories (i- > cache, d-cache, and write buffer) of microprocessors on fpga Xilinx > Virtex 5? Thanks! > > Wei The biggest thing to go wrong would be synthesizing memories on a Virtex5. You want your code to -infer- memories, not synthesize them. G.Article: 125333
>Does anyone know which algorithm or scheme is used by Quartus to >compress FPGA configuration files such as SOF or RBF (raw binary >file)? Even if the method were public: * Altera could change it from one device to another. * What good would it do you to know?Article: 125334
On Oct 22, 11:06 am, MikeShepherd...@btinternet.com wrote: > >Does anyone know which algorithm or scheme is used by Quartus to > >compress FPGA configuration files such as SOF or RBF (raw binary > >file)? > > Even if the method were public: > > * Altera could change it from one device to another. > * What good would it do you to know? I'll try to address your questions, but I get the feeling you don't have the answer I'm looking for. > * Altera could change it from one device to another. Ok, then lets narrow it down to Cyclone devices. > * What good would it do you to know? Enough to bother asking here ;) Given the amount of lossless compression schemes out there, I doubt Altera would want to reinvent the wheel. But I'm hoping someone has already gone through the exercise of figuring out the formatting - it would save me some time. Regards, JasonArticle: 125335
> > You want your code to -infer- memories, not synthesize them. > Generally I agree with that, but for some advanced features (different input/output data widths, etc.) instantiation is the only way to do it with built in logic. As my English teacher taught me, "your code implies memories, the synthesis tool infers memories", but nobody bothers with that distinction anymore... AndyArticle: 125336
>>> Does anyone know which algorithm or scheme is used by Quartus to >>> compress FPGA configuration files such as SOF or RBF (raw binary >>> file)? >> * What good would it do you to know? >Enough to bother asking here ;) It's difficult to express any enthusiasm when your interest appears to be academic. Quartus can compress a .SOF file for you. The device can unravel the result. Why would you want to do either of these yourself? If you tell us what your real problem is, it can be better addressed. Otherwise, some kind person will make what they think is a helpful contribution, to which you will then reply "Ah, but what I really want is...". So, why the secrecy? > I'm hoping someone has already gone through the exercise > of figuring out the formatting The only way to know the algorithm reliably is if Altera publish it. Maybe you can take a bunch of example files (maybe a million of them) and work out a conversion algorithm that works for all those files, but that doesn't mean it will work for any possible file. There is an infinite number of algorithms, all of which will work with the example files but none of which are correct. So, even if someone tells you that they have "figured it out", you can't rely on what they tell you. So, you need to ask Altera. If their reply is "we don't publish that information", you're stuck. MikeArticle: 125337
Markus wrote: > Neil Steiner schrieb: >> I would like to prevent GLOBAL_LOGIC0 and GLOBAL_LOGIC1 nets from >> stealing unused slices in a particular region. I don't mind if those or >> other nets pass through the region, but the logic within the region must >> remain untouched. >> >> Does anybody know how this might be accomplished? This is under ISE/EDK >> 8.1. I'm not presently using the PR flow, and would rather not use it >> if there is any alternate way of protecting the slices. >> >> (I did try defining an AREA_GROUP with attributes PLACE=CLOSED and >> MODE=RECONFIG, but that made no difference, either because the tools >> think these nets are exempt, or because I'm not using the PR flow.) > > Can you feed the GLOBAL_LOGIC0 and GLOBAL_LOGIC1 signals via ports (and bus > macros) into your module? Probably you have to modify the .edf files, > because the synthesis tool introduces some vcc/gnd symbols. I think we may be talking about different things. I'm not using the PR flow, so there are neither modules nor bus macros involved. The GLOBAL_LOGIC0 and GLOBAL_LOGIC1 nets originate with map, if I understand correctly. These are compound nets with multiple separate drivers and sinks, and par decides that it is free to steal unused slices for the drivers. That's the root of my problem: par using slices in an area that I want protected. As I mentioned initially, I don't mind at all if nets pass through my region; I just don't want any of its logic used.Article: 125338
jtang@magma.ca wrote: > Given the amount of lossless compression schemes out there, I doubt > Altera would want to reinvent the wheel. But I'm hoping someone has > already gone through the exercise of figuring out the formatting - it > would save me some time. I don't know what Altera does, but I would suppose it's pretty similar to what Xilinx does, and what they do is not a real compression at all. The configuration is written to the fpga in frames, and when some logic is not used, you get unused, empty frames. All the "compression" really does is not to put those empty frames in the bitstream, that's it, no Huffman-coding or Lempel-Ziv or whatever. That's why the FPGA can "decompress" it on-the-fly without too much of a hassle. I doubt Altera does it a lot differently... HTH, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 125339
Vagant wrote: > Which software from Xilinx is more appropriate to design such system - > WebPack ISE or EDK? EDK is not a stand-alone software, you need ISE for it to work. That said: - ISE is used for everything you need to do to get a bitfile for the FPGA in the first place: synthesis, map, place and route. - EDK is used for building FPGA system-on-chips with embedded microprocessors like MicroBlaze or the embedded PowerPC in certain Xilinx devices. EDK is more or less optional: It simplifies the task of building complex designs that include microprocessors. HTH, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 125340
On Oct 22, 1:52 pm, Sean Durkin <news_oc...@durkin.de> wrote: > jt...@magma.ca wrote: > > Given the amount of lossless compression schemes out there, I doubt > > Altera would want to reinvent the wheel. But I'm hoping someone has > > already gone through the exercise of figuring out the formatting - it > > would save me some time. > > I don't know what Altera does, but I would suppose it's pretty similar > to what Xilinx does, and what they do is not a real compression at all. > > The configuration is written to the fpga in frames, and when some logic > is not used, you get unused, empty frames. All the "compression" really > does is not to put those empty frames in the bitstream, that's it, no > Huffman-coding or Lempel-Ziv or whatever. That's why the FPGA can > "decompress" it on-the-fly without too much of a hassle. > > I doubt Altera does it a lot differently... > > HTH, > Sean > > -- > My email address is only valid until the end of the month. > Try figuring out what the address is going to be after that... Thanks Sean, Makes a lot of sense. I'll look into that. JasonArticle: 125341
Antti wrote: > On 21 Okt., 22:26, Wei Wang <camww...@gmail.com> wrote: > >>Hi, >> >>Just wondering what could go wrong when synthesizing memories (i- >>cache, d-cache, and write buffer) of microprocessors on fpga Xilinx >>Virtex 5? Thanks! >> >>Wei > > > anything ;) > You beat me to it! Absolutely, where do you PLAN to put your mistakes?! JonArticle: 125342
Il 22/10/2007 9.49, taco ha scritto: > Antonio Pasini wrote: > There are several examples to be found on internet. Did you type it in > google before asking here? > One example is: > http://www.xilinx.com/bvdocs/appnotes/xapp616.pdf (title: Huffman coding) > taco > > > >>> >>> I've been looking at available VHDL/Verilog implementations of huffman >>> coders. It appears that all currently available implementations use a >>> fixed codebook (e.g. the one specified in the MPEG standard) for I suppose the OP googled a bit before asking here. At least, I did. The OP asked for a *dynamic table* huffman encoder. Specifically, not a fixed table encoder, as the XAPP616 do (uses MPEG table, as I understand it).Article: 125343
On Oct 22, 9:16 am, Andy <jonesa...@comcast.net> wrote: > > You want your code to -infer- memories, not synthesize them. > > Generally I agree with that, but for some advanced features (different > input/output data widths, etc.) instantiation is the only way to do it > with built in logic. > > As my English teacher taught me, "your code implies memories, the > synthesis tool infers memories", but nobody bothers with that > distinction anymore... > > Andy OK, let's try it this way: You want your code to cause the synthesizer to infer memory, not synthesize it. Failing that, instantiate it directly. Better? G.Article: 125344
FYI: http://www.google.com/patents/pdf/Data_compression_and_decompression_techn.pdf Sean gets a gold star for being helpful.Article: 125345
"Vagant" <vladimir.v.korostelev@rambler.ru> wrote in message news:1193026963.417543.4930@y27g2000pre.googlegroups.com... > Hello, > > I want to design a system which includes ADC, digital filter, DAC with > dataflow chart like this: > > audio_signal1->ADC->digital filter->DAC->audio_signal2 > > digital filter has to be controlled from PC host running Windows > through a GUI written in Visual Basic. > > Which software from Xilinx is more appropriate to design such system - > WebPack ISE or EDK? > Do you know which FPGA you will be using? In any case the main question you need to answer is how precisely you are going to control the filter. If you decide that it would be beneficial to have a CPU running in your FPGA, then EDK will be a very useful addition to ISE, which you will need in any case. When it comes to actually using EDK you will have an option of creating your top level project in either ISE or EDK. I think for a project as you describe it is easier to have top-level project in ISE, but it is really a matter of taste. /MikhailArticle: 125346
On 22 Okt., 20:11, Jon Elson <el...@wustl.edu> wrote: > Antti wrote: > > On 21 Okt., 22:26, Wei Wang <camww...@gmail.com> wrote: > > >>Hi, > > >>Just wondering what could go wrong when synthesizing memories (i- > >>cache, d-cache, and write buffer) of microprocessors on fpga Xilinx > >>Virtex 5? Thanks! > > >>Wei > > > anything ;) > > You beat me to it! Absolutely, where do you PLAN to put your mistakes?! > > Jon ROTFL eh, really there are TOO MANY things that can go wrong. also the OP question was really too generic :) the frequency of the mistake is reverse proportional to the time left to the deadline hm, not very elegantly said, but think some will agree to that. extreme TTM pressure will in most cases cause more mistakes to be done. there is nothing wrong making mistakes, what counts is ability to find and fix them quick no matter the deadline pressure and hopefully not to repeat them too often ;) so what can go wrong? if you are doing some own soft-core for Virtex-5 ? well how old is EDK? version is 9.2 now. I started to work and _fight_ with the grandpa of EDK - a product called V2PDK. EDK has evolved great deal. but EDK 9.1SP2 can still not initialize a block of RAM when the size of it is say 24KB. If those 24KB are all you have and you need all of that, but EDK 9.1SP2 is only able to initialize the first 16K and not the rest to due the BMM mapping bug?? this means that the thing with SoC memory support aint so easy, or that hmm that Xilinx is doing a VERY BAD job at it, whatever you prefer. if you start from scratch, you will certainly get something wrong. this is what was the reasoning behind "anything" AnttiArticle: 125347
Hi, I'm trying to control a SDR SDRAM (Micron 64Mbit chip) using an Altera DE2 board. I've gotten the hardware interface squared away (thanks everyone for your help!). Now it's the tricky stuff. Any one have an idea how I can change the refresh rate while the RAM is in operation? I have the DRAM interface built using the SOPC builder that comes with Quartus II using the NIOS II system. I know you can change the refresh rate during the build but I need a way to change the refresh rate during operation. The only thing I can think of is maybe change the clock speed? I have it running off a 50Mhz clock.... Thanks, EricArticle: 125348
Neil Steiner schrieb: > Markus wrote: >> Neil Steiner schrieb: >>> I would like to prevent GLOBAL_LOGIC0 and GLOBAL_LOGIC1 nets from >>> stealing unused slices in a particular region. I don't mind if those or >>> other nets pass through the region, but the logic within the region must >>> remain untouched. >>> >>> Does anybody know how this might be accomplished? This is under ISE/EDK >>> 8.1. I'm not presently using the PR flow, and would rather not use it >>> if there is any alternate way of protecting the slices. >>> >>> (I did try defining an AREA_GROUP with attributes PLACE=CLOSED and >>> MODE=RECONFIG, but that made no difference, either because the tools >>> think these nets are exempt, or because I'm not using the PR flow.) >> >> Can you feed the GLOBAL_LOGIC0 and GLOBAL_LOGIC1 signals via ports >> (and bus >> macros) into your module? Probably you have to modify the .edf files, >> because the synthesis tool introduces some vcc/gnd symbols. > > I think we may be talking about different things. I'm not using the PR > flow, so there are neither modules nor bus macros involved. > > The GLOBAL_LOGIC0 and GLOBAL_LOGIC1 nets originate with map, if I > understand correctly. These are compound nets with multiple separate > drivers and sinks, and par decides that it is free to steal unused > slices for the drivers. That's the root of my problem: par using slices > in an area that I want protected. As I mentioned initially, I don't > mind at all if nets pass through my region; I just don't want any of its > logic used. I think there is nothing like a simple area group constraint that solves your problem. Maybe you can play with you netlists and convert them from .ncd to .xdl format (and back again) to manipulate them. You are correct, GLOBAL_LOGIC0 and GLOBAL_LOGIC1 nets originate with map. Map creates only one net for power and one for ground signals. I think at this point, the nets have no driving logic. The par tool splits those nets up into smaller nets, to achieve better routing results and adds driving logic. In most cases, GLOBAL_LOGIC1_xx nets are driven by local VCC resources that reside in each CLB. GLOBAL_LOGIC0_xx nets are driven by LUTs (extra slices) and you want to prevent them to get placed in your region. It is quite cumbersome, but you might be able to move them away in the FPGA_editor. -MarkusArticle: 125349
<sendthis@gmail.com> wrote in message news:1193118296.434575.124270@k35g2000prh.googlegroups.com... > Hi, > > I'm trying to control a SDR SDRAM (Micron 64Mbit chip) using an Altera > DE2 board. I've gotten the hardware interface squared away (thanks > everyone for your help!). > > Now it's the tricky stuff. Any one have an idea how I can change the > refresh rate while the RAM is in operation? > The most obvious question would be 'Why?' > I have the DRAM interface built using the SOPC builder that comes with > Quartus II using the NIOS II system. > That will limit your options (as would probably most other vendor IP DRAM controllers). > I know you can change the refresh rate during the build but I need a > way to change the refresh rate during operation. The only thing I can > think of is maybe change the clock speed? I have it running off a > 50Mhz clock.... > A simpler way would be to simply have a DRAM controller that has an explicit 'Refresh Request' input that would cause the controller to perform a refresh. Then connect that input up to any programmable timer or other logic that you would like to use. Changing the clock rate would be far down on my list of ways to accomplish your goal....but again, it begs the original question about why you would want to change the refresh rate dynamically at all. KJ
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