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Thanks. In Xcell Journal the proposed tool are "function-specific" or oriented to Hardware Acceleration. I'm looking for a work flow to develop generel purpose FPGA function, starting from high level description. For example I'd like to start from "C-model" or "MATLAB model" or "?!? model" and by using efficent compiler obtain a synthesizable RTL code. I don't know this world (I always used VHDL or block diagram)...plese be patient! thanks, thanksArticle: 125176
On Oct 17, 3:38 pm, mh <moazzamhuss...@gmail.com> wrote: > On Oct 16, 9:42 pm, morphiend <morphi...@gmail.com> wrote: > > > > > > > On Oct 16, 11:30 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > On 16 Okt., 17:26, morphiend <morphi...@gmail.com> wrote: > > > > > On Oct 16, 5:21 am, avrba...@hotmail.com wrote: > > > > > > On 16 Okt., 10:17, Laurent Pinchart <laurent.pinch...@skynet.be> > > > > > wrote: > > > > > > > Antti wrote: > > > > > > > On 16 Okt., 09:51, Laurent Pinchart <laurent.pinch...@skynet.be> > > > > > > > wrote: > > > > > > >> Antti wrote: > > > > > > >> > Xilinx Spartan3A on custom PCB. > > > > > > >> > was working ok > > > > > > >> > was stressed VCCINT=1.8V (regulator IC current limit 150ma) > > > > > > >> > it does configure ok from external configuration memory > > > > > > > >> > JTAG scan returns JTAGID from Virtex-II family. > > > > > > > >> > what is wrong? > > > > > > > >> Delays in the JTAG chain that shift the data by 1 bit ? Was the JTAGID > > > > > > >> manufacturer field still the Xilinx ID ? > > > > > > > >> Laurent Pinchart > > > > > > > > JTAG ID returned > > > > > > > vendor Xilinx > > > > > > > family Virtex-II > > > > > > > device 0 (invalid) > > > > > > > > this same (wrong!) JTAGID returned all the time > > > > > > > TDO driven by more than one component ? If two Xilinx parts drive TDO in > > > > > > sync (instead of being properly chained) conflicts will occur for the > > > > > > family and device ID by not the vendor ID. > > > > > > > Laurent Pinchart- Zitierten Text ausblenden - > > > > > > > - Zitierten Text anzeigen - > > > > > > single IC chain > > > > > Single IC chain, but is there more than one entity on the chain, say a > > > > V2 before/after it. If so, the spartan could have stuck itself in > > > > constant pass-through and the other device was the only one responding > > > > on the chain. > > > > > -- Mike- Zitierten Text ausblenden - > > > > > - Zitierten Text anzeigen - > > > > single chain, single TAP entity in the chain > > > > Antti > > > Is it possible that voltage feed for the ID code is sourced from two > > different locations inside the FPGA and that the first part of the ID > > is generated properly but the latter becomes erased/garbled?- Hide quoted text - > > > - Show quoted text - > > Recheck decoupling capacitors and power destribution on the board. > if you want to avoid this error, assign boundary scan descriptive > language file (of spartan 3A) to FPGA in IMPACT. > > Hope it won't help.... :-), but i solved my problem this way. > > MH- Hide quoted text - > > - Show quoted text - And yes, I forgot, change the computer or reintall Windows, (if you are using it)......... A logical solution to an illogical problem....Article: 125177
On 17 Okt., 12:38, mh <moazzamhuss...@gmail.com> wrote: > On Oct 16, 9:42 pm, morphiend <morphi...@gmail.com> wrote: > > > > > > > On Oct 16, 11:30 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > On 16 Okt., 17:26, morphiend <morphi...@gmail.com> wrote: > > > > > On Oct 16, 5:21 am, avrba...@hotmail.com wrote: > > > > > > On 16 Okt., 10:17, Laurent Pinchart <laurent.pinch...@skynet.be> > > > > > wrote: > > > > > > > Antti wrote: > > > > > > > On 16 Okt., 09:51, Laurent Pinchart <laurent.pinch...@skynet.be> > > > > > > > wrote: > > > > > > >> Antti wrote: > > > > > > >> > Xilinx Spartan3A on custom PCB. > > > > > > >> > was working ok > > > > > > >> > was stressed VCCINT=1.8V (regulator IC current limit 150ma) > > > > > > >> > it does configure ok from external configuration memory > > > > > > > >> > JTAG scan returns JTAGID from Virtex-II family. > > > > > > > >> > what is wrong? > > > > > > > >> Delays in the JTAG chain that shift the data by 1 bit ? Was the JTAGID > > > > > > >> manufacturer field still the Xilinx ID ? > > > > > > > >> Laurent Pinchart > > > > > > > > JTAG ID returned > > > > > > > vendor Xilinx > > > > > > > family Virtex-II > > > > > > > device 0 (invalid) > > > > > > > > this same (wrong!) JTAGID returned all the time > > > > > > > TDO driven by more than one component ? If two Xilinx parts drive TDO in > > > > > > sync (instead of being properly chained) conflicts will occur for the > > > > > > family and device ID by not the vendor ID. > > > > > > > Laurent Pinchart- Zitierten Text ausblenden - > > > > > > > - Zitierten Text anzeigen - > > > > > > single IC chain > > > > > Single IC chain, but is there more than one entity on the chain, say a > > > > V2 before/after it. If so, the spartan could have stuck itself in > > > > constant pass-through and the other device was the only one responding > > > > on the chain. > > > > > -- Mike- Zitierten Text ausblenden - > > > > > - Zitierten Text anzeigen - > > > > single chain, single TAP entity in the chain > > > > Antti > > > Is it possible that voltage feed for the ID code is sourced from two > > different locations inside the FPGA and that the first part of the ID > > is generated properly but the latter becomes erased/garbled?- Hide quoted text - > > > - Show quoted text - > > Recheck decoupling capacitors and power destribution on the board. > if you want to avoid this error, assign boundary scan descriptive > language file (of spartan 3A) to FPGA in IMPACT. > > Hope it won't help.... :-), but i solved my problem this way. > > MH- Zitierten Text ausblenden - > > - Zitierten Text anzeigen - and we have another WINNER, I think this answer should already accepted. I have not been able to fix the problem by adding bypass caps, but the issue is: "100MHz noise on VCCINT". a canned oscillator is generating extreme noise that seems to pass all bypass caps.. so what it looks: when supply connected to VCCINT regulator drops, so that VCCINT also drops, then VCCINT > 1.17V bad ID <1.17 maybe Virtex-ID <1V Correct ID it is related to the noise, depending on the probe connections the noise measured was up to 900mV p-p on VCCINT ! strange enough the FPGA seems to configure and work with noise on VCCINT that should make all mess. but the first thing that gets messed seems to be JTAG IDcode readback. what was also strange S3A seemed to work when I measured 0.6V on VCCINT ?? anyway the problem was really "extreme HF noise on VCCINT" so typical supply-bypass problem. so MH please contact me for your prize ;) Antti PS this problem DID NOT happen on the "FPGA miniconsole PCB" ;) but another board.Article: 125178
Hi thank you all for nice feedback and suggestion, for both posted FPGA- quiz's the accepted answers have been posted. Both WINNERs will receive a FPGA miniconsole from Xiltendo a photo from the very first prototype can be seen here http://www.xiltendo.com Antti LukatsArticle: 125179
On Oct 17, 11:40 am, Maroc <md2...@libero.it> wrote: > Thanks. > > In Xcell Journal the proposed tool are "function-specific" or oriented > to Hardware Acceleration. > > I'm looking for a work flow to develop generel purpose FPGA function, > starting from high level description. > > For example I'd like to start from "C-model" or "MATLAB model" or "?!? > model" and by using efficent compiler obtain a synthesizable RTL code. > > I don't know this world (I always used VHDL or block diagram)...plese > be patient! > > thanks, thanks There are a number of tools that operate in the ESL/synthesis space, however, you need a serious EDA budget to get any of these tools. In addition to this these tools are not general purpose and they normally operate well in a particular niche area (e.g. DSP/datapath). You already mentioned Catapult that can synthesize C/C++ to HDL (Verilog/ VHDL), other tools like Catalytic can convert M-Code to C, tools like SystemCrafters/ForteDS/BlueSpec/Agility/etc allow you to go from SystemC to HDL but as I mentioned, these tools are not cheap, work in a niche area and require specialist knowledge to drive them well. Hans www.ht-lab.comArticle: 125180
On Wed, 17 Oct 2007 01:50:15 -0700, Maroc <md2003@libero.it> wrote: >Hello everyone, > >in our company we're using FPGA Advantage of Mentor Graphics to >develop FPGA design. >The Boss ask for an "higher level" work flow than RTL level. It's easier to change your Boss than your toolset. Remind him or her of that from time to time. AllanArticle: 125181
Maroc wrote:
> in our company we're using FPGA Advantage of Mentor Graphics to
> develop FPGA design.
> The Boss ask for an "higher level" work flow than RTL level.
> Do someone give me some information about that?
Consider a change of style.
Single process vhdl design entities:
-- Higher level C-like sequential description.
-- vendor independence
-- variables
-- functions
-- procedures
-- nothing to buy.
Working synthesis examples here:
http://home.comcast.net/~mike_treseler/
-- Mike Treseler
I was going to change my shirt,
but I changed my mind instead.
-- Winnie the Pooh ...
Article: 125182"Antti" <Antti.Lukats@googlemail.com> wrote in message news:1192614128.095221.268270@q5g2000prf.googlegroups.com... > On 17 Okt., 11:22, Douglas <j.d.morri...@gmail.com> wrote: > > and yes the explanation is very plausible, the blink_one_led was > connected to port named UIREG6 of the UJTAG primitive of Actel > ProAsic3 FPGA > > 0x40 was used by the MCU to set the UIREG6 to high, it made the LED2 > on. now the LED off should have been 0x10 (or some other value in > range 16-127) to keep the IR register content in "user instruction" > range, but I accidentitally just cleared bit 6, so the instruction i > sent for LED2 off as 0x00 - EXTEST > > so that explains it all. no mystery. nothing wrong, expect small human > error in some coding. > Antti, Firstly I don't quite understand what the whole story had to do with FPGA, and secondly I among others asked you if the special purpose FPGA pins were involved and you said "no". IMHO, the UIREG6 port of the UJTAG primitive qualifies as such a pin... /MikhailArticle: 125183
Antti <Antti.Lukats@googlemail.com> wrote: > Hi > thank you all for nice feedback and suggestion, for both posted FPGA- > quiz's the accepted answers have been posted. Both WINNERs will > receive a FPGA miniconsole from Xiltendo > a photo from the very first prototype can be seen here > http://www.xiltendo.com Antti: Please summarize the answers. The answer is hard to find in the vast amount of guessing and quoting in the vast amount of postings... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 125184
Once routed, project won't simulate (ModelSim) unless "cleanup project files" is executed. Once simulated, project won't translate, map, ppr, etc until "cleanup project files" is executed (the only files removed here are a .fdo and a .wlf file). Anybody know what could be causing this? Its not a show stopper, but it's annoying. Xilinx ISE 9.2i with SP2 on a windows XP PC Thanks DanArticle: 125185
paragon.john@gmail.com wrote: > > This a digital signal processing application done mainly in System > Generator. > There is one "main" clock domain where all of the critical processing > is done. There are domains synchronous to this clock made using clock > enables (in System Generator) and also divided clocks that are output > by a DCM (in the VHDL that I wrap the sysgen design). I believe that > all of this is constrained and controlled properly. > > There is a asynchronous second clock domain that is used purely for > command and control of the design via setting and reading registers. > The signals crossing this domain would not affect the performance of > the design. The type of simulation mismatch I am seeing is the > "performance" of the algorithm I am implementing. The algorithm > works, just not as well as I see when I run simulations. > > I can't use ChipScope, unfortunately. I can get at some test signals > via a logic analyzer, but obviously not with the flexibility and ease > of chipscope. > I have not used system generator, and I don't know what you mean when you say there is a performance mismatch between the simulation and the hardware. I assume you are you simulating the VHDL/Verilog code of the complete system, in which case there should be an exact one to one match between the sim and the system. You are saying these don't match exactly? What I generally do in signal processing applications is to have commandable bits that steer different intermediate results to the output. I typically leave this even in the final circuit, since it adds very little complexity. One bit will send the raw input data to the output, another might send the output of the first FFT, another the output of intermediate processed FFT data, and no bits means the final processed data. That would allow narrowing down the location of the problem, and that might give a clue to what kind of problem there is. Sort of a poor man's substitute for chipscope, though.Article: 125186
Hello all,
I'm using EDK 9.1.02i to develop an application for the Xilinx
University Program Virtex-II Pro board.
I created a bare MicroBlaze project and ran the following program on it:
#include <stdio.h>
int main(void) {
unsigned int i = 10;
xil_printf("Signed: %d Unsigned: %u\r\n",(int) i, i);
return 0;
}
The output (over the serial port) was this:
Signed: 10 Unsigned:
Apparently xil_printf() ignores the %u format specifier. What's going on?
--
Philip Potter pgp <at> doc.ic.ac.uk
Article: 125187When generating EDIF from Synplify, I frequently notice buffers (LUT1_L primitives with INIT property of 2) inserted in the circuit. Does anybody know why the tool is doing this and/or whether it can be disabled? I realize that the presence of buffers with local outputs can suggest some packing hints, but I've also seen the likes of a LUT1_L buffer driving nothing but an inverter, in which case the buffer seems superfluous and the packing assumption falls apart. I'm a little uncertain on how to proceed with the buffers (32 of them out of 155 total cells in a 32-bit counter circuit), because I am using the generated EDIF as an input to custom CAD tools. In general I just trim these buffers -- I don't want to allocate LUTs that serve only as glorified pass-throughs -- but I'm still wondering why they're there in the first place, and whether they are actually supposed to serve some useful purpose. If I didn't know that Synplify generates high quality output, I would be much less puzzled. This is with Synplify Pro 8.4, in projects targeting an XC2VP30-6-FF896.Article: 125188
MM wrote: > "Antti" <Antti.Lukats@googlemail.com> wrote in message > news:1192614128.095221.268270@q5g2000prf.googlegroups.com... > >>On 17 Okt., 11:22, Douglas <j.d.morri...@gmail.com> wrote: >> >>and yes the explanation is very plausible, the blink_one_led was >>connected to port named UIREG6 of the UJTAG primitive of Actel >>ProAsic3 FPGA >> >>0x40 was used by the MCU to set the UIREG6 to high, it made the LED2 >>on. now the LED off should have been 0x10 (or some other value in >>range 16-127) to keep the IR register content in "user instruction" >>range, but I accidentitally just cleared bit 6, so the instruction i >>sent for LED2 off as 0x00 - EXTEST >> >>so that explains it all. no mystery. nothing wrong, expect small human >>error in some coding. >> > > > Antti, > > Firstly I don't quite understand what the whole story had to do with FPGA, > and secondly I among others asked you if the special purpose FPGA pins were > involved and you said "no". IMHO, the UIREG6 port of the UJTAG primitive > qualifies as such a pin... Let's just hope Antti is not let anywhere near setting Exam or Interview questions any time soon ! :) -jgArticle: 125189
Antti wrote: > Hi > > thank you all for nice feedback and suggestion, for both posted FPGA- > quiz's the accepted answers have been posted. Both WINNERs will > receive a FPGA miniconsole from Xiltendo > > a photo from the very first prototype can be seen here > http://www.xiltendo.com Even the web page is like an Antti contest! :) Key customer questions are inside the puzzle : ** What exactly does this module do (and NOT do) ? ** Why sort of user would want one ? ** Load from CF is nifty, that just leaves Code -> CF .... -jgArticle: 125190
On Oct 16, 5:31 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > paragon.j...@gmail.com wrote: > > There is one "main" clock domain where all of the critical processing > > is done. There are domains synchronous to this clock made using clock > > enables (in System Generator) and also divided clocks that are output > > by a DCM (in the VHDL that I wrap the sysgen design). I believe that > > all of this is constrained and controlled properly. > > Why not do everything with clock enables > and eliminate the divided clocks and > their constraints? I am using clock enables as much as possible, however, since the output of the design is connected to a piece of test equipment that requires a clock, I have to use the divided clock at the very end of the design before outputting the data (outside of any processing loops). > > > There is a asynchronous second clock domain that is used purely for > > command and control of the design via setting and reading registers. > > The signals crossing this domain would not affect the performance of > > the design. > > Unless one of the async registers > tries to tell the design > to start, stop, or turn left, sending > the machine into and "impossible" state > that simulation can't see. I don't have any way of removing this clock domain crossing. I double register the signals after they cross the domain boundary (data only crosses in one direction). Maybe there is something I am forgetting, but I thought this would be sufficient for this type of design. > > > The type of simulation mismatch I am seeing is the > > "performance" of the algorithm I am implementing. The algorithm > > works, just not as well as I see when I run simulations. > > If it doesn't match the simulation exactly > something is very wrong. > > > I can't use ChipScope, unfortunately. I can get at some test signals > > via a logic analyzer, but obviously not with the flexibility and ease > > of chipscope. > > A test point is much better than nothing. > Good luck. Yes, yes it is. > > -- Mike TreselerArticle: 125191
On Oct 17, 4:29 am, xenix <last...@gmail.com> wrote: > Hello all:) > > I am running a design in edk 6.1 version. and comes up with > > " Makefile cannot be saved to run process. Please ensure IPs in MHS > file point to the right MPDs". > > The MHS doesnt contain info about MPDs.. > > What i have to do on that? > > regards Actually, the MHS has ALL the info on the MPDs :). Since the MHS file is the single repository for the IP being used to create the system, each INSTNACE will have a corresponding MPD file. The MPD file that matches to an INSTANCE is easily decipherable. Let's take a look at an example: BEGIN plb_central_dma PARAMETER INSTANCE = dma_plb PARAMETER HW_VER = 1.00.a PARAMETER C_BASEADDR = 0xDC000000 PARAMETER C_HIGHADDR = 0xDC0000FF BUS_INTERFACE MSPLB = plb_1 PORT IP2INTC_Irpt = dma_int END Now for this instance: dma_plb it's being mapped to a plb_central_dma and that version number is 1.00.a. Therefore there will need to be a directory: plb_central_dma_1_00_a in one of the pcore directories (either global, or project local). The format of that directory is: \data \doc \hdl In the data directory, there should be plb_central_dma_v2_1_0.mpd file. (The v2_1_0 may change w/ EDK 6.1 since that's older than any of the version I've used). The content of that mpd file will start with a "BEGIN plb_central_dma". There may be #-comments before it, but the important part is that name. That's how EDK correlates the MPD to the core. And the version is correlated via pcore directory name. Does that make sense? -- MikeArticle: 125192
On Oct 17, 9:09 am, Mike Treseler <mike_trese...@comcast.net> wrote: > Maroc wrote: > > in our company we're using FPGA Advantage of Mentor Graphics to > > develop FPGA design. > > The Boss ask for an "higher level" work flow than RTL level. > > Do someone give me some information about that? > > Consider a change of style. > Single process vhdl design entities: > -- Higher level C-like sequential description. > -- vendor independence > -- variables > -- functions > -- procedures > -- nothing to buy. > Working synthesis examples here:http://home.comcast.net/~mike_treseler/ > > -- Mike Treseler > > I was going to change my shirt, > but I changed my mind instead. > -- Winnie the Pooh ... While it is possible to raise the level of abstraction using single processes, variables, functions, etc., the description must still be explicitly about what happens in each and every clock cycle. Even some simple cases of retiming can allow one to describe an operation that will take place over a specific number of clock cycles, but you have little or no control over the resulting division of the circuit across clock cycles. Catapult and other C or matlab tools allow you to take an untimed (no clock cycles yet) algorithm and play around with parallelism and pipelining to alter the latency/throughput (and area/speed) of the implementation, without touching the C code (ok, some major changes require modifying the C code). They do this by presenting you with various views of the algorithm (resources, gant charts, etc.) and allow you to manipulate those views by adjusting parameters (at least that's how Catapult works). The really nice thing about it is they automagically generate the control logic for all the scheduling, multiplexing, etc. That said, Catapult is clearly a datapath tool; it does not handle arbitrary control logic very well. But you can specify different types of interfaces (dual/single port memory, fifo, streaming, registers, etc.) and handshaking, and it will create and bolt that onto the algorithmic implementation for you. AndyArticle: 125193
On 17 Okt., 20:41, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Antti wrote: > > Hi > > > thank you all for nice feedback and suggestion, for both posted FPGA- > > quiz's the accepted answers have been posted. Both WINNERs will > > receive a FPGA miniconsole from Xiltendo > > > a photo from the very first prototype can be seen here > >http://www.xiltendo.com > > Even the web page is like an Antti contest! :) > > Key customer questions are inside the puzzle : > > ** What exactly does this module do (and NOT do) ? > > ** Why sort of user would want one ? > > ** Load from CF is nifty, that just leaves Code -> CF .... > > -jg Jim, give an old man an break. the EXTEST voppla story made me pretty upset, spent several perfectly good working hours on that. the Picolone is just a nice FPGA gadget. it reconfigure itself, and be what you Jim tell him. it will be bundled with basic boot system to select files for configuration. I had actually no intention to release any info so soon, but as big mouth made some prize offer so i placed some info online as well, withing 12 minute limit I had for that AnttiArticle: 125194
Hi ho here is code process (m_sck) begin if (m_sck'event and m_sck=3D'1') then do64(62 downto 0) <=3D do64(62 downto 0) & M_DI; end if; end process; LEDS <=3D do64s(63 downto 60); M_DI, M_SCK are driven by external MCU SPI interface. the MCU send either 0x90 00 00 00 00 00 00 00 or 0x00 00 00 00 00 00 00 00 symptoms: when FPGA is not full, the LED blink, all OFF, 1-0-0-1 when the FPGA is full, there will blink all off, then 1-1-0-1 repeating same pattern, not randomness changing maxfanout in synplify will change the erratic behaviour but I have not managed to get the shift register ever work in case where FPGA is really full. SPI clock is 4MHz (or lower doesn seem to make any difference) this time I am giving up, that is not trying to force the shift register to work, but find solution that works the problem only occourcs on Actel FPGA, and yes yes it works in s=EDmulation it works in xilinx FPGA, etc.. Antti who this time really doesnt know the solution :(Article: 125195
On 17 Okt., 17:43, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> wrote: > Antti <Antti.Luk...@googlemail.com> wrote: > > Hi > > thank you all for nice feedback and suggestion, for both posted FPGA- > > quiz's the accepted answers have been posted. Both WINNERs will > > receive a FPGA miniconsole from Xiltendo > > a photo from the very first prototype can be seen here > >http://www.xiltendo.com > > Antti: Please summarize the answers. The answer is hard to find in the vast > amount of guessing and quoting in the vast amount of postings... > -- > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Uwe you are very right quiz1: 2 LEDs, one seems to have coupling to another, despite the lack of dependancy in FPGA between driving signals. answer: EXTEST, signal driving LED2 was derived from the content of JTAG IR scan register, the other LED was exhibiting "wrong" behaviour due to the EXTEST instruction accidentially shifter into the TAP IR. quiz2: Spartan3A wrong JTAG ID readback answer: high frequency noise on VCCINT to all who responded, I tried to be fair and to answer all direct questions without giving too much extra information. It can be that i overlooked something, I will look the replies over to see if I was too unfair to some poster. AnttiArticle: 125196
Neil Steiner wrote: > When generating EDIF from Synplify, I frequently notice buffers (LUT1_L > primitives with INIT property of 2) inserted in the circuit. Does > anybody know why the tool is doing this and/or whether it can be disabled? > > I realize that the presence of buffers with local outputs can suggest > some packing hints, but I've also seen the likes of a LUT1_L buffer > driving nothing but an inverter, in which case the buffer seems > superfluous and the packing assumption falls apart. > > I'm a little uncertain on how to proceed with the buffers (32 of them > out of 155 total cells in a 32-bit counter circuit), because I am using > the generated EDIF as an input to custom CAD tools. In general I just > trim these buffers -- I don't want to allocate LUTs that serve only as > glorified pass-throughs -- but I'm still wondering why they're there in > the first place, and whether they are actually supposed to serve some > useful purpose. If I didn't know that Synplify generates high quality > output, I would be much less puzzled. > > This is with Synplify Pro 8.4, in projects targeting an XC2VP30-6-FF896. While the INIT property of 2 leaves me a little confused (I would expect 1 or 0 for a LUT1) the presence of "glorified pass-through" elements are often required to drive carry chains properly. Do you know the structure of the slice very well? I have a graphic of the slice internals pinned to my cubicle wall to refer to anytime I see something odd in my Synplify HDL Analyst technology view, usually because my coding comes up with something that doesn't fit the way I expect with the tool most often doing the right thing for the RTL I've presented. I usually just need to tweak my thinking and the code to get the "clean" results I thought I'd get the first round. - John_HArticle: 125197
Hi alls, I've a question which seems stupid, but I don't find answer anywhere.. ( maybe I don't search correctly ) What is the difference between XC5VLX50-1FFG676C and XC5VLX50-1FFG676CES ? I don't understand what does 'ES' mean at the end of the FPGA reference .. So, please, if anyone knows.. Thanks by advance, best regards, Michel.Article: 125198
<michel.talon@gmail.com> wrote in message news:1192632888.613296.239720@q5g2000prf.googlegroups.com... > Hi alls, > > I've a question which seems stupid, but I don't find answer anywhere.. > ( maybe I don't search correctly ) > What is the difference between XC5VLX50-1FFG676C and > XC5VLX50-1FFG676CES ? I don't understand what does 'ES' mean at the > end of the FPGA reference .. > > So, please, if anyone knows.. > > Thanks by advance, > > best regards, Michel. > I would bet that is stands for "engineering sample"Article: 125199
On 17 oct, 12:40, Maroc <md2...@libero.it> wrote:
> Thanks.
>
> In Xcell Journal the proposed tool are "function-specific" or oriented
> to Hardware Acceleration.
>
> I'm looking for a work flow to develop generel purpose FPGA function,
> starting from high level description.
>
> For example I'd like to start from "C-model" or "MATLAB model" or "?!?
> model" and by using efficent compiler obtain a synthesizable RTL code.
>
> I don't know this world (I always used VHDL or block diagram)...plese
> be patient!
>
> thanks, thanks
Hi again,
why don't you have a look to AccelDSP Synthesis Tool, from Xilinx?
of course it takes part of your budget, but it's easy to code in
matlab at any description level
you have and interesting discussion on this topic in chapter 11, C/
C++ etc.-Based Design Flows of Clive Maxfield's "the design warriors
guide to fpga's", it might be an article around, you can look for that
using keywords
csb
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