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<mrmoosavi@gmail.com> wrote in message news:d92a0d79-8236-40ec-9791-4e39670cc268@e10g2000prf.googlegroups.com... > On Dec 6, 11:12 pm, KJ <Kevin.Jenni...@unisys.com> wrote: >> On Dec 6, 9:10 am, mrmoos...@gmail.com wrote: >> > - Show quoted text - .. snip > > I do not have any of following folders! > simprim = D:/vendors/Xilinx/mti/simprim > x55 = D:/hdl_designs/x55/work_mti > XilinxCoreLib = D:/vendors/Xilinx/mti/xilinxcorelib > altera_mf = D:/vendors/quartus/mti/altera_mf > mercury = D:/vendors/quartus/mti/mercury > Shared_lib = D:/DEMO/demo_hdl_designer/Shared_lib/work_mti > ?? These are just Modelsim library mappings for my setup. I would suggest you delete the modelsim.ini file and create a new one using the vmap command. Then if required update the file with your primitive library mapping like simprim/lpm etc, this is easily done using the GUI (Right_Mouse_Button in the workspace tab -> new -> library), Hans www.ht-lab.comArticle: 127051
Frank Buss wrote: > I've read the Wikipedia article about Direct Digital Synthesis ( > http://en.wikipedia.org/wiki/Direct_digital_synthesis ) and building a DDS > generator with a FPGA, which interpolates between adjacent entries in the > lookup table, looks like some fun. This is my first try: > > http://it4systems.de/SignalGenerator/doc/index.html > > Maybe when I have some more time, I'll add more features, like a SPI > interface to control it from an external microcontroller and multiple > outputs. > > Any ideas how to improve it? I have read this paper: > > http://www.analog.com/UploadedFiles/Tutorials/450968421DDS_Tutorial_rev12-2-99.pdf > > In this document an Inverse Sinc Filter is mentioned, but without details > about it. Do you know how to implement it? And does it improve the output > of an interpolating generator or is this useful for non-interpolating > generators, only? > Xilinx has a good DDS in their CoreGen library so you could just use that if you need something already completed. The sinx/x filter could be skipped if your DAC sample rate is high enough compared to the DDS frequency. Some DACs also have built-in sinx/x correction. Interpolation in a DDS is usually handled differently than in, say, an interpolation filter. Normally it is done with a Taylor polynomial, which yields much better results than a linear interpolator. The usual problem with a Taylor polynomial is that it requires derivatives of the function. In a DDS, though, the derivitaves of the sine and cosine functions are the very same sines and cosines (and their opposites). So with a BRAM-based lookup table with two read ports, you can read both sine and cosine at the same time, so you effectively also have, for free, the first (and second and third, etc.) derivatives of the outputs. So then with little hardware you can make a first-order Taylor, and with a bit more you could even make a second-order, although rarely is this necessary. I'll send you a Xilinx paper that explains this. It's by Chris Dick and Fred Harris and called "Direct Digital Syhthesis - Some Options for FPGA Implementation". -KevinArticle: 127052
Kevin, Nice work! I had not thought of the problem as inverse operation pairs, but simply as operators for which there was no value of one argument such that the other argument did not still have control of the output; AND, OR, and their derivatives fail that test. Interesting also that, for a single bit, the + and - both reduce to XOR, but for multiple bits the bitwise XOR/XNOR is more efficient, since there is no serial propagation. The result would not always work for reals, since + and - are not always inverse (i.e. if d is small enough relative to qr that qf = d + qr = qr, then qf - qr would be 0, and not d). Therefore the immediate dynamic range of the registered value would be limited artificially. Similarly, true "integer" arithmetic would fail when the range limits were exceeded in qr or qf. You could pad the ranges of the two registers to accommodate. However, if we assume finite "vector-based" arithmetic (that rolls over) then it would work fine without extending the range. On the other hand, vectors already have XOR defined for them... AndyArticle: 127053
"Gabor" <gabor@alacron.com> wrote in message news:c9ad5d2d-41cb-46b5-b7e3-ca2652fef9f3@y5g2000hsf.googlegroups.com... > On Dec 10, 12:38 pm, mozilla <godzilla...@gmail.com> wrote: >> Just recently an error/bug arises in ISE when i go to synthesise a >> design. >> The synthesis will just error without any transcript text. when i >> cleanup the project files and then run XST it synthesises perfectly. >> >> Anyone have the same problem/ found a fix? > > I think you just mentioned the fix: cleanup the project. > > This problem usually occurs if you add/change/delete modules from > the hierarchy. I've also heard of this happening more frequently > with EDK, but I don't use EDK myself. Are you saying you need to > cleanup the project each time you want to rebuild (i.e. no new > modules just some editing of existing modules)? I haven't seen > that happen. > > The other workaround I found was to just start a new project and > include all of my sources from the broken one. That is a real > pain, though. > > Good Luck, > Gabor Yes, I'm seeing the same thing on some projects but not all. My problem is that when I go back and forth between simulation and Xilinx PPR it forces me to cleanup project files before it will run. In other words, if just ran PPR and now I want to simulate it won't, without cleanup. If I have just simuleted, I can't run PPR without cleanup. Its a pain. Anyone got a fix? A rebuild works, but its very painful, and I'm not sure it will work every time. DanArticle: 127054
Sean Durkin wrote: > Hi Ed, > > you wrote: > >> 2) The MGTREFCLK inputs do not have alternative standards so you should >> not attach a IOSTANDARD=LVDS_25 in the UCF constraint. > > So the clock to the GTPs does always have to be LVDS_25, no LVPECL > supported directly, like in the "regular" IOs? So I guess I need > external termination resistors like described in xapp696 if I want to > use a LVPECL clock source for the MGTs? > The MGT REFCLK inputs must be AC coupled and there is an internal bias for optimal performance. This means that either LVDS or LVPECL can be used as inputs so long as the voltage swings comply with Table 17 in the Virtex-5 data sheet: http://www.xilinx.com/support/documentation/data_sheets/ds202.pdf Ed McGettigan -- Xilinx Inc.Article: 127055
axalay wrote: > Thanks. > 1. Yes-I am use FF665 package > 2. This clock is LVDS (UG196 (325mV) AC-coupled > 3. If I write in UCF " INST "serdes/gtpdual1/gtp_dual" LOC = > "GTP_DUAL_X0Y1" ; ", may I do not write in UCF MGTREFCLK pin > locations? > 4. I find what You say in UG196 (v1.3) May 25, 2007 > > Now I have nex question: > ISE give error in Design Hierarchy Analysis: > ERROR:HDLCompilers:87 - "XXX.v" line 33 Could not find module/ > primitive 'gtpdualxxx' > > What files he do not find? > I am understand that: > I must write directory, where ISE may search this files in Syntesis > Option/Verilog Include Directories. > But I dont now - what files he whant.... Your error message is specific to your HDL implementation as the only simulation primitive model that is provided is the GTP_DUAL smartmodel/swift model. There is a chance that you have not correctly installed the GTP_DUAL models, but this should not result in the error message that you are reporting. I would strongly suggest that you use the CoreGen GTP Wizard to create your GTP module. You should run the example implementation top level design through simulation, synthesis and ISE so that you have a known good implementation that you can base your own design work on. BTW: The latest UG196 GTP User Guide is V1.4 Sept 12, 2007 Ed McGettigan -- Xilinx Inc.Article: 127056
On Dec 10, 12:38 pm, John_H <newsgr...@johnhandwork.com> wrote: > On Dec 10, 8:13 am, "theo...@gmail.com" <theo...@gmail.com> wrote: > > > I was wondering if anyone could help me figure out one thing that is > > holding us up for porting some Verilog code that works for Xilinx/ISE > > to Lattice/Synplicity. Specifically, for Xilinx, we use metacomments > > like this to prevent optimization across certain bits of logic: > > > //synthesis attribute keep_hierarchy of mux0 is yes > Use the Synplify help to look up the "syn_hier" directive to figure > out the differences between "firm" and "hard" that could affect your > outcome. Thank you. I will do that. Can you also suggest what to look for for the two other attributes below? // synthesis attribute MAX_FANOUT of ad_oe is 1 // synthesis attribute equivalent_register_removal of stop_oe is "no" Thanks!Article: 127057
On 8 d=E9c, 17:04, Louis Dupont <louis.dup...@gmail.com> wrote: > Hi, > > I ran into a small problem while trying to use a UCF file created for > ISE 8.2 within EDK 9.1. I had a few INSTs and NETs relatively deep > within the design's hierarchy: > > INST "ioring/U_top/u_adc_clk_dcm" FACTORY_JF =3D "ABCD"; > NET "ioring/U_top/sdram_clk_sig" TNM =3D sdramclk; > > I get an error from Xilinx stating it can find neither the instance > nor the net when trying to implement these constraints. Looking > around, I found the solution for the INST using the syntax: > > INST "ioring/*U_top/* u_adc_clk_dcm" FACTORY_JF =3D "ABCD"; > > But It didn't work for the net (sdram_clk_sig is a std_logic signal > within the U_top instance). Anybody knows the correct syntax to access > a net within such hierarchy with Xilinx 9.1? > > Thanks. > > Louis You could try to use FPGA Editor to browse the design and identify the correct name. XST most likely created slightly different names and this is why it's not working anymore. It's a pain but I don't know any other way unfortunately... PatrickArticle: 127058
Hello, I have a simple project in mind and have some GAL16V8 PLD's knocking around, could anyone suggest a design suite that still supports these devices along with an associated url. Many Thanks. Martin CharlwoodArticle: 127059
On Mon, 10 Dec 2007 21:40:06 +0000, Martin Charlwood wrote: > Hello, > I have a simple project in mind and have some GAL16V8 PLD's knocking > around, could anyone suggest a design suite that still supports these > devices along with an associated url. > > Many Thanks. > Martin Charlwood Do you have a PROM burner? The GAL predated incircuit programming, you will need a prom burner that supports the GAL16V8. If you don't have one then you should forget about using your GALs. You will also need ABEL or PALASM, Google for PALASM and ABEL.Article: 127060
On Dec 10, 12:27 pm, "theo...@gmail.com" <theo...@gmail.com> wrote: > On Dec 10, 12:38 pm, John_H <newsgr...@johnhandwork.com> wrote: > > > On Dec 10, 8:13 am, "theo...@gmail.com" <theo...@gmail.com> wrote: > > > > I was wondering if anyone could help me figure out one thing that is > > > holding us up for porting some Verilog code that works for Xilinx/ISE > > > to Lattice/Synplicity. Specifically, for Xilinx, we use metacomments > > > like this to prevent optimization across certain bits of logic: > > > > //synthesis attribute keep_hierarchy of mux0 is yes > > Use the Synplify help to look up the "syn_hier" directive to figure > > out the differences between "firm" and "hard" that could affect your > > outcome. > > Thank you. I will do that. Can you also suggest what to look for for > the two other attributes below? > > // synthesis attribute MAX_FANOUT of ad_oe is 1 > > // synthesis attribute equivalent_register_removal of stop_oe is "no" > > Thanks! I think syn_maxfan gives you your first attribute. The equivalent_register_removal = "no" sounds like syn_preserve = 1. I haven't used XST myself, so I'm guessing by the names. Two identical flops won't be optimized to one, constant registers aren't removed, and register retiming won't affect registers where syn_preserve=1.Article: 127061
"Martin Charlwood" <martincharlwood@hotmail.com> wrote in message news:Wmi7j.85109$EU1.36048@fe1.news.blueyonder.co.uk... > Hello, > I have a simple project in mind and have some GAL16V8 PLD's knocking > around, could anyone suggest a design suite that still supports these > devices along with an associated url. > > Many Thanks. > Martin Charlwood WinCUPLArticle: 127062
General Schvantzkopf wrote: > On Mon, 10 Dec 2007 21:40:06 +0000, Martin Charlwood wrote: > > >>Hello, >>I have a simple project in mind and have some GAL16V8 PLD's knocking >>around, could anyone suggest a design suite that still supports these >>devices along with an associated url. >> >>Many Thanks. >>Martin Charlwood > > > Do you have a PROM burner? The GAL predated incircuit programming, you > will need a prom burner that supports the GAL16V8. If you don't have one > then you should forget about using your GALs. > > You will also need ABEL or PALASM, Google for PALASM and ABEL. Atmel WinCUPL will support the 16V8, as well as 20V8 and 22V10. (Atmel's version is called ATF16V8BQL etc ) As mentioned, you will need a device programmer. -jgArticle: 127063
"Frank Buss" <fb@frank-buss.de> wrote in message news:1pksute7pasie.9eglznqt557g.dlg@40tude.net... > > Any ideas how to improve it? I have read this paper: > Hi Frank, Google for Sunderland algorithm and/or the sine phase difference algorithm. HTH, Syms. http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/702e081f02d6124/fd9afb0c72f61276?lnk=st&q=#fd9afb0c72f61276Article: 127064
John Larkin wrote: > We have 8 channels, which used up all the block rams in the biggest > Spartan. So we could only use 4k points per channel. The interpolation > does have a dramatic effect on near-carrier spurs. We have an option > to turn it off, for situations where the customer wants to make step > edges in an arbitrary waveform... the interpolation turns everything > into slopes. I assume the primary goal of your application was to generate arbitrary waveforms, because for sine and 14 bit output, one table with 51,471 words of size 14 bit is sufficient for max 1 LSB difference for adjacent values, so with using the symmetry of sine you'll need 12,868 words to produce a perfect sine. This is 180,152 bits and would fit in the second smallest Spartan3E, the XC3S250E. But when using 8 channels, it could be difficult for high speed output to use only one lookup table. 8 sine tables would require 1,441,216 bits. This would fit in the EP3C55 Cyclone 3. There is no price for it, but three EP3C25, which would work, too, costs about $135, a bit expensive just for a sine generator :-) Kevin Neilson has sent me a nice paper about Error Feed-Forward DDS, which helps to reduce the error, but I wonder if it would be possible to create a mathematically perfect 24 bit sine output, e.g. with fdlibm of netlib: http://www.netlib.org/fdlibm/k_sin.c There are many muls and adds, but how high do I need the degree of a polynomial to get 24 bit resolution and how do I calculate it? Would be cool to create a pure functional function generator in FPGA, which can produce perfect sine, square, triangle, sawtooth and noise at 24 bit, and with some memory for arbitrary waveforms. Do you think cubic interpolation would help for interpolating the arbitrary waveforms? -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 127065
Symon wrote: > Google for Sunderland algorithm and/or the sine phase difference algorithm. > HTH, Syms. > http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/702e081f02d6124/fd9afb0c72f61276?lnk=st&q=#fd9afb0c72f61276 Do you have some links? I've tried to Google, but found only results for buying documents. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 127066
Hi, I need a PCI parallel port card since the new PC is "legacy free". I use parallel port based JTAG debuggers and programmers for micros (AVRs), CPLDs (Xilinx/Altera/Lattice) and FPGAs (Xilinx/Altera). Which PCI parallel cards work or don't work for you? Tried it under Linux? Seems like most PCI parallel cards are based on chipsets from Netmos -- any luck with these? Thanks.Article: 127067
Kevin Neilson wrote: > So then with little hardware you can make a first-order Taylor, and > with a bit more you could even make a second-order, although rarely is > this necessary. I'll send you a Xilinx paper that explains this. It's > by Chris Dick and Fred Harris and called "Direct Digital Syhthesis - > Some Options for FPGA Implementation". Thanks, the Error Feed-Forward DDS looks interesting. But it is patented: http://www.google.com/patents?id=AAkIAAAAEBAJ&dq=6333649 This is no problem for me, because in Germany you can't patent algorithms and formulaes (at least this is what I know, hope they didn't change it), but would be nice to have a free algorithm, because I plan to publish it on my website, so everyone can use and build it for whatever they want, without the danger of maybe paying licence costs to Xilinx. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 127068
On Tue, 11 Dec 2007 00:41:20 +0100, Frank Buss <fb@frank-buss.de> wrote: >John Larkin wrote: > >> We have 8 channels, which used up all the block rams in the biggest >> Spartan. So we could only use 4k points per channel. The interpolation >> does have a dramatic effect on near-carrier spurs. We have an option >> to turn it off, for situations where the customer wants to make step >> edges in an arbitrary waveform... the interpolation turns everything >> into slopes. > >I assume the primary goal of your application was to generate arbitrary >waveforms, because for sine and 14 bit output, one table with 51,471 words >of size 14 bit is sufficient for max 1 LSB difference for adjacent values, >so with using the symmetry of sine you'll need 12,868 words to produce a >perfect sine. This is 180,152 bits and would fit in the second smallest >Spartan3E, the XC3S250E. But when using 8 channels, it could be difficult >for high speed output to use only one lookup table. 8 sine tables would >require 1,441,216 bits. This would fit in the EP3C55 Cyclone 3. There is no >price for it, but three EP3C25, which would work, too, costs about $135, a >bit expensive just for a sine generator :-) > >Kevin Neilson has sent me a nice paper about Error Feed-Forward DDS, which >helps to reduce the error, but I wonder if it would be possible to create a >mathematically perfect 24 bit sine output, e.g. with fdlibm of netlib: > >http://www.netlib.org/fdlibm/k_sin.c > >There are many muls and adds, but how high do I need the degree of a >polynomial to get 24 bit resolution and how do I calculate it? Would be >cool to create a pure functional function generator in FPGA, which can >produce perfect sine, square, triangle, sawtooth and noise at 24 bit, and >with some memory for arbitrary waveforms. Do you think cubic interpolation >would help for interpolating the arbitrary waveforms? This one http://www.highlandtechnology.com/DSS/V340DS.html does sine-triangle-sawtooth-pwm, with 14 bit dacs, 2K points per channel, 64 MHz dac clock, and uses a smallish fpga. This http://www.highlandtechnology.com/DSS/V346DS.html does 4k points at 128 MHz dac rate, standard waveforms plus arb plus noise. Both have interpolation available. Rams are 16 bits wide to add some headroom for amplitude scaling. Both are primitive relative to the levels you propose. At any decent speed, analog issues (noise, nonlinearity, thd, drift, crosstalk) overwhelm math accuracy, and at 14 dac bits we're already there. At 32 MHz and healthy swings, the thd limit is the output amplifiers, with 50-60 dB tough to hit. But most commercial arbs and RF signal generators have ghastly thd specs, like -30 or even -20 dBc. Your very hint of using non-powers-of-two memory size gives me the willies. JohnArticle: 127069
Gabor wrote: > The other workaround I found was to just start a new project and > include all of my sources from the broken one. That is a real > pain, though. When I was experimenting I found ISE would eat my project or hang eating all the CPU if I wasn't very careful (with 8.2) and I also wanted to swap between architectures. Furthermore the .ise file is not suitable for version control... I did some research and found there is a tool you can use to recreate the ISE file from a plain text file (you lose some info but it is very usable) Create the file foo.npl with the following contents.. # Create the project NewProject(foo.ise) # Set basic properties SetProperty(Device Family, spartan3) SetProperty(Device, xc3s400) SetProperty(Package, tq144) SetProperty(Speed Grade, -4) SetProperty(Top-Level Module Type, HDL) # Add the sources AddSource(foo.v, Verilog Design File) AddSource(foo.ucf, SA) AddSource(abc.xco, Coregen Design File) # Test bench sources AddSource(foo_test.v, Verilog Design File) # This doesn't actually work.. SetProperty(Simulation Run Time, 5000 ns, foo_test_v, Simulate Post-Place & Route Model, 9, SA) # Close the project to tidy up CloseProject() Then run pjcli -f foo.npl I've tested this on FreeBSD (linux emulation) & Windows with ISE8.2. Hope it helps. -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 127070
John Larkin wrote: > At any decent speed, analog issues (noise, nonlinearity, thd, drift, > crosstalk) overwhelm math accuracy, and at 14 dac bits we're already > there. At 32 MHz and healthy swings, the thd limit is the output > amplifiers, with 50-60 dB tough to hit. But most commercial arbs and > RF signal generators have ghastly thd specs, like -30 or even -20 dBc. I want to generate AES3 and S/PDIF as well, which needs 24 bit resolution. But for the audio signals the frequency needs only below 20kHz, so I think I can split this: very good 24 bit, but slow generator with direct sine calculation from fdlibm and DDS table lookup for faster signals. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 127071
Hi all!
I've really trouble to implement a simple application on a XUP Virtex-
II Board using the PPC and PLB as Interface.
I simply want to pass two inputs into the logic-core wire them to two
output ports. Additionally there shall be two output ports one driven
by slvreg0(0) and the other by slvreg1(0). To implement that I used
the created template from the "Create and Import Wizard" for an PLB
interface.
The Problem is after synthesising the system in EDK9.1 my PPC won't
run at all.
I simply tried to print an "Entering main" by using the uart in my c-
code. I didn't interacted with my core.
But it didn't run.
After that I had a look in the schematic report of ISE 9.1. For that I
used the ISE Projekt created by the "Create and Import Peripheral
Wizard". The first thing I found was that there was a different chip
selected than I use in EDK9.1. The second point was that the synthesis
report in ISE diverted from thta generated in EDK.
Has anyone discovered the same problem, or does anyone now wether ISE-
xst and EDK-xst use different parameters. How can I be sure, that the
schematic that is presented is the same that EDK would produce???
The other thing I found out by having a lokk at the schematic is that
the Port "Us_port_one_toggel_out" was replaced by the entire 32Bit
vector slvreg0.
I hope that one of you guys cann help me out at this point.
Best regards
Sven
Here is an example of my user_logic.vhd:
-------------------------------------------------------------
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
else
case slv_reg_write_select is
when "1000" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0100" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0010" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001" =>
for byte_index in 0 to (C_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <=
Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
--SA
Us_int_one_out <= Us_int_one_in; --Both Ports are std_logic
Us_int_two_out <= Us_int_two_in; --Both ports are std_logic
Us_port_one_toggel_out <= slv_reg0(0); --one_toggel_out is std_logic
Us_port_two_toggel_out <= slv_reg1(0); -- two_toggel_out is std_logic
--SA
Article: 127072Hello, I have successfully made an RPM core using the floorplanner "Write RPM to UCF" feature and created a core.ngc and a core.ucf file. Before I created the core I applied the AREA_GROUP constraint to get a rectangular shape. When I instantiate the core in another ISE project I can synthesize and implement without problems. However when I look at the placement of the design elements in floorplanner it looks nothing like what I saw when I made the core. Instead of a nice rectangular shape the core is now spread all over the FPGA! E.g. Two LUTs have RLOC values of X8Y13 and X23Y13 (delta_x,delta_y = -15,0) are placed in X3Y115 and X46Y1 (delta_x,delta_y = -43,114)! The core is fairly large and consists of about 1800 LUTs and 170 latches. I have tried to to convert the the .ngc file to a .ndf file using the ngc2edif tool to check that the RLOCs are properly written to the core.ngc file and they seem to be. When I created the core I did the following in ISE: - Synthesis properties: remove "Add I/O buffers" - Map Properties: remove "Trim Unconnected signals" - Synthesize - Implement->Translate - Implement->Translate->Floorplan Design - Assign AREA_GROUP contraint in floorplanner and write it to the ucf file. - Run MAP and PAR. - Implement->Place & Route->View/Edit Placed design. - In floorplanner I select Floorplan->Replace all with placement - I check that all elements in Design Hierarchy is placed on the floorplan. - Select File->Write RPM to UCF - Sets output UCF, input ngc, and output ngc file. I'm using ISE 9.2.03i and a Virtex5 fpga. What am I doing wrong? Any help is appreciated. Kind Regards Jon Neerup LassenArticle: 127073
Hi all, I am using Xilinx 9.2i schematic entry to design a simple clock circuit. The schematic uses come components that i wrote and i have added a counter from xilinx library. WHen i implement the design and fit it is ok, but when i assign package pins using PACE, i only see the inputs/outputs of the counter and not of the whole design. The target is a Coolrunner2 CPLD. Can someone explain to me whats happening. This is the first time i am mixing my entities with Xilinx built in components. Thanks a lot JosephArticle: 127074
On 8 dic, 19:24, emeb <ebromba...@gmail.com> wrote: > A few suggestions: > > * Use a longer Sine lookup table instead of interpolation. > * Store only 1/4 cycle of the sinewave in the lookup table and use bit > operations on the address and output to map the 1/4 cycle onto the > full wave. > * Use a dual-port RAM for the lookup table to simultaneously generate > sine & cosine (useful for digital radio applications) > > Inverse sinc filters are common ways to equalize the spectral droop > caused by the zero-order hold nature of the DAC. Typically a simple > FIR filter with a few taps (<10) can 'lift' the high frequency > response of the signal to compensate for this rolloff. This page > describes one way to do it: > > http://www.maxim-ic.com/appnotes.cfm/an_pk/3853 > EB An additional suggestion to what Emeb has said... Instead of directly storing the sine samples in the lookup table you may store the difference between the sine function and y=3Dx function. You'll save some bits in your table. C=E9sar
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