Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hello buddies, I loved surely all of you have written herein and hence, I would like to thank everyone of you. BUT, I am an ongoing process of trail and error with such a trouble. So, my WebPACK 9.2i updated on the process generate programming file, at Configure Device IMPACT, I got a couple of sad warnings came out and these are as follows Process "Configure Device (iMPACT)" completed successfully // *** BATCH CMD : setMode -bs // *** BATCH CMD : setMode -bs GUI --- Auto connect to cable... // *** BATCH CMD : setCable -port auto AutoDetecting cable. Please wait. PROGRESS_START - Starting Operation. Connecting to cable (Parallel Port - parport0). Linux release = 2.6.22-14-generic. WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the cable drivers. See Answer Record 22648. Cable connection failed. Connecting to cable (Parallel Port - parport1). Linux release = 2.6.22-14-generic. WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the cable drivers. See Answer Record 22648. Cable connection failed. Connecting to cable (Parallel Port - parport2). Linux release = 2.6.22-14-generic. WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the cable drivers. See Answer Record 22648. Cable connection failed. Connecting to cable (Parallel Port - parport3). Linux release = 2.6.22-14-generic. WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the cable drivers. See Answer Record 22648. Cable connection failed. Connecting to cable (Usb Port - USB21). Checking cable driver. Linux release = 2.6.22-14-generic. WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the cable drivers. See Answer Record 22648. Cable connection failed. PROGRESS_END - End Operation. Elapsed time = 0 sec. Cable autodetection failed. WARNING:iMPACT:923 - Can not find cable, check cable setup !// *** BATCH CMD : setCable -port ttyS0 -baud -1 Reusing A0018001 key. Reusing 24018001 key. Connecting to cable (Usb Port - USB21). Checking cable driver. Linux release = 2.6.22-14-generic. WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the cable drivers. See Answer Record 22648. Cable connection failed. ----------------------------------------------------------------------------------------- Till now, I have ever updated xusbdfwu.hex file to 1025 one and nothing happened !! I got this from my lsmod, awallon@AWALLON:~/Documents/SOFTWAREs/XILINX$ lsmod | grep par parport_pc 41896 0 parport 44172 3 ppdev,parport_pc,lp I compiled usb-driver without any trouble !! I was just great at that time !! lol Ohh, we are talking about a Ubuntu x86_64 SO so far. Another basic message, awallon@AWALLON:~/Documents/SOFTWAREs/XILINX$ lsusb Bus 007 Device 002: ID 03fd:0008 Xilinx, Inc. And to finish, I window titled like Cable Communication Setup appers whem I click with right button. So, inside of it, I set the Communication Mode to Xilinx USB Cable and also the Port to usb1 which appers. I believed all of this procedures could make me happy but unfortunately I didn't !!! Well, after lots of nightmares with windrvr6, I believe that someone else could be give some lights about what the hell is going on ?? This probably is the major disvantage of Xilinx regarding the other ones. So, Please every information will be most welcome !! Feel free to let me know about something Hugs Marco Hidalgo Brazil Please, send a reply to : awallon@ita.br CheersArticle: 126951
matadouros.home@gmail.com wrote: > Hello buddies, > > I loved surely all of you have written herein and hence, I would like > to thank everyone of you. ... > Hugs > > > Marco Hidalgo > Brazil > > "Hugs"? The engineering culture must be somewhat different down there in Brasil. -KevinArticle: 126952
On Dec 6, 1:03 pm, matadouros.h...@gmail.com wrote: > Hello buddies, > > I loved surely all of you have written herein and hence, I would like > to thank everyone of you. > BUT, I am an ongoing process of trail and error with such a trouble. > So, my WebPACK 9.2i updated on the process generate programming file, > at Configure Device IMPACT, I got a couple of sad warnings came out > and these are as follows > > Process "Configure Device (iMPACT)" completed successfully > // *** BATCH CMD : setMode -bs > // *** BATCH CMD : setMode -bs > GUI --- Auto connect to cable... > // *** BATCH CMD : setCable -port auto > AutoDetecting cable. Please wait. > PROGRESS_START - Starting Operation. > Connecting to cable (Parallel Port - parport0). > Linux release = 2.6.22-14-generic. > WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the > cable drivers. See Answer Record 22648. > Cable connection failed. > Connecting to cable (Parallel Port - parport1). > Linux release = 2.6.22-14-generic. > WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the > cable drivers. See Answer Record 22648. > Cable connection failed. > Connecting to cable (Parallel Port - parport2). > Linux release = 2.6.22-14-generic. > WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the > cable drivers. See Answer Record 22648. > Cable connection failed. > Connecting to cable (Parallel Port - parport3). > Linux release = 2.6.22-14-generic. > WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the > cable drivers. See Answer Record 22648. > Cable connection failed. > Connecting to cable (Usb Port - USB21). > Checking cable driver. > Linux release = 2.6.22-14-generic. > WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the > cable drivers. See Answer Record 22648. > Cable connection failed. > PROGRESS_END - End Operation. > Elapsed time = 0 sec. > Cable autodetection failed. > WARNING:iMPACT:923 - Can not find cable, check cable setup !// *** > BATCH CMD : setCable -port ttyS0 -baud -1 > Reusing A0018001 key. > Reusing 24018001 key. > Connecting to cable (Usb Port - USB21). > Checking cable driver. > Linux release = 2.6.22-14-generic. > WARNING:iMPACT - Module windrvr6 is not loaded. Please reinstall the > cable drivers. See Answer Record 22648. > Cable connection failed. > ------------------------------------------------------------------------------------------ > > Till now, I have ever updated xusbdfwu.hex file to 1025 one and > nothing happened !! I got this from my lsmod, > > awallon@AWALLON:~/Documents/SOFTWAREs/XILINX$ lsmod | grep par > parport_pc 41896 0 > parport 44172 3 ppdev,parport_pc,lp > > I compiled usb-driver without any trouble !! I was just great at that > time !! lol > Ohh, we are talking about a Ubuntu x86_64 SO so far. > > Another basic message, > awallon@AWALLON:~/Documents/SOFTWAREs/XILINX$ lsusb > Bus 007 Device 002: ID 03fd:0008 Xilinx, Inc. > > And to finish, I window titled like Cable Communication Setup appers > whem I click with right button. So, inside of it, I set the > Communication Mode to Xilinx USB Cable and also the Port to usb1 which > appers. I believed all of this procedures could make me happy but > unfortunately I didn't !!! > > Well, after lots of nightmares with windrvr6, I believe that someone > else could be give some lights about what the hell is going on ?? > This probably is the major disvantage of Xilinx regarding the other > ones. > > So, Please every information will be most welcome !! > Feel free to let me know about something > > Hugs > > Marco Hidalgo > Brazil > > Please, send a reply to : awal...@ita.br > > Cheers Maybe you could get better results from a different cable driver setup. Look back at the thread started Feb 24th "Xilinx Platform cable USB and impact on linux without windrvr" found here: http://groups.google.com/group/comp.arch.fpga/browse_frm/thread/f149e5b6028e2c70Article: 126953
Did anyone get the DDR SDRAM work on the Xilinx Spartan 3E Starter board? I have tried to load the pre-built BIT file specifically for this board: s3e_starter_revD_mig_ddr. The readme file states that the LED1 should be slightly lit while LED0 should be OFF. In my case the LED1 is fine, but the LED0 is constantly ON. I tried to load the ChipScope - enabled version of the bitstream and get the same result. Also the lfsr_data has nothing in common with read_data_reg in ChipScope. I tried running on 100, 50 and even 32 MHz (should be 80-133). Same effect. And help highly appreciated. -Alex.Article: 126954
On Dec 5, 6:30 pm, "KJ" <kkjenni...@sbcglobal.net> wrote: > Instead what is more useful is a known way to reliably write code to perform > that function that will work well. The form I chose was deliberately done > to demonstrate a technique to that, by simple inspection, can be seen to be > functionally equivalent and synthesizable. The better approach for a double > edged flop that you'd really like to use in an actual design was > demonstrated by Andy and Mike...but as you can see from rickman's > misinterpretation it wasn't obvious to him at first glance, whereas my > approach was obvious but left him uneasy about using the clock in logic (and > rightly so). One other disadvantage of the explicit coding is that you cannot implement it with data types for which XOR (or XNOR) operations are not defined, like enumerated types, records, arrays, integers, etc. at least not without additional code to define the XOR, which may or may not limit further optimization. For example, you can define an XOR operator for an enumerated type, but you must dictate a binary mapping explicitly, rather than letting the synthesis tool figure out the best mapping. My point is you can infer an SDR register that will store any data type with a simple assignment in a clocked process. It should be that simple with DDR registers too. AndyArticle: 126955
On Dec 6, 1:13 am, PatC <p...@patocarr.com> wrote: [...] > I've had a similar problem recently, and it was fixed by LOCking the DCM > to the higher side (of a V5) because the tool insisted on placing the > DCM at the bottom, and use the BUFGMUX at the top. > > YMMV w/xc3v This type of thing is certainly not restricted to V5. It happening to me back 5 years ago with V2's... well, something very close at least: the tools would randomly use non-dedicated routing from a clock input pin to the DCM. I took to putting a MAXDELAY of something like 1 ns on that net, which was easy to meet if it does the right thing, and impossible to meet if it didn't. Have fun, MarcArticle: 126956
Hi, ratemonotonic wrote: > Is it possible to use FSL read on an interrupt basis rather than > polling? Sure, you can connect the FSL_is_data signal to an interrupt port in the MHS file. > I have a scenario where i only want to read data using get instruction > if there is data on the bus. You need to design your interrupt handler carefully - to disable the FSL interrupt immediately and only re-enable it when it has drained the channel. > Are there any example projects ? Not that I am aware of. Regards, JohnArticle: 126957
glen herrmannsfeldt wrote: > KJ wrote: > (I wrote) > >>> Absolute delays will likely never be synthesizable, for example. > > >> Perhaps you should explain to the makers of discrete delay lines that >> they are doing the impossible. > > > OK, how about long absolute delays. You can delay some nanoseconds, > but I can write a 1s delay in verilog. It would take a very large > delay line to do that. > >> If you're referring instead to synthesizing a delay inside a >> programmable part like FPGA (which you probably did) than I'd say that >> the most likely reason for lack of delay line primitives in FPGAs has >> more to do with lack of demand for such a feature than it is any >> technical issues that can't be resolved in a profitable manner for the >> suppliers....but that's a business decision, not technical. > > > There are many things I would like to see added to FPGAs before analog > delay lines. > > -- glen > Not to mention that it is usually considered poor form to use delay lines in digital design.Article: 126958
On Dec 6, 11:11 am, truongt1...@gmail.com wrote: > I'm a final yr student undertaking a project which requires a > microcontroller with an operating clk freq at 60MHz. > > My university has altera DE2 boards available, which to my > understanding has oscillators @ 50MHz. > > A suggestion was to overclock the fpga, however I don't know where to > start looking. Would someone be able to point me in the right > directions to obtaining such information ? I also have that board. In the board lower right hand corner. There is a ext. clock input. What you need to do is 1. Find a cable with connect for that input 2. Connect the cable to a clock generator with the MHzyou want. or you need to know how to configure PLL to get the clk you need.Article: 126959
On Dec 6, 3:33 pm, KJ <Kevin.Jenni...@unisys.com> wrote: > > > On Dec 5, 8:49 pm, Yui <aikenp...@gmail.com> wrote: > > > I would want to know anyone try to build a FSM to "talk" with the > > > Avalon bus before? > > Yes, many times. > > > > What should I do/understand first for build a FSM to work as Master in > > > Avalon bus? > > The Avalon specification would be the a good start. > > > On Dec 6, 11:53 am, ghel...@lycos.com wrote: > > But (IMHO) the only reason to use Avalon is to take advantage of > > NIOS. I would use Wishbone for the situation you describe. > > > The Wishbone bus is also very well documented.- Hide quoted text - > > While Wishbond and Avalon are both well documented, I would disagree > with you about only using Avalon to take advantage of Nios. Tommy > Thorn's post is right on the money about the ways that Avalon can be > superior to Wishbone and I'd also add that for simple transactions > with no read latency, Wishbone and Avalon are pretty much functionally > identical, only the signal names are different. You don't need Nios, > SOPC Builder or even be targetting an Altera part to make Avalon > compatible widgets....but based on the questions of the original post, > I think there are very basic hurdles that Yui needs to clear first > since it doesn't appear that he has perused the Avalon specification > since transactions are almost painfully simple handshakes (as with > Wishbone). > > Kevin Jennings Anywhere I can find some same for the "FSM" master in Avalon bus?Article: 126960
Ray Andraka wrote: > glen herrmannsfeldt wrote: (snip) >> There are many things I would like to see added to FPGAs >> before analog delay lines. > Not to mention that it is usually considered poor form to use delay > lines in digital design. Yes. I did used to see them in DRAM controllers, though. Also, in NTSC decoders to get the chrominance and luminance signals right. (That isn't a digital design, though.) -- glenArticle: 126961
In UCF I write: NET "RefClkp" LOC = "AB4" | IOSTANDARD = "LVDS_25" ; NET "RefClkn" LOC = "AB3" | IOSTANDARD = "LVDS_25" ; In project: IBUFDS ref_clk_buffer (Test, RefClkp, RefClkn); But ISE swear in mapping: ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB component: PAD symbol "2RefClkn" (Pad Signal = RefClkn) SlaveBuffer symbol "ref_clk_buffer/SLAVEBUF.DIFFIN" (Output Signal = ref_clk_buffer/SLAVEBUF.DIFFIN) Each of the following constraints specifies an illegal physical site for a component of type IOB: Symbol "RefClkn" (LOC=AB3 [Physical Site Type = IPAD]) The component type is determined by the types of logic and the properties and configuration of the logic it contains. Please double check that the types of logic elements and all of their relevant properties and configuration options are compatible with the physical site type of the constraint. Please correct the constraints accordingly. ERROR:Pack:1107 - Unable to combine the following symbols into a single IOB component: PAD symbol "RefClkp" (Pad Signal = RefClkp) DIFFAMP symbol "ref_clk_buffer/IBUFDS" (Output Signal = Test_OBUF) Each of the following constraints specifies an illegal physical site for a component of type IOB: Symbol "RefClkp" (LOC=AB4 [Physical Site Type = IPAD]) The component type is determined by the types of logic and the properties and configuration of the logic it contains. Please double check that the types of logic elements and all of their relevant properties and configuration options are compatible with the physical site type of the constraint. Please correct the constraints accordingly. In UG196 (v1.3) May 25, 2007 I see in page 51 that: This section shows key elements of a UCF that instantiates seven GTP_DUAL tiles. The file implements the example configuration shown in Figure 5-5, page 71. The device and package combination chosen in this example is an XC5VLX110T-FF1136. ; ; Instantiate the GTP_DUAL tiles in locations X0Y7 to X0Y1 ; INST design_root/gtp_dual[1]/gtp_dual LOC=GTP_DUAL_X0Y1; INST design_root/gtp_dual[2]/gtp_dual LOC=GTP_DUAL_X0Y2; INST design_root/gtp_dual[3]/gtp_dual LOC=GTP_DUAL_X0Y3; INST design_root/gtp_dual[4]/gtp_dual LOC=GTP_DUAL_X0Y4; INST design_root/gtp_dual[5]/gtp_dual LOC=GTP_DUAL_X0Y5; INST design_root/gtp_dual[6]/gtp_dual LOC=GTP_DUAL_X0Y6; INST design_root/gtp_dual[7]/gtp_dual LOC=GTP_DUAL_X0Y7; ; ; Connect the REFCLK_PAD_(N/P) differential pair to the middle ; GTP_DUAL tile (GTP_DUAL_X0Y4) ; NET refclk_pad_n LOC=P4; NET refclk_pad_p LOC=P3; The instantiation of the GTP_DUAL tiles and the IBUFDS primitive is typically done in HDL code within the design hierarchy. That code also connects the output of the IBUFDS primitive to the CLKIN inputs of the GTP_DUAL tiles, as illustrated by the following Verilog code fragment: // // Instantiate the GTP_DUAL tiles // genvar tile_num; generate for (tile_num = 1; tile_num <= 7; ++tile_num) begin: gtp_dual GTP_DUAL gtp_dual ( .CLKIN(refclk), ... The remaining GTP_DUAL ports are not shown ) end endgenerate // // Instantiate the IBUFDS for the reference clock // IBUFDS ref_clk_buffer ( .IN(refclk_pad_n), .IP(refclk_pad_p), .O(refclk) ) Question: If I dont put in project GTP_DUAL I may use MGTREFCLK pins. I want first see that clock after IBUFDS correctly and after that include GTP_DUAL in my project.Article: 126962
If this clock I may use only in GTP_DUAL?Article: 126963
>On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote: >> >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote: >> >> Anuja wrote: >> >> > assign Q = (rst==0)?Q_int:1'do; >> >> >> > How do i convert this to vhdl? I have to use a concurrent statement >> as >> >> >> Q <= Q_int when rst = '0' else '0'; >> >> >Hi, >> >> >I am having simulation problems with my code. I am trying to convert >> >Verilog code to VHDL. I can compile correctly. When i simulate the >> >following code in VHDL, value of Q_int is stuck at "00". It does not >> >change at all. Please let me know what the problem could be. >> >> Remove the line: >> >> Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00"; >> >> after the BEGIN of the architecture.- Hide quoted text - >> >> - Show quoted text - > >How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0; > >if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else >"00"; > Sorry, my bad. I read your code too quickly, and thought you were assigning to Q in the clocked precess as well. Try: Q(1 downto 0) <= Q_int(1 downto 0) when rst = '0' else "00"; Or better: Q(1 downto 0) <= "00" when rst = '1' else Q_int(1 downto 0);Article: 126964
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message news:fj9r03$2vv1@cnn.xsj.xilinx.com... > matadouros.home@gmail.com wrote: >> Hello buddies, >> >> I loved surely all of you have written herein and hence, I would like >> to thank everyone of you. > ... >> Hugs >> >> >> Marco Hidalgo >> Brazil >> >> > "Hugs"? The engineering culture must be somewhat different down there in > Brasil. -Kevin Hmmm, I notice Amma has been to Brazil... http://news.bbc.co.uk/1/hi/magazine/7130151.stm Coincidence? I think not! :-) Syms. xxArticle: 126965
>
> Anywhere I can find some same for the "FSM" master in Avalon bus?- Hide quoted text -
>
> - Show quoted text -
You're going to have a hard time if you're not willing to pick up and
read and attempt to understand the Avalon bus. If you have read it
and are still asking about how to find a "FSM" master then it's
apparent that you do not understand it so I would suggest some further
study on your part.
In any case, no state machine is required, see below for the template
that is Avalon compliant and insert your code where mentioned.
process(Clock)
begin
if rising_edge(Clock) then
if (Reset = '1') then
Read <= '0';
Write <= '0';
elsif (Wait_Request = '0') then
-- Insert your code here that defines when you want to read
something
-- Insert your code here that defines when you want to set
write something
-- Insert your code here that defines what data you would
like to write
-- Insert your code here that defines which Address you would
like to access.
if (Read = '1') then
Data_That_I_Read <= Readdata;
end if;
end if;
end if;
end process;
Kevin Jennings
Article: 126966Hi All, I have a XupV2P board, ISE 9.1 and Windows Vista. I can't find the right driver for my USB cable to download my bitstream. Does anyone know where to find it ? Thanks, Andre.Article: 126967
On Dec 6, 9:55 am, John Adair <g...@enterpoint.co.uk> wrote: > The M25P40 is the standard serial flash memory fitted. So there is > some capacity to run a Microblaze etc.. I'll have to check the > footprints but I think we can go to 16Mbit and possibly 32/64 Mbit as > options. > > Power can be put in the pin header as an option and variants of the > board with straight pins are an option we are considering offering. > > If you don't want the RS232, pins etc, then maybe the Craignell series > are better for your application. They are smaller take the shape of a > standard DIL/DIP (28,32,36,40 pins available) and very minimalist. > Otherwise they are identical to the Drigmorn1. > > Leaving a site for something else is a possibility the future. We may > also do a companion board to do some more. > > John Adair > Enterpoint Ltd. > > On 6 Dec, 10:54, posedg...@yahoo.com wrote: > > > On Dec 5, 6:19 pm, John Adair <g...@enterpoint.co.uk> wrote: > > > > We have been promising this for a while and I am finally pleased to > > > show first images and details of Drigmorn1 herehttp://www.enterpoint.co.uk/component_replacements/drigmorn1.html. We > > > are aiming this to be the cheapest develoment board out there so if > > > know any cheaper do let me know. We have some more testing to do > > > before we let it out in the wild but hopefully that will be complete > > > before Christmas to allow shipment before the holidays. > > > > Use of this board is simplistic. A simple 5v jack for power and a > > > RS232 interface to allow control by a PC using a terminal emulator > > > Why use 40 MHz when most other Xilinx FPGA boards are fitted with 50 > > MHz.? > > (would ease code portability) > > > * Maybe you could leave some TSSOP54 or similar pad for soldering on a > > SDRAM chip..? > > > * What are the three larger chips for? (one is M25P40 I assume) > > > A further simplification would be to rid of the rs232, leds, and the > > dc power jack. Dc power can be had from the dil-40 pins. I'd buy 2 or 3 if it had twice the number of pins. So instead of a 1x20 header strip on each side there would be a 2x20 header strip per side. -Dave PollumArticle: 126968
Andre van der Avoird wrote: > Hi All, > > I have a XupV2P board, ISE 9.1 and Windows Vista. > I can't find the right driver for my USB cable to download my bitstream. > Does anyone know where to find it ? > > Thanks, Andre. ...in the Xilinx ISE installation program. I noticed it in the 9.2i setup.exe on XP when the items are checked by the user for installation of the components. In addition to the various CPLD and FGPA families, there are check-boxes for "standalone programmer" and "cable driver." That last item is critical. Maybe it's time to upgrade to 9.2i since you need to reinstall this item anyway. - John_HArticle: 126969
On Dec 7, 4:02 am, "RCIngham" <robert.ing...@gmail.com> wrote: > >On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote: > >> >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote: > >> >> Anuja wrote: > >> >> > assign Q = (rst==0)?Q_int:1'do; > > >> >> > How do i convert this to vhdl? I have to use a concurrent > statement > >> as > > >> >> Q <= Q_int when rst = '0' else '0'; > > >> >Hi, > > >> >I am having simulation problems with my code. I am trying to convert > >> >Verilog code to VHDL. I can compile correctly. When i simulate the > >> >following code in VHDL, value of Q_int is stuck at "00". It does not > >> >change at all. Please let me know what the problem could be. > > >> Remove the line: > > >> Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00"; > > >> after the BEGIN of the architecture.- Hide quoted text - > > >> - Show quoted text - > > >How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0; > > >if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else > >"00"; > > Sorry, my bad. I read your code too quickly, and thought you were > assigning to Q in the clocked precess as well. > > Try: > Q(1 downto 0) <= Q_int(1 downto 0) when rst = '0' else "00"; > Or better: > Q(1 downto 0) <= "00" when rst = '1' else Q_int(1 downto 0);- Hide quoted text - > > - Show quoted text - neither one works. I am still having the same problemArticle: 126970
Thanks John, Can I upgrade with an online update from 9.1 or do I need a complete new install ? Problem is my webupdate doesn't work. Andre John_H wrote: > Andre van der Avoird wrote: >> Hi All, >> >> I have a XupV2P board, ISE 9.1 and Windows Vista. >> I can't find the right driver for my USB cable to download my bitstream. >> Does anyone know where to find it ? >> >> Thanks, Andre. > > ...in the Xilinx ISE installation program. I noticed it in the 9.2i > setup.exe on XP when the items are checked by the user for installation > of the components. In addition to the various CPLD and FGPA families, > there are check-boxes for "standalone programmer" and "cable driver." > That last item is critical. Maybe it's time to upgrade to 9.2i since > you need to reinstall this item anyway. > > - John_HArticle: 126971
Dave It's possible to do as the chip has enough I/O but it would need microvias and extra layers in the pcb to achieve that and that all comes at a cost. However we will see how many we ship and if the numbers are large enough then doing these sorts of things may be possible and keeping the low cost aspect. In the future we will be having some bigger "on the bench" boards that compete against boards like the Spartan-3 Starter Kit but that's not for a while. We have some more interesting "concept boards" yet to release before that happens. John Adair Enterpoint Ltd. On 7 Dec, 13:21, Dave Pollum <vze24...@verizon.net> wrote: > On Dec 6, 9:55 am, John Adair <g...@enterpoint.co.uk> wrote: > > > > > > > The M25P40 is the standard serial flash memory fitted. So there is > > some capacity to run a Microblaze etc.. I'll have to check the > > footprints but I think we can go to 16Mbit and possibly 32/64 Mbit as > > options. > > > Power can be put in the pin header as an option and variants of the > > board with straight pins are an option we are considering offering. > > > If you don't want the RS232, pins etc, then maybe the Craignell series > > are better for your application. They are smaller take the shape of a > > standard DIL/DIP (28,32,36,40 pins available) and very minimalist. > > Otherwise they are identical to the Drigmorn1. > > > Leaving a site for something else is a possibility the future. We may > > also do a companion board to do some more. > > > John Adair > > Enterpoint Ltd. > > > On 6 Dec, 10:54, posedg...@yahoo.com wrote: > > > > On Dec 5, 6:19 pm, John Adair <g...@enterpoint.co.uk> wrote: > > > > > We have been promising this for a while and I am finally pleased to > > > > show first images and details of Drigmorn1 herehttp://www.enterpoint.co.uk/component_replacements/drigmorn1.html. We > > > > are aiming this to be the cheapest develoment board out there so if > > > > know any cheaper do let me know. We have some more testing to do > > > > before we let it out in the wild but hopefully that will be complete > > > > before Christmas to allow shipment before the holidays. > > > > > Use of this board is simplistic. A simple 5v jack for power and a > > > > RS232 interface to allow control by a PC using a terminal emulator > > > > Why use 40 MHz when most other Xilinx FPGA boards are fitted with 50 > > > MHz.? > > > (would ease code portability) > > > > * Maybe you could leave some TSSOP54 or similar pad for soldering on a > > > SDRAM chip..? > > > > * What are the three larger chips for? (one is M25P40 I assume) > > > > A further simplification would be to rid of the rs232, leds, and the > > > dc power jack. Dc power can be had from the dil-40 pins. > > I'd buy 2 or 3 if it had twice the number of pins. So instead of a > 1x20 header strip on each side there would be a 2x20 header strip per > side. > -Dave Pollum- Hide quoted text - > > - Show quoted text -Article: 126972
On Dec 4, 5:27 pm, Anuja <thakkar.an...@gmail.com> wrote: > Hello > > I am trying to convert the following code to vhdl > > assign Q = (rst==0)?Q_int:1'do; > > How do i convert this to vhdl? I have to use a concurrent statement as > this statement is not in the always block hence concurrent. I cannot > use an if then else statement as it is sequential. > > Please help Could there be an issue with not having a "wait" at the bottom of your testbench process? Maybe that process is executing every delta cycle, with time never moving forward.Article: 126973
On Dec 7, 9:44 am, Dave <dhsch...@gmail.com> wrote: > On Dec 4, 5:27 pm, Anuja <thakkar.an...@gmail.com> wrote: > > > Hello > > > I am trying to convert the following code to vhdl > > > assign Q = (rst==0)?Q_int:1'do; > > > How do i convert this to vhdl? I have to use a concurrent statement as > > this statement is not in the always block hence concurrent. I cannot > > use an if then else statement as it is sequential. > > > Please help > > Could there be an issue with not having a "wait" at the bottom of your > testbench process? Maybe that process is executing every delta cycle, > with time never moving forward. It maybe possible. Let me check on this and see what happens.Article: 126974
On Dec 7, 8:14 am, Anuja <thakkar.an...@gmail.com> wrote:
> On Dec 7, 4:02 am, "RCIngham" <robert.ing...@gmail.com> wrote:
>
>
>
> > >On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote:
> > >> >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote:
> > >> >> Anuja wrote:
> > >> >> > assign Q = (rst==0)?Q_int:1'do;
>
> > >> >> > How do i convert this to vhdl? I have to use a concurrent
> > statement
> > >> as
>
> > >> >> Q <= Q_int when rst = '0' else '0';
>
> > >> >Hi,
>
> > >> >I am having simulation problems with my code. I am trying to convert
> > >> >Verilog code to VHDL. I can compile correctly. When i simulate the
> > >> >following code in VHDL, value of Q_int is stuck at "00". It does not
> > >> >change at all. Please let me know what the problem could be.
>
> > >> Remove the line:
>
> > >> Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00";
>
> > >> after the BEGIN of the architecture.- Hide quoted text -
>
> > >> - Show quoted text -
>
> > >How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0;
>
> > >if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else
> > >"00";
>
> > Sorry, my bad. I read your code too quickly, and thought you were
> > assigning to Q in the clocked precess as well.
>
> > Try:
> > Q(1 downto 0) <= Q_int(1 downto 0) when rst = '0' else "00";
> > Or better:
> > Q(1 downto 0) <= "00" when rst = '1' else Q_int(1 downto 0);- Hide quoted text -
>
> > - Show quoted text -
>
> neither one works. I am still having the same problem
I'm not sure where you got the code, but it looks like it is a flop
with a synchronous reset and enable, and then anding the output with
reset after the register.
I would convert it as follows to a standard asynchronous reset
circuit. The only difference in behavior would be if rst is high for
less than a clock cycle, but not while the clock is actually rising
(in which case the original circuit output would be 0 while rst, but
return to whatever q_int was afterwards, whereas the new circuit will
stay at 0 until something is clocked into q).
process (clk, rst) is
begin
if rst = '1' then
q <= (others => '0');
elsif rising_edge(clk) and (en = '1') then
q <= d;
end if;
end process;
Hints: you don't need to write "(1 downto 0)" when that is the entire
range of the array/vector. In a clocked process, you also don't need
to reassign q (or q_int) to itself when it needs to remain the same.
and get rid of that concurrent statement (it is handled now by the
async reset)
Andy
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z