Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Dave, > In AR# 19804 at http://www.xilinx.com/support/answers/19804.htm, the you need to look at OCM like caches in a Harvard architecture, i.e. dedicated blocks for data and instruction accesses. Like it is not possible during program execution to read data from the instruction cache it is not possible to read data from the instruction cache. IOCM is actually a little bit worse because the data (code) gets in there through the debugger or a program like you have written and not through a processor initiated load operation, i.e. data loaded by the processor through a load operation can never end up in the instruction cache. For OCM that means that the compiler and linker strictly need to separate instruction and data sections. Now, the newlib libraries are written something like this: .text data: .long 0xdeadbeef code: lis r2, data@h ori r2, r2, data@l lwz r3, 0(r2) Instruction and data are mixed within a .text segment. When the debugger or your program loads that code into ISOCM the "data" variable becomes inaccessible to the "code" because of the Harvard nature of OCM. > AR# 19099, at http://www.xilinx.com/support/answers/19099.htm, seems to This problem only occurs on the DOCM and not on the IOCM. The best way to work around this problem is to turn off interrupts and exceptions before accessing data in the DOCM. If that does not work, then, yes you have to write the routines that access the DOCM in assembler or disassemble the compiler generated code and inspect it so that the instruction sequence doesn't occur. - PeterArticle: 127226
bunty wrote:
> On Dec 14, 1:21 pm, "mynewlife...@yahoo.com.cn"
> <mynewlife...@yahoo.com.cn> wrote:
>> When i usechipscope9.2 to configerate bit file, sometimes will
>> occour warning like this "WARNING - Device 0: ICON Core version v15.15
>> is not supported", and the configeration failed. When this happen, I
>> rerun the some project, then configeration is successed. Please tell
>> me why this happen, thanks!
>
> XILINX version is not compatible when compared to lower versions.
> Which version you have used to generate bit file. Is it with ISE 9.2
> and you should use Chipscope of same version ie 9.1i and upto 8.2i.
> (you can use)
> First confirm which version for chipscope and ISE ur using for
> debugging.
I don't think that this a version problem (BTW, ChipScope Analyzer will
support older revision cores for backward compatibility). I do think
that this is one of two possible timing problems. The problem description
is vague so I don't know which of these is the more likely cause.
1) If "rerun the some project, then configeration is successed" means
that the board was powered on, ChipScope was started, the bitstream
was downloaded, the error message appeared, the bitstream was
downloaded again and ChipScope found and recognized the core, then
the problem is likely a system level state timing issue.
Possible Causes:
- There are other devices or a system level control that holds DONE
low for some amount of time after the configuration is complete.
This keeps the device inactive and when the ChipScope SW scans
the chain it doesn't get back valid data.
o If you close the JTAG cable and open the JTAG cable again and
the core is present this is the most likely cause.
- There is something else in the system that is accessing the
configuration logic and preventing correction operation of the
JTAG controller and internal logic. This could be caused by
something accessing the internal ICAP port or external configuration
reloading a bitstream
o If you download the bitstream again without power cycling or
closing/opening the cable then this is the most likely cause.
Setting the USERID field to different values is a useful debug
tool for ensure that the correct bitstream has been loaded.
2) If "rerun the some project, then configeration is successed" means
you went back to the start and reimplemented the design from the
synthesis through ISE and it worked this time.
Possible Cause:
- Timing problem on the internal JTAG clock distribution for the
ChipScope core clocking.
o Select the option to use a BUFG on this net during the ICON
core generation for reduced clock skew.
Ed McGettigan
--
Xilinx Inc.
Article: 127227cpope wrote: > This is probably a long shot but I'm wondering if serial ATA can be run at a > speed less than 1.5 Gbps? I have a V4 fpga but no MGTs so it would be nice > if I could make it work with regular chipsync resources which can only go > about 800 mbps. No. All of the SATA hard drives have an on board clock source that transmits and receives at 1.5 Gbps. Ed McGettigan -- Xilinx Inc.Article: 127228
psihodelia@googlemail.com wrote:
> The Motto of MyHDL Project says: "From Python to silicon". Many people
> are interested to see any clear example of how one can produce a bit
> file for a FPGA from MyHDL.
The open source motto says: "Try it and see."
> For example, it could be an example of binding MyHDL with popular XST,
> demonstrating, say, simple UART/VGA/LED/ or even SRAM controller.
That binding is verilog code.
Run it through your tools and see if works.
The process of converting verified hdl code
into an fpga image is vendor specific.
I would have as little interest in hearing
about the xst process as you would hearing
about quartus.
> At the same time, VHDL analogous program should be available for the
> comparison.
Open source projects have no marketing department.
Such comparisons are done by interested users.
-- Mike Treseler
Article: 127229On Thu, 13 Dec 2007 12:29:30 +0000, Brian Drummond <brian_drummond@btconnect.com> wrote: >On Wed, 12 Dec 2007 22:36:39 -0800 (PST), Josh.OuterSpace@gmail.com >wrote: > >>On Dec 12, 10:47 pm, John Larkin >><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>> On Wed, 12 Dec 2007 13:45:47 -0800 (PST), Josh.OuterSp...@gmail.com >>> wrote: >>> >>> >How come in the pdf of the vq100 diagram, it shows something with 64 >>> >pins. This is odd because the spartan 3e sure doesn't come in a vq64, >>> >it comes in a vq100. Maybe they mean the vq100 has 64 pins but that >>> >doesn't make sense because the pinout spreadsheet has 100 entries. >>> >And how would you divide 100 by 4 to fill up 4 sides of a square >>> >chip? You cant do that with 100 unless its a 5 sided chip. >>> >>> >Thanks. >>> >>> I couldn't swear to it, but I think that 100 divided by 4 is close to >>> 25. >>> >>> John >> >>It makes more sense to me to have 5 sides than an odd number of pins >>one side > >Tell that to a 7400. > >- Brian Three horroble mistakes were made, that we suffer from to this day: dip packages are physically symmetric; pins are numbered circularly; Vcc and ground are in the corners. JohnArticle: 127230
On Wed, 12 Dec 2007 22:36:39 -0800 (PST), Josh.OuterSpace@gmail.com wrote: >On Dec 12, 10:47 pm, John Larkin ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> On Wed, 12 Dec 2007 13:45:47 -0800 (PST), Josh.OuterSp...@gmail.com >> wrote: >> >> >How come in the pdf of the vq100 diagram, it shows something with 64 >> >pins. This is odd because the spartan 3e sure doesn't come in a vq64, >> >it comes in a vq100. Maybe they mean the vq100 has 64 pins but that >> >doesn't make sense because the pinout spreadsheet has 100 entries. >> >And how would you divide 100 by 4 to fill up 4 sides of a square >> >chip? You cant do that with 100 unless its a 5 sided chip. >> >> >Thanks. >> >> I couldn't swear to it, but I think that 100 divided by 4 is close to >> 25. >> >> John > >It makes more sense to me to have 5 sides than an odd number of pins >one side Well, you are from outer space. JohnArticle: 127231
Mike, you are great man, you deserve respect for what you've done, I grew up on your VHDL materials (and a lot of others as well), but that's a hit at me; why so sadistic irony ? I am proponent of Open Source ideology, you know it, and I do I believe that egoistic actions stops real progress in the science, in the industry, in the society, it stops to bring new knowledge to others. To others, who has no gates to best universities. Don't ever forget about that it's a lot of young people sometimes maybe from the very edges of the world who has not enough abilities to get knew knowledge. But many have now the Internet. And they spent their money to study new things, they pay their last money only to have an access to WWW. We are to help them, to share our knowledge. An Open Source motto is not just "Try it and see." , it is much more to went into it full bore.Article: 127232
Wolfgang Grafen wrote:
> Now I remember, I had problems
> describing and simulating a design composed of several modules. It is
> only me - I didn't know how to do it and I would like the documentation
> extended in this way.
http://www.jandecaluwe.com/Tools/MyHDL/manual/model-structure.html
> People who have to decide whether MyHDL will used
> for a project or not would like to see even more, a proof, e.g. a
> complete project,
http://myhdl.jandecaluwe.com/doku.php/projects:phoenixsid_65x81
> multiple clock domains,
http://www.jandecaluwe.com/Tools/MyHDL/manual/intro-hier.html
> individual delays on signals
http://www.jandecaluwe.com/Tools/MyHDL/manual/ref-sig.html
> asynchronous logic handling come in my mind.
From reading the introduction:
http://www.jandecaluwe.com/Tools/MyHDL/manual/intro.html
it will be clear that the MyHDL simulator is just an event-driven
simulator, in good old Verilog and VHDL tradition.
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
Article: 127233
psihodelia@googlemail.com wrote:
> The Motto of MyHDL Project says: "From Python to silicon". Many people
> are interested to see any clear example of how one can produce a bit
> file for a FPGA from MyHDL.
>
> For example, it could be an example of binding MyHDL with popular XST,
> demonstrating, say, simple UART/VGA/LED/ or even SRAM controller. At
> the same time, VHDL analogous program should be available for the
> comparison.
Has been done, with an example from Xilinx itself:
http://myhdl.jandecaluwe.com/doku.php/cookbook:stopwatch
> In that case, people can compare two digital design flows, executed
> using different languages. Results will show the quality of
> synthesized code, expended translation/synthesis time, and maybe will
> reveal some difficulties.
Note that for synthesis, MyHDL *relies* on a Verilog/VHDL design flow.
Synthesis results will thus be similar, obviously.
Jan
--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Kaboutermansstraat 97, B-3000 Leuven, Belgium
From Python to silicon:
http://myhdl.jandecaluwe.com
Article: 127234>I am proponent of Open Source ideology, you know it, and >I do I believe that egoistic actions stops real progress in the >science, in the industry, in the society, >it stops to bring new knowledge to others. Don't propound. We're just artisans here, not philosophers. We all have notions of how certain things might be done better, but this group is for practical problems, not for changing the world.Article: 127235
On Dec 12, 6:06 pm, Kris Vorwerk <kris.vorw...@gmail.com> wrote: > > Can anybody suggest some books I could start with? > > It's probably a bit dated, but when I was working on PCB design, I > found the following book to be quite useful ... > > http://www.amazon.com/High-Speed-Digital-Design-Semiconductor/dp/0133... > > (I worked for a company that brought the author in for an afternoon to > give a talk & answer questions. It was pretty interesting.) > > K. I second this recommendation. It's got a lot of useful concepts, though the book is a bit too cookbook-y for my taste. The most useful PCB design material, I've found, has been manufacturer datasheets and app notes. (For my first time designing an FPGA board, I found dev board schematics to be very useful.) In particular, Analog Devices has a lot of material on board design considerations for data conversion. You'll probably find yourself reading lots of app notes on various associated topics, like power regulation. And yes, making (cheap) mistakes is a great way to learn. MikeArticle: 127236
What voltage swing will and common voltage will a LVDS_25 configured port output when the Vcco is 3.3V and not 2.5V as the datasheet specify ..? Will it damage the FPGA or anything else ..?Article: 127237
Thank you for everyone's input your help was much appreciated. :)Article: 127238
On Fri, 14 Dec 2007 19:18:48 -0800 (PST), posedge52@yahoo.com wrote:
>What voltage swing will and common voltage will a LVDS_25 configured
>port output when the Vcco is 3.3V and not 2.5V as the datasheet
>specify ..?
>Will it damage the FPGA or anything else ..?
This message should be viewed in a fixed-width font.
--------------------------------------------------
Given a target line impedance, you need to find what drive resistors
will:
1) match that impedance
2) give compliant voltage levels
In both examples below, the output voltages comply with the LVDS
specification and the transmitter presents 100 ohm to the line
(neglecting any impedance of the device output).
--------------------------------------------------
For differential drive between 0V and 2.5V:
+V -----170ohm-----:--------->
|
|
240ohm
|
|
-V -----170ohm-----:--------->
--------------------------------------------------
For differential drive between 0V and 3.3V:
+V -----150ohm-----:--------->
|
|
150ohm
|
|
-V -----150ohm-----:--------->
--------------------------------------------------
Clearly, there is more power dissipated in the second design (both in
the resistors and in the differential drive circuits), but it avoids a
separate 2.5V supply.
As far as damaging the hardware is concerned...
In my first experiment with LVDS (a Cyclone II driving an LCD via four
LVDS pairs at 350Mbit/s), I decided it was rather tedious to fit the
twelve matching resistors, so I just connected the FPGA outputs to the
line. It ran continuously for several months before I did it "right"
and I saw no evidence of damage (or errors). But to mention such
"design" at polite dinner parties may lead to embarrassed silences and
shuffling of feet, so it's better to do it right.
Mike
Article: 127239On Fri, 14 Dec 2007 13:52:59 -0800, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >On Thu, 13 Dec 2007 12:29:30 +0000, Brian Drummond ><brian_drummond@btconnect.com> wrote: > >>On Wed, 12 Dec 2007 22:36:39 -0800 (PST), Josh.OuterSpace@gmail.com >>wrote: >> >>>On Dec 12, 10:47 pm, John Larkin >>><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >>>> On Wed, 12 Dec 2007 13:45:47 -0800 (PST), Josh.OuterSp...@gmail.com >>>> wrote: >>>It makes more sense to me to have 5 sides than an odd number of pins >>>one side >> >>Tell that to a 7400. >> >>- Brian > > >Three horroble mistakes were made, that we suffer from to this day: >dip packages are physically symmetric; pins are numbered circularly; >Vcc and ground are in the corners. ... except for the 7490. Which was probably an even worse mistake than the original corner power pinning, just from the surprise factor. - BrianArticle: 127240
What's the 6-pin connection "J8" on the lower-left of the Xilinx/ Digilent "Spartan-3E starter kit" (rev D) wired too ..?, can't find it in the schematics.. Google search doesn't turn up anything useful either.Article: 127241
On Dec 15, 12:56 pm, MikeShepherd...@btinternet.com wrote: > On Fri, 14 Dec 2007 19:18:48 -0800 (PST), posedg...@yahoo.com wrote: > >What voltage swing will and common voltage will a LVDS_25 configured > >port output when the Vcco is 3.3V and not 2.5V as the datasheet > >specify ..? > >Will it damage the FPGA or anything else ..? > > This message should be viewed in a fixed-width font. > -------------------------------------------------- > Given a target line impedance, you need to find what drive resistors > will: > > 1) match that impedance > 2) give compliant voltage levels > > In both examples below, the output voltages comply with the LVDS > specification and the transmitter presents 100 ohm to the line > (neglecting any impedance of the device output). > > -------------------------------------------------- > For differential drive between 0V and 2.5V: > > +V -----170ohm-----:---------> > | > | > 240ohm > | > | > -V -----170ohm-----:---------> > > -------------------------------------------------- > For differential drive between 0V and 3.3V: > > +V -----150ohm-----:---------> > | > | > 150ohm > | > | > -V -----150ohm-----:---------> > > -------------------------------------------------- > Clearly, there is more power dissipated in the second design (both in > the resistors and in the differential drive circuits), but it avoids a > separate 2.5V supply. > > As far as damaging the hardware is concerned... > > In my first experiment with LVDS (a Cyclone II driving an LCD via four > LVDS pairs at 350Mbit/s), I decided it was rather tedious to fit the > twelve matching resistors, so I just connected the FPGA outputs to the > line. It ran continuously for several months before I did it "right" > and I saw no evidence of damage (or errors). But to mention such > "design" at polite dinner parties may lead to embarrassed silences and > shuffling of feet, so it's better to do it right. So it's a must to have a resistor setup at the fpga lvds output driver ..? (Or maybe it only applies to Altera and not Xilinx?)Article: 127242
>So it's a must to have a resistor setup at the fpga lvds output >driver ..? >(Or maybe it only applies to Altera and not Xilinx?) I have no experience of Xilinx products, but I understand that there is some provision for internal matching resistors. If you want to use those and they present the desired impedance to the load then you need to check that, with a 3.3V supply, the output voltages are within your specification. It seems likely that any internal matching resistors can be disabled in configuration, so that you can use a different I/O supply or drive lines with a different impedance. You need to read the Xilinx specification in detail. MikeArticle: 127243
Hi there - I recently got a Digilent Spartan 3E Starter Board (http:// www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Products&Nav2=Programmable). It's been a while since I played with an FPGA, so I was hoping to find a really comprehensive guide that would walk me through everything, from making a new project (using Xilinx's software, preferrably), to writing a simple program (ie hello world, led blink, etc.), to putting it on the Spartan 3E starter board. Does anybody know of such a guide? I had expected one to be included with the board, but I can't seem to find one. Thanks! -MichaelArticle: 127244
On Sat, 15 Dec 2007 13:14:57 +0000, MikeShepherd564@btinternet.com wrote: >>So it's a must to have a resistor setup at the fpga lvds output >>driver ..? >>(Or maybe it only applies to Altera and not Xilinx?) > >I have no experience of Xilinx products, but I understand that there >is some provision for internal matching resistors. If you want to use >those and they present the desired impedance to the load then you need >to check that, with a 3.3V supply, the output voltages are within your >specification. > >It seems likely that any internal matching resistors can be disabled >in configuration, so that you can use a different I/O supply or drive >lines with a different impedance. You need to read the Xilinx >specification in detail. > >Mike We tested a Spartan3 lvds input, at 3.3 volts Vccio. It appears to be a pretty good rail-to-rail comparator. JohnArticle: 127245
posedge, I am presuming that you are referring to a Spartan 3E/3A/3AN/3D series part. If not, then please let me know if it is a Xilinx part, and which one. First, LVDS is a standard, and does not have a specified Vcc. By that, I mean the output voltages, and input ranges are all detailed in the IEEE/ANSI standards, and the designer can choose how to power it. We chose (in the referenced parts above) to power it from 2.5V. If instead, you power the bank from 3.3V, no harm is done, both the driver and the receiver will function (operate), but the specifications of LVDS (drive impedances, input termination impedances, p-p voltage swing, common mode voltage) may not be within the LVDS standard's specifications. That said, if you characterize it over voltage, and temperature, and feel you have sufficient margins, and accept responsibility for using it this way, then, be our guest. Of course, if it doesn't meet one or more of your requirements, don't expect Xilinx to do anything for you, as your use is outside of the recommended data sheet parameters. AustinArticle: 127246
Michael, http://homepages.wmich.edu/~grantner/ece355/ is just one of thousands of college courses which use the Digilent pcb. I suggest you use a few minutes of time to google through, and find a course you like, and then do the labs. I know that there is a huge amount of content out there (I have a Digilent pcb that I got for my personal use). You just need to take some time, and effort, to find it. AustinArticle: 127247
posedge52@yahoo.com wrote: > What voltage swing will and common voltage will a LVDS_25 configured > port output when the Vcco is 3.3V and not 2.5V as the datasheet > specify ..? > Will it damage the FPGA or anything else ..? A little elaboration on what's been stated, perhaps, to tie it all up. The mention of resistors is valid when using full rail-to-rail outputs such as LVCMOS_33 to drive the two single-ended outputs. This is the technique used for devices that don't have native LVDS or for BusLVDS signals. Even though the resistors look like they could cut the signal level for the *receive* side as well in a transceiver, all it does is slow down the signal a little with the series resistor into the parasitic capacitance. The resistor network is not valid for native LVDS outputs as the transmit level will be severely reduced; it may work, but with less noise immunity. I expect the Xilinx software will complain about putting LVDS standards on a 3.3V bank such that you have to specify 2.5V in the software to get MAP and PAR to complete then wire it up to 3.3V later. As far as what this will do to the other I/Os you had at 3.3V is not obvious if you have to specify LVCMOS_25 at 12 mA versus LVCMOS_33 and some other drive current. The transmit and receive impedances will be different at 3.3V than what you'd expect at 2.5V and I don't believe the IBIS models will help you out here. It's been underscored that the LVDS inputs can be in any VCCO-powered bank in some of these newer parts but the internal receive terminations will NOT be in the 100-120 ohm range expected for the 2.5V VCCO but much lower impedance at 3.3V. I haven't even thought about looking at the transmit impedance at 3.3V since the other problems keep me powering my LVDS with 2.5V. It might be safest from a software and integrity standpoint to use the resistor terminations and use LVCMOS_33 to drive the lines if you're not going over 400 Mb/s. For a receiver, you can use a lone external 100 ohm differential resistor (as opposed to those darned hard-to-solder single-ended resistors) instead of the three resistor network. If you have a transceiver, things might get weird: if you use LVCMOS transmitters, you can't use a differential receiver; if you use the full-swing BLVDS signal to get the differential receiver, you may have the same problem specifying a 3.3V VCCO for your bank from the software perspective. If you need transceivers, get back to us; we might be able to find a solution anyway. - John_HArticle: 127248
Michael wrote: > Hi there - I recently got a Digilent Spartan 3E Starter Board (http:// > www.digilentinc.com/Products/Detail.cfm?Prod=S3EBOARD&Nav1=Products&Nav2=Programmable). > It's been a while since I played with an FPGA, so I was hoping to find > a really comprehensive guide that would walk me through everything, > from making a new project (using Xilinx's software, preferrably), to > writing a simple program (ie hello world, led blink, etc.), to putting > it on the Spartan 3E starter board. Does anybody know of such a guide? > I had expected one to be included with the board, but I can't seem to > find one. > > Thanks! > > -Michael Austin pointed out some great "getting started" ideas but please note there's a comprehensive users guide for the board that might not have come in the package from a direct-from-digilent starter board. http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf It has good information about what's on the board and - I believe - what's in the pre-loaded bitstream. It's good reference information that will help with your journey but those other labs will help you get your feet wet in the Xilinx tool flow and beginning design. - John_HArticle: 127249
posedge52@yahoo.com wrote: > What's the 6-pin connection "J8" on the lower-left of the Xilinx/ > Digilent "Spartan-3E starter kit" (rev D) wired too ..?, can't find it > in the schematics.. > > Google search doesn't turn up anything useful either. J8 appears to be labeled on the board as "CPLD JTAG." I don't have my revD board here at home but I looked through the user guide and found figure 2-3, page 16, had a good closeup of that corner of the board http://www.xilinx.com/support/documentation/boards_and_kits/ug230.pdf I don't believe this is the "J28" mentioned for an alternate JTAG in the user guide but, instead, part of the super-secret embedded USB JTAG programmer. If you download the schematics separately http://www.xilinx.com/support/documentation/boards_and_kits/S3E_Starter_Schematic.pdf you'll find page 3 is intentionally left blank. It's here that the USB chip and supporting circuitry would be found. If you find an undocumented CPLD next to the Cypress chip, you'll probably find its JTAG pins connected to J8. Have fun with your board! - John_H
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z