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On Jan 4, 12:56=A0pm, Jon Beniston <j...@beniston.com> wrote: > On 4 Jan, 17:08, FPGA <FPGA.unkn...@gmail.com> wrote: > > > I want to write a function to > > 1) convert single precision 32 bit floating point number to integer > > and return integer > > 2) convert integer to single precision floating point number and > > return 32 bit floating point > > > What are the parameters I should give to each functions and what logic > > do I use for both the functions. > > > Do i need to write seperate function for signed and unsigned numbers? > > > Your help would be appreciated > > Is this homework / an assignment? yesArticle: 127651
FPGA wrote:
> I have 2 inputs
> x : unsigned
> bw : integer
> when x>bw I want to check if x(x'length downto bw) = "1111111......"
> How do i write this in VHDL since my length of x is unknown
A vector of unknown length could be
an entity port or a subprogram parameter.
These are usually handled using
the array attributes 'length or 'range.
and a for loop like this:
for i in x'range loop
result := some_function(result, x(i));
end loop;
-- Mike Treseler
Article: 127652On Dec 14 2007, 12:21=A0am, "mynewlife...@yahoo.com.cn" <mynewlife...@yahoo.com.cn> wrote: > When i use chipscope 9.2 to configerate bit file, sometimes will > occour warning like this "WARNING - Device 0:ICONCoreversionv15.15 > is not supported", and the configeration =A0failed. When this happen, I > rerun the some project, then configeration is successed. Please tell > me why this happen, thanks! I recently came across the same problem when trying to use ChipScope on an older product using VirtexE devices while using the 9.1i Xilinx tools version. It worked without the warning when I went back to the older 6.3i version of the Xilinx tools.Article: 127653
On Fri, 4 Jan 2008 10:15:45 -0800 (PST), FPGA <FPGA.unknown@gmail.com> wrote: >On Jan 4, 12:56 pm, Jon Beniston <j...@beniston.com> wrote: >> On 4 Jan, 17:08, FPGA <FPGA.unkn...@gmail.com> wrote: >> >> > I want to write a function to >> > 1) convert single precision 32 bit floating point number to integer >> > and return integer >> > 2) convert integer to single precision floating point number and >> > return 32 bit floating point >> >> > What are the parameters I should give to each functions and what logic >> > do I use for both the functions. >> >> > Do i need to write seperate function for signed and unsigned numbers? >> >> > Your help would be appreciated >> >> Is this homework / an assignment? > >yes do we get the diploma if we answer or does it still go to you?Article: 127654
On Jan 4, 9:00 am, FPGA <FPGA.unkn...@gmail.com> wrote: > I fixed the problem which I had initially. > I have a new one now :) > > ** Fatal: (vsim-3420) Array lengths do not match. Left is 3 (2 downto > 0). Right is 0 (-1 downto 0 (null array)). > # Time: 0 ns Iteration: 0 Process: /util_tb/uut/line__55 File: C:/ > Modeltech_pe_edu_6.3c/examples/floor_top.vhd > # Fatal error in Architecture behavioral at C:/Modeltech_pe_edu_6.3c/ > examples/floor_top.vhd line 55 > # > > line 55 is > y <= floor(x,bw); > > Please help > > On Jan 4, 9:39 am, Brian Drummond <brian_drumm...@btconnect.com> > wrote: > > > On Fri, 4 Jan 2008 05:10:39 -0800 (PST), FPGA <FPGA.unkn...@gmail.com> > > wrote: > > > >I havw writtent the following code. It compiles correctly. When i run > > >the simulation it just stops and points to this statement > > >variable result : unsigned(bw-1 downto 0); > > > It would. > > > >The code and test bench are as below > > >-- VHDL library declarations > > >library ieee; > > >use ieee.std_logic_1164.all; > > >use ieee.std_logic_unsigned.all; > > > This is NOT a standard library. Don't use it.>use ieee.numeric_std.all; > > > This is a standard library and works well. > > > What you have done here is introduce two different incompatible > > definitions of "unsigned"... > > - Brian For some reason, and I'm not sure why yet, bw is starting out at zero. The earlier comments about the assignment taking place at 0 + 1 or more deltas is correct, but as per the previous comment, I would have expected the initial value on bw to be integer'low which is at least -(2**31-1). There are a couple of ways to fix the problem, the simplest it to explicitly initialize bw to 3 in its declaration. However, the bw parameter shouldn't really be associated with a signal or even a variable, since it sets the width of the return value, and that must match the static width of the signal to which the result is being assigned. Therefore, bw should probably be a constant, or could also be replaced by y'length in the call to floor. I would also declare the bw constant to be of type positive, since you know it has to be greater than zero. If it were a generic, I would certainly declare it with type positive to ensure that nobody tried to set it to zero or negative. On the subject of generics, I noticed the comment in your code that test bench entities are ALWAYS EMPTY. Such is not the case. It can be very useful to put generic declarations on the test bench entity, with default values, so that they can be overridden via command-line option when compiled/elaborated/simulated. This can be used to run different test cases without changing the code. Hope this helps, AndyArticle: 127655
On Tue, 1 Jan 2008 12:07:17 -0800 (PST), Peter Alfke <alfke@sbcglobal.net> wrote: > >For the next-generation clock box (1 Hz to 1.5 GHz with ~50 ps >jitter) >I need an LCD-backlit or OLED display, 128 x 64 bits, single or >multiple colors, about 2 inch diagonal. >OSRAM had a nice OLED display, but they went out of that business. >Billions of cellphones, cameras, and iPods are being made, but where >can I buy a couple of hundred displays? >This is holding up a neat project. :-( >Any help is really appreciated ! >Peter Alfke We just got the demo Newhaven 20x2, 30 mm high COG white backlit LCD. It's all glass, no PCB, so it would be mounted by soldering the leads, plus some adhesive or foam tape to a motherboard. Visually, it's gorgeous. $7.07 single-piece price! ftp://66.117.156.8/Lcd_front.JPG ftp://66.117.156.8/Lcd_back.jpg ftp://66.117.156.8/Lcd_demo_bd.JPG JohnArticle: 127656
vasile wrote: > Please enlight me: how do you know the trace you are discussing about > will have the "reference" plane either the ground plane or the ground > signal plane ? > The return path will be the smallest impedance path. Meaning it could > be a part from the ground plane and a part of your solid signal ground > plane. You haven't too many options in controlling precisely the > return path as long you have plenty of vias between those two ground > planes... The current will be inverse proportional to the impedance of the different paths. Thinking about this again, as the frequency increases the dI/dt increases but the period decreases so the needed current stays constant and the charge per cycle decreases. If that charge comes from the capacitance of the ground and power planes, the required area depends on the current and capacitance, and decreases with increasing frequency (to first order, anyway). Considering the one plane case (no continuous ground plane like the recent discussion was considering.) For 50 ohms and 2 volts, the current is 40ma, the charge per cycle 40ma/f. This will be the same amount of charge per cycle as that on the signal line itself, and so can be connected to the capacitance of the signal line. That charge will be over an area of the trace width times the wavelength. The effect of the discontinuity is expected to start becoming significant as the wavelength approaches 10 times the gap width. Assuming gap width is close to trace width, the area needed is 10 times (trace width) squared, or about a radius of sqrt(10) times trace width around the point where the signal crosses the gap. (sqrt(10*trace width * gap width) is the trace width is not close to the gap width.) If one wants the voltage in the split plane to be about 1/10 of the signal voltage another factor of 10 to the area, or sqrt(10) to the width. This would seem to indicate that if the traces as they cross the gap are spaced more than about 10 trace widths apart then the plane capacitance should be enough to cover the needed charge. -- glenArticle: 127657
"FPGA" <FPGA.unknown@gmail.com> wrote in message news:d058a299-05ae-41aa-80de-be4db769c99c@f3g2000hsg.googlegroups.com... On Jan 4, 12:56 pm, Jon Beniston <j...@beniston.com> wrote: > On 4 Jan, 17:08, FPGA <FPGA.unkn...@gmail.com> wrote: > > > I want to write a function to > > 1) convert single precision 32 bit floating point number to integer > > and return integer > > 2) convert integer to single precision floating point number and > > return 32 bit floating point > > > What are the parameters I should give to each functions and what logic > > do I use for both the functions. > > > Do i need to write seperate function for signed and unsigned numbers? > > > Your help would be appreciated > > Is this homework / an assignment? > > yes At least you are honest. I would suggest you search the web first since there is a lot of stuff available on-line and then come back with specific questions. If you know a bit of C/C++ then I would suggest you also look at GCC's floatlibc.c which contains these 2 functions, if you understand them then translating them to VHDL shouldn't be too difficult. Good luck! Hans www.ht-lab.comArticle: 127658
On Jan 4, 2:00=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: > > The current will be inverse proportional to the impedance of > the different paths. > > Thinking about this again, as the frequency increases the dI/dt > increases but the period decreases so the needed current stays > constant and the charge per cycle decreases. > > If that charge comes from the capacitance of the > ground and power planes, the required area depends on the > current and capacitance, and decreases with increasing > frequency (to first order, anyway). > > Considering the one plane case (no continuous ground > plane like the recent discussion was considering.) > For 50 ohms and 2 volts, the current is 40ma, the charge per > cycle 40ma/f. =A0This will be the same amount of charge per > cycle as that on the signal line itself, and so can be > connected to the capacitance of the signal line. =A0That charge > will be over an area of the trace width times the wavelength. > The effect of the discontinuity is expected to start becoming > significant as the wavelength approaches 10 times the gap width. > Assuming gap width is close to trace width, the area needed > is 10 times (trace width) squared, or about a radius of sqrt(10) > times trace width around the point where the signal crosses > the gap. =A0(sqrt(10*trace width * gap width) is the trace width > is not close to the gap width.) =A0If one wants the voltage in > the split plane to be about 1/10 of the signal voltage another > factor of 10 to the area, or sqrt(10) to the width. > > This would seem to indicate that if the traces as they cross the > gap are spaced more than about 10 trace widths apart then the plane > capacitance should be enough to cover the needed charge. > > -- glen Glen, You don't appear to take into account what the plane capacitance is. Are we 3pF/sqin? 100pF/sqcm? The results should be significantly different for those extremes in plane capacitance. The factor of 10 for wavelength calculations is used widely for transmission line issues but I don't see where this applies to a signal crossing a split. - John_HArticle: 127659
Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> wrote: >Nico Coesel <nico@puntnl.niks> wrote: >> "Pat Magnits" <Pat@Magnits.com> wrote: > >> >Hi, >> > >> >Am far from being an expert in fpga usage and programming, I was wondering >> >if there exists any ip cores out there that would allow the use of >> >ethernet interfaces on recent FPGAs. For instance say that I have a >> >rather important bandwidth (500Mb/s) and that I want to send that >> >over the Gigabit interface of a Virtex 5 in UDP frames. Is there >> >any blackbox concept IP Core that would allow me to do that without >> >having to learn about UDP frame and TCP >> >and the use of the Xilinx ethernet MAC usage etc etc ? > >> Sending UDP packets is rather straightforward. Look here: > >> http://www.fpga4fun.com/10BASE-T.html > >10base-t and Gigabit ethernet have different implementation difficulty >levels ;-) Not if you are using an external phy (which are relatively cheap). In that case you'll have to implement an MII-like interface which is not very difficult. I estimate a Spartan 3 speed grade 5 should do just fine. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 127660
John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >On Tue, 1 Jan 2008 12:07:17 -0800 (PST), Peter Alfke ><alfke@sbcglobal.net> wrote: > >> >>For the next-generation clock box (1 Hz to 1.5 GHz with ~50 ps >>jitter) >>I need an LCD-backlit or OLED display, 128 x 64 bits, single or >>multiple colors, about 2 inch diagonal. >>OSRAM had a nice OLED display, but they went out of that business. >>Billions of cellphones, cameras, and iPods are being made, but where >>can I buy a couple of hundred displays? >>This is holding up a neat project. :-( >>Any help is really appreciated ! >>Peter Alfke > > >We just got the demo Newhaven 20x2, 30 mm high COG white backlit LCD. >It's all glass, no PCB, so it would be mounted by soldering the leads, >plus some adhesive or foam tape to a motherboard. Visually, it's >gorgeous. $7.07 single-piece price! > >ftp://66.117.156.8/Lcd_front.JPG > >ftp://66.117.156.8/Lcd_back.jpg > >ftp://66.117.156.8/Lcd_demo_bd.JPG Now that is neat! Is it ROHS? Website? -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 127661
On Jan 4, 3:40 pm, n...@puntnl.niks (Nico Coesel) wrote: > John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > >On Tue, 1 Jan 2008 12:07:17 -0800 (PST), Peter Alfke > ><al...@sbcglobal.net> wrote: > > >>For the next-generation clock box (1 Hz to 1.5 GHz with ~50 ps > >>jitter) > >>I need an LCD-backlit or OLED display, 128 x 64 bits, single or > >>multiple colors, about 2 inch diagonal. > >>OSRAM had a nice OLED display, but they went out of that business. > >>Billions of cellphones, cameras, and iPods are being made, but where > >>can I buy a couple of hundred displays? > >>This is holding up a neat project. :-( > >>Any help is really appreciated ! > >>Peter Alfke > > >We just got the demo Newhaven 20x2, 30 mm high COG white backlit LCD. > >It's all glass, no PCB, so it would be mounted by soldering the leads, > >plus some adhesive or foam tape to a motherboard. Visually, it's > >gorgeous. $7.07 single-piece price! > > >ftp://66.117.156.8/Lcd_front.JPG > > >ftp://66.117.156.8/Lcd_back.jpg > > >ftp://66.117.156.8/Lcd_demo_bd.JPG > > Now that is neat! Is it ROHS? Website? > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U opwww.adresboekje.nl Google is your friend: http://www.newhavendisplay.com/index.cfm/page/ptype=product/product_id=316/category_id=223/home_id=155/mode=prod/prd316.htm EBArticle: 127662
On 2008-01-04, Pat Magnits <Pat@Magnits.com> wrote: > FPGAs. For instance say that I have a rather important > bandwidth (500Mb/s) and that I want to send that over the Gigabit interface > of a Virtex 5 in UDP frames. That is not particularly difficult if you are using a dedicated hardware MAC in a Xilinx part or even if you are talking GMII directly to an external PHY. To send UDP frames you don't need to be able to receive anything[*]. Most of the difficulty will actually be in forming the first packet header. For UDP data, you can probably reuse the exact header over and over (as long as the length is always the same). There's a lot of stuff in the header that you take for granted which is provided by your network stack (some of which is done by executing low level protocols over the interface[*]). Also, if you are making a commercial product, you will need to get some actual MAC addresses for your interfaces. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 127663
On 2008-01-04, Habib Bouaziz-Viallet <habib@rigel.systems> wrote: > > Hey what makes you think that the behaviour would be unspecified ? I'm not the original guy, nor do I think it's unspecified, but it's not a strange way to interpret a bunch of nonblocking assignments. After all, x <= x_new; x_old <= x; works just as well as: x_old <= x; x <= x_new; because they happen simultaneously. Why would someone assume: x <= 1; x <= 2; works unless they happened to know it was in the spec? -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 127664
John_H wrote: (I wrote) >>Considering the one plane case (no continuous ground >>plane like the recent discussion was considering.) >>For 50 ohms and 2 volts, the current is 40ma, the charge per >>cycle 40ma/f. This will be the same amount of charge per >>cycle as that on the signal line itself, and so can be >>connected to the capacitance of the signal line. That charge >>will be over an area of the trace width times the wavelength. >>The effect of the discontinuity is expected to start becoming >>significant as the wavelength approaches 10 times the gap width. >>Assuming gap width is close to trace width, the area needed >>is 10 times (trace width) squared, or about a radius of sqrt(10) >>times trace width around the point where the signal crosses >>the gap. (sqrt(10*trace width * gap width) is the trace width >>is not close to the gap width.) If one wants the voltage in >>the split plane to be about 1/10 of the signal voltage another >>factor of 10 to the area, or sqrt(10) to the width. (snip) > You don't appear to take into account what the plane capacitance is. > Are we 3pF/sqin? 100pF/sqcm? The results should be significantly > different for those extremes in plane capacitance. The factor of 10 > for wavelength calculations is used widely for transmission line > issues but I don't see where this applies to a signal crossing a > split. I think the other terms cancel out. I was comparing the capacitance per unit area of the transmission line to the capacitance per unit area needed to support the current (charge) at the boundary. Lower capacitance per unit area will result in higher impedance (for the same trace width), and lower current. I was considering it as a transmission line with a short length impedance discontinuity. The impedance should be the same on both sides of the gap, but different across the gap. The effect, then, depends on the wavelength relative to gap width. -- glenArticle: 127665
On Jan 4, 4:38=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote: <snip> > > I was considering it as a transmission line with a short length > impedance discontinuity. =A0The impedance should be the same on both > sides of the gap, but different across the gap. =A0The effect, then, > depends on the wavelength relative to gap width. > > -- glen- Hide quoted text - > > - Show quoted text - The gap width determines the coupling between the two parts of the plane across the gap. Board level decoupling is important in addition to plane-to-plane capacitance when looking at the effects across the split. If you have only one plane with one full slit and no decoupling from the one side to the other, bad things will happen. The situation doesn't "cancel out." If the planes are poor from a decoupling standpoint (including plane-to-plane capacitance) bad things will happen. What's been suggested with respect to "Black Magic" and such is that the decoupling capacitance in well designed boards swamps out most of the problems the hand-wavers claim will kill a board, providing good signal fidelity and low EMI and crosstalk. If there's no capacitance to aid in the decoupling across that split, bad things will happen. - John_HArticle: 127666
John Larkin wrote: > On Tue, 1 Jan 2008 12:07:17 -0800 (PST), Peter Alfke > <alfke@sbcglobal.net> wrote: > >> For the next-generation clock box (1 Hz to 1.5 GHz with ~50 ps >> jitter) >> I need an LCD-backlit or OLED display, 128 x 64 bits, single or >> multiple colors, about 2 inch diagonal. >> OSRAM had a nice OLED display, but they went out of that business. >> Billions of cellphones, cameras, and iPods are being made, but where >> can I buy a couple of hundred displays? >> This is holding up a neat project. :-( >> Any help is really appreciated ! >> Peter Alfke > > > We just got the demo Newhaven 20x2, 30 mm high COG white backlit LCD. > It's all glass, no PCB, so it would be mounted by soldering the leads, > plus some adhesive or foam tape to a motherboard. Visually, it's > gorgeous. $7.07 single-piece price! > > ftp://66.117.156.8/Lcd_front.JPG > > ftp://66.117.156.8/Lcd_back.jpg > > ftp://66.117.156.8/Lcd_demo_bd.JPG > > > John > > > > You have seen these ? http://www.lcd-module.de/eng/dog/dog.htm -- Regards, Adrian Jansen adrianjansen at internode dot on dot net Design Engineer J & K Micro Systems Microcomputer solutions for industrial control Note reply address is invalid, convert address above to machine form.Article: 127667
John_H wrote: (snip regarding crossing a split power or ground plane) > The gap width determines the coupling between the two parts of the > plane across the gap. Board level decoupling is important in addition > to plane-to-plane capacitance when looking at the effects across the > split. If you have only one plane with one full slit and no > decoupling from the one side to the other, bad things will happen. Yes. The question left is how bad those things might be. Someone had previously suggested that the capacitance of the plane itself would be enough to reduce the effect of those bad things. > The situation doesn't "cancel out." What cancels out is the effect of capacitance per unit area. That is, the result is not dependent on it. That doesn't cancel out the bad things, only how you compare them. > If the planes are poor from a decoupling standpoint (including > plane-to-plane capacitance) bad things will happen. > What's been suggested with respect to "Black Magic" and such is that > the decoupling capacitance in well designed boards swamps out most of > the problems the hand-wavers claim will kill a board, providing good > signal fidelity and low EMI and crosstalk. If there's no capacitance > to aid in the decoupling across that split, bad things will happen. There can't be no capacitance. Just like all wires have inductance, all ground planes have capacitance. The question is, then, how much is there and how much is needed. Question: If you have a metal sphere of radius R in an otherwise empty universe, what is its capacitance? (Hint: it isn't zero.) -- glenArticle: 127668
Le Fri, 04 Jan 2008 14:25:01 +0000, Brian Drummond a écrit: > On 03 Jan 2008 14:44:20 GMT, Habib Bouaziz-Viallet <habib@rigel.systems> > wrote: > >>Le Thu, 03 Jan 2008 15:31:26 +0100, Arlet Ottens a écrit: >> >>> Habib Bouaziz-Viallet wrote: >>> >>>> Le Thu, 03 Jan 2008 15:02:31 +0100, Arlet Ottens a écrit: >>>> >>>>> Habib Bouaziz-Viallet wrote: >>>>>> Hi all ! >>>>>> >>>>>> I simulate a simple design (synchronus RESET/LOAD 8-bits counter) with >>>>>> iverilog and testbench associated. Waveforms with gtkwave looks good. >>>>>> > >>>>>> The "Translate" phase failed : > >>>>>> What's wrong with this ? > >> >>The problem was that some files in ../bin/lin/ have not executing perms. i >>made this : chmod +x winds* or something ... and it compiles fine now ! > > Glad you found the problem this time; but a pointer to finding problems > in general may be useful... Yes it is, but this may be not a general problem because no one has experienced the same. > > the "Translate" phase is basically the NGDbuild program, which writes a > ".bld" report file. This ought to contain a messsage (in your case, such > as "<something> was not found, or not executable : NGDbuild aborting".) > pointing straight at the problem. In fact, be sure that no message of any type has been found in console tab within ise. I've resolved the problem by doing "strace ../bin/lin/ise" > Ditto failures at the "Map" phase; in the ".mrp" map report file, or at > the "PAR" phase, in the ".par" report file. > > - Brian -- HBVArticle: 127669
Le Fri, 04 Jan 2008 13:03:59 +0100, Arlet Ottens a écrit: > Habib Bouaziz-Viallet wrote: >> Le Fri, 04 Jan 2008 11:51:56 +0100, Arlet Ottens a écrit: >> >>> Andreas Ehliar wrote: >>>> On 2008-01-03, Arlet Ottens <usenet+5@c-scape.nl> wrote: >>>>> Habib Bouaziz-Viallet wrote: >>>>>> always @(posedge clk) >>>>>> begin >>>>>> out<=out+1; >>>>>> if (reset==1) >>>>>> out[7:0] <= 0; >>>>>> else if(load==1) >>>>>> out[7:0] <= in[7:0]; >>>>>> end >>>>> You're doing two assignments to 'out' in the same clock cycle. >>>> Doing more than one assignment to a signal is allowed for >>>> synthesizable code, both in Verilog and VHDL. The last assignment >>>> in the process block takes precedence. (This assumes that >>>> all assignments are done in the same process, if not you >>>> will have a whole bunch of problems...) >>> I didn't know that.. Thanks. >>> >>> I noticed it synthesized OK, but I assumed the behavior would be >>> unspecified. >> >> Hey what makes you think that the behaviour would be unspecified ? > > That's just what I had assumed. It is actually specified to take the > last one, like Andreas said, so your original code works as intended. > > Still, you may prefer to make the priority encoding explicit by putting > the "out <= out + 1" assignment in an "else" branch. That way, you won't > be tempted to write something like: > > out <= out + 1; > if( condition ) > out <= out + 1; obviously i never ever write such a thing in any language. Anyway thank you for the topic. -- HBVArticle: 127670
Hi all !
For those who want to download bitstream to Xilinx FPGA via a
microcontroller, i have been writing a small perl script (with a blessed
relief from a guy down her in Grenoble ENSIMAG) that transcript
an rbt file
Xilinx ASCII Bitstream
Created by Bitstream J.40
Design name: my_design.ncd
Architecture: spartan3
Part: 3s50pq208
Date: Thu Jan 3 17:36:05 2008
Bits: 439264
11111111111111111111111111111111
10101010100110010101010101100110
00110000000000001000000000000001
0000000000000000000000000 ....
to a C char array file
(const char tableau[439264] = {0xaa, 0x99, 0x55, 0x66, ...};.
Let me know if someone is interrested.
--
HBV
Article: 127671Ben Jackson <ben@ben.com> wrote: >On 2008-01-04, Pat Magnits <Pat@Magnits.com> wrote: >> FPGAs. For instance say that I have a rather important >> bandwidth (500Mb/s) and that I want to send that over the Gigabit interface >> of a Virtex 5 in UDP frames. > >That is not particularly difficult if you are using a dedicated hardware >MAC in a Xilinx part or even if you are talking GMII directly to an >external PHY. To send UDP frames you don't need to be able to receive >anything[*]. > >Most of the difficulty will actually be in forming the first packet header. >For UDP data, you can probably reuse the exact header over and over (as >long as the length is always the same). There's a lot of stuff in the >header that you take for granted which is provided by your network stack >(some of which is done by executing low level protocols over the >interface[*]). > >Also, if you are making a commercial product, you will need to get >some actual MAC addresses for your interfaces. In theory yes. However there are still loads of MAC address ranges assigned to companies which are long gone or have moved into a different direction. Unless you will be making millions of units, it is quite safe to pick one of those. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 127672
I have a Xilinx/Digilent Spartan-3E starter kit Rev D (with 46V32M16 -6T F). Is there any *simple* demo that stores a picture bitmap in the builtin DDR SDRAM and sends the bitmap to the VGA port continously ..? Is it correct that the DDR SDRAM won't go below 75 MHz due the DLL used ..? (Micron indicate that SDRAM can go as low as a few kHz in clock frequency if needed) I had a look at 3 Xilinx examples, but they seem almost more complicated to get running than to code a sdram controller by myself. Currently trying out opencores controller, but it seems to get stuck synthesis. What voltage is Vtt supposed to have for ddr sdram?, Is every resistor needed, or can one do with a simpler interface if the dram <-> fpga path is less than 1 inch/2 cm ..?Article: 127673
A EP2C5Q208C8 in one of our boards has gone short circuit on the 3v3 supply. We manufacture this board in quantities without any problems, so we would like to investigate why this could have happened, mainly for peace of mind. We removed the chip, and there is less than 70 ohm between all the vccio4,vccio2 pins and GND. So we suspect the chip must have fused internally somehow. However, vccio1 shows no short. The chip 's 3v3 and 1v2 are supplied from two low power regulators (LM317L variety) which can supply no more than 100mA each, so we are a bit puzzled. We suspect two possibilities: 1) A momentary short between one of the I/O pins and the main 5V supply (which can supply high current drive) 2) A software bug might have caused eight of the Cyclone I/O pins to output directly to the output of a 245 CMOS buffer (also fed from the 3v3 current limited supply) . With both FPGA and 245 pins outputting straight into each other. Not sure which way round (possibly cyclone=low 254=high) This situation may have lasted for a long time. Could anybody with experience of these devices suggest whether any of these could have caused the fault?? TIA TedArticle: 127674
On Jan 4, 3:18 pm, "T.Hansen" <honninghu...@hotmail.com> wrote: > If I am looking for buying just the FPGA chip itself - not a development > board - where could I buy this? What do commercial buyers do? Digikey.com have them in single quantities. However they keep a higher price level than many competitors.
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