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Kevin, I just looked at your template again. I think it's slightly wrong: > process(Clock) > begin > if rising_edge(Clock) then > if (Reset = '1') then > Read <= '0'; > Write <= '0'; > elsif (Wait_Request = '0') then > -- Insert your code here that defines when you want to read > something etc. > if (Read = '1') then > Data_That_I_Read <= Readdata; > end if; > end if; > end if; > end process; The "if (Read = '1') then" should be outside the dependency on waitrequest. The waitrequest only has bearing on the input, not on the output. It especially shows up with the slave supports multiple outstanding requests. Regards, TommyArticle: 127001
I've read the Wikipedia article about Direct Digital Synthesis ( http://en.wikipedia.org/wiki/Direct_digital_synthesis ) and building a DDS generator with a FPGA, which interpolates between adjacent entries in the lookup table, looks like some fun. This is my first try: http://it4systems.de/SignalGenerator/doc/index.html Maybe when I have some more time, I'll add more features, like a SPI interface to control it from an external microcontroller and multiple outputs. Any ideas how to improve it? I have read this paper: http://www.analog.com/UploadedFiles/Tutorials/450968421DDS_Tutorial_rev12-2-99.pdf In this document an Inverse Sinc Filter is mentioned, but without details about it. Do you know how to implement it? And does it improve the output of an interpolating generator or is this useful for non-interpolating generators, only? -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 127002
Some more information on our new low cost Spartan-3E development board Drigmorn1. First FAQ and reference design material now on our engineering website. Links to FAQ and application/reference pages here http://www.enterpoint.co.uk/component_replacements/drigmorn1.html. Pricing for the XC3S500E version now posted as well. We are hoping first units will ship this week subject to a passing a final few design tests. A small number of 500E version will be available in the same time frame. John Adair Enterpoint Ltd.Article: 127003
On Dec 8, 1:39 am, Alex Freed <al...@mirrow.com> wrote: > I need to build a sort of a simple video processor to drive a TFT LCD > screen in an embedded system. The plan is to use a small and cheap FPGA > with some memory. Low cost is very important, so fast SRAM is not an > option. > > I want to test the concept on an off-the-shelf board before making my > own, so I got the Spartan 3E "starter kit" that comes with DDR SDRAM. > Unfortunately I can't make the memory work using the core generator. > Most likely I'm not doing something right, but maybe there is some > problem with the hardware. [...] > There is also PSRAM as an option and a Digilent board with S3e and > PSRAM, but it is more expensive than plain SDRAM by far. > > My volume is about 10,000 a year. I figure about $5 for FPGA and $1.5 > for SDRAM (8 MB). PSRAM is more like $5. > > Am I missing something? I'd like to hear opinions before making the next > move. Howdy Alex, First the eval board: yes, it is most likely not a problem with your board. If you are counting pennies on your BOM and need a decent amount of RAM, SDRAM (or DDR - its cheaper this week) is the only way to go, so you need to take the time to debug the one you have. Now, vendors: if your product is really that cost sensitive, get 5k or 10k piece prices from all of the vendors. Include Lattice and others in the mix as well. Whomever has the most responsive sales and support organization, combined with the lowest price, wins your business. The companies will try to turn you against the others, and turn it into a religious argument - but it doesn't sound like you are doing anything that requires pushing any envelopes, so multiple parts from multiple vendors will do. All you need is a good idea of which device size in each family is required so that you can do valid price comparisons. Use the free tools from each company (or request an eval copy) for that if you need. Good luck! MarcArticle: 127004
On Dec 8, 8:50 am, Marc Randolph <mr...@my-deja.com> wrote: > On Dec 8, 1:39 am, Alex Freed <al...@mirrow.com> wrote: > > > > > I need to build a sort of a simple video processor to drive a TFT LCD > > screen in an embedded system. The plan is to use a small and cheap FPGA > > with some memory. Low cost is very important, so fast SRAM is not an > > option. > > > I want to test the concept on an off-the-shelf board before making my > > own, so I got the Spartan 3E "starter kit" that comes with DDR SDRAM. > > Unfortunately I can't make the memory work using the core generator. > > Most likely I'm not doing something right, but maybe there is some > > problem with the hardware. > [...] > > There is also PSRAM as an option and a Digilent board with S3e and > > PSRAM, but it is more expensive than plain SDRAM by far. > > > My volume is about 10,000 a year. I figure about $5 for FPGA and $1.5 > > for SDRAM (8 MB). PSRAM is more like $5. > > > Am I missing something? I'd like to hear opinions before making the next > > move. > > Howdy Alex, > > First the eval board: yes, it is most likely not a problem with your > board. If you are counting pennies on your BOM and need a decent > amount of RAM, SDRAM (or DDR - its cheaper this week) is the only way > to go, so you need to take the time to debug the one you have. > > Now, vendors: if your product is really that cost sensitive, get 5k or > 10k piece prices from all of the vendors. Include Lattice and others > in the mix as well. Whomever has the most responsive sales and > support organization, combined with the lowest price, wins your > business. The companies will try to turn you against the others, and > turn it into a religious argument - but it doesn't sound like you are > doing anything that requires pushing any envelopes, so multiple parts > from multiple vendors will do. All you need is a good idea of which > device size in each family is required so that you can do valid price > comparisons. Use the free tools from each company (or request an eval > copy) for that if you need. > > Good luck! > > Marc One other thing: if you're using an FPGA that doesn't have built in configuration memory (I think each vendor may have one line that does), don't forget to include that in your preliminary BOM. MarcArticle: 127005
"Tommy Thorn" <tommy.thorn@gmail.com> wrote in message
news:a09b0ab6-dc10-41ce-a306-c8b168e1b5d2@a35g2000prf.googlegroups.com...
> Kevin,
>
> I just looked at your template again. I think it's slightly wrong:
>
>> process(Clock)
>> begin
>> if rising_edge(Clock) then
>> if (Reset = '1') then
>> Read <= '0';
>> Write <= '0';
>> elsif (Wait_Request = '0') then
>> -- Insert your code here that defines when you want to read
>> something etc.
>> if (Read = '1') then
>> Data_That_I_Read <= Readdata;
>> end if;
>> end if;
>> end if;
>> end process;
>
> The "if (Read = '1') then" should be outside the dependency on
> waitrequest. The waitrequest only has bearing on the input, not on the
> output. It especially shows up with the slave supports multiple
> outstanding requests.
>
The template is correct for an Avalon master that is not 'latency aware',
which is a master that does not happen to support the optional
'readdatavalid' input. For a master that does support latency you would
have the following code outside of the entire above loop which is what I
think you're referring to.
if rising_edge(Clock) then
if (readdatavalid = '1') then
Data_That_I_Read <= Readdata;
end if;
end if;
Depending on whether the interface is to a device that has latency (like a
controller for an external memory) or if it is some internal interface
between two processing blocks inside the FPGA would be the thing that
determines whether or not one should bother to design the master to handle
latency. You gain no performance advantage by adding latency awareness to
an interface between two things that do not require it, but you pay a price
in terms of logic resources to implement that connection, since the master
and the Avalon fabric (either SOPC generated or home grown) needs to know
and keep track of how many reads are pending and insure that they don't
exceed the 'max_pending_read_transactions' parameter. By the same token,
you definitely lose performance by not supporting latency when talking to a
device that will inherently have it (like a DRAM type memory controller)
where master side latency support allows the master to queue up several
requests on consecutive clocks even before the data from any of the reads
has come back yet and allows you to run DRAM type memory at one access per
clock (except for page hits and refresh of course).
Given the OP's apparent lack of knowledge about Avalon in general, I thought
it best to start off easy and not use readdatavalid which means that
readdata will be valid when the master is requesting a read (Read='1') and
the Waitrequest input to the master is '0'.
Kevin Jennings
Article: 127006Regarding to necessary changes to verilog code, am I missing something, 1. caches and memories, replacing using FPGA block rams. 2. clock gating to clock enable 3. change latches to registers Anything else?Article: 127007
Hi,
I've been able to run a simulation of a PPC405 system example with
ModelsimPE if the executable elf file fits into block ram, but I can't find
a good example of running a program out of external ram. I have a Virtex4FX
card from Avnet with a 32x16Mb DDR ram. They only document with the card
shows how to run the examples on the actual card not simulating the code
I've done this and it works fine but I'd like to look at the execution in
Modelsim. I found an app note via Google (Xilinx App note: XUG436 EDK System
Simulation Tutorial) that aided me in getting me through the block ram
simulation setup but when it discusses running out of external ram it uses
verilog instead of vhdl and I got lost a bit. BTW, I couldn't actually find
this appnote on the Xilinx site- it was generated in Feb 07 but must have
been pulled off the site for some reason?
Do I have to load the file to the simulator via XMD?
Does anyone know of a link to a good tutorial to get me started here?
Thanks
CTW
Article: 127008> My volume is about 10,000 a year. I figure about $5 for FPGA and $1.5 > for SDRAM (8 MB). PSRAM is more like $5. > > Am I missing something? I'd like to hear opinions before making the next > move. Regarding the "X vs. A" discussion, I encourage you to price out options from all competitors, and see what's right. For instance, Actel's Fusion line of flash-based FPGAs includes a built-in oscillator, D/A and A/D converter, temperature monitor, NVRAM, etc..... You might find that it suits your overall (low-cost, low- power) requirements. K.Article: 127009
Alex Freed <alexf@mirrow.com> wrote: > >I need to build a sort of a simple video processor to drive a TFT LCD >screen in an embedded system. The plan is to use a small and cheap FPGA >with some memory. Low cost is very important, so fast SRAM is not an >option. > >I want to test the concept on an off-the-shelf board before making my >own, so I got the Spartan 3E "starter kit" that comes with DDR SDRAM. >Unfortunately I can't make the memory work using the core generator. >Most likely I'm not doing something right, but maybe there is some >problem with the hardware. > >While searching for info on SDRAM interfacing I got an impression that >the DDR SDRAM is very difficult to use and the board layout is very >critical. For my application 133 MHZ DDR is a heck of an overkill as I >only need to read 16 bits of consecutive data at 50 MHz (burst) max. Most DDR wil operate down to 81 MHz. At 81MHz it is not so difficult to get DDR working. Just stay away from the MIG tools for simple down to earth solutions. >So regular SDRAM is probably a better choice. I'm also using Micron >SDRAM elsewhere on my device (with the PXA255 CPU). You can probably design a controller which does both SDRAM and DDR. The control signals are very similar. The only difference is that DDR outputs data on both edges. >Looking for a board with built in SDRAM I came across the $150 Altera >DE1. Traditionally I used X more than A, but those were CPLDs rather >than FPGAs. The data sheet looks promising. Only 2 power voltages. Same >cost (Cyclone 2 vs. Spartan 3e). > >There is also PSRAM as an option and a Digilent board with S3e and >PSRAM, but it is more expensive than plain SDRAM by far. > >My volume is about 10,000 a year. I figure about $5 for FPGA and $1.5 >for SDRAM (8 MB). PSRAM is more like $5. > >Am I missing something? I'd like to hear opinions before making the next >move. One thing to watch out for is that (AFAIK) Altera has no memory in their slices. In Xilinx FPGAs it is possible to use the lookup table as a 1x16 bit memory. This can prove very usefull for creating small memories (like dual buffers, fifos, etc). In Altera devices you'll need to use flipflops. A 32x16 memory uses 16 slices in a Xilinx device and probably at least 256 or 512 slices (some extra slices are needed for the memory decoder and data muxes) in an Altera device. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 127010
Dear ctw,
I have a application with a microblaze for a ML401-Board. For this
system i have setup a simulation environment.
1. Compile your application and set the program start to the external
memory.
2. convert your elf file into a .mem file. In my application there a two
16 bit memory combined to a 32bit Memory. You need two files, on for
every memory.
convert cmd:
>>
data2mem -bx ./ -u -i -o m ddr -p xc4vlx25 -bm memory_init.bmm -bd
executable.elf
<<
My .bmm File:
>>
ADDRESS_BLOCK DDR_memory MEMORY [0x00000000:0x03FFFFFF]
BUS_BLOCK
system_tb/ddr1 [31:16] OUTPUT = ddr1.mem;
system_tb/ddr0 [15:0] OUTPUT = ddr0.mem;
END_BUS_BLOCK;
END_ADDRESS_BLOCK;
<<
3. You need a memory model, for example from micron. (verilog only, )
Compile all files in Modelsim.
4. Preload memory with following commands and run simulation:
>>
vsim -t ps test_opb_spi_slave_master_tb_behavior_cfg
view wave
do test_opb_spi_slave_master_tb_w.do
mem load -infile ../../test_spi/ddr1.mem -format hex
"/test_opb_spi_slave_master_tb/mt46v16m16_1/mem_array"
mem load -infile ../../test_spi/ddr0.mem -format hex
"/test_opb_spi_slave_master_tb/mt46v16m16_2/mem_array"
run 400 us
<<
5. There are many possible problems with the Simulation
- After every restart of your Simulation you must reload the memorys
- There are some memory controllers from Xilinx with special adressing
map. For example mch_opb_ddr_v1_00_c.
Normal Adress-Mapping:
ddr-adress <= ba_adress & row_adress & colum_adress;
Xilinx special Mode:
ddr-adress <= row_adress & ba_adress & colum_adress;
- Check little an big endian issues.
- Many memory-models support only a small permanent memory, all other
memory calls a allocated on demand. For micron Model set in the
ddr_parameters.vh file the parameter "part_mem_bits = 10" to a high
value if your application is bigger.
- many more ..
I want to share my experience with the community. There will a example
design availably next year at www.opencores.org for the IP-Core OPB SPI
Slave.
Daniel
cwoodring schrieb:
> Hi,
> I've been able to run a simulation of a PPC405 system example with
> ModelsimPE if the executable elf file fits into block ram, but I can't
find
> a good example of running a program out of external ram. I have a
Virtex4FX
> card from Avnet with a 32x16Mb DDR ram. They only document with the card
> shows how to run the examples on the actual card not simulating the code
> I've done this and it works fine but I'd like to look at the execution in
> Modelsim. I found an app note via Google (Xilinx App note: XUG436 EDK
System
> Simulation Tutorial) that aided me in getting me through the block ram
> simulation setup but when it discusses running out of external ram it
uses
> verilog instead of vhdl and I got lost a bit. BTW, I couldn't actually
find
> this appnote on the Xilinx site- it was generated in Feb 07 but must have
> been pulled off the site for some reason?
> Do I have to load the file to the simulator via XMD?
> Does anyone know of a link to a good tutorial to get me started here?
>
> Thanks
>
> CTW
>
>
cwoodring schrieb:
> Hi,
> I've been able to run a simulation of a PPC405 system example with
> ModelsimPE if the executable elf file fits into block ram, but I can't find
> a good example of running a program out of external ram. I have a Virtex4FX
> card from Avnet with a 32x16Mb DDR ram. They only document with the card
> shows how to run the examples on the actual card not simulating the code
> I've done this and it works fine but I'd like to look at the execution in
> Modelsim. I found an app note via Google (Xilinx App note: XUG436 EDK System
> Simulation Tutorial) that aided me in getting me through the block ram
> simulation setup but when it discusses running out of external ram it uses
> verilog instead of vhdl and I got lost a bit. BTW, I couldn't actually find
> this appnote on the Xilinx site- it was generated in Feb 07 but must have
> been pulled off the site for some reason?
> Do I have to load the file to the simulator via XMD?
> Does anyone know of a link to a good tutorial to get me started here?
>
> Thanks
>
> CTW
>
>
Article: 127011On Dec 8, 8:55 am, n...@puntnl.niks (Nico Coesel) wrote: > Alex Freed <al...@mirrow.com> wrote: > > >I need to build a sort of a simple video processor to drive a TFT LCD > >screen in an embedded system. The plan is to use a small and cheap FPGA > >with some memory. Low cost is very important, so fast SRAM is not an > >option. > > >I want to test the concept on an off-the-shelf board before making my > >own, so I got the Spartan 3E "starter kit" that comes with DDR SDRAM. > >Unfortunately I can't make the memory work using the core generator. > >Most likely I'm not doing something right, but maybe there is some > >problem with the hardware. > > >While searching for info on SDRAM interfacing I got an impression that > >the DDR SDRAM is very difficult to use and the board layout is very > >critical. For my application 133 MHZ DDR is a heck of an overkill as I > >only need to read 16 bits of consecutive data at 50 MHz (burst) max. > > Most DDR wil operate down to 81 MHz. At 81MHz it is not so difficult > to get DDR working. Just stay away from the MIG tools for simple down > to earth solutions. > > >So regular SDRAM is probably a better choice. I'm also using Micron > >SDRAM elsewhere on my device (with the PXA255 CPU). > > You can probably design a controller which does both SDRAM and DDR. > The control signals are very similar. The only difference is that DDR > outputs data on both edges. > > >Looking for a board with built in SDRAM I came across the $150 Altera > >DE1. Traditionally I used X more than A, but those were CPLDs rather > >than FPGAs. The data sheet looks promising. Only 2 power voltages. Same > >cost (Cyclone 2 vs. Spartan 3e). > > >There is also PSRAM as an option and a Digilent board with S3e and > >PSRAM, but it is more expensive than plain SDRAM by far. > > >My volume is about 10,000 a year. I figure about $5 for FPGA and $1.5 > >for SDRAM (8 MB). PSRAM is more like $5. > > >Am I missing something? I'd like to hear opinions before making the next > >move. > > One thing to watch out for is that (AFAIK) Altera has no memory in > their slices. In Xilinx FPGAs it is possible to use the lookup table > as a 1x16 bit memory. This can prove very usefull for creating small > memories (like dual buffers, fifos, etc). In Altera devices you'll > need to use flipflops. A 32x16 memory uses 16 slices in a Xilinx > device and probably at least 256 or 512 slices (some extra slices are > needed for the memory decoder and data muxes) in an Altera device. > > -- > Reply to nico@nctdevpuntnl (punt=.) > Bedrijven en winkels vindt U opwww.adresboekje.nl- Hide quoted text - > > - Show quoted text - Hi Alex and Nico, The Stratix III devces allow individual LABS to be configured as small grain distributed memory. More details can be found at: http://www.altera.com/products/devices/stratix3/overview/architecture/st3-trimatrix.html The Stratix III devices have the additional advantage of being the most power efficient devices in their class today. Hope this helps, Subroto Datta Altera Corp.Article: 127012
"Nico Coesel" <nico@puntnl.niks> wrote in message news:475acaae.411023049@news.planet.nl... > Alex Freed <alexf@mirrow.com> wrote: > > One thing to watch out for is that (AFAIK) Altera has no memory in > their slices. In Xilinx FPGAs it is possible to use the lookup table > as a 1x16 bit memory. This can prove very usefull for creating small > memories (like dual buffers, fifos, etc). In Altera devices you'll > need to use flipflops. A 32x16 memory uses 16 slices in a Xilinx > device and probably at least 256 or 512 slices (some extra slices are > needed for the memory decoder and data muxes) in an Altera device. Brand A has M4K (4K bits) and M512 (512 bits) available depending on which device you're targetting. That's just the basic memory primitive, if you need more Quartus will assemble the proper number of these primitives, you won't be constructing look up tables from logic and flops if your code is written per the usual template for synthesizable memory devices. Different but roughly equivalent to brand X. KJArticle: 127013
On Dec 8, 8:27 am, wei.wang.can...@googlemail.com wrote: > Regarding to necessary changes to verilog code, am I missing > something, > 1. caches and memories, replacing using FPGA block rams. > 2. clock gating to clock enable > 3. change latches to registers > Anything else? That's a very broad question. What you need to do during the ASIC- >FPGA conversion is very dependent on the architecture of the target FPGA. For example, many (but not all) modern FPGAs include multiplier or MAC macros and fast adder chains. If your ASIC used multiply or add operations they may have been coded at the gate level which is wasteful if your FPGA has these built-in. In this case you'll want to abstract the arithmetic functions to allow inference of the native FPGA resources, or instantiate the primitives in your source code. EBArticle: 127014
Frank Buss wrote:
> I've read the Wikipedia article about Direct Digital Synthesis (
> http://en.wikipedia.org/wiki/Direct_digital_synthesis ) and building a DDS
> generator with a FPGA, which interpolates between adjacent entries in the
> lookup table, looks like some fun. This is my first try:
>
> http://it4systems.de/SignalGenerator/doc/index.html
Thanks for posting the code examples.
Good work.
I like your coding style, and judging
from the scope trace, it must be working.
> Any ideas how to improve it?
I would work on the testbench.
It is stuck in idle as is.
Then add an assertion or two
to verify some functionality.
-- Mike Treseler
Article: 127015On Dec 8, 6:15 am, Frank Buss <f...@frank-buss.de> wrote: > I've read the Wikipedia article about Direct Digital Synthesis (http://en.wikipedia.org/wiki/Direct_digital_synthesis) and building a DDS > generator with a FPGA, which interpolates between adjacent entries in the > lookup table, looks like some fun. This is my first try: > > http://it4systems.de/SignalGenerator/doc/index.html > > Maybe when I have some more time, I'll add more features, like a SPI > interface to control it from an external microcontroller and multiple > outputs. > > Any ideas how to improve it? I have read this paper: > > http://www.analog.com/UploadedFiles/Tutorials/450968421DDS_Tutorial_r... > > In this document an Inverse Sinc Filter is mentioned, but without details > about it. Do you know how to implement it? And does it improve the output > of an interpolating generator or is this useful for non-interpolating > generators, only? > > -- > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-systems.de A few suggestions: * Use a longer Sine lookup table instead of interpolation. * Store only 1/4 cycle of the sinewave in the lookup table and use bit operations on the address and output to map the 1/4 cycle onto the full wave. * Use a dual-port RAM for the lookup table to simultaneously generate sine & cosine (useful for digital radio applications) Inverse sinc filters are common ways to equalize the spectral droop caused by the zero-order hold nature of the DAC. Typically a simple FIR filter with a few taps (<10) can 'lift' the high frequency response of the signal to compensate for this rolloff. This page describes one way to do it: http://www.maxim-ic.com/appnotes.cfm/an_pk/3853 EBArticle: 127016
"KJ" <kkjennings@sbcglobal.net> wrote: > >"Nico Coesel" <nico@puntnl.niks> wrote in message >news:475acaae.411023049@news.planet.nl... >> Alex Freed <alexf@mirrow.com> wrote: >> >> One thing to watch out for is that (AFAIK) Altera has no memory in >> their slices. In Xilinx FPGAs it is possible to use the lookup table >> as a 1x16 bit memory. This can prove very usefull for creating small >> memories (like dual buffers, fifos, etc). In Altera devices you'll >> need to use flipflops. A 32x16 memory uses 16 slices in a Xilinx >> device and probably at least 256 or 512 slices (some extra slices are >> needed for the memory decoder and data muxes) in an Altera device. > >Brand A has M4K (4K bits) and M512 (512 bits) available depending on which >device you're targetting. That's just the basic memory primitive, if you >need more Quartus will assemble the proper number of these primitives, you >won't be constructing look up tables from logic and flops if your code is >written per the usual template for synthesizable memory devices. Different >but roughly equivalent to brand X. Not at all. The way Xilinx's devices work is much more flexible and consumes less routing resources because the memory can be mixed/combined with logic. If you need to bring signals to and from a memory block, you'll need more routing resources and require the logic to be concentrated close to the memory. Both resulting in more delays, lower speed and hot spots on the die. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 127017
Alex Freed <alexf@mirrow.com> wrote: > >I need to build a sort of a simple video processor to drive a TFT LCD >screen in an embedded system. The plan is to use a small and cheap FPGA >with some memory. Low cost is very important, so fast SRAM is not an >option. Why not choose a CPU with build-in LCD controller? For instance, the LCD controller in the Blackfin from Analog Devices should -according to the maximum pixel clock- be able to do 1280x1024 @ 50Hz. You can buy 2 Blackfins for the price of one FPGA and get the design ready much faster. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 127018
"Frank Buss" <fb@frank-buss.de> wrote in message news:1pksute7pasie.9eglznqt557g.dlg@40tude.net... > > Any ideas how to improve it? I have read this paper: > Nice job. You should synchronize 'reset' to the clock and then use that synchronized reset to reset your state machine and the counter signal). If reset happens to go away inside of the setup/hold window of any of the flops you'll get into an odd initial state or count. KJArticle: 127019
Hi, I ran into a small problem while trying to use a UCF file created for ISE 8.2 within EDK 9.1. I had a few INSTs and NETs relatively deep within the design's hierarchy: INST "ioring/U_top/u_adc_clk_dcm" FACTORY_JF = "ABCD"; NET "ioring/U_top/sdram_clk_sig" TNM = sdramclk; I get an error from Xilinx stating it can find neither the instance nor the net when trying to implement these constraints. Looking around, I found the solution for the INST using the syntax: INST "ioring/*U_top/* u_adc_clk_dcm" FACTORY_JF = "ABCD"; But It didn't work for the net (sdram_clk_sig is a std_logic signal within the U_top instance). Anybody knows the correct syntax to access a net within such hierarchy with Xilinx 9.1? Thanks. LouisArticle: 127020
Marc Randolph wrote: Thanks for comments, Marc >> >> First the eval board: yes, it is most likely not a problem with your >> board. If you are counting pennies on your BOM and need a decent >> amount of RAM, SDRAM (or DDR - its cheaper this week) is the only way >> to go, so you need to take the time to debug the one you have. OK, I didn't doubt much that SDRAM was the way to go, but I got an impression that DDR is way more difficult to work with and I don't need the bandwidth. So probably the regular SDR is it. Especially considering I already have it in my BOM. >> >> Now, vendors: if your product is really that cost sensitive, get 5k or >> 10k piece prices from all of the vendors. Include Lattice and others >> in the mix as well. Probably not. I'm well used to X tools, somewhat used to A tools and unless there is a huge potential win would rather not learn yet another toolset. >> Use the free tools from each company (or request an eval >> copy) for that if you need. As I said I was using the tools for a long time. It's just the SDRAM that I have zero experience with. > > One other thing: if you're using an FPGA that doesn't have built in > configuration memory (I think each vendor may have one line that > does), don't forget to include that in your preliminary BOM. Well, modern FPGAs from both X and A work with dirt cheap commodity serial flash. However I have a hard CPU with 32 MB of flash, so I can configure FPGAs for free. More flexible too. -Alex.Article: 127021
Subroto Datta wrote: > > Hi Alex and Nico, > > The Stratix III devces allow individual LABS to be configured as > small grain distributed memory. This is nice to know, but probably not relevant to my design that calls for rock bottom priced silicon. -Alex.Article: 127022
Nico Coesel wrote: > > Why not choose a CPU with build-in LCD controller? I have a build-in LCD controller in the PXA255. It just does not have the performance needed. So I want to preserve most software of the existing system and add better graphics. >For instance, the > LCD controller in the Blackfin from Analog Devices should -according > to the maximum pixel clock- be able to do 1280x1024 @ 50Hz. You can > buy 2 Blackfins for the price of one FPGA and get the design ready > much faster. > It's worth looking into, but a quick look-up only showed ucLinux ported. Does it mean there is no MMU? -Alex.Article: 127023
"Andy" <jonesandy@comcast.net> wrote in message
news:af32e2be-225e-41c7-96ae-17ff1612049e@d27g2000prf.googlegroups.com...
> On Dec 5, 6:30 pm, "KJ" <kkjenni...@sbcglobal.net> wrote:
>> Instead what is more useful is a known way to reliably write code to
>> perform
>> that function that will work well. The form I chose was deliberately
>> done
>> to demonstrate a technique to that, by simple inspection, can be seen to
>> be
>> functionally equivalent and synthesizable. The better approach for a
>> double
>> edged flop that you'd really like to use in an actual design was
>> demonstrated by Andy and Mike...but as you can see from rickman's
>> misinterpretation it wasn't obvious to him at first glance, whereas my
>> approach was obvious but left him uneasy about using the clock in logic
>> (and
>> rightly so).
>
> One other disadvantage of the explicit coding is that you cannot
> implement it with data types for which XOR (or XNOR) operations are
> not defined, like enumerated types, records, arrays, integers, etc. at
> least not without additional code to define the XOR, which may or may
> not limit further optimization. For example, you can define an XOR
> operator for an enumerated type, but you must dictate a binary mapping
> explicitly, rather than letting the synthesis tool figure out the best
> mapping.
That's one view of it. A more general view is that the 'xor' pair that
precedes the flip flops and the 'xor' that does the final combination to
produce the outputs perform inverse functions...it just happens that 'xor'
is a function that is its own functional inverse. With this more general
view of it as performing some function that has an exact inverse function,
one could instead use integers or reals as the 'd', 'q' signals (as well as
integers or reals for the 'qr' and 'qf' variables) and have a double edge
entity for integers or reals as well (code for integers is posted at the end
of this posting) and it synthesizes just fine with Quartus (for integers).
You use the "-" operator to replace the 'xor' feeding the registers and the
"+" operator to replace the 'xor' that combines the register results into
the final result.
The 'xor' is an operator that only applies to boolean logic signals whereas
"+" and "-" are operators that work with numbers. Obviously "+" and "-" are
inverse functions of each other so they meet the minimum criteria. Another
criteria has to do with closed loop system stability (switch the usage "+"
and "-" and watch the simulation oscillate). This is why the "-" is applied
prior to the register and the "+" to compute the final output. In a sense
the "-" compuation is computing a difference signal in a form like is
routinely done in a closed loop control system.
The nice thing on this example is that it clearly demonstrates the different
roles that 'xor' is really playing where it computes the final output as
opposed to its role in computing the register inputs. The reason you can't
apply this technique to enumerated types and records and such is because
there are no mathematical operators that apply to these types....but there
are mathematical operators for numbers as well as booleans. It's the lack
of mathematical operators that is the problem, not any sort of limitation in
the language or boolean logic.
>
> My point is you can infer an SDR register that will store any data
> type with a simple assignment in a clocked process. It should be that
> simple with DDR registers too.
>
I'm not seeing any reason why this would be of any practical use though. On
the rare instances where I've needed to sample on rising and falling edges
it's been because of the timing of some part that is external to the
FPGA/CPLD. In those rare situations, the critical timing path runs right up
to the input of those registers. If the inputs are simply brought right in,
they can always be placed in a flop in the IOB which minimizes any min/max
differences in the delay from the input pin to the 'D' input of the flop.
Inserting any logic (like the 'xor') forces it out of the IOB and increases
not only the delay from the pin to the 'D' input of the flip flop, but more
importantly, the uncertainty increases as well (i.e. the difference between
Tsu(min) and Tsu(max)) which makes timing verification more difficult.
I've never run across the situation where an internal interface to the FPGA
required using both edges. If it did, the interface is the problem, it
should be widened. Given that, one can reason that it is not very likely
that one would ever want double edge flops anyplace except at the I/O pins
of the device....and those I/O pins in any practical design are not going to
be records or enumerated types....they are mostly std_logic(_vector).
Kevin Jennings
================
Synthesizable code that performs rising/falling edge sampling of an integer.
Blatently based on (OK copied from) Mike Tresler's posting earlier in this
thread which used std_logic for 'd' and 'q'.
library ieee;
use ieee.std_logic_1164.all;
entity double_edge_integer is
generic (vec_len : positive := 8);
port (
clk : in std_ulogic;
rst : in std_ulogic;
d : in integer;
q : out integer
);
end entity double_edge_integer;
----------------------------------------------
architecture synth of double_edge_integer is
begin
double_edge : process (clk, rst) is
variable qr, qf : integer;
begin
if rst = '1' then
qr := 0;
qf := 0;
elsif rising_edge(clk) then
qr := d - qf;
elsif falling_edge(clk) then
qf := d - qr;
end if;
q <= qr + qf;
-- combinatorial "+" of registered qr,qf
end process double_edge;
end architecture synth;
Article: 127024"Ray Andraka" <ray@andraka.com> wrote in message news:6Mg6j.3083$AN1.1540@newsfe16.lga... > I remember seeing them in DRAM controllers too. That doesn't make it good > design though. There were fewer choices then since the DRAM generally ran > off the processor clock making it difficult and expensive to get a > multiplied clock (PLLs of the day were much slower than the clock rates > for DRAM) needed to get clock edges placed at fractional cycle points > without using delay lines to generate those clocks. The better DRAM > designs used the delay line to generate a delayed clock rather than > delaying memory signals. Hmmm....at the start of paragraph you imply that the usage of delay lines in DRAM controllers is not 'good design' but later on go on to say that the 'better DRAM designs' used them..... KJ
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