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On Sat, 8 Dec 2007 14:15:57 +0100, Frank Buss <fb@frank-buss.de> wrote: >I've read the Wikipedia article about Direct Digital Synthesis ( >http://en.wikipedia.org/wiki/Direct_digital_synthesis ) and building a DDS >generator with a FPGA, which interpolates between adjacent entries in the >lookup table, looks like some fun. This is my first try: > >http://it4systems.de/SignalGenerator/doc/index.html > >Maybe when I have some more time, I'll add more features, like a SPI >interface to control it from an external microcontroller and multiple >outputs. > >Any ideas how to improve it? I have read this paper: Consider redesigning it to incorporate the following features: 1. Produce an output every clock. This allows much higher output update rates, which can greatly improve the quality of the output. You'll have to throw away your state machine and go to a fully pipelined datapath approach. 2. Increase the maximum clock rate. Design it so that the Fmax of the ram is the only limitation. 3. The mid-sized rams from both X and A are dual port. This allows you to do two lookups in the same clock, which is needed for step 1. 4. As others have pointed out, utilise the symmetry of the sine function to reduce the size of the lookup table by a factor of 4. Equivalently, get 4 times the phase resolution in your table for a given size of ram. Regards, Allan.Article: 127026
Hi everyone: Is there any manual about the symbols in Timing closure Floorplan, Quartus II? I do not find a detailed description about that. Especially, I don't clearly understand the clock control block in the Timing closure Floorplan (Cyclone II). There is symbol called "...@CLKDELAYCTRL_GO". Does that mean the user can add a delay to a clock signal before it drives the global clock network? If this is true, how can I fulfill this by the setting the Quartus II? Also,I have a question about the timing assignments for individual paths. In the box of Assignment Name (Assigment editor window with the category of timing), there are two terms called" input maximum delay" and "tsu". I do not know the difference between their functions. Can this two terms have the relationship of: tsu= tclk-input maximum delay? Or can a function implemented by " input maximum delay" be implemented by "tsu"? Thank you. Leon,Article: 127027
On Dec 7, 4:06 pm, KJ <Kevin.Jenni...@unisys.com> wrote:
> On Dec 7, 3:22 pm, steve_blah <srpen...@gmail.com> wrote:
>
>
>
> > Hey folks,
>
> > I'm working on a PCB that will have an Altera FPGA (Cyclone II in 672
> > ball FBGA). There is no code to be loaded to the FPGA yet so it makes
> > testing the pin assignment hard (impossible?). On the PCB I'm
> > planning to have a 256Mb of DDR SDRAM (16-bit wide DQ bus). I'm
> > concerned that some of my other signals to and from the FPGA may cause
> > problems with the DDRA SDRAM lines. What I was hoping to do was open
> > up Quartus II and assign my pins for given directions, drive
> > strengths, IO standards etc. The run the assignment checking tool to
> > see if any of the signals were brought in on pins that are not
> > acceptable. Does anyone know how to do this kind of testing when
> > there is no RTL code driving the pins (yet)?
>
> > Thanks,
>
> Create a 'dummy' design. Use all of the same signal names and signal
> directions (in/out/inout) that will be on the final FPGA design. Make
> up any sort of dummy logic that uses all of the inputs to drive all of
> the outputs and inouts. Run it through Quartus and make sure that it
> doesn't generate any warnings about inputs that are not used or
> outputs that are driven to a constant. Now you have something that
> you do pin placement on and from that point simply run the I/O
> assignment analysis every now and then as you get pins assigned,
> Quartus will complain if you have any errors.
>
> About the only considerations you'll need to make in creating the
> dummy logic has to do with clocks and PLLs. Make sure that any input
> clocks that will be connected to flip flops at least clock in
> 'something' in your dummy logic. If you'll be using PLLs instantiate
> them and configure them for the estimated design frequency that you
> intend to run it at, and if those PLL outputs will be driving output
> pins (like the DDR clock as an example) make sure the PLL output is
> connected to the appropriate output signal. By doing this, Quartus
> will generate errors or warnings when running the I/O assignment
> analysis if you try to do something that you shouldn't or can't do.
>
> Lastly, since you're using some form of DDR controller, refer to the
> Altera documentation on the preferred pins to use for the controller I/
> O otherwise you may have trouble getting the proper DDR performance
> that you need for your project. Quartus won't generate any warnings
> about this ('specially since the dummy logic won't have any DDR
> controller), you'll have to manually check it.
>
> Kevin Jennings
Kevin,
Thanks for the descriptive reply. This is the route I figured I was
going to get stuck following. I suppose I best get started!
Thanks again,
Steve
Article: 127028On Dec 7, 4:32 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > steve_blah wrote: > > Does anyone know how to do this kind of testing when > > there is no RTL code driving the pins (yet)? > > KJ explained it well. > > But note that rushing to make a circuit board > does not always save any time or money. > > Having some working FPGA code before starting > a layout can eliminate one or two > board spins. > > -- Mike Treseler Mike, I agree wholeheartedly, unfortunately I'm not being given much of a choice. The RAM interface isn't absolutely crucial though, it's a "nice to have". So if I end up not being able to use it it's not the end of the world. Thanks for the reply, steveArticle: 127029
On Dec 7, 10:35 pm, Subroto Datta <sda...@altera.com> wrote: > On Dec 7, 12:22 pm, steve_blah <srpen...@gmail.com> wrote: > > > > > Hey folks, > > > I'm working on a PCB that will have an Altera FPGA (Cyclone II in 672 > > ball FBGA). There is no code to be loaded to the FPGA yet so it makes > > testing the pin assignment hard (impossible?). On the PCB I'm > > planning to have a 256Mb of DDR SDRAM (16-bit wide DQ bus). I'm > > concerned that some of my other signals to and from the FPGA may cause > > problems with the DDRA SDRAM lines. What I was hoping to do was open > > up Quartus II and assign my pins for given directions, drive > > strengths, IO standards etc. The run the assignment checking tool to > > see if any of the signals were brought in on pins that are not > > acceptable. Does anyone know how to do this kind of testing when > > there is no RTL code driving the pins (yet)? > > > Thanks, > > > Steve > > Hi Steve, Please read the Early Pin Planning section in the Pin > Planner section of the handbookhttp://www.altera.com/literature/hb/qts/qts_qii52013.pdf > and the section on Validating Pin Assignments in the same section. > This will answer a lot of your questions. > > Hope this helps, > Subroto Datta > Altera Corp. Subroto, Thanks for the reply. I'd only been looking at the FPGA documentation, clearly I overlooked the Quartus documentation, which was a mistake. This looks to be much more useful than what I was working with. Thanks a lot, it's funny that I get answers from someone on Altera through a forum faster than my service requests. Cheers, SteveArticle: 127030
On Dec 8, 7:41 pm, Alex Freed <al...@mirrow.com> wrote: > Nico Coesel wrote: > > > Why not choose a CPU with build-in LCD controller? > > I have a build-in LCD controller in the PXA255. It just does not have > the performance needed. So I want to preserve most software of the > existing system and add better graphics. > > >For instance, the > > LCD controller in the Blackfin from Analog Devices should -according > > to the maximum pixel clock- be able to do 1280x1024 @ 50Hz. You can > > buy 2 Blackfins for the price of one FPGA and get the design ready > > much faster. > > It's worth looking into, but a quick look-up only showed ucLinux ported. > Does it mean there is no MMU? Yes, the MMU in the Blackfin is really only a simple memory protection unit. That is why it only runs uClinux.Article: 127031
> >> Now, vendors: if your product is really that cost sensitive, get 5k or > >> 10k piece prices from all of the vendors. Include Lattice and others > >> in the mix as well. > > Probably not. I'm well used to X tools, somewhat used to A tools and > unless there is a huge potential win would rather not learn yet another > toolset. Howdy Alex, If you're truly concerned about low cost, why wouldn't it be worth an extra week or so of getting your design through a different tool set (or even several) if it dropped the price a dollar or more per unit? Regards, MarcArticle: 127032
Alex Freed <alexf@mirrow.com> wrote: >Nico Coesel wrote: >> >> Why not choose a CPU with build-in LCD controller? > >I have a build-in LCD controller in the PXA255. It just does not have >the performance needed. So I want to preserve most software of the >existing system and add better graphics. I can imagine. But I think getting the FPGA together will take as much time as migrating the software to a new SoC. If the PXA255 is 'an older device' you may even save money on the SoC itself and get better overall performance. >>For instance, the >> LCD controller in the Blackfin from Analog Devices should -according >> to the maximum pixel clock- be able to do 1280x1024 @ 50Hz. You can >> buy 2 Blackfins for the price of one FPGA and get the design ready >> much faster. >> > >It's worth looking into, but a quick look-up only showed ucLinux ported. >Does it mean there is no MMU? Yes. But from what I've read this doesn't make much difference in the way Linux looks & feels. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 127033
KJ wrote:
>>> The form I chose was deliberately done
>>> to demonstrate a technique to that,
>>> by simple inspection, can be seen to be
>>> functionally equivalent and synthesizable.
>>> The better approach for a double
>>> edged flop that you'd really like to use in an actual design was
>>> demonstrated by Andy and Mike...but as you can see from rickman's
>>> misinterpretation it wasn't obvious to him at first glance, whereas my
>>> approach was obvious but left him uneasy about using the clock in logic
>>> (and rightly so).
All line encodings are a little mysterious.
NRZI, Manchester, HDLC etc.
> I've never run across the situation where an internal interface to the FPGA
> required using both edges. If it did, the interface is the problem, it
> should be widened.
Yes. It's the line encoding trade-off.
I add local logic to save on long distance wires or pins.
HDLC instead of start/stop controls.
RAS, CAS instead of separate buses
PCI express pairs instead of PCI buses.
etc.
> Synthesizable code that performs rising/falling edge sampling of an integer
> Blatently based on (OK copied from) Mike Tresler's posting earlier in this
> thread
Which was quietly pasted from Andy's posting ;)
-- Mike Treseler
Article: 127034On Dec 8, 3:43 am, naliali <nali...@gmail.com> wrote: > Hi all, > I'm trying to implement an analoge capturing project using Xilinx sx55 > fpga and AD9510 as ADC. But I'v difficulty to program AD9510 clock > distribution IC via its serial controller port to set divider > parameters. The problem is that no handshake signal is recieved from > serial port. because the signaling between SCP of AD9510 and V4-sx55 > can not be simulated, I can not debug my code. I'd like to know has > anyone worked with this A/D or other similar ICs? any App-note or > practical code? > > any comment will be appreciated > Thanks I'm not sure if you made a typo or what. When I looked at the ADI web site they say the 9510 is a PLL clock distribution chip, not an ADC. Perhaps you mean you are using the 9510 as the clock chip in an ADC circuit? So you are asking how to program the 9510 via the serial port? The control port appears to be a serial port, much like an SPI port. The default operation in fact, is just like SPI. The only restriction is speed is to keep the clock rate no higher than 25 MHz. There is no handshake signals. This is not like RS-232, it is synchronous. The clock and CSB signals control all of the timing. This is all described very well in the serial control port section of the data sheet, page 42. This is a very complex part, both the control and the details of using it for generating high speed, low skew clocks. You need to study every part of the data sheet and make sure you understand all of the implications before you design it into a project.Article: 127035
Marc Randolph wrote: > > If you're truly concerned about low cost, why wouldn't it be worth an > extra week or so of getting your design through a different tool set > (or even several) if it dropped the price a dollar or more per unit? I would definitely consider learning new tool if I *knew* that would save at least a buck per unit. I'm reluctant to go for a fishing expedition. > > Regards, > > Marc Thanks anyway for the suggestion, Marc. -Alex.Article: 127036
On Sun, 09 Dec 2007 15:37:20 +1100, Allan Herriman <allanherriman@hotmail.com> wrote: >On Sat, 8 Dec 2007 14:15:57 +0100, Frank Buss <fb@frank-buss.de> >wrote: > >>I've read the Wikipedia article about Direct Digital Synthesis ( >>http://en.wikipedia.org/wiki/Direct_digital_synthesis ) and building a DDS >>generator with a FPGA, which interpolates between adjacent entries in the >>lookup table, looks like some fun. This is my first try: >> >>http://it4systems.de/SignalGenerator/doc/index.html >> >>Maybe when I have some more time, I'll add more features, like a SPI >>interface to control it from an external microcontroller and multiple >>outputs. >> >>Any ideas how to improve it? I have read this paper: > >Consider redesigning it to incorporate the following features: > >1. Produce an output every clock. This allows much higher output >update rates, which can greatly improve the quality of the output. >You'll have to throw away your state machine and go to a fully >pipelined datapath approach. > >2. Increase the maximum clock rate. Design it so that the Fmax of >the ram is the only limitation. > >3. The mid-sized rams from both X and A are dual port. This allows >you to do two lookups in the same clock, which is needed for step 1. > >4. As others have pointed out, utilise the symmetry of the sine >function to reduce the size of the lookup table by a factor of 4. >Equivalently, get 4 times the phase resolution in your table for a >given size of ram. > >Regards, >Allan. We've done that: dual-port out of the lookup table, mul+add to interpolate based on lower-order bits of the phase accumulator, do all that and load the dac every clock. We got 128 MHz on a Spartan3, with a 4k x 16 full-cycle lookup table (we need to do arbs, too, and you can't fold arbitrary waveforms) and 16 bit interpolation into, err, a 14 bit dac. It doesn't help harmonic distortion much (that's mostly an analog problem) but it whacks the heck out of close-in spurs. JohnArticle: 127037
John Larkin wrote: > We've done that: dual-port out of the lookup table, mul+add to > interpolate based on lower-order bits of the phase accumulator, do all > that and load the dac every clock. We got 128 MHz on a Spartan3, with > a 4k x 16 full-cycle lookup table (we need to do arbs, too, and you > can't fold arbitrary waveforms) and 16 bit interpolation into, err, a > 14 bit dac. This sounds interesting, but I wonder why do you need to interpolate at all, if you have only a 14 bit dac, because then it should be possible to use 14 bit width words and a dense table, with only 1 LSB difference between two adjacent samples max. The only interpolation needed then is to decide if you need to use the index from the higher order bits of the accumulator, or the next index, if the lower order bits are >0.5. Of course, you'll need a bit more memory, but e.g. a 14k, 14bit memory could fit easily in the smallest Cyclone III, which you can buy for $15. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 127038
Thanks. 1. Yes-I am use FF665 package 2. This clock is LVDS (UG196 (325mV) AC-coupled 3. If I write in UCF " INST "serdes/gtpdual1/gtp_dual" LOC = "GTP_DUAL_X0Y1" ; ", may I do not write in UCF MGTREFCLK pin locations? 4. I find what You say in UG196 (v1.3) May 25, 2007 Now I have nex question: ISE give error in Design Hierarchy Analysis: ERROR:HDLCompilers:87 - "XXX.v" line 33 Could not find module/ primitive 'gtpdualxxx' What files he do not find? I am understand that: I must write directory, where ISE may search this files in Syntesis Option/Verilog Include Directories. But I dont now - what files he whant....Article: 127039
On Dec 6, 11:12 pm, KJ <Kevin.Jenni...@unisys.com> wrote: > On Dec 6, 9:10 am, mrmoos...@gmail.com wrote: > > > > > On Nov 24, 1:04 pm, "HT-Lab" <han...@ht-lab.com> wrote: > > > > "fl" <rxjw...@gmail.com> wrote in message > > > >news:ccb086d1-775c-44cf-8666-bc357a309d93@b15g2000hsa.googlegroups.com... > > > > > Hi, > > > > I want to learn the implementation ofCORDIC. I find the following > > > > website has some code which I would like begin with it. > > > > >http://www.ht-lab.com/freecores/cordic/cordic.html > > > > > But I cannot simply simulate it in my Modelsim PE (student version) > > > > because of the setup problem. Could you, the FPGA and VHDL experts can > > > > tell me how to simulate it? Especially could you tell me how its > > > > structure about the behaviour and synthesis files arranged? > > > > > Thanks in advance. > > > > Send me an email and I will create a standalone Modelsim version for you. I > > > wrote this code some time ago using HDL Designer and Modelsim. > > > > Regards, > > > Hanswww.ht-lab.com > > > We do appreciate, if it be possible to use a standalone Modelsim > > version of project. > > Would U plz upload it or give some clue. > > Sincerely. > > MrM- Hide quoted text - > > > - Show quoted text - > > Try Altera or Xilinx, etc. for the web or student version where they > bundle in a limited version of Modelsim. > > KJ I do not have any of following folders! simprim = D:/vendors/Xilinx/mti/simprim x55 = D:/hdl_designs/x55/work_mti XilinxCoreLib = D:/vendors/Xilinx/mti/xilinxcorelib altera_mf = D:/vendors/quartus/mti/altera_mf mercury = D:/vendors/quartus/mti/mercury Shared_lib = D:/DEMO/demo_hdl_designer/Shared_lib/work_mti ??Article: 127040
austin schrieb: > L. Schreiber, > > The module flow was removed from this app note (no longer supported). > > PlanAhead is available to universities through the XUP (Xilinx > University Program). Ask your professor to request a copy and a license. > > Austin Now it's working and thus the flow, too. It's not necessary to LOC-constraint. For clock signals you should add the global clocking network ressources in toplevel by hand. Otherwise an ibuf could mistakenly be added to the clock net by xst instead and so the routing of clock isn't possible for the reconfigurable module. Greetings, LarsArticle: 127041
On Mon, 10 Dec 2007 08:11:30 +0100, Frank Buss <fb@frank-buss.de> wrote: >John Larkin wrote: > >> We've done that: dual-port out of the lookup table, mul+add to >> interpolate based on lower-order bits of the phase accumulator, do all >> that and load the dac every clock. We got 128 MHz on a Spartan3, with >> a 4k x 16 full-cycle lookup table (we need to do arbs, too, and you >> can't fold arbitrary waveforms) and 16 bit interpolation into, err, a >> 14 bit dac. > >This sounds interesting, but I wonder why do you need to interpolate at >all, if you have only a 14 bit dac, because then it should be possible to >use 14 bit width words and a dense table, with only 1 LSB difference >between two adjacent samples max. The only interpolation needed then is to >decide if you need to use the index from the higher order bits of the >accumulator, or the next index, if the lower order bits are >0.5. Of >course, you'll need a bit more memory, but e.g. a 14k, 14bit memory could >fit easily in the smallest Cyclone III, which you can buy for $15. We have 8 channels, which used up all the block rams in the biggest Spartan. So we could only use 4k points per channel. The interpolation does have a dramatic effect on near-carrier spurs. We have an option to turn it off, for situations where the customer wants to make step edges in an arbitrary waveform... the interpolation turns everything into slopes. JohnArticle: 127042
I was going to try to the first but the second sounds better. Could you explain how to set that up ? I'm a newby here, all I can find in the manuals is to use the serial port and run hyperterminal to read and write. To use your method I'd need to know how to tell the board to send the IO over JTAG and also how to view the data on my PC. Thanks a lot in advance, Andre. On Dec 7, 11:34 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > Two very simple options, use a USB to RS-232 converter or use the built-in > BSCAN primitive and the user register to communicate over JTAG. If you use > the latter, you can have a virtual development board on a computer and all > you need in hardware is a PCB with a FPGA and a JTAG header (i.e. no buttons, > no LEDs, no switches, no slow comm. interfaces). > > ---Matthew Hicks > > > > > Reinstalling the drivers of 9.1 didn't work but the full 9.2 WebPack > > does the trick. > > Once the driver was ok I went back to using 9.1 to be able to keep my > > EDK 9.1. > > Now the downloading works. > > Now I've only to find a way to get my IO without having a serial port > > on my laptop. > > Thanks again, Andre. > > John_H wrote: > > >> On Dec 7, 6:23 am, Andre van der Avoird <an...@becanus.nl> wrote: > > >>> Thanks John, Can I upgrade with an online update from 9.1 or do I > >>> need a > >>> complete new install ? > >>> Problem is my webupdate doesn't work. > >>> Andre > > >>> John_H wrote: > > >>>> Andre van der Avoird wrote: > > >>>>> Hi All, > >>>>> I have a XupV2P board, ISE 9.1 and Windows Vista. > >>>>> I can't find the right driver for my USB cable to download my > >>>>> bitstream. > >>>>> Does anyone know where to find it ? > >>>>> Thanks, Andre. > >>>> ...in the Xilinx ISE installation program. I noticed it in the > >>>> 9.2i > >>>> setup.exe on XP when the items are checked by the user for > >>>> installation > >>>> of the components. In addition to the various CPLD and FGPA > >>>> families, > >>>> there are check-boxes for "standalone programmer" and "cable > >>>> driver." > >>>> That last item is critical. Maybe it's time to upgrade to 9.2i > >>>> since > >>>> you need to reinstall this item anyway. > >>>> - John_H- Hide quoted text - > >>> - Show quoted text - > > >> If you do a fresh install of 9.2i, it'll be everything. If you do a > >> reinstall of 9.1i, you can probably just install the cable drivers > >> through I haven't gone through that exercise myself. The tools are > >> already up to service pack 3 on 9.2i.- Hide quoted text - > > - Show quoted text -Article: 127043
KJ wrote: > "Ray Andraka" <ray@andraka.com> wrote in message > news:6Mg6j.3083$AN1.1540@newsfe16.lga... > >>I remember seeing them in DRAM controllers too. That doesn't make it good >>design though. There were fewer choices then since the DRAM generally ran >>off the processor clock making it difficult and expensive to get a >>multiplied clock (PLLs of the day were much slower than the clock rates >>for DRAM) needed to get clock edges placed at fractional cycle points >>without using delay lines to generate those clocks. The better DRAM >>designs used the delay line to generate a delayed clock rather than >>delaying memory signals. > > > Hmmm....at the start of paragraph you imply that the usage of delay lines in > DRAM controllers is not 'good design' but later on go on to say that the > 'better DRAM designs' used them..... > > KJ > > Basically, I am saying that if delay lines are used at all in a logic design, they should only be used in the clock generation to generate delayed or out of phase clocks that are used by the rest of the logic. With modern FPGAs, that use of delays is not necessary because the ability to phase shift and/or multiply clocks is built into the FPGA's clock manager circuitry. More often than not, when folks are asking about how to synthesize a delay, it is a delay they are trying to add to their logic rather than to a clock circuit. It is that use of a delay line that I was saying is poor form. There were some cheap DRAM designs around that inserted logic as a delay on various signals rather than using a delay line to produce an out of phase clock. If you are going to use a delay, it should be used in the clocking logic to produce a delayed clock that is then used by all the logic rather than inserting delays on signal lines to delay those signals. What I was saying is the better designs among those DRAM designs that used delay lines used them to generate a delayed clock rather than to directly delay signals. With modern clock multiplication circuitry, there is little excuse for delay lines in user designs.Article: 127044
I was wondering if anyone could help me figure out one thing that is holding us up for porting some Verilog code that works for Xilinx/ISE to Lattice/Synplicity. Specifically, for Xilinx, we use metacomments like this to prevent optimization across certain bits of logic: //synthesis attribute keep_hierarchy of mux0 is yes Would anyone happen to know the equivalent metacomment for Lattice/ Synplicity? Thank you very much for your help!Article: 127045
Hi I just tried to initialise the JTAG Scan when I get the following error: Info: impact:501 - 1 Added Device xc95144xl.bsd done ERROR iMPACT 477 - The bsdl for the device 'UNKNOWN' is out of date Please check your installation. Anyone encountered this problem and knows a solution for that? I am using ISE 7.1 in combination with the Multilinx Cable. Is probabaly the cable the problem? On the Xilinx homepage it states that an additional 200 Ohm external Pullup on the Pin is recommended. Any other tips that I could quickly try? Thanks!Article: 127046
On Dec 10, 8:13 am, "theo...@gmail.com" <theo...@gmail.com> wrote: > I was wondering if anyone could help me figure out one thing that is > holding us up for porting some Verilog code that works for Xilinx/ISE > to Lattice/Synplicity. Specifically, for Xilinx, we use metacomments > like this to prevent optimization across certain bits of logic: > > //synthesis attribute keep_hierarchy of mux0 is yes > > Would anyone happen to know the equivalent metacomment for Lattice/ > Synplicity? > > Thank you very much for your help! Use the Synplify help to look up the "syn_hier" directive to figure out the differences between "firm" and "hard" that could affect your outcome.Article: 127047
Just recently an error/bug arises in ISE when i go to synthesise a design. The synthesis will just error without any transcript text. when i cleanup the project files and then run XST it synthesises perfectly. Anyone have the same problem/ found a fix?Article: 127048
mrmoosavi@gmail.com wrote: > I do not have any of following folders! > simprim = D:/vendors/Xilinx/mti/simprim > x55 = D:/hdl_designs/x55/work_mti > XilinxCoreLib = D:/vendors/Xilinx/mti/xilinxcorelib > altera_mf = D:/vendors/quartus/mti/altera_mf > mercury = D:/vendors/quartus/mti/mercury > Shared_lib = D:/DEMO/demo_hdl_designer/Shared_lib/work_mti > ?? !! If you write your own code, you won't need them. See the testbench example here: http://home.comcast.net/~mike_treseler/Article: 127049
On Dec 10, 12:38 pm, mozilla <godzilla...@gmail.com> wrote: > Just recently an error/bug arises in ISE when i go to synthesise a > design. > The synthesis will just error without any transcript text. when i > cleanup the project files and then run XST it synthesises perfectly. > > Anyone have the same problem/ found a fix? I think you just mentioned the fix: cleanup the project. This problem usually occurs if you add/change/delete modules from the hierarchy. I've also heard of this happening more frequently with EDK, but I don't use EDK myself. Are you saying you need to cleanup the project each time you want to rebuild (i.e. no new modules just some editing of existing modules)? I haven't seen that happen. The other workaround I found was to just start a new project and include all of my sources from the broken one. That is a real pain, though. Good Luck, Gabor
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