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Messages from 126725

Article: 126725
Subject: Re: Hand solder that FPGA on your prototype
From: MikeShepherd564@btinternet.com
Date: Fri, 30 Nov 2007 11:54:55 +0000
Links: << >>  << T >>  << A >>
>I only ask first name & email address when joining, and then you can 
>unsubscribe from the email list immediately if you want to - you get to keep 
>the free lifetime membership so that you can watch the videos any time.

>http://SuperSolderingSecrets.com

I'm always suspicious when someone suggests that they have "secrets"
to reveal.

Why do you want these details from those who visit your site?  How
will you store them?  How do we know that they are secure?  Why do you
keep details for a "lifetime" after a user "unsubscribes"?

There are lots of good videos about soldering available without
registration:

http://www.howardelectronics.com/navigate/videoclips.html

Article: 126726
Subject: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 30 Nov 2007 12:10:25 -0000
Links: << >>  << T >>  << A >>
"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote in 
message news:5ra56hF139idpU1@mid.individual.net...
>> inductance.
>
> Symon,
>
> You've posted useful snapshots of board desing before (ie to illustrate 
> the
> usefulness of micro-vias).
>
> Any change of a screen shot of a board you've done using this technique to
> illustrate things better?
>

I'll have to ask my client if it's ok.
>
> We have an interrupted power plane with is _really_ well decoupled at the
> FPGA and DDR so our current thinking is to use routinh on layers 1 3 and 
> 6.
>
So, just to be clear, how are you planning on connecting all your supplies? 
Vccint, Vcco for each bank, Vccaux, to use the Xilinx names. Do you have 
different voltages on some Vcco banks? I usually have 3.3 and 2.5 volt 
banks.
Cheers, Syms. 



Article: 126727
Subject: Re: Global Reset using Global Buffer
From: "RCIngham" <robert.ingham@gmail.com>
Date: Fri, 30 Nov 2007 06:50:24 -0600
Links: << >>  << T >>  << A >>
>
>But I'm still looking for a FPGA that has global generic nets.
>
>
Try looking on the Actel web-site. From memory, the ProASIC family has
them.

(If my memory is wrong, I apologise in advance for the waste of time).



Article: 126728
Subject: Re: Pipelining of FPGA code
From: "RCIngham" <robert.ingham@gmail.com>
Date: Fri, 30 Nov 2007 07:03:40 -0600
Links: << >>  << T >>  << A >>
>Hi,
>
>I am trying to understand what Pipelined designing/architecture for
>FPGA's mean ?
>
<snip />
>
>It would help me if someone could point to some article / book /
>example (and
>preferably a Verilog based one) which explains pipelining  at in
>depth.
>
For a definition oriented towards computing architecture, see
http://foldoc.org/?pipeline

More generally, by putting sets of registers into a combinatorial logic
function, the containing system can be run at a faster clock rate, but
takes more clock cycles. The "art" is in determining when this is
appropriate, and how many stages is optimal. My consultancy rate is
GBPmany/hour.



Article: 126729
Subject: Using DDR RAM on XUP V2Pro board
From: marek.kraft@gmail.com
Date: Fri, 30 Nov 2007 05:11:56 -0800 (PST)
Links: << >>  << T >>  << A >>
Hello,

I'd like to ask if there's a way to get the DDR RAM on the XUP V2Pro
board by Digilent up and running without using the PLB DDR controller?
I know here are a few designs for V2Pro, but I'm not an expert in
uding DRAM-s and haven't planned to become one (although I'm starting
to get an impression that without a significant amount of expertise I
won't be able to deal with the problem). The new MIG by Xilinx does
not support older parts, and the previous versions got me confused by
just looking at them. Anyway, it takes more than a headache to
discourage me from trying to get the memory to work, so I've dug out
the parameters of the DIMM module and the IC's mounted on it (I'm
using the 256MB Kingston module sold by Digilent, I've got it with the
board), checked it a few times, passed it to the editor and stumbled
upon the problem with the pins and banks settings (more dialogs, more
options...). I cannot work on this problem during the weekend, but I
just wanted to make sure if it is possible to create a working
controller for my board with the MIG? Does it require any fine-tuning
after implementation? Did anyone try it (and succeeded)? Are there
maybe other, more user-friendly, or maybe even ready-made, tested
soultions? Any help, guidance, directions are appreciated. I don't
want to spend too much time tackling this problem (although I'm aware
it might not be that easy).

Kind regards.

Article: 126730
Subject: Re: Global Reset using Global Buffer
From: neilla@pipstechnology.co.uk
Date: Fri, 30 Nov 2007 05:45:00 -0800 (PST)
Links: << >>  << T >>  << A >>
On 30 Nov, 12:50, "RCIngham" <robert.ing...@gmail.com> wrote:
> >But I'm still looking for a FPGA that has global generic nets.
>
> Try looking on the Actel web-site. From memory, the ProASIC family has
> them.
>
> (If my memory is wrong, I apologise in advance for the waste of time).

Yes Actel does have this facility, the ProAsic family anyway.  They
also have the ability to split a single global net into lots of little
local global nets, or spines as they call them.  I have previously
used this on the APA devices and found it very useful for things like
enables.  The PA3 and fusion devices give you even more global nets to
play with.

Depending on your design complexity, they are well worth a look at.
My only problem with them is the lack of dedicated multipliers.

Article: 126731
Subject: Re: CPU design uses too many slices
From: Brian Drummond <brian_drummond@btconnect.com>
Date: Fri, 30 Nov 2007 13:58:48 +0000
Links: << >>  << T >>  << A >>
On Thu, 29 Nov 2007 22:33:56 +0100, Jürgen Böhm <jboehm@gmx.net> wrote:

>rickman wrote:

>   Considering the ALU, it seems that it can become quite heavy. The
>utilization figure above are with an ALU that misses some operations
>which I really would have liked to implement, especially a r/lshift(x,y)
>operation which shifts the 32 bit word x by an amount of y[4:0]. As long
>as I kept this in the ALU I nearly had 90% device utilization and, what
>is even worse, only maximal 46Mhz speed for the CPU.

One trick with the barrel shifter is to use the multiplier blocks to
implement it : for a 32*16 shifter, 2 multipliers are enough. 
Simply decode the shift distance to one-of-16.
Unless they are already fully employed elsewhere.

- Brian

Article: 126732
Subject: Re: Pipelining of FPGA code
From: "Symon" <symon_brewer@hotmail.com>
Date: Fri, 30 Nov 2007 14:13:33 -0000
Links: << >>  << T >>  << A >>
http://www.eetimes.com/story/OEG20000807S0037 



Article: 126733
Subject: Re: What tools do you use ? Why ?
From: "psihodelia@googlemail.com" <psihodelia@googlemail.com>
Date: Fri, 30 Nov 2007 06:56:54 -0800 (PST)
Links: << >>  << T >>  << A >>
What I don't fully understand is why so many people use ModelSim ? I
did try it but it is slow and it has many bugs. On the other side, I
see many people use emacs with vhdl-mode. Emacs is one of the best
text editors and I think in the 21st century it would be not too bad
to teach some widely recognized Open Source tools already at the
middle school. Today's complexity of the software is so huge that
almost all Closed Source Solutions are predefined to be buggy,
unproductive, short-living. The same arguments are applicable to the
current situation about synthesis tools. I wonder if current situation
will start slowly change. Commercial interests depend on the
technological progress. Progress will be faster if Open Source will be
more important. For example, many Universities could provide more
intensive research on VHDL behavioral synthesis if synthesis tools
will be Open Source.

Article: 126734
Subject: Re: Asynchronous FIFO and almost empty - bug?
From: Peter Alfke <alfke@sbcglobal.net>
Date: Fri, 30 Nov 2007 07:02:29 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 30, 12:44 am, "heinerl...@googlemail.com"
<heinerl...@googlemail.com> wrote:
> Hi Peter,
>
> we are using Virtex4 FX devices. The FIFO runs at 100 MHz and was
> generated with coregen 3.5. We just found out that there have been
> several modifications regarding the almost empty signal in coregen
> 4.2. We'll try that out first.
>
> Point is we NEED an almost empty signal at threshold == 1 which we can
> rely on 100%. If I understand you correctly this is not given with the
> Xilinx sync FIFOs so we would have to build our own, right?
>
> regards, Heiner
>
> On Nov 29, 5:35 pm, Peter Alfke <al...@sbcglobal.net> wrote:
>
> > On Nov 29, 3:46 am, "heinerl...@googlemail.com"
>
> > <heinerl...@googlemail.com> wrote:
> > > Hi,
>
> > > we are using an asynchronous FIFO to bridge two clock domains. Both
> > > domains have "the same" clock speed but different clock oscillators.
>
> > > We shift data phits in the FIFO which always form a data packet. In
> > > between a packet data is shifted in continously without a break.
> > > Breaks (no shift in) are only allowed in between packets.
> > > On the output side of the FIFO we need a steady data stream during a
> > > data packet. The packet may not be interrupted. As the input side may
> > > be slower we start shift-out data if at least two data phits are in
> > > the FIFO. As the 2 clocks have almost the same frequency this
> > > guarantees that we never have a buffer underflow.
>
> > > The problem we found is that the almost empty flag is only asserted if
> > > the FIFO is beeing emptied and not if it is beeing filled. So if the
> > > FIFO was empty and we get a shift in the almost empty is not asserted
> > > although we set the treshold to one. Is this a bug?
>
> > Which FPGA family, which type of FIFO controller, and also what clock
> > rate?
> > Peter Alfke, Xilinx Applications>
>
> > > We tried to solve that problem by generating a delay-empty signal at
> > > the output which guarantees that if the FIFO was emtpy and than
> > > receives a shift in we still wait another cycle so we get another
> > > shift in to avoid underflow.
>
> > > This solution however does not solve the problem if the FIFO exactly
> > > had one entry when starting to shift out a packet. In this case
> > > neither delayed-empty nor almost empty is asserted, hence we get an
> > > underflow.
>
> > > Why isn't the almost empty signal asserted every time there is a
> > > single packet in the FIFO? Ideas?


Article: 126735
Subject: Re: Fedora 8 and ISE 9.2
From: Thomas Feller <tmueller@rbg.informatik.tu-darmstadt.de>
Date: Fri, 30 Nov 2007 16:05:30 +0100
Links: << >>  << T >>  << A >>
Michael Laajanen wrote:
> Hi,
> 
> I am trying to install ISE 9.2 on a Fedora 8 machine, but have numerous
> problems.
> 
> Is there anyone that managed to do this?
> 
> /michael

Hi Michael,

perhaps it would help if you supply some error messages. Maybe someone
has had the same problems with another distro.

regards
	Thomas

Article: 126736
Subject: Re: Asynchronous FIFO and almost empty - bug?
From: Peter Alfke <alfke@sbcglobal.net>
Date: Fri, 30 Nov 2007 07:05:42 -0800 (PST)
Links: << >>  << T >>  << A >>
As I wrote, the problem is easy to solve for the synchronous case
(identical clocks) but difficult or impossible to solve for the
asynchronous case.
You wrote synchronous ???
Peter Alfke

On Nov 30, 12:44 am, "heinerl...@googlemail.com"
<heinerl...@googlemail.com> wrote:
> Hi Peter,
>
> we are using Virtex4 FX devices. The FIFO runs at 100 MHz and was
> generated with coregen 3.5. We just found out that there have been
> several modifications regarding the almost empty signal in coregen
> 4.2. We'll try that out first.
>
> Point is we NEED an almost empty signal at threshold == 1 which we can
> rely on 100%. If I understand you correctly this is not given with the
> Xilinx sync FIFOs so we would have to build our own, right?
>
> regards, Heiner
>
> On Nov 29, 5:35 pm, Peter Alfke <al...@sbcglobal.net> wrote:
>
> > On Nov 29, 3:46 am, "heinerl...@googlemail.com"
>
> > <heinerl...@googlemail.com> wrote:
> > > Hi,
>
> > > we are using an asynchronous FIFO to bridge two clock domains. Both
> > > domains have "the same" clock speed but different clock oscillators.
>
> > > We shift data phits in the FIFO which always form a data packet. In
> > > between a packet data is shifted in continously without a break.
> > > Breaks (no shift in) are only allowed in between packets.
> > > On the output side of the FIFO we need a steady data stream during a
> > > data packet. The packet may not be interrupted. As the input side may
> > > be slower we start shift-out data if at least two data phits are in
> > > the FIFO. As the 2 clocks have almost the same frequency this
> > > guarantees that we never have a buffer underflow.
>
> > > The problem we found is that the almost empty flag is only asserted if
> > > the FIFO is beeing emptied and not if it is beeing filled. So if the
> > > FIFO was empty and we get a shift in the almost empty is not asserted
> > > although we set the treshold to one. Is this a bug?
>
> > Which FPGA family, which type of FIFO controller, and also what clock
> > rate?
> > Peter Alfke, Xilinx Applications>
>
> > > We tried to solve that problem by generating a delay-empty signal at
> > > the output which guarantees that if the FIFO was emtpy and than
> > > receives a shift in we still wait another cycle so we get another
> > > shift in to avoid underflow.
>
> > > This solution however does not solve the problem if the FIFO exactly
> > > had one entry when starting to shift out a packet. In this case
> > > neither delayed-empty nor almost empty is asserted, hence we get an
> > > underflow.
>
> > > Why isn't the almost empty signal asserted every time there is a
> > > single packet in the FIFO? Ideas?


Article: 126737
Subject: Re: Drawing timing-diagrams for documentation
From: Chris Maryan <kmaryan@gmail.com>
Date: Fri, 30 Nov 2007 07:11:01 -0800 (PST)
Links: << >>  << T >>  << A >>
I thought this was rather cool, a timing diagram font:
http://www.pcserviceselectronics.co.uk/fonts/
I've played around with it and it seems pretty good for most needs.

Chris

Article: 126738
Subject: Re: What's the difference for VHDL code between simulation and
From: rickman <gnuarm@gmail.com>
Date: Fri, 30 Nov 2007 07:40:25 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 27, 3:43 pm, fl <rxjw...@gmail.com> wrote:
> Hi,
> The following is from Xilinx "Synthesis and Simulation Design Guide".
> Could you give me an example to show their differences? And explain a
> little to me? Thank you very much.
>
> You may need to modify your code to successfully synthesize your
> design because certain
> design constructs that are effective for simulation may not be as
> effective for synthesis. The synthesis syntax and code set may differ
> slightly from the simulator syntax and code set.

I think one thing that others have not pointed out is the fact that an
HDL is just that... a Hardware Description Language.  You can use an
HDL to write programs and they will run in a simulator.  This is often
done in developing a test bench to drive signals to your device and to
monitor the outputs in simulation.  But if you want to write code that
can be synthesized by the compiler, you have to be describing
hardware.

"Describing hardware" means you can only use constructs that the
compiler understands.  See the difference?  Simulation operates on the
full language.  Synthesis only works with a subset that actually
describes hardware.

The examples are far too numerous to list, but here is one.  If you
want to use a register, you show it as a process which is scheduled to
run when the clock transitions or the async reset transitions.

  Example1: process (SysClk, Reset) begin
    if (Reset = '1') then
	  DataOutReg <= (others => '0');
    elsif (rising_edge(SysClk)) then
	  if (SCFG_CMD = '1') THEN
	    DataOutReg <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
RTS;
	  end if;
	end if;
  end process Example1;

This code "describes" an 8 bit register with SysClk as the clock, and
async reset - Reset and SCFG_CMD as an enable.

To make this unsynthesizable in a way that is sometimes attempted by
newbies...

  Example2: process (SysClk, Reset) begin
    if (Reset = '1') then
	  DataOutReg <= (others => '0');
    elsif (rising_edge(SysClk) or falling_edge(SysClk)) then
	  if (SCFG_CMD = '1') THEN
	    DataOutReg <= TT & SD & PCMT0 & PCMT1 & WP_SDO0 & WP_SDO1 & DTR &
RTS;
	  end if;
	end if;
  end process Example2;

You can imagine a register that clocks on both the rising and falling
edge, but you can't build it in an FPGA.  It may be useful in
simulation as part of a testbench.  For example, you might want to
generated data on both edges of the clock as data returning from a DDR
memory.

Every synthesis tool I have ever used will give you many examples of
valid hardware description code for you to examine.  I am not so
familiar with the Altera tools, but I know the Xilinx tools have
provided good examples.  Just download one of these free packages and
take it for a test ride.  The last time I used the Altera package, the
built in editor was so good, I often forgot whether I was using the
built in editor or my favorite editor. So you shouldn't have too much
trouble learning to use the IDE.

Try the tools and if you have problems, come back and ask about the
problems.

Article: 126739
Subject: ise timing analysis + different clock domains
From: "u_stadler@yahoo.de" <u_stadler@yahoo.de>
Date: Fri, 30 Nov 2007 07:53:52 -0800 (PST)
Links: << >>  << T >>  << A >>
hi

since i'm pretty new ise i have a couple questions regarding timing:

currently i'm working on a design for an spi interface. so far
everything is ok but now i need to work with 2 clock domains. from the
microkontroller side i have an 100MHz clock and the spi side should
run at 12 MHz   (i should work with the ppc by the way so it's going
to be integrated with edk).

when i was working with only one clock (the 100MHz one) my design
synthesized at about 450 MHz.
now when i connect the parts of my design that work with the different
clock rates it suddenly drops to 80 MHz. The design is not that big
(about 90 slices) so routing and placing should not be a problem. I
assume this has something to do with the two clock domains.
I wonder if ther is a state of the art way how to design with two
clock domains. (right now i'm using registers. is there anything
better or smarter? perhaps some examples ?)

another question is how does ise come up with those numbers? in
synthesis there is no timing information or am i wrong?

and last is there any paper or maual on how to use the timing analyzer
from ise?
the other thing is the i need to place anrd route the design befor i
can use that? so how can i find out the critical path from synthesis?

thanks
urban

Article: 126740
Subject: Re: What tools do you use ? Why ?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 30 Nov 2007 08:12:46 -0800
Links: << >>  << T >>  << A >>
psihodelia@googlemail.com wrote:
> What I don't fully understand is why so many people use ModelSim ? I
> did try it but it is slow and it has many bugs. On the other side, I
> see many people use emacs with vhdl-mode. Emacs is one of the best
> text editors

Emacs vhdl-mode is the best editor available for vhdl design entry.
Modelsim SE is the best simulator available for vhdl debug.
One is open source, the other isn't.
Each has its annoyances and delightful surprises.

         -- Mike Treseler

Article: 126741
Subject: Re: What tools do you use ? Why ?
From: emeb <ebrombaugh@gmail.com>
Date: Fri, 30 Nov 2007 08:24:03 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 30, 7:56 am, "psihode...@googlemail.com"
<psihode...@googlemail.com> wrote:
> What I don't fully understand is why so many people use ModelSim ? I
> did try it but it is slow and it has many bugs. On the other side, I
> see many people use emacs with vhdl-mode. Emacs is one of the best
> text editors and I think in the 21st century it would be not too bad
> to teach some widely recognized Open Source tools already at the
> middle school. Today's complexity of the software is so huge that
> almost all Closed Source Solutions are predefined to be buggy,
> unproductive, short-living. The same arguments are applicable to the
> current situation about synthesis tools. I wonder if current situation
> will start slowly change. Commercial interests depend on the
> technological progress. Progress will be faster if Open Source will be
> more important. For example, many Universities could provide more
> intensive research on VHDL behavioral synthesis if synthesis tools
> will be Open Source.

Looks like MikeShepard...@btinternet.com called this one. :)

That said, since I use Verilog, GHDL isn't an option for me. I use
Nedit (when it's working on Fedora) or Scite for text, Modelsim, Cver
or Icarus for simulation and XST for synthesis.

I don't know what problems you've had with Modelsim, but it's worked
well for me. It's faster than Cver and more reliable than Icarus on my
designs (YMMV). I do appreciate the open-source/free simulators though
and try to keep current with them.

The advantages of GHDL you cite sound useful. Reading up on that tool
suggests it supports an older rev of the VHDL standard though. If
that's true, have you found it to be an issue?

EB

Article: 126742
Subject: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Fri, 30 Nov 2007 08:29:59 -0800
Links: << >>  << T >>  << A >>
On Fri, 30 Nov 2007 08:47:40 -0000, "Symon" <symon_brewer@hotmail.com>
wrote:

>"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message 
>news:061vk3hncpn2man9udarrgt80b2lasfl97@4ax.com...
>>
>> I sometimes add a few SMA connector footprints to pc boards, so I can
>> TDR the power planes relative to the ground plane. It's amazing. A
>> typical power plane, on an unloaded board, looks like a perfect
>> capacitor to 20 GHz, with no evidence of reflections or edge effects.
>> Then if you start adding bypass caps *anywhere*, it just looks like a
>> bigger perfect capacitor.
>>
>Hi John,
>As we've discussed before, I think that would be a really useful experiment 
>if this thread was about microwave engineering (say). Sadly, we're talking 
>about FPGA PDSs. FPGAs don't have SMA connections to hook up their power 
>supplies to a board's planes, so, altough interesting, I think the TDR 
>experiment results aren't applicable in this case. It doesn't matter how 
>amazing the capacitance quality is, you can't wire it to the silicon.
>I still say, ditch the power planes, put the bypass caps (maybe X2Y types) 
>on power puddles near the device, that'll work great. This save planes, 
>which you can use as ground planes. This topology allows the designer to 
>filter the supplies near the FPGA to isolate it. If you believe that your 
>high speed signals work better with a return path, and I know some folk on 
>CAF apparently don't, then when these signals swap reference from one ground 
>plane to another you can just use a ground via for the return path as 
>opposed to the situation where a signal switches from ground referred to 
>power plane referred, which costs a bypass cap and two vias and has much 
>more inductance.
>One thing from John's post I do find intriguing is his mate who doesn't use 
>any bypass caps. I can quite believe that his stuff works just fine. I still 
>think it's easier to get PDS right than wrong. Most designs will 'work'. 
>That's why this subject is perfect for a usenet religious war!
>HTH, Syms.
>
>p.s. From experience, I know John likes to read links I post so he can offer 
>his reasoned critique. I saw the comment about 'bypass caps *anywhere*' in 
>his post, and so I eagerly await John's response to this.
>http://www.x2y.com/bypass/method/does_position_matter.pdf
>:-)
>

His footprints make no sense to me. Why three pads and six vias for
one bypass cap? Is an X2Y cap something nonstandard?

Yes, most bypass schemes work, which is why so many people have such
different opinions. 

John


Article: 126743
Subject: Re: Gnd plane coupling with DDR routing from FPGA <-> DDR?
From: John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com>
Date: Fri, 30 Nov 2007 08:44:04 -0800
Links: << >>  << T >>  << A >>
On Fri, 30 Nov 2007 09:50:09 -0000, "Nial Stewart"
<nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> wrote:

>> I know one guy who doesn't use bypass caps at all, and his stuff works
>> too.
>
>
>For FPGA designs with multiple syncronous fast IOs?
>
>
>
>
>Nial 
>

Don't know what he's doing lately. Last time I visited him, he was
doing big boards with a lot of msi and ecl logic.

Most FPGA designs use "high frequency" power, in that there's not much
low frequency component to the supply currents. Contrast this to a CPU
that may go from low power to 100 watts in nanoseconds.

Close power:ground planes are great at furnishing current into
high-frequency loads. Bypass caps furnish the brute charge storage
that keeps the rails stiff at lower frequencies, if there are any.

Our fpga-type boards use a single ground plane (even for mixed
analog/digital stuff) and typically two split power planes. We usually
use four bypass caps per voltage per fpga, 0.33 uF 0603 typically. We
don't distinguish "reference planes", but assume any plane or pour is
at AC ground. We don't worry about logic signal traces crossing pour
boundaries or changing "reference" planes. We may worry about very
low-level analog signals riding over a power pour that could be
noisy... we're talking microvolts here.

Certainly more complex stuff - multiple ground planes, zillions of
mixed-value bypass caps, extra vias to "supply return currents" will
work too.

John


Article: 126744
Subject: Re: Hand solder that FPGA on your prototype
From: nico@puntnl.niks (Nico Coesel)
Date: Fri, 30 Nov 2007 17:20:06 GMT
Links: << >>  << T >>  << A >>
"Tony Burch" <tony@burched.com.au> wrote:

>Hi all,
>
>I've just finished constructing a new site that has web videos of soldering 
>techniques, including how to hand solder quad flat packs. Very handy for 
>prototyping.
>
>You can go and get a free membership there, which lets you see 5 videos on 
>how to hand solder quad flat packs. Watch me hand solder a Spartan 2E in a 
>PQ208 package onto a board:) http://supersolderingsecrets.com/

WOW! I'm really impressed (NOT!). But tell me how much you make money
selling the e-mail addresses to spammers.

-- 
Reply to nico@nctdevpuntnl (punt=.)
Bedrijven en winkels vindt U op www.adresboekje.nl

From removethisthenleavejea@replacewithcompanyname.co.uk Fri Nov 30 09:24:07 2007
Path: newsdbm04.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin1!goblin.stu.neva.ru!news.albasani.net!feeder.erje.net!feeder.news.heanet.ie!newsfeed.esat.net!news.clara.net!mephistopheles.news.clara.net!proxy00.news.clara.net
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Newsgroups: comp.arch.fpga
Subject: Christmas and New Year at Enterpoint
Date: Fri, 30 Nov 2007 17:24:07 -0000
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Xref: prodigy.net comp.arch.fpga:138816

Guys and Girls

We are going to have an extended Christmas and New Year shutdown at 
Enterpoint this year. Last date for us to ship a board is 21st December 2007 
and restarting 7th January 2008. Technical support with be by email only 
during this period and response times may be a lot longer that usual.

I'll take this opportunity to thank all customers that bought products this 
year and gave us a record year. As a bit of a celebration I have authorised 
our sales team to have some festive offers and these will be on a newsletter 
shortly for those that are interested. For non-professionals of you after a 
Drigmorn1 I am hoping these will ship before Christmas allowing some play 
time over the holidays.

John Adair
Enterpoint Ltd. 



Article: 126745
Subject: Re: Cascaded DCMs with variable phase shift (Xilinx)
From: austin <austin@xilinx.com>
Date: Fri, 30 Nov 2007 10:48:16 -0800
Links: << >>  << T >>  << A >>
OK,

Here is an answer from the experts:

"Hi Austin,

We took a quick look at this don't see any major issues. It looks as if
he is using the inverted lock signal from the first DCM to reset the
second DCM. No problems here.

Not sure why is CLKFB for first DCM is fed through an IOB. External
feedback? Can add noise perhaps?

I don't think he is using the variable PS correctly though. See this link.

http://www.xilinx.com/support/answers/13824.htm

For every PSEN pulse, I believe the user must wait for PSDONE high
before asserting PSEN again. In this case, it seems like he is just
holding PSEN high for a number of PSCLK cycles, expecting to see an
increment for each PSCLK cycle that the signal was held high for. This
may explain why he is seeing failures.

Let me know if you think this is the case."

Austin

Article: 126746
Subject: Re: CPU design uses too many slices
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 30 Nov 2007 11:19:31 -0800
Links: << >>  << T >>  << A >>
Just make sure that you force the Enable and the Write Enable inputs of 
the unused port Low. Nothing else.

BTW: Use the 18 x 18 multipliers to implement barrel shifters. It saves 
many LUTs and is faster.
(Multiplying by a power of 2 generates a shift by the appropriate number 
of positions.
The multiplexing is done inside the multiplier "at no cost".)
Peter Alfke, Xilinx Applications.

rickman wrote:
> On Nov 29, 7:30 pm, Jürgen Böhm <jbo...@gmx.net> wrote:
>> rickman wrote:
>>> On Nov 29, 4:47 pm, Jürgen Böhm <jbo...@gmx.net> wrote:
>>>> Eric Smith wrote:
>>>>> Jürgen Böhm wrote:
>>>> 1. I noticed that using a dual port RAMB instead of a single port
>>>> increases (slightly) the number of used slices, even if only one port
>>>> the RAMB was used. I do not know the reason for this, maybe it is
>>>> because some external dual-port logic has to generated and added.
>>>> 2. More importantly the access delay seems to be shorter for a single
>>>> port BRAM - I could lift my design from 46Mhz above the 50Mhz barrier
>>>> only by replacing dual port with single port BRAM.
>>> This sounds odd to me, but obviously your dual port design is
>>> different from the single port design in other ways than just the
>>> ram.  You need two address busses and control signal sets, not to
>>> mention the two data paths.  How did you connect the dual port ram
>>> that was different from the single port ram?  I am pretty sure the
>>> block ram itself fully implements the dual port memory and does not
>>> require any slices to be used.
>> Actually I just used "dummy signals" at the unused port B ADDR, DI,
>> DO,.. signals. That is, first I wrote (because of laziness, I did only
>> copy&paste) something like
>>
>> RAMB16_S36_S36  micro_store ( ... ,.DOB(dummydob), ... );
>>
>> and used only the port A. (dummydob is a signal left undeclared).
>>
>> Secondly I wrote explicitly
>>
>> RAMB16_S36 micro_store (..)
>>
>> and got the results with faster timing and less slices used.
> 
> I don't know the impact of dummydob.  I would expect it to use LUTs to
> source a fixed value signals since you are instantiating a fixed ram
> block, but I don't really know what the tools would do with that.  If
> it doesn't provide signal drivers it would have to minimize the dual
> port rams to single port rams since that is all that is being used.  I
> don't think the ram blocks can ignore inputs, but again, I don't know
> for sure.  One of the Xilinx guys could tell you for sure.

Article: 126747
Subject: Re: Asynchronous FIFO and almost empty - bug?
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 30 Nov 2007 11:31:07 -0800 (PST)
Links: << >>  << T >>  << A >>
On Nov 30, 12:44 am, "heinerl...@googlemail.com"
<heinerl...@googlemail.com> wrote:
> Hi Peter,
>
> we are using Virtex4 FX devices. The FIFO runs at 100 MHz and was
> generated with coregen 3.5. We just found out that there have been
> several modifications regarding the almost empty signal in coregen
> 4.2. We'll try that out first.
>
> Point is we NEED an almost empty signal at threshold == 1 which we can
> rely on 100%. If I understand you correctly this is not given with the
> Xilinx sync FIFOs so we would have to build our own, right?
>
> regards, Heiner
>
> On Nov 29, 5:35 pm, Peter Alfke <al...@sbcglobal.net> wrote:
>
> > On Nov 29, 3:46 am, "heinerl...@googlemail.com"
>
> > <heinerl...@googlemail.com> wrote:
> > > Hi,
>
> > > we are using an asynchronous FIFO to bridge two clock domains. Both
> > > domains have "the same" clock speed but different clock oscillators.
>
> > > We shift data phits in the FIFO which always form a data packet. In
> > > between a packet data is shifted in continously without a break.
> > > Breaks (no shift in) are only allowed in between packets.
> > > On the output side of the FIFO we need a steady data stream during a
> > > data packet. The packet may not be interrupted. As the input side may
> > > be slower we start shift-out data if at least two data phits are in
> > > the FIFO. As the 2 clocks have almost the same frequency this
> > > guarantees that we never have a buffer underflow.
>
> > > The problem we found is that the almost empty flag is only asserted if
> > > the FIFO is beeing emptied and not if it is beeing filled. So if the
> > > FIFO was empty and we get a shift in the almost empty is not asserted
> > > although we set the treshold to one. Is this a bug?
>
> > Which FPGA family, which type of FIFO controller, and also what clock
> > rate?
> > Peter Alfke, Xilinx Applications>
Heiner, if you have questions about asynchronous FIFOs, just send me
an e-mail.
English oder Deutsch. But I'll be on vacation starting next Tuesday.
Peter Alfke (peter@xilinx.com)

> > > We tried to solve that problem by generating a delay-empty signal at
> > > the output which guarantees that if the FIFO was emtpy and than
> > > receives a shift in we still wait another cycle so we get another
> > > shift in to avoid underflow.
>
> > > This solution however does not solve the problem if the FIFO exactly
> > > had one entry when starting to shift out a packet. In this case
> > > neither delayed-empty nor almost empty is asserted, hence we get an
> > > underflow.
>
> > > Why isn't the almost empty signal asserted every time there is a
> > > single packet in the FIFO? Ideas?


Article: 126748
Subject: Re: ise timing analysis + different clock domains
From: Mike Treseler <mike_treseler@comcast.net>
Date: Fri, 30 Nov 2007 11:32:00 -0800
Links: << >>  << T >>  << A >>
u_stadler@yahoo.de wrote:

> I wonder if ther is a state of the art way how to design with two
> clock domains. (right now i'm using registers. is there anything
> better or smarter? perhaps some examples ?)

Easiest way to do everything on the fast clock
and synchronize the slow clock as an input.

If that is not possible, then do separate modules
for each clock with explicit synchronization.

google a  bit
http://groups.google.com/groups/search?q=%22toggle+flip-flop+used+in+clock+domain+crossings%22


      -- Mike Treseler


Article: 126749
Subject: Re: CPU design uses too many slices
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Fri, 30 Nov 2007 13:22:54 -0800
Links: << >>  << T >>  << A >>
rickman wrote:
(snip)

> Yes, an n stage barrel shifter is a very logic intensive function.  It
> can easily be larger than all of the other ALU functions combined.  If
> you consider what is required, you in essence need to build a mux with
> an input for each possible shift on every bit.  If you are shifting in
> zeros instead of rotating the other bits back on the other end, you
> can cut your mux roughly in half.  But it is still huge.  If you want
> to be able to shift both left and right it is doubled again and if you
> want to shift right either arithmetic or logical it is larger yet and
> if you want to rotate as well it is even larger.

The more usual barrel shifter would be log2(n) 2 input muxes,
which is still a lot of CLBs, or maybe log4(n) 4 input muxes.

It is barrel shifters that make floating point addition and subtraction
so expensive in FPGAs.  You need one for prenormalization (shift to
align the radix point), and one for postnormalization (remove leading
zeros in the result and adjust the exponent).

-- glen




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