Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Dec 13, 2:55 pm, PatC <p...@patocarr.com> wrote: > Ed McGettigan wrote: > > sachin wrote: > >> HI everyone, > > >> I have purchased ML505 virtex5 based kit for PCIe testing. It has one > >> pre-loaded compact flash with some in-built testing environment. My > >> uses is PCIe testing which this compact flash doesn't have the testing > >> utility nor Xilinx having any utility for the same. I have contacted > >> Xilinx but didn't get any proper answer. > >> As per user guide it requires external CF reader for copying .ace file > >> to compact flash after executing using core gen for PCIe. Does any > >> body know how to read/write compact flash on-board(ML505), any utility > >> to copy any file to compact flash, anybody having?? I don't have CF > >> reader. I want to copy generated .ace file to CF using on-board ML505. > >> Your early reply is highly appreciated. > > > Sorry, but what you are asking for (to write to the CF Card while it is > > plugged into the ML505 board through PCI Express) is not a standard design. > > It is possible to access the CF Card from the FPGA and there is an EDK > > design using MicroBlaze and SystemACE peripheral that is available in > > the online ML505 reference designs > >http://www.xilinx.com/products/boards/ml505/reference_designs.htm > > > You will save yourself a lot of time and effort by going down to your > > local electronics store and picking up a CompactFlash Card Reader/Writer. > > This should be with the $5-10 range. > > > Also, there is a PCIe reference design available for the ML505 here: > >http://www.xilinx.com/products/boards/ml505/pcie.htm > > The bitfiles are included with the board and the documentation on the > > above page provides the instructions for setting the configuration > > control switches to get the example design loaded. > > > Ed McGettigan > > -- > > Xilinx Inc. > > I'd add that this bitfile can be loaded through JTAG, bypassing the CF > card method altogether. In the JTAG chain you should see 5 components > IIRC, being one of the the Virtex5. After programming the completer > example application onto it and rebooting, the host PC now sees a > virtual memory on the PCIe bus, which can be accessed by ie. Pcitree > software. > I took this example application as a starting point and modified it to > change it into a requester app. One bit of advice, use the PCIe core > Plus instead of the hard core. It's much easier to interface with, from > an end-user point of view. Unless you need multiple virtual channels and > extreme flexibility, core Plus is the way to go. > > HTH, > -P@- Hide quoted text - > > - Show quoted text - All advise above is good. On our project we have been talking to the ML506 (same board with sx50t) using linux. Linux is nice for bringing up pci and pcie cards because utilities like lspci and scanpci are built into the OS. Also drivers are easy to write that make the pci(e) hardware accessible to C programming.Article: 127201
Paul wrote: > >> Typically, I already have some sort of interface that goes to a >> computer, allowing me to capture data to a file. I commonly include some >> debugging circuitry within my designs that allow me to steer >> intermediate data to the output, so that I can verify the operation of >> different stages in the data path. > > That sounds interesting, maybe also useful for me. Are there some > webresources that tells me the basics whats the best way to achieve this? > For this part, I really don't know of web resources. The way I do it is very much implementation dependent. I have done boards for VME, PMC and PCI busses, so I simply use that interface to get data into the computer. The thing I am currently working on has a RocketIO link, and I have another board with a RocketIO link plugged into a computer, so that is where I steer data to. That was why I was wondering what interfaces the board currently has.Article: 127202
I'm running Xindows XP & in Calif. I've tried calling Digilent as well as email. Also searched throught their site looking for any info. John: Thank you very much for a most generous offer. I have already ordered another Spartan3E kit from Avnet( same board but Avnet includes hopefully matching SW). I'm sure it'll work eventually. Thanks again. "John_H" <newsgroup@johnhandwork.com> wrote in message news:683314d1-064a-4c8d-ad02-4d2883809119@a35g2000prf.googlegroups.com... > On Dec 13, 12:37 pm, "ereader" <r...@myhouse.com> wrote: >> I would do that but my Virtex 4 board doesn't support USB downloading. >> The USB cable that came with my new digilent board doesn't work at all. >> I have 3 digilent parallel III cables that are suppose to work at 1.5, >> 1.8 & >> 2.5v. >> Either these things are not tested before shipping or the design is just >> flat >> out wrong. Digilent seems to be like those chinese companies that have no >> idea as to what they are selling & can't provide anyone to answer the >> most >> basic question. > > Are you on Windows XP? Vista? Ubunto Linux? > Are you in the US such that I could send/lend you my Digilent > Spartan3E (rev D) board for comparison? I can connect by USB cable > without issue. But I'm not messing with Linux issues, I'm just on > Windows XP. > > I'm up in the Portland, OR area and would like to see you having a > better experience with the Pullman, Washington company that shares > this corner of the US. Your experience should be much better than you > appear to be having. Digilent is a small company and doesn't have a > support staff large enough to outsource. If email gets you nowhere, > perhaps a phone call could. I hooked up an overseas purchaser with > the right folks just by placing a phone call to get the right email to > the right place. > > If you'd like to pass along shipping info to take me up on the offer > to lend you my board or start up a side conversation, feel free to > email me directly. > > - John_HArticle: 127203
I have been thinking about doing 1 or 2 expansion boards for the Spartan 3E starter board to add Gb ethernet & camera capability. Has anyone done this already & is willing to sell a copy ? Save me some work.Article: 127204
Göran Bilski wrote: > There is no extra magic inside the FPGA, just the usual magic. I'll have to remember that one! :-)Article: 127205
Kevin Neilson wrote: > > I don't know if I'd call it an exact computation because > the second lookup table it still yields an approximation. > Not sure I follow you about there being an approximation? If you mean phase truncation of the fine table index, partitioning the phase accumulator 3-12-12 would give 27 bits of untruncated phase with 4K deep tables; or, 2-10-10 gives 22 bits of phase and 1K deep tables. By 'exact', I mean that implementing the coarse*fine vector rotation with a complex multiply computes the correct value of sin/cos limited only by the numerical precision of the table values and complex multiplier; the calculation could be performed in 16 bit, 32 bit, or floating point without needing to change the basic algorithm ( vs. adding more terms onto a series expansion. ) ------------------------------ Anyhow, if Frank can afford multiple cycles per output sample, the most compact implementation would probably be a word-serial CORDIC rotation, which doesn't need any multipliers at all, just three accumulators, shift muxes, and a small arctan lookup table. I thought that had been mentioned earlier, but I don't see it in re-reading the thread tonight. BrianArticle: 127206
On 2007-11-27, Andreas Hofmann <ahnews@gmx.net> wrote: > naresh schrieb: >> I am using Xilinx dual processor reference design suite to develop >> dual processor (xapp996) system on virtex-2 pro. >> I want to port an operating system on to this design >> Is it possible to port an OS that uses this dual-core system. > > That depends on your operating system. The PPC405 has no support for > cache coherency so a system with physically shared memory can't use the > caches out of the box. If you're only using the on-chip BRAMs this won't > make much a difference. If you have to use external memory it will kill > your performance. > > Maybe there is a way to implement a mixed hardware/software support for > cache coherency. Building a module to snoop the memory buses of the > PPC405s shouldn't be much of a problem but you have to be sure that you > see all memory transactions. Bad luck if the cache is write-back. > > So all in all throwing Linux with a SMP kernel on it won't work. Something I have been thinking about is modifying the Linux kernel so that one of the processors act as a master processor with full access to the entire system and also the possibility to allocate the second processor as a slave processor. If the slave processor wants to make a system call, all the caches have to be flushed, so this should obviously not be done lightly, but it might be a perfect setup where one of the processors is used for general OS management, UI, etc and one of the processors is used for real-time tasks, etc, while still retaining the impression of a relatively friendly programming environment for the slave processor. There would also have to be some additional restrictions on the second processor. mmap() could present a problem for example. /AndreasArticle: 127207
Peter, That worked! I copied some code to the ISOCM and called the function and it works fine, so it was copying to the BRAM all along. I did not realize the ISOCM was protected from memory reads. Thanks a million; it would have taken me forever to figure that one out. I wonder if I could bother you to could clarify a couple of other points: In AR# 19804 at http://www.xilinx.com/support/answers/19804.htm, the solution does not seem to jive with my understanding of the problem. The problem description seems to be saying that placing getchar() in ISOCM would be a problem, but the solution seems to be saying calling getchar() from a function that is itself in ISOCM should be avoided. But if getchar() itself is left in regular memory, why should calling it be an issue? AR# 19099, at http://www.xilinx.com/support/answers/19099.htm, seems to imply using OCM in any code where an exception could occur could be very dangerous. It looks like the only workaround is to write everything in assembler. Is that an accurate statement? Thanks, Dave Peter Ryser wrote: > Hi David, > > you can't read the ISOCM in Virtex-II Pro. You can only write it and > execute from it. > > - Peter > >Article: 127208
Brian Davis wrote: > Anyhow, if Frank can afford multiple cycles per output sample, > the most compact implementation would probably be a word-serial > CORDIC rotation, which doesn't need any multipliers at all, just > three accumulators, shift muxes, and a small arctan lookup table. > > I thought that had been mentioned earlier, but I don't see it > in re-reading the thread tonight. There was another thread last month in this newsgroup, with this link: http://www.ht-lab.com/freecores/cordic/cordic.html Maybe I'll use this for the low frequency (<200kHz) generator and a lookup table for high frequency and arbitrary waveforms. The "Direct Digital Frequency Synthesizers" book is shipped, I'm sure there are some other interesting ideas and implementation hints in the book. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 127209
This is a multi-part message in MIME format. ------=_NextPart_000_0041_01C83E32.04930510 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi, From your email I found this. It looks everything has been trimmed away since you are using 0% slices = and 0 pads. If you look at the system_map.mrp file, there is a section on what has = been trimmed away. That could give you a hint what is causing this. You might also add the = option "-detail" to the map tool. G=F6ran Device utilization summary: --------------------------- Selected Device : 3s400pq208-4 Number of Slices: 0 out of 3584 0% Number of IOs: 206 Number of bonded IOBs: 0 out of 141 0% Number of BRAMs: 16 out of 16 100% "ratemonotonic" <niladri1979@gmail.com> wrote in message = news:42df5ae8-8e9c-4475-983d-adc4c8c5b9f1@s8g2000prg.googlegroups.com... > On Dec 13, 12:23 pm, Brian Drummond <brian_drumm...@btconnect.com> > wrote: >> On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic >> >> <niladri1...@gmail.com> wrote: >> >Hi All , >> >> >I am new to FPGA development and have learned VHDL using text books. >> >NOW! that doesn't teach practical aspects! >> >I am extremely confused with the following discovery - >> >> >Now the confusing part - I have designed an IP which consumes 15 >> >Block Rams , and when I include the IP in my microblaze system , the >> >bitstream gets generated! The synthesis report shows that my IP is >> >using up 15 Block Rams and that microblaze momories are using up 16 >> >Block Rams! That means that the system is using up 31 Block Rams! >> >> >How is that Possilbe? >> >> The final synthesis report probably shows about 190% of the BRAM >> resources are used. >> >> The synthesis output is valid - BUT - will not pass through the >> implementation tools until you either: redesign to use fewer = resources, >> or: target a bigger FPGA. >> >> If you don't want to re-design, low cost boards are available with = the >> Spartan-3 1500. Here's one... >> >> http://www.enterpoint.co.uk/moelbryn/raggedstone1.html >> >> - Brian >=20 > yes it is confusing because I am able to burn the logic and step > through the C code! > The system.mhh is as follows - >=20 >=20 >=20 > # > = #########################################################################= ##### > # Created by Base System Builder Wizard for Xilinx EDK 9.2 Build > EDK_Jm.16 > # Tue Dec 11 11:23:35 2007 > # Target Board: Memec Spartan-3 3S400LC Development Board Rev 2 > # Family: spartan3 > # Device: XC3S400 > # Package: PQ208 > # Speed Grade: -4 > # Processor: microblaze_0 > # System clock frequency: 50.000000 MHz > # On Chip Memory : 16 KB > # > = #########################################################################= ##### > PARAMETER VERSION =3D 2.1.0 >=20 >=20 > PORT fpga_0_RS232_RX_pin =3D fpga_0_RS232_RX, DIR =3D I > PORT fpga_0_RS232_TX_pin =3D fpga_0_RS232_TX, DIR =3D O > PORT fpga_0_DIP_Switches_4Bit_GPIO_in_pin =3D > fpga_0_DIP_Switches_4Bit_GPIO_in, DIR =3D I, VEC =3D [0:3] > PORT sys_clk_pin =3D dcm_clk_s, DIR =3D I, SIGIS =3D CLK, CLK_FREQ =3D > 50000000 > PORT sys_rst_pin =3D sys_rst_s, DIR =3D I, RST_POLARITY =3D 0, SIGIS = =3D RST >=20 >=20 > BEGIN microblaze > PARAMETER HW_VER =3D 7.00.a > PARAMETER INSTANCE =3D microblaze_0 > PARAMETER C_DEBUG_ENABLED =3D 1 > PARAMETER C_AREA_OPTIMIZED =3D 1 > PARAMETER C_FSL_LINKS =3D 1 > PARAMETER C_FAMILY =3D spartan3 > PARAMETER C_INSTANCE =3D microblaze_0 > BUS_INTERFACE DPLB =3D mb_plb > BUS_INTERFACE IPLB =3D mb_plb > BUS_INTERFACE DEBUG =3D microblaze_0_dbg > BUS_INTERFACE SFSL0 =3D modem_fsl_wrapper_0_to_microblaze_0_0 > BUS_INTERFACE DLMB =3D dlmb > BUS_INTERFACE ILMB =3D ilmb > BUS_INTERFACE MFSL0 =3D microblaze_0_to_modem_fsl_wrapper_0_0 > PORT RESET =3D mb_reset > PORT INTERRUPT =3D microblaze_0_INTERRUPT > END >=20 > BEGIN plb_v46 > PARAMETER INSTANCE =3D mb_plb > PARAMETER HW_VER =3D 1.00.a > PORT PLB_Clk =3D sys_clk_s > PORT SYS_Rst =3D sys_bus_reset > END >=20 > BEGIN lmb_v10 > PARAMETER INSTANCE =3D ilmb > PARAMETER HW_VER =3D 1.00.a > PORT LMB_Clk =3D sys_clk_s > PORT SYS_Rst =3D sys_bus_reset > END >=20 > BEGIN lmb_v10 > PARAMETER INSTANCE =3D dlmb > PARAMETER HW_VER =3D 1.00.a > PORT LMB_Clk =3D sys_clk_s > PORT SYS_Rst =3D sys_bus_reset > END >=20 > BEGIN lmb_bram_if_cntlr > PARAMETER INSTANCE =3D dlmb_cntlr > PARAMETER HW_VER =3D 2.10.a > PARAMETER C_BASEADDR =3D 0x00000000 > PARAMETER C_HIGHADDR =3D 0x00007FFF > BUS_INTERFACE SLMB =3D dlmb > BUS_INTERFACE BRAM_PORT =3D dlmb_cntlr_BRAM_PORT > END >=20 > BEGIN lmb_bram_if_cntlr > PARAMETER INSTANCE =3D ilmb_cntlr > PARAMETER HW_VER =3D 2.10.a > PARAMETER C_BASEADDR =3D 0x00000000 > PARAMETER C_HIGHADDR =3D 0x00007FFF > BUS_INTERFACE SLMB =3D ilmb > BUS_INTERFACE BRAM_PORT =3D ilmb_cntlr_BRAM_PORT > END >=20 > BEGIN bram_block > PARAMETER INSTANCE =3D lmb_bram > PARAMETER HW_VER =3D 1.00.a > BUS_INTERFACE PORTB =3D dlmb_cntlr_BRAM_PORT > BUS_INTERFACE PORTA =3D ilmb_cntlr_BRAM_PORT > END >=20 > BEGIN xps_uartlite > PARAMETER INSTANCE =3D RS232 > PARAMETER HW_VER =3D 1.00.a > PARAMETER C_BAUDRATE =3D 9600 > PARAMETER C_DATA_BITS =3D 8 > PARAMETER C_ODD_PARITY =3D 0 > PARAMETER C_USE_PARITY =3D 0 > PARAMETER C_SPLB_CLK_FREQ_HZ =3D 50000000 > PARAMETER C_BASEADDR =3D 0x83c12000 > PARAMETER C_HIGHADDR =3D 0x83c121ff > BUS_INTERFACE SPLB =3D mb_plb > PORT RX =3D fpga_0_RS232_RX > PORT TX =3D fpga_0_RS232_TX > END >=20 > BEGIN xps_gpio > PARAMETER INSTANCE =3D DIP_Switches_4Bit > PARAMETER HW_VER =3D 1.00.a > PARAMETER C_GPIO_WIDTH =3D 4 > PARAMETER C_IS_DUAL =3D 0 > PARAMETER C_ALL_INPUTS =3D 1 > PARAMETER C_IS_BIDIR =3D 0 > PARAMETER C_BASEADDR =3D 0x81400000 > PARAMETER C_HIGHADDR =3D 0x8140ffff > BUS_INTERFACE SPLB =3D mb_plb > PORT GPIO_in =3D fpga_0_DIP_Switches_4Bit_GPIO_in > END >=20 > BEGIN xps_timer > PARAMETER INSTANCE =3D timer_counter > PARAMETER HW_VER =3D 1.00.a > PARAMETER C_ONE_TIMER_ONLY =3D 1 > PARAMETER C_BASEADDR =3D 0x83c00000 > PARAMETER C_HIGHADDR =3D 0x83c0ffff > BUS_INTERFACE SPLB =3D mb_plb > PORT Interrupt =3D timer1 > PORT CaptureTrig0 =3D net_gnd > END >=20 > BEGIN clock_generator > PARAMETER INSTANCE =3D clock_generator_0 > PARAMETER HW_VER =3D 1.00.a > PARAMETER C_EXT_RESET_HIGH =3D 1 > PARAMETER C_CLKIN_FREQ =3D 50000000 > PARAMETER C_CLKOUT0_FREQ =3D 50000000 > PARAMETER C_CLKOUT0_PHASE =3D 0 > PARAMETER C_CLKOUT0_GROUP =3D NONE > PORT CLKOUT0 =3D sys_clk_s > PORT CLKIN =3D dcm_clk_s > PORT LOCKED =3D Dcm_all_locked > PORT RST =3D net_gnd > END >=20 > BEGIN mdm > PARAMETER INSTANCE =3D debug_module > PARAMETER HW_VER =3D 1.00.a > PARAMETER C_MB_DBG_PORTS =3D 1 > PARAMETER C_USE_UART =3D 1 > PARAMETER C_UART_WIDTH =3D 8 > PARAMETER C_BASEADDR =3D 0x84400000 > PARAMETER C_HIGHADDR =3D 0x8440ffff > BUS_INTERFACE SPLB =3D mb_plb > BUS_INTERFACE MBDEBUG_0 =3D microblaze_0_dbg > PORT Debug_SYS_Rst =3D Debug_SYS_Rst > END >=20 > BEGIN proc_sys_reset > PARAMETER INSTANCE =3D proc_sys_reset_0 > PARAMETER HW_VER =3D 2.00.a > PARAMETER C_EXT_RESET_HIGH =3D 0 > PORT Slowest_sync_clk =3D sys_clk_s > PORT Dcm_locked =3D Dcm_all_locked > PORT Ext_Reset_In =3D sys_rst_s > PORT MB_Reset =3D mb_reset > PORT Bus_Struct_Reset =3D sys_bus_reset > PORT MB_Debug_Sys_Rst =3D Debug_SYS_Rst > END >=20 > BEGIN fsl_v20 > PARAMETER INSTANCE =3D modem_fsl_wrapper_0_to_microblaze_0_0 > PARAMETER HW_VER =3D 2.11.a > PORT FSL_Clk =3D sys_clk_s > PORT SYS_Rst =3D net_gnd > END >=20 > BEGIN modem_fsl_wrapper > PARAMETER INSTANCE =3D modem_fsl_wrapper_0 > BUS_INTERFACE MFSL =3D modem_fsl_wrapper_0_to_microblaze_0_0 > BUS_INTERFACE SFSL =3D microblaze_0_to_modem_fsl_wrapper_0_0 > PORT FSL_Clk =3D sys_clk_s > END >=20 > BEGIN fsl_v20 > PARAMETER INSTANCE =3D microblaze_0_to_modem_fsl_wrapper_0_0 > PARAMETER HW_VER =3D 2.11.a > PORT FSL_Clk =3D sys_clk_s > PORT SYS_Rst =3D net_gnd > END >=20 > BEGIN xps_intc > PARAMETER INSTANCE =3D xps_intc_0 > PARAMETER HW_VER =3D 1.00.a > PARAMETER C_BASEADDR =3D 0x83c14000 > PARAMETER C_HIGHADDR =3D 0x83c141ff > BUS_INTERFACE SPLB =3D mb_plb > PORT Irq =3D microblaze_0_INTERRUPT > PORT Intr =3D timer1 > END >=20 > BEGIN util_vector_logic > PARAMETER INSTANCE =3D util_vector_logic_0 > PARAMETER HW_VER =3D 1.00.a > END >=20 > The guilty modules are - > 1)modem_fsl_wrapper whose device utilisation summary is - > Selected Device : 3s400pq208-4 >=20 > Number of Slices: 665 out of 3584 18% > Number of Slice Flip Flops: 841 out of 7168 11% > Number of 4 input LUTs: 995 out of 7168 13% > Number used as logic: 923 > Number used as Shift registers: 72 > Number of IOs: 140 > Number of bonded IOBs: 0 out of 141 0% > Number of BRAMs: 15 out of 16 93% > Number of MULT18X18s: 16 out of 16 100% > Number of GCLKs: 6 out of 8 75% > 2) Local BRAM - > device utilisatioin - > Device utilization summary: > --------------------------- >=20 > Selected Device : 3s400pq208-4 >=20 > Number of Slices: 0 out of 3584 0% > Number of IOs: 206 > Number of bonded IOBs: 0 out of 141 0% > Number of BRAMs: 16 out of 16 100% >=20 >=20 >=20 >=20 > Thanks for the guidance ! > BR > Rate ------=_NextPart_000_0041_01C83E32.04930510 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; = charset=3Diso-8859-1"> <META content=3D"MSHTML 6.00.2900.3132" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY> <DIV><FONT face=3DArial size=3D2>Hi,</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D1><FONT size=3D2>From your email</FONT> = <FONT size=3D2>I=20 found this.</FONT></FONT></DIV> <DIV><FONT face=3DArial size=3D2>It looks everything has been trimmed = away since you=20 are using 0% slices and 0 pads.</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>If you look at the system_map.mrp file, = there is a=20 section on what has been trimmed away.</FONT></DIV> <DIV><FONT face=3DArial size=3D2>That could give you a hint what is = causing this.=20 You might also add the option "-detail" to the map tool.</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>G=F6ran</FONT></DIV> <DIV><FONT face=3DArial size=3D2><EM><FONT = size=3D1></FONT></EM></FONT> </DIV> <DIV><FONT face=3DArial size=3D2><EM><FONT size=3D1>Device utilization=20 summary:<BR>---------------------------<BR><BR>Selected Device :=20 3s400pq208-4<BR><BR> Number of=20 Slices: = =20 0 out of 3584 = 0%<BR> Number of=20 IOs: &nb= sp; =20 206<BR> Number of bonded=20 IOBs: &n= bsp; =20 0 out of 141 = 0%<BR> Number=20 of=20 BRAMs: &= nbsp; =20 16 out of 16 =20 100%</FONT></EM><BR></DIV></FONT> <DIV><FONT face=3DArial size=3D2>"ratemonotonic" <</FONT><A=20 href=3D"mailto:niladri1979@gmail.com"><FONT face=3DArial=20 size=3D2>niladri1979@gmail.com</FONT></A><FONT face=3DArial = size=3D2>> wrote in=20 message </FONT><A=20 href=3D"news:42df5ae8-8e9c-4475-983d-adc4c8c5b9f1@s8g2000prg.googlegroups= .com"><FONT=20 face=3DArial=20 size=3D2>news:42df5ae8-8e9c-4475-983d-adc4c8c5b9f1@s8g2000prg.googlegroup= s.com</FONT></A><FONT=20 face=3DArial size=3D2>...</FONT></DIV><FONT face=3DArial size=3D2>> = On Dec 13, 12:23=20 pm, Brian Drummond <</FONT><A=20 href=3D"mailto:brian_drumm...@btconnect.com"><FONT face=3DArial=20 size=3D2>brian_drumm...@btconnect.com</FONT></A><FONT face=3DArial=20 size=3D2>><BR>> wrote:<BR>>> On Wed, 12 Dec 2007 07:49:18 = -0800 (PST),=20 ratemonotonic<BR>>><BR>>> <</FONT><A=20 href=3D"mailto:niladri1...@gmail.com"><FONT face=3DArial=20 size=3D2>niladri1...@gmail.com</FONT></A><FONT face=3DArial = size=3D2>>=20 wrote:<BR>>> >Hi All ,<BR>>><BR>>> >I am new to = FPGA=20 development and have learned VHDL using text books.<BR>>> >NOW! = that=20 doesn't teach practical aspects!<BR>>> >I am extremely confused = with=20 the following discovery -<BR>>><BR>>> >Now the confusing = part=20 - I have designed an IP which consumes 15<BR>>> >Block = Rams , and=20 when I include the IP in my microblaze system , the<BR>>> = >bitstream=20 gets generated! The synthesis report shows that my IP is<BR>>> = >using=20 up 15 Block Rams and that microblaze momories are using up = 16<BR>>>=20 >Block Rams! That means that the system is using up 31 Block=20 Rams!<BR>>><BR>>> >How is that = Possilbe?<BR>>><BR>>>=20 The final synthesis report probably shows about 190% of the = BRAM<BR>>>=20 resources are used.<BR>>><BR>>> The synthesis output is = valid - BUT=20 - will not pass through the<BR>>> implementation tools until you = either:=20 redesign to use fewer resources,<BR>>> or: target a bigger=20 FPGA.<BR>>><BR>>> If you don't want to re-design, low cost = boards=20 are available with the<BR>>> Spartan-3 1500. Here's=20 one...<BR>>><BR>>> </FONT><A=20 href=3D"http://www.enterpoint.co.uk/moelbryn/raggedstone1.html"><FONT = face=3DArial=20 size=3D2>http://www.enterpoint.co.uk/moelbryn/raggedstone1.html</FONT></A= ><BR><FONT=20 face=3DArial size=3D2>>><BR>>> - Brian<BR>> <BR>> yes = it is=20 confusing because I am able to burn the logic and step<BR>> through = the C=20 code!<BR>> The system.mhh is as follows -<BR>> <BR>> <BR>> = <BR>>=20 #<BR>>=20 #########################################################################= #####<BR>>=20 # Created by Base System Builder Wizard for Xilinx EDK 9.2 Build<BR>> = EDK_Jm.16<BR>> # Tue Dec 11 11:23:35 2007<BR>> # Target = Board: Memec=20 Spartan-3 3S400LC Development Board Rev 2<BR>> # Family: = spartan3<BR>> #=20 Device: XC3S400<BR>> # Package: PQ208<BR>> # Speed Grade: = -4<BR>> #=20 Processor: microblaze_0<BR>> # System clock frequency: 50.000000 = MHz<BR>>=20 # On Chip Memory : 16 KB<BR>> #<BR>>=20 #########################################################################= #####<BR>> PARAMETER=20 VERSION =3D 2.1.0<BR>> <BR>> <BR>> PORT = fpga_0_RS232_RX_pin =3D=20 fpga_0_RS232_RX, DIR =3D I<BR>> PORT fpga_0_RS232_TX_pin =3D=20 fpga_0_RS232_TX, DIR =3D O<BR>> PORT = fpga_0_DIP_Switches_4Bit_GPIO_in_pin=20 =3D<BR>> fpga_0_DIP_Switches_4Bit_GPIO_in, DIR =3D I, VEC =3D=20 [0:3]<BR>> PORT sys_clk_pin =3D dcm_clk_s, DIR =3D I, SIGIS =3D = CLK, CLK_FREQ=20 =3D<BR>> 50000000<BR>> PORT sys_rst_pin =3D sys_rst_s, DIR = =3D I,=20 RST_POLARITY =3D 0, SIGIS =3D RST<BR>> <BR>> <BR>> BEGIN=20 microblaze<BR>> PARAMETER HW_VER =3D = 7.00.a<BR>> PARAMETER=20 INSTANCE =3D microblaze_0<BR>> PARAMETER C_DEBUG_ENABLED =3D=20 1<BR>> PARAMETER C_AREA_OPTIMIZED =3D 1<BR>> PARAMETER = C_FSL_LINKS=20 =3D 1<BR>> PARAMETER C_FAMILY =3D = spartan3<BR>> PARAMETER C_INSTANCE=20 =3D microblaze_0<BR>> BUS_INTERFACE DPLB =3D=20 mb_plb<BR>> BUS_INTERFACE IPLB =3D = mb_plb<BR>> BUS_INTERFACE DEBUG=20 =3D microblaze_0_dbg<BR>> BUS_INTERFACE SFSL0 =3D=20 modem_fsl_wrapper_0_to_microblaze_0_0<BR>> BUS_INTERFACE DLMB = =3D=20 dlmb<BR>> BUS_INTERFACE ILMB =3D ilmb<BR>> BUS_INTERFACE = MFSL0 =3D=20 microblaze_0_to_modem_fsl_wrapper_0_0<BR>> PORT RESET =3D=20 mb_reset<BR>> PORT INTERRUPT =3D microblaze_0_INTERRUPT<BR>>=20 END<BR>> <BR>> BEGIN plb_v46<BR>> PARAMETER INSTANCE =3D=20 mb_plb<BR>> PARAMETER HW_VER =3D 1.00.a<BR>> PORT = PLB_Clk =3D=20 sys_clk_s<BR>> PORT SYS_Rst =3D sys_bus_reset<BR>> = END<BR>> <BR>>=20 BEGIN lmb_v10<BR>> PARAMETER INSTANCE =3D = ilmb<BR>> PARAMETER=20 HW_VER =3D 1.00.a<BR>> PORT LMB_Clk =3D = sys_clk_s<BR>> PORT SYS_Rst=20 =3D sys_bus_reset<BR>> END<BR>> <BR>> BEGIN=20 lmb_v10<BR>> PARAMETER INSTANCE =3D dlmb<BR>> PARAMETER = HW_VER =3D=20 1.00.a<BR>> PORT LMB_Clk =3D sys_clk_s<BR>> PORT SYS_Rst = =3D=20 sys_bus_reset<BR>> END<BR>> <BR>> BEGIN=20 lmb_bram_if_cntlr<BR>> PARAMETER INSTANCE =3D=20 dlmb_cntlr<BR>> PARAMETER HW_VER =3D = 2.10.a<BR>> PARAMETER=20 C_BASEADDR =3D 0x00000000<BR>> PARAMETER C_HIGHADDR =3D=20 0x00007FFF<BR>> BUS_INTERFACE SLMB =3D = dlmb<BR>> BUS_INTERFACE=20 BRAM_PORT =3D dlmb_cntlr_BRAM_PORT<BR>> END<BR>> <BR>> BEGIN=20 lmb_bram_if_cntlr<BR>> PARAMETER INSTANCE =3D=20 ilmb_cntlr<BR>> PARAMETER HW_VER =3D = 2.10.a<BR>> PARAMETER=20 C_BASEADDR =3D 0x00000000<BR>> PARAMETER C_HIGHADDR =3D=20 0x00007FFF<BR>> BUS_INTERFACE SLMB =3D = ilmb<BR>> BUS_INTERFACE=20 BRAM_PORT =3D ilmb_cntlr_BRAM_PORT<BR>> END<BR>> <BR>> BEGIN=20 bram_block<BR>> PARAMETER INSTANCE =3D = lmb_bram<BR>> PARAMETER=20 HW_VER =3D 1.00.a<BR>> BUS_INTERFACE PORTB =3D=20 dlmb_cntlr_BRAM_PORT<BR>> BUS_INTERFACE PORTA =3D=20 ilmb_cntlr_BRAM_PORT<BR>> END<BR>> <BR>> BEGIN=20 xps_uartlite<BR>> PARAMETER INSTANCE =3D = RS232<BR>> PARAMETER=20 HW_VER =3D 1.00.a<BR>> PARAMETER C_BAUDRATE =3D = 9600<BR>> PARAMETER=20 C_DATA_BITS =3D 8<BR>> PARAMETER C_ODD_PARITY =3D = 0<BR>> PARAMETER=20 C_USE_PARITY =3D 0<BR>> PARAMETER C_SPLB_CLK_FREQ_HZ =3D=20 50000000<BR>> PARAMETER C_BASEADDR =3D = 0x83c12000<BR>> PARAMETER=20 C_HIGHADDR =3D 0x83c121ff<BR>> BUS_INTERFACE SPLB =3D=20 mb_plb<BR>> PORT RX =3D fpga_0_RS232_RX<BR>> PORT TX =3D = fpga_0_RS232_TX<BR>> END<BR>> <BR>> BEGIN=20 xps_gpio<BR>> PARAMETER INSTANCE =3D=20 DIP_Switches_4Bit<BR>> PARAMETER HW_VER =3D = 1.00.a<BR>> PARAMETER=20 C_GPIO_WIDTH =3D 4<BR>> PARAMETER C_IS_DUAL =3D = 0<BR>> PARAMETER=20 C_ALL_INPUTS =3D 1<BR>> PARAMETER C_IS_BIDIR =3D = 0<BR>> PARAMETER=20 C_BASEADDR =3D 0x81400000<BR>> PARAMETER C_HIGHADDR =3D=20 0x8140ffff<BR>> BUS_INTERFACE SPLB =3D mb_plb<BR>> PORT = GPIO_in =3D=20 fpga_0_DIP_Switches_4Bit_GPIO_in<BR>> END<BR>> <BR>> BEGIN=20 xps_timer<BR>> PARAMETER INSTANCE =3D = timer_counter<BR>> PARAMETER=20 HW_VER =3D 1.00.a<BR>> PARAMETER C_ONE_TIMER_ONLY =3D=20 1<BR>> PARAMETER C_BASEADDR =3D = 0x83c00000<BR>> PARAMETER=20 C_HIGHADDR =3D 0x83c0ffff<BR>> BUS_INTERFACE SPLB =3D=20 mb_plb<BR>> PORT Interrupt =3D timer1<BR>> PORT = CaptureTrig0 =3D=20 net_gnd<BR>> END<BR>> <BR>> BEGIN=20 clock_generator<BR>> PARAMETER INSTANCE =3D=20 clock_generator_0<BR>> PARAMETER HW_VER =3D = 1.00.a<BR>> PARAMETER=20 C_EXT_RESET_HIGH =3D 1<BR>> PARAMETER C_CLKIN_FREQ =3D=20 50000000<BR>> PARAMETER C_CLKOUT0_FREQ =3D = 50000000<BR>> PARAMETER=20 C_CLKOUT0_PHASE =3D 0<BR>> PARAMETER C_CLKOUT0_GROUP =3D=20 NONE<BR>> PORT CLKOUT0 =3D sys_clk_s<BR>> PORT CLKIN =3D = dcm_clk_s<BR>> PORT LOCKED =3D Dcm_all_locked<BR>> PORT = RST =3D=20 net_gnd<BR>> END<BR>> <BR>> BEGIN mdm<BR>> PARAMETER = INSTANCE =3D=20 debug_module<BR>> PARAMETER HW_VER =3D = 1.00.a<BR>> PARAMETER=20 C_MB_DBG_PORTS =3D 1<BR>> PARAMETER C_USE_UART =3D = 1<BR>> PARAMETER=20 C_UART_WIDTH =3D 8<BR>> PARAMETER C_BASEADDR =3D=20 0x84400000<BR>> PARAMETER C_HIGHADDR =3D=20 0x8440ffff<BR>> BUS_INTERFACE SPLB =3D = mb_plb<BR>> BUS_INTERFACE=20 MBDEBUG_0 =3D microblaze_0_dbg<BR>> PORT Debug_SYS_Rst =3D=20 Debug_SYS_Rst<BR>> END<BR>> <BR>> BEGIN=20 proc_sys_reset<BR>> PARAMETER INSTANCE =3D=20 proc_sys_reset_0<BR>> PARAMETER HW_VER =3D = 2.00.a<BR>> PARAMETER=20 C_EXT_RESET_HIGH =3D 0<BR>> PORT Slowest_sync_clk =3D=20 sys_clk_s<BR>> PORT Dcm_locked =3D = Dcm_all_locked<BR>> PORT=20 Ext_Reset_In =3D sys_rst_s<BR>> PORT MB_Reset =3D = mb_reset<BR>> PORT=20 Bus_Struct_Reset =3D sys_bus_reset<BR>> PORT MB_Debug_Sys_Rst = =3D=20 Debug_SYS_Rst<BR>> END<BR>> <BR>> BEGIN = fsl_v20<BR>> PARAMETER=20 INSTANCE =3D = modem_fsl_wrapper_0_to_microblaze_0_0<BR>> PARAMETER HW_VER =3D=20 2.11.a<BR>> PORT FSL_Clk =3D sys_clk_s<BR>> PORT SYS_Rst = =3D=20 net_gnd<BR>> END<BR>> <BR>> BEGIN=20 modem_fsl_wrapper<BR>> PARAMETER INSTANCE =3D=20 modem_fsl_wrapper_0<BR>> BUS_INTERFACE MFSL =3D=20 modem_fsl_wrapper_0_to_microblaze_0_0<BR>> BUS_INTERFACE SFSL = =3D=20 microblaze_0_to_modem_fsl_wrapper_0_0<BR>> PORT FSL_Clk =3D=20 sys_clk_s<BR>> END<BR>> <BR>> BEGIN = fsl_v20<BR>> PARAMETER=20 INSTANCE =3D = microblaze_0_to_modem_fsl_wrapper_0_0<BR>> PARAMETER HW_VER =3D=20 2.11.a<BR>> PORT FSL_Clk =3D sys_clk_s<BR>> PORT SYS_Rst = =3D=20 net_gnd<BR>> END<BR>> <BR>> BEGIN = xps_intc<BR>> PARAMETER=20 INSTANCE =3D xps_intc_0<BR>> PARAMETER HW_VER =3D=20 1.00.a<BR>> PARAMETER C_BASEADDR =3D = 0x83c14000<BR>> PARAMETER=20 C_HIGHADDR =3D 0x83c141ff<BR>> BUS_INTERFACE SPLB =3D=20 mb_plb<BR>> PORT Irq =3D = microblaze_0_INTERRUPT<BR>> PORT Intr =3D=20 timer1<BR>> END<BR>> <BR>> BEGIN=20 util_vector_logic<BR>> PARAMETER INSTANCE =3D=20 util_vector_logic_0<BR>> PARAMETER HW_VER =3D 1.00.a<BR>> = END<BR>>=20 <BR>> The guilty modules are -<BR>> 1)modem_fsl_wrapper = whose device=20 utilisation summary is -<BR>> Selected Device : 3s400pq208-4<BR>>=20 <BR>> Number of=20 Slices: = =20 665 out of 3584 = 18%<BR>> Number of=20 Slice Flip = Flops: =20 841 out of 7168 = 11%<BR>> Number of 4=20 input=20 LUTs: &n= bsp; =20 995 out of 7168 =20 13%<BR>> Number used as=20 logic: &= nbsp; =20 923<BR>> Number used as Shift=20 registers: 72<BR>> Number of=20 IOs: &nb= sp; =20 140<BR>> Number of bonded=20 IOBs: &n= bsp; =20 0 out of 141 =20 0%<BR>> Number of=20 BRAMs: &= nbsp; =20 15 out of 16 =20 93%<BR>> Number of=20 MULT18X18s: &n= bsp; =20 16 out of 16 = 100%<BR>> Number=20 of=20 GCLKs: &= nbsp; =20 6 out of 8 = 75%<BR>> 2)=20 Local BRAM -<BR>> device utilisatioin -<BR>> Device utilization=20 summary:<BR>> ---------------------------<BR>> <BR>> Selected = Device :=20 3s400pq208-4<BR>> <BR>> Number of=20 Slices: = =20 0 out of 3584 = 0%<BR>> Number=20 of=20 IOs: &nb= sp; =20 206<BR>> Number of bonded=20 IOBs: &n= bsp; =20 0 out of 141 =20 0%<BR>> Number of=20 BRAMs: &= nbsp; =20 16 out of 16 100%<BR>> = <BR>>=20 <BR>> <BR>> <BR>> Thanks for the guidance !<BR>> BR<BR>>=20 Rate</FONT></BODY></HTML> ------=_NextPart_000_0041_01C83E32.04930510--Article: 127210
When i use chipscope 9.2 to configerate bit file, sometimes will occour warning like this "WARNING - Device 0: ICON Core version v15.15 is not supported", and the configeration failed. When this happen, I rerun the some project, then configeration is successed. Please tell me why this happen, thanks!Article: 127211
Specification
EDK version:8.2i
FPGA Board: Virtex II Pro
Compiler : mb-g++
I'm tring to create a file stream using ifstream instr("ba1.bits")
or ifstream instr("a:\\ba1.bits") to create a file stream from
CF card.
In addition I've added #include <stdio.h> which is necessary to
ensure that microblaze compiler recognizes the the c++ sections of
code.
I've amended the file ....\EDK\sw\lib\sw_services\xilfatfs_v1_00_a
\src\include\sysace_stdio.h uncommenting the following lines
#define SYSACE_FILE FILE
// typedef void FILE;
#define fopen sysace_fopen
#define fclose sysace_fclose
#define fread sysace_fread
#define fwrite sysace_fwrite
File cannot be read...
Alternatively I tried using sysace_fopen directly -> char array ->
streambuf
streambuf * pbuf;
void myrun(void * mybuf) {
sysace_fread( (void *) mybuf, 1, 1, outfile);
// pbuf->sputn (charbuffin,sizeof(charbuffin)-1);
}
Int main (){
void *mainbuf;
if ((outfile = sysace_fopen("file.txt", "r")) == NULL)
{
xil_printf("Couldn't open the file\r\n");
}
else{
for (int i=0;i<4;i++){
myrun(mainbuf);
pbuf->sputc( (char *) mainbuf);
usleep(1000);
}
return 0;
}
System hangs at this point.........
Please do let me know how file from CF card ->input stream?
Priyantha
Article: 127212On Dec 12, 3:13 pm, Poonam <poonam.mur...@gmail.com> wrote: > I am interested in learning about designing boards myself with FPGAs, ADCs, DACs etc. I am new to > board design and am wondering where to start. What sort of speed of signals are you anticipating on your board? This will have a great effect on whether you have a productive or painfully fruitless learning experience. Maybe it would be better to knock up a few small boards with some discretes on first. That way you are more likely to learn about the design/manufacturing process, without making expensive mistakes. You could even do this purely as a paper exercise. Draw the schematic of a circuit, then cut out some component shapes from card. Position the shapes on a piece of paper the way you think they would best fit. Then draw a few interconnecting lines, and see if you can route them by hand. AndrewArticle: 127213
On Dec 14, 1:21 pm, "mynewlife...@yahoo.com.cn" <mynewlife...@yahoo.com.cn> wrote: > When i usechipscope9.2 to configerate bit file, sometimes will > occour warning like this "WARNING - Device 0: ICON Core version v15.15 > is not supported", and the configeration failed. When this happen, I > rerun the some project, then configeration is successed. Please tell > me why this happen, thanks! XILINX version is not compatible when compared to lower versions. Which version you have used to generate bit file. Is it with ISE 9.2 and you should use Chipscope of same version ie 9.1i and upto 8.2i. (you can use) First confirm which version for chipscope and ISE ur using for debugging.Article: 127214
Does anybody have experience with Chrontel 7010A (CH7010A)? I input BT.656 digital video to Chrontel 7010A. I'm trying to get DVI output. For now, my only concern is the DVI mode of operation (not TV mode). Therefore; there is not a crystal connected to it. I intend to use it in slave clock mode. I set serial programming registers of CH7010A once without a proper order. Do I have to write them in a sequence? My input is BT.656 video from a video decoder with 27 MHz clock. First, I tried interlaced output of the video decoder as input to the CH7010A. (In this mode 27 MHz clock is 2xpixel rate) Then, I generated progressive PAL video syncs in the FPGA and input it to CH7010A. Neither one of them didn't work although I tried many register setting combinations. I could only get DVI output a couple of times. It was not a valid DVI output. After power down, even that invalid DVI output did not show with the same register settings. CH7010A seems as if it is in power down although it has all the supply voltages, slave clock, and proper "Power Down Register" setting. I verified that I can write to its registers except the GPIO control register 1EH. I am trying to set its GPIOs as outputs giving high. High nibble of 1EH must be set as "0011" for this setting. But I read this nibble as "0000".Article: 127215
In order to clarify the problem: - LCD monitor did not display the invalid DVI output. - Invalid DVI output, which I could only get a couple of times, disappears after a cold restart. - Slave clock setup and hold times are OK.Article: 127216
Hi all, I am using XPS 8.2i and ISE 8.2i and a virtex-4 board.As a part of assignment, I have to write a verilog/vhdl code for a BRAM controller by which we can perform read/write operation on a BRAM block.I have written a desired verilog code for BRAM controller. Also I have added a Bram block to my assembly from pool.But My System assembly does not show any port in my BRAM controller to which I can connect the BRAM block. Any suggestions would be greatly appreciated thanks Rinky .Article: 127217
On Dec 14, 3:53 am, Andrew Burnside <andrew.burns...@sli- institute.ac.uk> wrote: > On Dec 12, 3:13 pm, Poonam <poonam.mur...@gmail.com> wrote: > > > I am interested in learning about designing boards myself with FPGAs, ADCs, DACs etc. I am new to > > board design and am wondering where to start. > > What sort of speed of signals are you anticipating on your board? > This will have a great effect on whether you have a productive or > painfully fruitless learning experience. > > Maybe it would be better to knock up a few small boards with some > discretes on first. That way you are more likely to learn about the > design/manufacturing process, without making expensive mistakes. > You could even do this purely as a paper exercise. Draw the schematic > of a circuit, then cut out some component shapes from card. Position> > Andrew FWIW, we have in the past prototyped parts of systems using prefabricated PCBs from Bellin Dynamic Systems (www.beldynsys.com). They stock a wide variety of break-apart cards with different IC footprints and surrounding pads that make it quite simple to build up quick prototype circuits. JohnArticle: 127218
On Wed, 12 Dec 2007 07:13:46 -0800 (PST), Poonam <poonam.murali@gmail.com> wrote: >Hi, > >I have been developing applications in Xilinx FPGAs using VHDL for the >past 3 years for a small company in Virginia. As our designs are >getting larger and more complex, the off-the-shelf boards we have been >using are proving to be insufficient. I am interested in learning >about designing boards myself with FPGAs, ADCs, DACs etc. I am new to >board design and am wondering where to start. Any suggestions would be >greatly appreciated. As a first step, consider taking an off-the-shelf board which (a) is a reasonably close match (only some peripherals you need are missing) and (b) has spare I/O connectivity. As an example, see the spare connectors on this board http://www.enterpoint.co.uk/moelbryn/raggedstone1.html (If I have misjudged your requirements, there are other boards, from this and other suppliers, with much more I/O to play with...) Now design a circuit board containing ONLY the missing peripherals, to connect to the available I/O headers. The cost, complexity and risk are much lower with this approach, and you still end up with a solution tailored specifically to your needs. If it matters, your customers cannot simply buy the original board and bypass you either... If this means you can get away with a small two-layer or four-layer board instead of a large complex 6 or 8-layer board, it greatly increases your chances of first-time success. It also means you are within the realm of low-cost prototyping services, like PCB123.com, who offer a crude but very usable PCB layout tool for free. The catch: it is only programmed to submit board designs to pcb123.com!However, given their prices and delivery speeds, that is not much of a catch. (Incidentally PCB123 is usable with SMT devices including QFP package FPGAs, but not realistically for larger BGA packages, because it imposes restrictions on minimum via size that will not fit between 1mm BGA pins. So it will do your add-on board, but possibly not your complete FPGA board. Also the schematic editor is not very useful. I used it on a simple design, and edited the resulting netlist to generate a more complex design) Combining the whole solution on to a single board can come later, but depending on the economics it may not be necessary. - BrianArticle: 127219
On Dec 13, 12:00 pm, Neil Steiner <neil.stei...@vt.edu> wrote:
> Does anybody know if XST defines any testable variables when compiling
> verilog code?
>
> Some of the compilers or simulators that I'm using have differing
> $readmemh() semantics, and I'd like to be able to write something like:
>
> `ifdef INCA
> initial $readmemh("memory",configurations,0,15);
> `else
> `ifdef XST
> initial $readmemh("memory",configurations,0,15);
> `else
> initial $readmemh("memory",configurations);
> `endif
> `endif
If you are using the GUI flow, the synthesis Properties page allows
you to add defines. You may
need to use the advanced properties page.
Hope this helps.
John Providenza
Article: 127220On Thu, 13 Dec 2007 08:19:26 -0800 (PST), ratemonotonic <niladri1979@gmail.com> wrote: >On Dec 13, 12:23 pm, Brian Drummond <brian_drumm...@btconnect.com> >wrote: >> On Wed, 12 Dec 2007 07:49:18 -0800 (PST), ratemonotonic >> >> The synthesis output is valid - BUT - will not pass through the >> implementation tools until you either: redesign to use fewer resources, >> or: target a bigger FPGA. >spartan 3 400 has 56Kbit distributed RAM is it possible that the >synthesizer is using then as block RAMs as well? Not if your design specifically calls for BRAMS, so not likely. In any case it would appear in the synth report and map.mrp as "LUTs used as memory" or equivalent wording. I am confused by the separate synthesis reports yu posted for modem_wrapper and local_bram ... are you synthesising the two separately? If so, how are you combining them into one project? Is this built entirely under EDK or are you combining an EDK design with an XST design? It is possible that something is going wrong with that step; apparently leaving you with a working Microblaze so presumably no modem... you have to get through this step to correctly fail, THEN worry about economising memory. - BrianArticle: 127221
> Tell us more about the off-the-shelf boards that don't meet your new > requirements. Have you looked at Digilent's products? They make > Xilinx FPGA starter boards. Perhaps it would be simpler/cheaper to > design a daughter board that has ADCs, DACs, whatever, than to design > a FPGA board from scratch. > -Dave Pollum (Burke, VA) I looked at Digilent's products and their A/D and D/A sampling frequencies do not meet my requirements, I need about 50-100MHz. In fact, I have looked at companies which offer FPGA based boards that can fit daughter cards. Very few of them really match my needs. And the ones that accomodate all my requirements are expensive. Thats why the move to designing custom boards. We figure, the initial investment might be a little heavy but it will prove to be better in the long run.. I like both ideas from John and Brian, it will probably be the best option instead of designing a whole board from scratch. But before getting into all that, I will design some small boards, hopefully learn how not to make expensive mistakes. Thank you all for all the suggestions. They have been very helpful to me. PoonamArticle: 127222
This is probably a long shot but I'm wondering if serial ATA can be run at a speed less than 1.5 Gbps? I have a V4 fpga but no MGTs so it would be nice if I could make it work with regular chipsync resources which can only go about 800 mbps. Thanks, ClarkArticle: 127223
Hi Priyantha -
Try replacing "file.txt" with "a:\\file.txt". To the standalone OS, the
CF drive looks like the "a:\" drive.
Thomas Werne
Bathala wrote:
> Specification
> EDK version:8.2i
> FPGA Board: Virtex II Pro
> Compiler : mb-g++
>
> I'm tring to create a file stream using ifstream instr("ba1.bits")
> or ifstream instr("a:\\ba1.bits") to create a file stream from
> CF card.
>
> In addition I've added #include <stdio.h> which is necessary to
> ensure that microblaze compiler recognizes the the c++ sections of
> code.
>
> I've amended the file ....\EDK\sw\lib\sw_services\xilfatfs_v1_00_a
> \src\include\sysace_stdio.h uncommenting the following lines
>
> #define SYSACE_FILE FILE
> // typedef void FILE;
>
> #define fopen sysace_fopen
> #define fclose sysace_fclose
> #define fread sysace_fread
> #define fwrite sysace_fwrite
>
> File cannot be read...
>
> Alternatively I tried using sysace_fopen directly -> char array ->
> streambuf
>
>
> streambuf * pbuf;
>
> void myrun(void * mybuf) {
> sysace_fread( (void *) mybuf, 1, 1, outfile);
> // pbuf->sputn (charbuffin,sizeof(charbuffin)-1);
> }
>
>
> Int main (){
> void *mainbuf;
>
> if ((outfile = sysace_fopen("file.txt", "r")) == NULL)
> {
> xil_printf("Couldn't open the file\r\n");
> }
> else{
>
> for (int i=0;i<4;i++){
> myrun(mainbuf);
> pbuf->sputc( (char *) mainbuf);
> usleep(1000);
> }
> return 0;
> }
>
> System hangs at this point.........
>
> Please do let me know how file from CF card ->input stream?
>
> Priyantha
>
>
--
All personal and professional opinions presented herein are my
own and do not, in any way, represent the opinion or policy of JPL
Article: 127224The Motto of MyHDL Project says: "From Python to silicon". Many people are interested to see any clear example of how one can produce a bit file for a FPGA from MyHDL. For example, it could be an example of binding MyHDL with popular XST, demonstrating, say, simple UART/VGA/LED/ or even SRAM controller. At the same time, VHDL analogous program should be available for the comparison. In that case, people can compare two digital design flows, executed using different languages. Results will show the quality of synthesized code, expended translation/synthesis time, and maybe will reveal some difficulties. Of course, MyHDL has preliminary preference because of its simplicity, syntax, and power.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z