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Hi I am designing an 8 layer board with a Virtex 4 device on it. I will have 2 solid ground planes and 2 split power planes. If I have a signal plane that is between a ground and power plane will it matter if I cross a split on the power plane with a signal track. I know that you should not cross a split it in a plane if you are referencing to that plane. But if I have a solid ground plane beneath the track will it use this plane as its reference rather than the power plane. Cheers JonArticle: 127526
For the next-generation clock box (1 Hz to 1.5 GHz with ~50 ps jitter) I need an LCD-backlit or OLED display, 128 x 64 bits, single or multiple colors, about 2 inch diagonal. OSRAM had a nice OLED display, but they went out of that business. Billions of cellphones, cameras, and iPods are being made, but where can I buy a couple of hundred displays? This is holding up a neat project. :-( Any help is really appreciated ! Peter AlfkeArticle: 127527
Peter Alfke <alfke@sbcglobal.net> writes: > OSRAM had a nice OLED display, but they went out of that business. http://www.osddisplays.com/Article: 127528
Peter Alfke wrote: > For the next-generation clock box (1 Hz to 1.5 GHz with ~50 ps > jitter) > I need an LCD-backlit or OLED display, 128 x 64 bits, single or > multiple colors, about 2 inch diagonal. Only 1.4" diagonal, but a nice 128x128 color display: http://www.sparkfun.com/commerce/product_info.php?products_id=712 The integrated controller has some graphics primitives already included (rectangle fill, scrolling etc.), so it is very easy to use (I've tested it with a microcontroller), but the parallel interface should be fast enough to refresh the whole display with 60 Hz from FPGAs, too. Your clock box sounds interesting. How do you manage 50 ps jitter? Is it possible with your clock box to create e.g. 1.4 GHz and 1.5 GHz with 50% duty cycle and 50 ps jitter? With my first experiments with DDS, jitter can be as worse as 1/main clock frequency. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 127529
On Tue, 1 Jan 2008 12:07:17 -0800 (PST), Peter Alfke <alfke@sbcglobal.net> wrote: > >For the next-generation clock box (1 Hz to 1.5 GHz with ~50 ps >jitter) 50 ps jitter at 1 Hz? That *is* a neat project! When can I buy one? I was considering getting one of the SRS clock boxes, but yours might do. JohnArticle: 127530
Wojciech Zabolotny wrote:
> Trying to implement a required state machine, I've found an idea which is
> quite interesting, but may also seem to be crazy:
> A state machine with "subroutines". The idea is to implement typical,
> often used state sequences as "subroutines", which may be "called"
> after pushing the next state to the stack. In the last state of the
> subrtoutine-sequence the next state is retrieved from the stack.
> It seems, that this approach may lead to relatively simple implementation
> of the complex state machines.
Thanks for posting your code.
If you like your style and the design fits
and makes timing, go ahead and use it.
I agree that almost any description is
better than one huge case statement.
There are two ways I know to use procedural code
targeting programmable logic.
One way is to make an HDL description of a custom processor to
"reduce" the problem to assembly language programming.
This seems to be the default academic track found in textbooks.
In this style, I would design a hardware processor
to execute a custom instruction set.
The downside, as Jonathan points out, is that before I can work
on solving my problem, I must first designing a custom description
language and hardware to run it.
The other way is to use a sequential HDL process
to describe all of the clocked register updates
by making use of variables, functions and procedures.
This style uses the HDL itself as a virtual cpu to describe
the cycle by cycle updates to the registers
In this method, a simulator is used to debug code
by tracing variable values and looking at waveforms.
The advantage to this style is that the
hdl "instructions" execute in zero time.
The real hardware limits are found by static timing,
and the design trade-off is pipeline ticks vs Fmax.
-- Mike Treseler
Article: 127531"maxascent" <maxascent@yahoo.co.uk> wrote in message news:xfKdnTDf__teAefaRVn_vwA@giganews.com... > > Hi > > I am designing an 8 layer board with a Virtex 4 device on it. I will have > 2 solid ground planes and 2 split power planes. If I have a signal plane > that is between a ground and power plane will it matter if I cross a split > on the power plane with a signal track. I know that you should not cross a > split it in a plane if you are referencing to that plane. But if I have a > solid ground plane beneath the track will it use this plane as its > reference rather than the power plane. > > Cheers > > Jon Hi Jon, There will be an impedance discontinuity at the split. The magnitude of this and whether it matters to your design will depend on the geometry of the stack up and signals; also the rise time of the signals. Why not put the powers on layers 4,5 and make 3 and 6 ground. Then you won't have this problem. HTH., Syms.Article: 127532
On Tue, 01 Jan 2008 14:04:19 -0600, "maxascent" <maxascent@yahoo.co.uk> wrote: > >Hi > >I am designing an 8 layer board with a Virtex 4 device on it. I will have >2 solid ground planes and 2 split power planes. If I have a signal plane >that is between a ground and power plane will it matter if I cross a split >on the power plane with a signal track. I know that you should not cross a >split it in a plane if you are referencing to that plane. But if I have a >solid ground plane beneath the track will it use this plane as its >reference rather than the power plane. > >Cheers > >Jon No, it doesn't matter. The strange concept of "reference planes" is irrelevent here... how does the signal know what plane you think it's referenced to? If the power planes are bypassed well enough to make them reliable power sources, then they are AC equipotential with the ground plane, so the signal sees them all as ground. And a small slit in a power plane is essentially invisible for edges slower than a few 10's of picoseconds. JohnArticle: 127533
Thanks, Frank, for the URL. I will investigate. A little pricey, but not out of the question. Regarding the jitter, I can be more specific in a few weeks, when we have the pre-production version (with the OSRAM display) really working. Until now we have used various form of emulation. Yes, jitter is the overwhelming issue, and it is 1/fclock coming out of the DDS accumulator, about 2 ns. There is a lot of trickery involved to get the jitter down. The most demanding chore is reducing "wander", i.e. low-frequency components in the jitter spectrum that cannot be filtered out by any analog PLL, but I think we are (almost) there. We did build a few hundred older boxes for our FAEs some years ago, and they had <70 ps cycle-to-cycle jitter, although the accumulator was running at only 160 MHz clock frequency. Some trickery... The frequency resolution was and is 1 Hz, and the new box has two independent output channels. Jitter is a fascinating subject, challenging and also frustrating. I'll keep you informed... Happy New Year ! Peter Alfke On Jan 1, 1:22=A0pm, Frank Buss <f...@frank-buss.de> wrote: > Peter Alfke wrote: > > For the next-generation clock box (1 Hz to 1.5 GHz with ~50 ps > > jitter) > > I need an LCD-backlit or OLED display, =A0128 x 64 bits, single or > > multiple colors, about 2 inch diagonal. > > Only 1.4" diagonal, but a nice 128x128 color display: > > http://www.sparkfun.com/commerce/product_info.php?products_id=3D712 > > The integrated controller has some graphics primitives already included > (rectangle fill, scrolling etc.), so it is very easy to use (I've tested i= t > with a microcontroller), but the parallel interface should be fast enough > to refresh the whole display with 60 Hz from FPGAs, too. > > Your clock box sounds interesting. How do you manage 50 ps jitter? Is it > possible with your clock box to create e.g. 1.4 GHz and 1.5 GHz with 50% > duty cycle and 50 ps jitter? With my first experiments with DDS, jitter ca= n > be as worse as 1/main clock frequency. > > -- > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-syst= ems.deArticle: 127534
Peter Alfke wrote: > Thanks, Frank, for the URL. I will investigate. A little pricey, but > not out of the question. Instead of a display, you could use a program on a PC. There is always a PC or laptop nearby. For example I've implemented a simple GUI and a serial port on the FPGA for my signal generator: http://www.frank-buss.de/SignalGenerator/ > Yes, jitter is the overwhelming issue, and it is 1/fclock coming out > of the DDS accumulator, about 2 ns. > There is a lot of trickery involved to get the jitter down. The most > demanding chore is reducing "wander", i.e. low-frequency components in > the jitter spectrum that cannot be filtered out by any analog PLL, > but I think we are (almost) there. A PLL sounds like a good idea, if you don't want to change the output frequency very fast. Maybe I'll try this with my generator and the internal PLL of the FPGA, if possible. I wonder how they manage 500 fs (yes, femto seconds) jitter with this cheap chip: http://www.analog.com/en/prod/0,2877,AD9540,00.html Is this the performance of the DDS, or just the jitter the device adds to the reference clock? But nevertheless, a programmable delay line would be a nice idea for eliminating jitter, without the need for analog circuits. The required delay time could be calculated with the current accumulator value (the bits below the carry). > Happy New Year ! Thank you, the same to you! -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 127535
On Jan 1, 4:49=A0pm, Frank Buss <f...@frank-buss.de> wrote: > Peter Alfke wrote: > > Thanks, Frank, for the URL. I will investigate. A little pricey, but > > not out of the question. > > Instead of a display, you could use a program on a PC. There is always a P= C > or laptop nearby. For example I've implemented a simple GUI and a serial > port on the FPGA for my signal generator: > > http://www.frank-buss.de/SignalGenerator/ > > > Yes, jitter is the overwhelming issue, and it is 1/fclock coming out > > of the DDS accumulator, about 2 ns. > > There is a lot of trickery involved to get the jitter down. The most > > demanding chore is reducing "wander", i.e. low-frequency components in > > the jitter spectrum that cannot be filtered out by any analog PLL, > > but I think we are (almost) there. > > A PLL sounds like a good idea, if you don't want to change the output > frequency very fast. Maybe I'll try this with my generator and the interna= l > PLL of the FPGA, if possible. > > I wonder how they manage 500 fs (yes, femto seconds) jitter with this chea= p > chip: > > http://www.analog.com/en/prod/0,2877,AD9540,00.html > > Is this the performance of the DDS, or just the jitter the device adds to > the reference clock? But nevertheless, a programmable delay line would be = a > nice idea for eliminating jitter, without the need for analog circuits. Th= e > required delay time could be calculated with the current accumulator value= > (the bits below the carry). > > > Happy New Year ! > > Thank you, the same to you! > > -- > Frank Buss, f...@frank-buss.dehttp://www.frank-buss.de,http://www.it4-syst= ems.de There are wonderful marketing methods for specifying jitter. Using "RMS" you can divide the "worst-case cycle-to-cycle jitter" value by a factor 14. And worst-case cycle-to-cycle jitter totally ignores the aspect of "wander". But also: Do not under-estimate the performance of a dedicated "cheap" chip. Have you looked at GPS receiver chips? Astounding ! Gru=DF Peter AlfkeArticle: 127536
On Jan 1, 2:40=A0pm, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > On Tue, 1 Jan 2008 12:07:17 -0800 (PST), Peter Alfke > > <al...@sbcglobal.net> wrote: > > >For the next-generation clock box (1 Hz to 1.5 GHz with ~50 ps > >jitter) > > 50 ps jitter at 1 Hz? That *is* a neat project! > > When can I buy one? I was considering getting one of the SRS clock > boxes, but yours might do. > > John Give us a few months. In the meantime, Stanford Research is a good choice. Amazingly cheap for a very complex traditional design. I'll pack almost everything into one Virtex-5 LXT part. Smaller, simpler and cheaper. PeterArticle: 127537
Peter Alfke <alfke@sbcglobal.net> writes: > Billions of cellphones, cameras, and iPods are being made, but where > can I buy a couple of hundred displays? http://www.sparkfun.com/ They don't have anything that meets your exact description, but they probably have something you can live with. The companies that make such displays don't even want to waste time talking to a potential customer if that party isn't likely to buy 100K units.Article: 127538
John Larkin wrote: > On Tue, 01 Jan 2008 14:04:19 -0600, "maxascent" > <maxascent@yahoo.co.uk> wrote: > >> Hi >> >> I am designing an 8 layer board with a Virtex 4 device on it. I will have >> 2 solid ground planes and 2 split power planes. If I have a signal plane >> that is between a ground and power plane will it matter if I cross a split >> on the power plane with a signal track. I know that you should not cross a >> split it in a plane if you are referencing to that plane. But if I have a >> solid ground plane beneath the track will it use this plane as its >> reference rather than the power plane. >> >> Cheers >> >> Jon > > No, it doesn't matter. The strange concept of "reference planes" is > irrelevent here... how does the signal know what plane you think it's > referenced to? > > If the power planes are bypassed well enough to make them reliable > power sources, then they are AC equipotential with the ground plane, > so the signal sees them all as ground. And a small slit in a power > plane is essentially invisible for edges slower than a few 10's of > picoseconds. > > John John, You're the only person who I won't directly challenge on your assertion because of your experience in producing quality products while confronting these types of issues directly. Suffice it to say that "today's common theory" suggests crossing the split in the specified case - like crossing any split - can be the root of crosstalk and EMI issues in addition to signal fidelity issues, just to a lesser extent than for signals on the outside layers. I'd love to be able to wrap my mind around how crossing this split wouldn't affect the signal in measurable ways, but the things I've been taught - my "faith" perhaps - suggests otherwise. I was once of a mind where crossing the split would be a non-issue but was brought over to the dark side with convincing arguments that tied in mith my more fundamental understanding of transmission line theory. - John_HArticle: 127539
Peter Alfke wrote: > For the next-generation clock box (1 Hz to 1.5 GHz with ~50 ps > jitter) > I need an LCD-backlit or OLED display, 128 x 64 bits, single or > multiple colors, about 2 inch diagonal. > OSRAM had a nice OLED display, but they went out of that business. > Billions of cellphones, cameras, and iPods are being made, but where > can I buy a couple of hundred displays? Digikey show 58, and over a dozen in stock. Highest stock one (also cheapest) shows 1,476 avail - would seem a good target ? but WHY do you need a 128x64 dot display, for a Clock generator ? Is there some driving (marketdroid?) need to display the Xilinx logo ;) For under half the price, you can get a nice 9.22mm H x 4.84mm W Char 16x2, with a nice large Viewing Area 99.00mm L x 23.00mm W -jgArticle: 127540
On Tue, 01 Jan 2008 17:41:14 -0800, John_H <newsgroup@johnhandwork.com> wrote: >John Larkin wrote: >> On Tue, 01 Jan 2008 14:04:19 -0600, "maxascent" >> <maxascent@yahoo.co.uk> wrote: >> >>> Hi >>> >>> I am designing an 8 layer board with a Virtex 4 device on it. I will have >>> 2 solid ground planes and 2 split power planes. If I have a signal plane >>> that is between a ground and power plane will it matter if I cross a split >>> on the power plane with a signal track. I know that you should not cross a >>> split it in a plane if you are referencing to that plane. But if I have a >>> solid ground plane beneath the track will it use this plane as its >>> reference rather than the power plane. >>> >>> Cheers >>> >>> Jon >> >> No, it doesn't matter. The strange concept of "reference planes" is >> irrelevent here... how does the signal know what plane you think it's >> referenced to? >> >> If the power planes are bypassed well enough to make them reliable >> power sources, then they are AC equipotential with the ground plane, >> so the signal sees them all as ground. And a small slit in a power >> plane is essentially invisible for edges slower than a few 10's of >> picoseconds. >> >> John > >John, > >You're the only person who I won't directly challenge on your assertion >because of your experience in producing quality products while >confronting these types of issues directly. > >Suffice it to say that "today's common theory" suggests crossing the >split in the specified case - like crossing any split - can be the root >of crosstalk and EMI issues in addition to signal fidelity issues, just >to a lesser extent than for signals on the outside layers. > >I'd love to be able to wrap my mind around how crossing this split >wouldn't affect the signal in measurable ways, but the things I've been >taught - my "faith" perhaps - suggests otherwise. I was once of a mind >where crossing the split would be a non-issue but was brought over to >the dark side with convincing arguments that tied in mith my more >fundamental understanding of transmission line theory. > >- John_H ground============================================================ signal------------------------------------------------------------ power ======================== ================================= whatever ======================================================== OK, there's a slit in the power plane. It's probably about as wide as a normal trace width, call it 8 mils. Let's say the plane-plane spacings are similar distances. Both halves of the split power plane are bypassed to the ground plane by real capacitors and by the considerable large-area plane-plane capacitance. In order for the trace impedance to change as the trace cruises over the gap, the potential in the middle of the gap would have to be non-zero. But the electric field from the signal trace can hardly penetrate through the gap... that's simple electrostatics. The signal sees uniform ground above, and a slightly lower dielectric constant below, in the gap region. That raises the trace impedance a tiny bit just above the gap, for a tiny distance. The "reference plane" issue is silly, as all the planes are at AC ground. I've built and TDR's such structures to better than 30 ps resolution. A reflection from such a gap is lost in the normal impedance noise, caused by thickness variations and the glass weave in the board. In the nanosecond domain, it's totally invisible. On a 2-sided board, a microstrip trace on one side and a cut ground plane on the other, signal----------------------------------- ground================== ============== a narrow slit in the ground plane is still a tiny impedance discontinuity on a TDR plot. All this "reference plane" stuff is ludicrous. It sure ain't "transmission line theory", it's folklore. JohnArticle: 127541
On Jan 1, 8:45=A0pm, -jg <Jim.Granvi...@gmail.com> wrote: > Peter Alfke wrote: > > For the next-generation clock box (1 Hz to 1.5 GHz with ~50 ps > > jitter) > > I need an LCD-backlit or OLED display, =A0128 x 64 bits, single or > > multiple colors, about 2 inch diagonal. > > OSRAM had a nice OLED display, but they went out of that business. > > Billions of cellphones, cameras, and iPods are being made, but where > > can I buy a couple of hundred displays? > > Digikey show 58, and over a dozen in stock. > Highest stock one (also cheapest) shows 1,476 avail - would seem a > good target ? > > but WHY do you need a 128x64 dot display, for a Clock generator ? > > Is there some driving (marketdroid?) need to display the Xilinx > logo ;) > > For under half the price, you can get a nice =A0 =A09.22mm H x 4.84mm W Ch= ar > 16x2, with a > nice large =A0Viewing Area =A0 =A0 =A0 =A099.00mm L x 23.00mm W > > -jg The original design had a non-backlit 16-character LCD for $4. Now I need twice as much, for 2 independent channels. Also, the crummy display distracted from the quality of the whole box. OLED seemed like a nice solution, but OSRAM went out of that business. 128 x 64 is a slight overkill, but the character generator is free in the Virtex-5, and it allows for some fancy GUI... "How you're gonna keep 'em down on the farm, after they've seen Paree ?" Peter AlfkeArticle: 127542
On Tue, 1 Jan 2008 15:54:06 -0800 (PST), Peter Alfke <alfke@sbcglobal.net> wrote: >Thanks, Frank, for the URL. I will investigate. A little pricey, but >not out of the question. > >Regarding the jitter, I can be more specific in a few weeks, when we >have the pre-production version (with the OSRAM display) really >working. Until now we have used various form of emulation. > >Yes, jitter is the overwhelming issue, and it is 1/fclock coming out >of the DDS accumulator, about 2 ns. >There is a lot of trickery involved to get the jitter down. The most >demanding chore is reducing "wander", i.e. low-frequency components in >the jitter spectrum that cannot be filtered out by any analog PLL, >but I think we are (almost) there. Are you planning to reduce the DDS jitter to sub-clock levels on-chip, or are you going to use an external dac-filter-comparator thing? The on-chip thing could get awfully interesting. Wander will of course depend on the phase noise of the external master clock. And fpga prop delays will stagger around with tiny temperature fluctuations. Adding thermal insulation and thermal mass to both the fpga and the xo can do remarkable things. We're getting under 30 ps RMS jitter+wander from a delay generator that uses a cheap xo and a Spartan3. A cheap xo will typically have a 1/f sort of jitter corner in the 500 Hz sort of ballpark, hitting a few ns RMS at 1 Hz. Somebody just quoted us on a 16x2 backlit alphanumeric lcd, 30 mm high, about $7 in small quantity. Do you really need graphics? JohnArticle: 127543
On Jan 1, 9:53=A0pm, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > On Tue, 1 Jan 2008 15:54:06 -0800 (PST), Peter Alfke > > <al...@sbcglobal.net> wrote: > >Thanks, Frank, for the URL. I will investigate. A little pricey, but > >not out of the question. > > >Regarding the jitter, I can be more specific in a few weeks, when we > >have the pre-production version (with the OSRAM display) really > >working. Until now we have used various form of emulation. > > >Yes, jitter is the overwhelming issue, and it is 1/fclock coming out > >of the DDS accumulator, about 2 ns. > >There is a lot of trickery involved to get the jitter down. The most > >demanding chore is reducing "wander", i.e. low-frequency components in > >the jitter spectrum that cannot be filtered out by any analog PLL, > >but I think we are (almost) there. > > Are you planning to reduce the DDS jitter to sub-clock levels on-chip, > or are you going to use an external dac-filter-comparator thing? > > The on-chip thing could get awfully interesting. > > Wander will of course depend on the phase noise of the external master > clock. And fpga prop delays will stagger around with tiny temperature > fluctuations. Adding thermal insulation and thermal mass to both the > fpga and the xo can do remarkable things. We're getting under 30 ps > RMS jitter+wander from a delay generator that uses a cheap xo and a > Spartan3. A cheap xo will typically have a 1/f sort of jitter corner > in the 500 Hz sort of ballpark, hitting a few ns RMS at 1 Hz. > > Somebody just quoted us on a 16x2 backlit alphanumeric lcd, 30 mm > high, about $7 in small quantity. Do you really need graphics? > > John John, please tell me more about that display. Graphics is just a nice luxury, but backlit or OLED is important. With "wander" I mean low-frequency jitter: Use a 500 MHz accumulator clock, then use DDS to generate 100.000 001 MHz. There is no way any PLL can completely even out the once-a-second period change. I picked an extreme example, but there are many simpler cases. I was not referring to any instability in the time-base xtal oscillator. That would be on top. Anyhow, I am glad I asked the original question. I got several good leads. And seem to have created some interest...All on a holiday! Thanks, guys ! PeterArticle: 127544
-jg <Jim.Granville@gmail.com> writes: > but WHY do you need a 128x64 dot display, for a Clock generator ? I don't know about the OP, but in my projects, dot matrix means that you can have a "big font" mode and a regular font mode. It also allows more flexible icons. http://www.delorie.com/house/furnace/therm-front.html http://www.delorie.com/electronics/alarmclock/20070911-sim1.html http://www.delorie.com/electronics/alarmclock/20070911-sim2.htmlArticle: 127545
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:fh7mn3pl84g9ccugdov2vml0nfg3f8le45@4ax.com... > All this "reference plane" stuff is ludicrous. It sure ain't > "transmission line theory", it's folklore. It's aimed at getting people to not use *large* slits in their ground planes that *could* turn into significant problems. And you can certainly run simulations and show that -- if you choose a low enough frequency -- current will divert around the slit, like Howard and friends like to draw diagrams of in their books. The problem is that once everyone nods their heads up and down that, ok, sure, slits in the plane affect what happens electromagnetically, where many people (include me) get off-track in their thinking is in overestimating the detrimental impact of a small slit here or there, when in acutality even significant impedance bumps (say, +/-20% of "nominal" --> 50 ohms nomial going to ~40-60 ohms) of "reasonable" electrical length just don't perturb signals much at all. If they did, simple things like connectors would start becoming Big Deals down in the MHz range rather than the some- to many-GHz range where they usually do. That being said, I've observed co-workers trying to do things like obtain 60dB isolation at 3GHz on regular old FR-4 circuit boards, and it's not trivial. Without careful design, it's easy to get only, say, 40dB isolation between two traces, even though that's just a *miniscule* amount of energy loss than you're never going to miss it from the original transmitted signal. This is the angle the EMI guys are coming from: While here-a-slit, there-a-slit isn't going to significantly alter your transmitted signal one bit (i.e., your box will still work fine), it can easily cause you to fail EMI testing if you're not careful to make sure those 40-60dB down "sneak" paths never make it out of the box. I did hear a lecture from one guy who mentioned that if you already have bad enough self-interference (e.g., ground bounce and crosstalk) that your box doesn't work as intended, don't even bother doing an EMI test -- you're already guaranteed to fail. :-) Have you ever measured the isolation between output channels on your function generators, John? I'd be curious to know the results... :-) ---JoelArticle: 127546
> The original design had a non-backlit 16-character LCD for $4. > Now I need twice as much, for 2 independent channels. So is 16x2 enough ? > Also, the crummy display distracted from the quality of the whole box. > OLED seemed like a nice solution, but OSRAM went out of that business. > 128 x 64 is a slight overkill, but the character generator is free in > the Virtex-5, > and it allows for some fancy GUI... You could maybe do a Spartan model with the large font 16x 2 I suggested (large chars are much better than smaller ones... ) and a Virtex model, with the FLASH driver, and Animated Xilinx logo reveal, (with full sound effects, too, of course...) etc etc... What specs would a modern Spartan run to ? -jgArticle: 127547
Symon wrote: > "maxascent" <maxascent@yahoo.co.uk> wrote in message > news:xfKdnTDf__teAefaRVn_vwA@giganews.com... >>I am designing an 8 layer board with a Virtex 4 device on it. I will have >>2 solid ground planes and 2 split power planes. If I have a signal plane >>that is between a ground and power plane will it matter if I cross a split >>on the power plane with a signal track. I know that you should not cross a >>split it in a plane if you are referencing to that plane. But if I have a >>solid ground plane beneath the track will it use this plane as its >>reference rather than the power plane. The current in the two will be proportional to the capacitance (per unit length), which will depend on the dielectric constant and thickness of the dielectric. > There will be an impedance discontinuity at the split. Well, the impedance is the same on both sides, but getting the current where it is needs to go is the problem. As someone else mentioned, bypass capacitors will help. You could put a capacitor across the split between the two power planes. Capacitors to ground from each side should also work. As someone else mentioned, the capacitance of the power plane itself might be enough. > The magnitude of this > and whether it matters to your design will depend on the geometry of the > stack up and signals; also the rise time of the signals. Why not put the > powers on layers 4,5 and make 3 and 6 ground. Then you won't have this > problem. The impedance will be higher, but otherwise it should work. -- glenArticle: 127548
On Tue, 1 Jan 2008 17:28:39 -0800 (PST), Peter Alfke <alfke@sbcglobal.net> wrote: >On Jan 1, 2:40 pm, John Larkin ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> On Tue, 1 Jan 2008 12:07:17 -0800 (PST), Peter Alfke >> >> <al...@sbcglobal.net> wrote: >> >> >For the next-generation clock box (1 Hz to 1.5 GHz with ~50 ps >> >jitter) >> >> 50 ps jitter at 1 Hz? That *is* a neat project! >> >> When can I buy one? I was considering getting one of the SRS clock >> boxes, but yours might do. >> >> John > >Give us a few months. In the meantime, Stanford Research is a good >choice. >Amazingly cheap for a very complex traditional design. >I'll pack almost everything into one Virtex-5 LXT part. Smaller, >simpler and cheaper. Does LXT imply that you are using the transceiver outputs to generate a high effective sample frequency? Thanks, AllanArticle: 127549
"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:fh7mn3pl84g9ccugdov2vml0nfg3f8le45@4ax.com... > > In order for the trace impedance to change as the trace cruises over > the gap, the potential in the middle of the gap would have to be > non-zero. But the electric field from the signal trace can hardly > penetrate through the gap... that's simple electrostatics. The signal > sees uniform ground above, and a slightly lower dielectric constant > below, in the gap region. That raises the trace impedance a tiny bit > just above the gap, for a tiny distance. The "reference plane" issue > is silly, as all the planes are at AC ground. > Hi John, I contend that the flaw in your thinking is that you are _only_ considering "electrostatics", i.e. the electric field and associated capacitance of the system. If you only understand voltage and capacitance, the slot is not a problem for you. In fact, by the reasoning you follow above, a big slot in both planes wouldn't be a problem, and I think this is what you're saying. Unfortunately, back in the real world, it's called electromagnetism. The magnetic field is important in these systems. The slit will affect the system, changing the loop area for the currents flowing, and the faster the rise time, the more effect you will see due to this added inductance. The effect may or may not be important, but what is important is to consider it. I'm gonna try this again. I think you do accept that current flows along the trace, so where does the return current flow? Here's a clue. It's in the planes. So, the current is flowing in a loop, right? And a loop has inductance, right? And a big slot in the plane will make the loop area bigger, right? And a bigger area loop has more inductance, right? However, the two of us have been here before, and I know you don't believe this. I'm posting for the benefit of others who might be caught out by ignoring the magnetic field set up by the currents in the planes and traces so they can make up their own minds. (I suggest SI-list for further reading) Up until recently, regular FPGA I/O circuits were not quick enough for this to be a big problem, but they will be for everyone soon. Maybe not today. Maybe not tomorrow, but soon and for the rest of your life! I know this won't help, Syms. p.s. I agree, having a slot in only one plane is nowhere near the same as a slot in both. Here's a link for why a single reference plane with a slot is bad. It's easy to see that another plane can all but short out the return current. http://www.hottconsultants.com/techtips/tips-slots.html
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