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Threads Starting Feb 1999
14481: 99/02/01: Samer EL HAJJ: FPGA Express Evaluation...
14495: 99/02/01: Bruce Nepple: Re: FPGA Express Evaluation...
14503: 99/02/02: Jim King: Re: FPGA Express Evaluation...
14522: 99/02/03: Matthias Brucke: Re: FPGA Express Evaluation...
14488: 99/02/01: Bin Fang: SPWM model needed
14499: 99/02/01: Barry Chu: Need Help! clock multiplier!
14538: 99/02/03: <ems@riverside-machines.com.NOSPAM>: Re: Need Help! clock multiplier!
14545: 99/02/04: Markus Michel: Re: Need Help! clock multiplier!
14664: 99/02/09: Lev Razamat: Re: Need Help! clock multiplier!
14506: 99/02/02: Robert Myers: Opinions requested : Minc/Synario alternatives
14508: 99/02/02: Randy Robinson: Re: Opinions requested : Minc/Synario alternatives
14514: 99/02/02: Steve Dewey: Re: Opinions requested : Minc/Synario alternatives
14544: 99/02/04: Jonathan Bromley: Re: Opinions requested : Minc/Synario alternatives
14546: 99/02/04: <peter.trott@vantis.com>: Re: Opinions requested : Minc/Synario alternatives
14552: 99/02/04: Bob Myers: Re: Opinions requested : Minc/Synario alternatives
14572: 99/02/04: Kevin Jennings: Re: Opinions requested : Minc/Synario alternatives
14706: 99/02/12: <milostnik@my-dejanews.com>: Re: Opinions requested : Minc/Synario alternatives
14779: 99/02/16: Nick: Re: Opinions requested : Minc/Synario alternatives
14509: 99/02/02: <lisa_crawford@cmagroup.com>: Job: New York; Senior Engineer; FPGA, Imaging, Video
14524: 99/02/03: David Pashley: ANNOUNCE: Technical seminar on IP Integration (UK)
14525: 99/02/03: Gerd Beil: Q:EEPROM for Xilinx XC4k
14528: 99/02/03: Tom Burgess: Re: Q:EEPROM for Xilinx XC4k
14740: 99/02/14: Alex Rast: Re: Q:EEPROM for Xilinx XC4k
14536: 99/02/03: Mark Korsloot: Re: Q:EEPROM for Xilinx XC4k
14661: 99/02/09: Steven K. Knapp: Re: Q:EEPROM for Xilinx XC4k
14529: 99/02/03: Marty Stan: Contract Job: Boston; Xilinx, FPGA; ATM
14530: 99/02/03: Celeritous: VHDL clocked one-shot Implementation Problem
14531: 99/02/03: Jamie Sanderson: Re: VHDL clocked one-shot Implementation Problem
14566: 99/02/04: Hans Lindkvist: Re: VHDL clocked one-shot Implementation Problem
14581: 99/02/04: Celeritous: Re: VHDL clocked one-shot Implementation Problem
14534: 99/02/03: Richard Iachetta: Re: VHDL clocked one-shot Implementation Problem
14579: 99/02/04: Bruce Nepple: Re: VHDL clocked one-shot Implementation Problem
14540: 99/02/03: Mitch Thornton: CFP: =?iso-8859-1?Q?Reed=2DM=FCller?= Workshop RM99
14541: 99/02/04: <grcook@my-dejanews.com>: ASIC or Digital Board Design in the UK - choice?
14585: 99/02/05: John: Re: ASIC or Digital Board Design in the UK - choice?
14547: 99/02/04: Martin van Eersel: PCI based development board?
14558: 99/02/04: Steven K. Knapp: Re: PCI based development board?
14548: 99/02/04: Lars Fomsgaard: VHDL problem (Xilinx-problem)
14550: 99/02/04: Lasse Langwadt Christensen: Re: VHDL problem (Xilinx-problem)
14573: 99/02/04: Bruce Nepple: Re: VHDL problem (Xilinx-problem)
14554: 99/02/04: Brian Boorman: Re: VHDL problem (Xilinx-problem)
14556: 99/02/04: Markus Michel: Re: VHDL problem (Xilinx-problem)
14559: 99/02/04: David Kessner: Re: VHDL problem (Xilinx-problem)
14564: 99/02/04: <mench@mench.com>: Re: VHDL problem (Xilinx-problem)
14570: 99/02/04: Lasse Langwadt Christensen: Re: VHDL problem (Xilinx-problem)
14583: 99/02/05: Lars Fomsgaard: Re: VHDL problem (Xilinx-problem)
14555: 99/02/04: Matthias D. Kistler: DES in VHDL for FPGAs
14582: 99/02/04: David G. Koontz: Re: DES in VHDL for FPGAs
14594: 99/02/05: Christof Paar: Re: DES in VHDL for FPGAs
14632: 99/02/07: Chris Eilbeck: Re: DES in VHDL for FPGAs
14563: 99/02/04: <kfalser@durst.it>: Timing Simulation and Foundation
14565: 99/02/04: Fadi Sibai: Call for Papers - PERH'99
14567: 99/02/04: <Benjamin_Boicourt@css.mot.com>: career
14644: 99/02/08: Wendy Lockhart: career
14568: 99/02/04: Asawaree Kalavade: Synplify/Xilinx4085XLA question
14574: 99/02/04: Brian Boorman: Re: Synplify/Xilinx4085XLA question
14575: 99/02/04: Randy Robinson: Re: Synplify/Xilinx4085XLA question
14589: 99/02/05: Brian Boorman: Re: Synplify/Xilinx4085XLA question
14604: 99/02/06: Matt Bielstein: Re: Synplify/Xilinx4085XLA question
14616: 99/02/06: Edward Moore: Re: Synplify/Xilinx4085XLA question
14569: 99/02/04: <rajesh52@hotmail.com>: Re: Verilog ROM Models
14571: 99/02/04: <cbkohw@penis.nl>: _____FAQ list for this newsgroup_____ 8899
14576: 99/02/05: Lars Freund: can I trust Altera Simulator?
14586: 99/02/05: James Kellar: Re: can I trust Altera Simulator?
14593: 99/02/05: Lars Freund: Re: can I trust Altera Simulator?
14590: 99/02/05: Brian Boorman: Re: can I trust Altera Simulator?
14728: 99/02/12: Nick: Re: can I trust Altera Simulator?
14580: 99/02/05: <VAX>: Re: Timing Simulation and Foundation
14588: 99/02/05: <okmbsi@faqlist.be>: _____FAQ for this NEWSGROUP_____ 2269
14592: 99/02/05: Soren Kristensen: Lattice ispLSI 2000V opendrain problem.
14595: 99/02/05: <eonxvt@faqlist.net>: _____FAQ update for this newsgroup_____ 3732
14597: 99/02/05: Eduardo Augusto Bezerra: VHDL synthesis
14615: 99/02/06: <ems@riverside-machines.com.NOSPAM>: Re: VHDL synthesis
14624: 99/02/06: Brian Boorman: Re: VHDL synthesis
14625: 99/02/07: Eduardo Augusto Bezerra: Re: VHDL synthesis
14633: 99/02/07: Eduardo Augusto Bezerra: Re: VHDL synthesis
14598: 99/02/05: Evan Speight: Place and Route Times question
14601: 99/02/06: Hamish Moffatt: dual port RAM on XC4000
14608: 99/02/06: Koenraad Schelfhout: Re: dual port RAM on XC4000
14609: 99/02/06: Hamish Moffatt: Re: dual port RAM on XC4000
14621: 99/02/06: Brian Drummond: Re: dual port RAM on XC4000
14629: 99/02/07: Hamish Moffatt: Re: dual port RAM on XC4000
14643: 99/02/08: Brian Drummond: Re: dual port RAM on XC4000
14637: 99/02/07: Peter Alfke: Re: dual port RAM on XC4000
14642: 99/02/08: Brian Drummond: Re: dual port RAM on XC4000
14650: 99/02/08: Peter Alfke: Re: dual port RAM on XC4000
14658: 99/02/09: Manfred Kraus: Re: dual port RAM on XC4000
14662: 99/02/09: Peter Alfke: Re: dual port RAM on XC4000
14670: 99/02/10: Brian Drummond: Re: dual port RAM on XC4000
14627: 99/02/07: Austin Franklin: Re: dual port RAM on XC4000
14630: 99/02/07: Hamish Moffatt: Re: dual port RAM on XC4000
14631: 99/02/07: Alexander Sherstuk: RE: dual port RAM on XC4000
14638: 99/02/08: Austin Franklin: Re: dual port RAM on XC4000
14603: 99/02/05: Endric Schubert: routability of FPGA - is this an issue?
14620: 99/02/06: Ray Andraka: Re: routability of FPGA - is this an issue?
14645: 99/02/08: Endric Schubert: Re: routability of FPGA - is this an issue?
14646: 99/02/08: Ray Andraka: Re: routability of FPGA - is this an issue?
14607: 99/02/05: handi: Fpga Express and Xilinx Alliance1.5 questions
14610: 99/02/06: Scott Paul Johnston: NEW ENGINEERING PAGE: Please Visit
14622: 99/02/06: John Larkin: Xilinx de-compiler
14623: 99/02/06: Your Name: Re: Xilinx de-compiler
14628: 99/02/07: John Larkin: Thank You
14635: 99/02/07: Lasse Langwadt Christensen: Re: Xilinx de-compiler
14636: 99/02/07: John Larkin: Re: Xilinx de-compiler
14641: 99/02/08: Brian Boorman: Re: Xilinx de-compiler
14669: 99/02/10: Sergio A. Cuenca Asensi: Re: Xilinx de-compiler
14685: 99/02/11: David Kessner: Re: Xilinx de-compiler
14690: 99/02/11: Peter: Re: Xilinx de-compiler
14704: 99/02/12: Achim Gratz: Re: Xilinx de-compiler
14715: 99/02/12: <timolmst@cyberramp.net>: Re: Xilinx de-compiler
14751: 99/02/15: Achim Gratz: Re: Xilinx de-compiler
14781: 99/02/16: Nick: Re: Xilinx de-compiler
14743: 99/02/14: <jelle@bang.zap>: Re: Xilinx de-compiler
14780: 99/02/16: Nick: Re: Xilinx de-compiler
14895: 99/02/23: Ian McLaren: Re: Xilinx de-compiler
14900: 99/02/24: Cameron Watt: Re: Xilinx de-compiler
14626: 99/02/06: Sanjeev: Board for XC4085XL
14659: 99/02/09: Apinetr Unakul: Re: Board for XC4085XL
14667: 99/02/10: Matthias Brucke: Re: Board for XC4085XL
14737: 99/02/13: APS: Re: Board for XC4085XL
14660: 99/02/09: Steven K. Knapp: Re: Board for XC4085XL
14668: 99/02/10: Bill: Re: Board for XC4085XL
14703: 99/02/12: Malki: Re: Board for XC4085XL
14736: 99/02/13: APS: Re: Board for XC4085XL
14634: 99/02/07: Sanjeev: Board for XC4085XL?
14639: 99/02/08: Hamish Moffatt: xc4000 obselete to xc4000e
14640: 99/02/08: John Chambers: PLX9050 Dev. Software
14674: 99/02/10: Thomas Ebert: Re: PLX9050 Dev. Software
14869: 99/02/22: Iain Rankin: Re: PLX9050 Dev. Software
14647: 99/02/08: Stephen Swearingen: Contract Job in Boston
14648: 99/02/08: Stephen Swearingen: Contract Job in Boston II
14649: 99/02/08: T. Franklin: comp.arch.fpga Archives
14754: 99/02/15: Markus Wannemacher: Re: comp.arch.fpga Archives
14761: 99/02/15: Steven K. Knapp: Re: comp.arch.fpga Archives
14655: 99/02/09: Soha Hassoun: Ph.D. Forum at DAC: Announcement & First Call for participation
14663: 99/02/09: Lev Razamat: Re: AHDL & VHDL
14665: 99/02/09: GOVJOBS.COM: FPGA - Ground Unit Design Engineering
14666: 99/02/09: ali Benkhalil: AHDL & VHDL
14726: 99/02/12: Nick: Re: AHDL & VHDL
14772: 99/02/16: ali Benkhalil: Re: AHDL & VHDL
14671: 99/02/10: Farhad Abdolian: Q: How to add contstraints in synopsys->Xilinx?
14738: 99/02/13: APS: Re: Q: How to add contstraints in synopsys->Xilinx?
14672: 99/02/10: Steven K. Knapp: Visit The Programmable Logic Jump Station (www.optimagic.com)
14673: 99/02/10: Thomas Ebert: Altera freecore library ?
14682: 99/02/11: "Håkan Pettersson": Altera freecore library ?
14684: 99/02/11: Steven K. Knapp: Re: Altera freecore library ?
14694: 99/02/12: Rune Baeverrud: Re: Altera freecore library ?
14881: 99/02/22: Frank A. Vorstenbosch: Re: Altera freecore library ?
14675: 99/02/10: Arrigo Benedetti: Supercomputer uses 280 Xilinx FPGAs
14676: 99/02/10: Don Husby: Re: Supercomputer uses 280 Xilinx FPGAs
14677: 99/02/10: Stefan Ludwig: Re: Supercomputer uses 280 Xilinx FPGAs
14683: 99/02/11: Achim Gratz: Re: Supercomputer uses 280 Xilinx FPGAs
14722: 99/02/12: Guy Gerard Lemieux: Re: Supercomputer uses 280 Xilinx FPGAs
14729: 99/02/13: Reiner Hartenstein: Re: Supercomputer uses 280 Xilinx FPGAs
14730: 99/02/13: Hans: Re: Supercomputer uses 280 Xilinx FPGAs
14679: 99/02/11: John Huang: Current of I/O driver
14686: 99/02/11: jerry english: Re: Current of I/O driver
14693: 99/02/11: Brad Taylor: Re: Current of I/O driver
14680: 99/02/11: Thomas Zipper: Parity and flex10k
14699: 99/02/11: Ray Andraka: Re: Parity and flex10k
14723: 99/02/12: Guy Gerard Lemieux: Re: Parity and flex10k
14681: 99/02/11: Thomas Ebert: Q: PCMCIA Interface For ALTERA
14687: 99/02/11: <m-gupta@nwu.edu>: Mentor-Alliance Interface
14688: 99/02/11: GOVJOBS.COM: FPGA - Ground Unit Design Engineering
14689: 99/02/11: Carlhermann Schlehaus: JTAG Test fuer FPGA
14692: 99/02/11: GOVJOBS.COM: GOVJOBS.COM - JOB BANK - private sector opportunities in high-technologies only!
14695: 99/02/12: Walt Bax: reconfiguring Logiblox ROM's
14700: 99/02/11: Ray Andraka: Re: reconfiguring Logiblox ROM's
14707: 99/02/12: jamie morken: Re: reconfiguring Logiblox ROM's
14713: 99/02/12: Ray Andraka: Re: reconfiguring Logiblox ROM's
14697: 99/02/11: Jason Lohn: 2nd CFP: THE FIRST NASA/DoD WORKSHOP ON EVOLVABLE HARDWARE
14698: 99/02/12: ÀÓÀçȯ: help to look for VHDL source related with PCI.
14701: 99/02/11: John Abt: HDTV SMPTE 292 FPGA Parallel de-scrambler
14702: 99/02/12: <mathai@ecf.toronto.edu>: asyncronous finite state machines on FPGAs?
14712: 99/02/12: Ray Andraka: Re: asyncronous finite state machines on FPGAs?
14705: 99/02/12: Utku Ozcan: Very Long Write Enable in Xilinx Dual Port RAMs
14709: 99/02/12: Philip Freidin: Re: Very Long Write Enable in Xilinx Dual Port RAMs
14710: 99/02/12: Alexander Sherstuk: RE: Very Long Write Enable in Xilinx Dual Port RAMs
14720: 99/02/12: Tom Burgess: Re: Very Long Write Enable in Xilinx Dual Port RAMs
14724: 99/02/12: Peter Alfke: Re: Very Long Write Enable in Xilinx Dual Port RAMs
14708: 99/02/12: jamie morken: XC6200 series
14711: 99/02/12: Hamish Moffatt: M1 error message
14714: 99/02/12: Hamish Moffatt: Re: M1 error message
14756: 99/02/15: Bob Sefton: Re: M1 error message
14716: 99/02/12: GOVJOBS.COM: FPGA - Ground Unit Design Engineering
14717: 99/02/12: GOVJOBS.COM: FPGA - Digital Flight Unit Design Engineering
14718: 99/02/12: GOVJOBS.COM: FPGA - Digital Flight Unit Design Engineering
14719: 99/02/12: GOVJOBS.COM: Communications Systems Engineering
14721: 99/02/12: Tximo: Problems with Xilinx F1.5 & latchs
14725: 99/02/13: Wiggo Olufsen: Re: Problems with Xilinx F1.5 & latchs
14750: 99/02/14: <ems@riverside-machines.com.NOSPAM>: Re: Problems with Xilinx F1.5 & latchs
14758: 99/02/15: Bob Sefton: Re: Problems with Xilinx F1.5 & latchs
14760: 99/02/15: Tximo: Re: Problems with Xilinx F1.5 & latchs
14731: 99/02/13: Hamish Moffatt: M1 problems with TDO pin
14732: 99/02/13: Eduardo Augusto Bezerra: Synplify resource usage report for Virtex devices
14741: 99/02/14: Utku Ozcan: Re: Synplify resource usage report for Virtex devices
14766: 99/02/16: Eduardo Augusto Bezerra: Re: Synplify resource usage report for Virtex devices
14746: 99/02/14: Philip Freidin: Re: Synplify resource usage report for Virtex devices
14767: 99/02/16: Eduardo Augusto Bezerra: Re: Synplify resource usage report for Virtex devices
14785: 99/02/17: David Decker: Re: Synplify resource usage report for Virtex devices
14786: 99/02/17: Philip Freidin: Re: Synplify resource usage report for Virtex devices
14790: 99/02/17: Eduardo Augusto Bezerra: Re: Synplify resource usage report for Virtex devices
14813: 99/02/18: Brian Drummond: Re: Synplify resource usage report for Virtex devices
14814: 99/02/18: Andrew Brown: Re: Synplify resource usage report for Virtex devices
14733: 99/02/13: Luis de Funes: cpld internal oscillator
14735: 99/02/13: APS: Derived Clocks and Clock enables in XILINX parts
14742: 99/02/14: Brian Drummond: Re: Derived Clocks and Clock enables in XILINX parts
14749: 99/02/14: <ems@riverside-machines.com.NOSPAM>: Re: Derived Clocks and Clock enables in XILINX parts
14739: 99/02/14: SArmitage: Lucent Orca $95 design tools
14744: 99/02/14: <Fremont>: EEProm erasing?
14745: 99/02/14: Thomas A. Coonan: Re: EEProm erasing?
14747: 99/02/14: Simon: Re: EEProm erasing?
14748: 99/02/14: Jeff Hunsinger: Xilinx Foundation Base = Useless?
14778: 99/02/16: Jaroslaw Kaczynski: Re: Xilinx Foundation Base = Useless?
14783: 99/02/16: Jeff Hunsinger: Re: Xilinx Foundation Base = Useless?
14752: 99/02/15: Sergio A. Cuenca Asensi: xnf de-compiler
14771: 99/02/16: Bruce Nepple: Re: xnf de-compiler
14789: 99/02/17: Craig Slorach: Re: xnf de-compiler
14777: 99/02/16: Ray Andraka: Re: xnf de-compiler
14753: 99/02/15: Stuart J Adams: Xilinx Spartan and pin-locking
14759: 99/02/15: Austin Franklin: Re: Xilinx Spartan and pin-locking
14782: 99/02/17: <ibaggett@bagotronix.com>: Re: Xilinx Spartan and pin-locking
14791: 99/02/17: Ray Andraka: Re: Xilinx Spartan and pin-locking
14792: 99/02/17: Austin Franklin: Re: Xilinx Spartan and pin-locking
14807: 99/02/18: Hal Murray: Re: Xilinx Spartan and pin-locking
14820: 99/02/18: Philip Freidin: Re: Xilinx Spartan and pin-locking
14788: 99/02/17: Keith Wootten: Re: Xilinx Spartan and pin-locking
14762: 99/02/15: Steve: Re: Xilinx Spartan and pin-locking
14755: 99/02/15: Jan Gray: FPGA array computers
14757: 99/02/15: <rajesh52@hotmail.com>: Verilog FAQ
14763: 99/02/16: moshe moalem: orcad
14764: 99/02/15: Steve: Re: orcad
14774: 99/02/16: bob elkind: Re: orcad
14775: 99/02/16: Steve: Re: orcad
14765: 99/02/16: Richard Hogers: Anyone experience with Aptix?
14793: 99/02/17: <edwinpark@my-dejanews.com>: Re: Anyone experience with Aptix?
14768: 99/02/16: Sagaert Johan: Any FREE soft for XC5000 series ?
14769: 99/02/16: <rajesh52@hotmail.com>: Verilog FAQ
14770: 99/02/16: Anthony Ellis - LogicWorks: Flex6016 config. problem.
14773: 99/02/16: Pascal Dornier: Re: Flex6016 config. problem.
14784: 99/02/17: Philip Freidin: Re: Flex6016 config. problem.
14802: 99/02/17: Carlhermann Schlehaus: Re: Flex6016 config. problem.
14822: 99/02/18: Philip Freidin: Re: Flex6016 config. problem.
14787: 99/02/17: J. Khatib: Free circuit design
14798: 99/02/17: Sander Vesik: Re: Free circuit design
14810: 99/02/18: Sander Vesik: Re: Free circuit design
14806: 99/02/18: Geir Harris Hedemark: Re: Free circuit design
14809: 99/02/18: Thomas Reinemann: Re: Free circuit design
14867: 99/02/21: Rainer Dorsch: Re: Free circuit design
14794: 99/02/17: <schaltung@hotmail.com>: Digital PLL
14797: 99/02/17: Peter Alfke: Re: Digital PLL
14800: 99/02/17: Wiggo Olufsen: Re: Digital PLL
14811: 99/02/18: Jeff Streznetcky: Re: Digital PLL
14795: 99/02/17: Paul Baxter: Re: "Altera FreeCore Library" back on the web
14801: 99/02/17: Carlhermann Schlehaus: Re: "Altera FreeCore Library" back on the web
14817: 99/02/18: Andy Peters: Re: "Altera FreeCore Library" back on the web
14851: 99/02/20: Hamish Moffatt: Re: "Altera FreeCore Library" back on the web
14796: 99/02/17: <edwinpark@my-dejanews.com>: P&R times for Altera10K200E and Virtex
14821: 99/02/18: Philip Freidin: Re: P&R times for Altera10K200E and Virtex
14839: 99/02/19: Jamie Lokier: Re: P&R times for Altera10K200E and Virtex
14844: 99/02/19: Ray Andraka: Re: P&R times for Altera10K200E and Virtex
14860: 99/02/20: Jamie Lokier: Re: P&R times for Altera10K200E and Virtex
14825: 99/02/18: Edwin Grigorian: Re: P&R times for Altera10K200E and Virtex
14826: 99/02/18: Edwin Grigorian: Re: P&R times for Altera10K200E and Virtex
14837: 99/02/19: Andres David Garcia Garcia: Re: P&R times for Altera10K200E and Virtex
14799: 99/02/17: EKC: Xilinx Foundation V1.5
14827: 99/02/19: Cameron Watt: Re: Xilinx Foundation V1.5
14803: 99/02/17: Rune Baeverrud: "Altera FreeCore Library" back on the web
14808: 99/02/18: Achim Gratz: Re: "Altera FreeCore Library" back on the web
14804: 99/02/17: HDL Conference: Announcing HDL Conference
14805: 99/02/17: muzo: virtex vs apex ?
14880: 99/02/22: Nick: Re: virtex vs apex ?
14812: 99/02/18: jamie morken: four signals into array?
14815: 99/02/18: Brian Dam Pedersen: Re: four signals into array?
14824: 99/02/18: Lasse Langwadt Christensen: Re: four signals into array?
14818: 99/02/18: Zhen Luo: edge-triggered registers on Xilinx 4000e.
14823: 99/02/18: Alex V. Sherstuk: Re: edge-triggered registers on Xilinx 4000e.
14819: 99/02/18: Vaughn Betz: Packing, Placement and Routing Tools for Academic FPGA Research
14828: 99/02/18: Rinzai Bell: Xilinx Programming via a Processor
14835: 99/02/19: Rudolf Mühlenbein: Re: Xilinx Programming via a Processor
14829: 99/02/19: Utku Ozcan: multiple clock domain problem
14833: 99/02/19: Jamie Sanderson: Re: multiple clock domain problem
14842: 99/02/19: <frannhagen@my-dejanews.com>: Re: multiple clock domain problem
14853: 99/02/20: <ems@riverside-machines.com.NOSPAM>: Re: multiple clock domain problem
14852: 99/02/20: <ems@riverside-machines.com.NOSPAM>: Re: multiple clock domain problem
14854: 99/02/20: Utku Ozcan: Re: multiple clock domain problem
14855: 99/02/20: Utku Ozcan: Re: multiple clock domain problem
14856: 99/02/20: <ems@riverside-machines.com.NOSPAM>: Re: multiple clock domain problem
14857: 99/02/20: Utku Ozcan: Re: multiple clock domain problem
14861: 99/02/20: Ken McElvain: Re: multiple clock domain problem
14858: 99/02/20: Bob Perlman: Re: multiple clock domain problem
14862: 99/02/21: Jonas Thor: Re: multiple clock domain problem
14830: 99/02/19: Hul Tytus: Just Texting
14831: 99/02/19: Hul Tytus: just testing
14832: 99/02/19: ggg fff: testing, just testing
14834: 99/02/19: <apodgorny@my-dejanews.com>: DPLL&ADPLL tutorials needed.
14836: 99/02/19: Andres David Garcia Garcia: Power estimation on FLEX10K applications
14838: 99/02/19: <idr@iss-dsp.com>: Jobs in Silicon DSP IP - any takers?
14840: 99/02/19: ReginaHT: US-CA jobs/ASIC-SCSI engineer
14841: 99/02/19: John Larkin: Xilinx config from MC68332
14843: 99/02/19: Andy Peters: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
14846: 99/02/19: Andy Peters: Re: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
14872: 99/02/22: Darrin Nagy: Re: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
14879: 99/02/22: Andy Peters: Re: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
14882: 99/02/22: Andy Peters: Re: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
14894: 99/02/23: <ems@riverside-machines.com.NOSPAM>: Re: Inferring IOFFs with FPGA Express 3.x and Foundation 1.5i
14845: 99/02/19: John Schewel: Final CP Reconfigurable Technology: FPGAs for Computing and Applications
14847: 99/02/19: jamie morken: Re: four signals into array?
14848: 99/02/19: jamie morken: variable assignment in process or outside of process
14849: 99/02/20: Jonas Thor: Anyone done any GPS designs?
14850: 99/02/20: Tyrone Thompson: Bus Interface
14940: 99/02/25: Joe Bender: Bus Interface
14859: 99/02/20: rk: pcb design costs
14863: 99/02/21: wong ying: Free Tool For FPGA ??
14864: 99/02/21: Krzycho: Eval Activ-VHDL only for 30 day :(
14868: 99/02/22: mw: Re: Eval Activ-VHDL only for 30 day :(
14873: 99/02/22: Krzycho: Re: Eval Activ-VHDL only for 30 day :(
14871: 99/02/22: Cameron Watt: Re: Eval Activ-VHDL only for 30 day :(
14874: 99/02/22: Krzycho: Re: Eval Activ-VHDL only for 30 day :(
14877: 99/02/22: Gary Seely: Re: Eval Activ-VHDL only for 30 day :(
14865: 99/02/21: <bmathew@hotmail.com>: Under-clocking SDRAM
14994: 99/03/02: Tim Hubberstey: Re: Under-clocking SDRAM
14866: 99/02/21: Leprechaun: connecting 2 FPGA
14875: 99/02/22: Steve: Re: connecting 2 FPGA
14870: 99/02/22: Daryl Bradley: Xilinx Virtex
14898: 99/02/24: mark: Re: Xilinx Virtex
14932: 99/02/25: Ray Andraka: Re: Xilinx Virtex
14876: 99/02/22: Marty Stan: Houston - Need FPGA Work
14878: 99/02/22: Sergio A. Cuenca Asensi: Problem with xilinx M1
14885: 99/02/23: Philip Freidin: Re: Problem with xilinx M1
14887: 99/02/23: Sergio A. Cuenca Asensi: Re: Problem with xilinx M1
14890: 99/02/23: Jonas Thor: Re: Problem with xilinx M1
14943: 99/02/26: Sergio A. Cuenca Asensi: Re: Problem with xilinx M1
14896: 99/02/23: Andy Peters: Re: Problem with xilinx M1
14945: 99/02/26: Sergio A. Cuenca Asensi: Re: Problem with xilinx M1
14960: 99/02/27: Andy Peters: Re: Problem with xilinx M1
14968: 99/03/01: Sergio A. Cuenca Asensi: Re: Problem with xilinx M1
14983: 99/03/01: Andy Peters: Re: Problem with xilinx M1
14984: 99/03/01: Hobson Frater: Re: Problem with xilinx M1
14997: 99/03/02: Sergio A. Cuenca Asensi: Re: Problem with xilinx M1
15092: 99/03/05: Brian Boorman: Re: Problem with xilinx M1
14888: 99/02/23: <tryggvem@my-dejanews.com>: Re: Problem with xilinx M1
14891: 99/02/23: Jonas Thor: Re: Problem with xilinx M1
14883: 99/02/23: Khaled benkrid: High Fanout Signals
14886: 99/02/23: Philip Freidin: Re: High Fanout Signals
14889: 99/02/23: <tryggvem@my-dejanews.com>: Re: High Fanout Signals
14931: 99/02/25: Ray Andraka: Re: High Fanout Signals
15072: 99/03/05: Khaled benkrid: Re: High Fanout Signals
15086: 99/03/05: Ray Andraka: Re: High Fanout Signals
15073: 99/03/05: Khaled benkrid: Re: High Fanout Signals
15074: 99/03/05: Khaled benkrid: Re: High Fanout Signals
15075: 99/03/05: Khaled benkrid: Re: High Fanout Signals
15082: 99/03/05: Khaled benkrid: Re: High Fanout Signals
14884: 99/02/23: Simon: Re: Xilinx/VHDL query - two clocks in one CLB
14892: 99/02/23: Valentin Serb: test, ignore please
14893: 99/02/23: Kevin Jennings: Replace an Intel 82380 or 8344 with a CPLD/FPGA
14897: 99/02/23: Chris Waterman: FLEX PROBLEM
14899: 99/02/23: Zhen Luo: Your view on this article?
14903: 99/02/24: Aldo Mozzi: Re: Your view on this article?
14904: 99/02/24: Ilija Hadzic: Re: Your view on this article?
14939: 99/02/25: Wade D. Peterson: Re: Your view on this article?
14908: 99/02/25: Tom Kean: Re: Your view on this article?
14936: 99/02/25: Christof Paar: Re: Your view on this article?
14963: 99/02/27: Nick Hartl: Re: Your view on this article?
15112: 99/03/07: Ray Andraka: Re: Your view on this article?
14901: 99/02/24: Sergio A. Cuenca Asensi: How to avoid GRS inferred in Synopsys
14902: 99/02/24: Andrew Bunsick: FPGA/ASIC Design Teams Available
14911: 99/02/25: David Decker: Re: FPGA/ASIC Design Teams Available
14905: 99/02/24: Brian Schott: synlibs for XC40150XV Synopsys fpga_shell
14969: 99/03/01: Robert Ayre: Re: synlibs for XC40150XV Synopsys fpga_shell
14906: 99/02/24: Steve Vallerand: 4002A .bit -> .hex
14975: 99/03/01: Brian Boorman: Re: 4002A .bit -> .hex
14907: 99/02/24: Jason Chan: Batch compliation using Altera maxplus2?
14913: 99/02/25: <bjong@my-dejanews.com>: Re: Batch compliation using Altera maxplus2?
14909: 99/02/25: Carl Stern: Re: Place and Route Times question
14910: 99/02/24: Jim: JTAG HANG UP......
14914: 99/02/25: Mike H.: Re: JTAG HANG UP......
14926: 99/02/25: rk: Re: JTAG HANG UP......
14935: 99/02/25: Matthew Murphy: Re: JTAG HANG UP......
14937: 99/02/25: Jim: Re: JTAG HANG UP......
14952: 99/02/26: Ying C.: Re: JTAG HANG UP......
14956: 99/02/26: Ray Andraka: Re: JTAG HANG UP......
14970: 99/03/01: Brian Boorman: Re: JTAG HANG UP......
14971: 99/03/01: Ray Andraka: Re: JTAG HANG UP......
14981: 99/03/01: bibico: Re: JTAG HANG UP......
14912: 99/02/25: Michal: WTB: MPA1036DH FPGAs
14915: 99/02/25: Don Brouse: Xilinx ABEL?
14916: 99/02/25: Steven K. Knapp: Re: Xilinx ABEL?
14948: 99/02/26: Russell May: Re: Xilinx ABEL?
14917: 99/02/25: <timolmst@cyberramp.net>: Re: Xilinx ABEL?
14918: 99/02/25: David Decker: Re: Xilinx ABEL?
14922: 99/02/25: Dave Decker: Re: Xilinx ABEL?
14919: 99/02/25: Joel Kolstad: Re: Xilinx ABEL?
14921: 99/02/25: Bertram Geiger: Re: Xilinx ABEL?
14928: 99/02/25: Austin Franklin: Re: Xilinx ABEL?
14929: 99/02/25: <ems@riverside-machines.com.NOSPAM>: Re: Xilinx ABEL?
14934: 99/02/25: Bruce Nepple: Re: Xilinx ABEL?
14947: 99/02/26: Richard Russell: Re: Xilinx ABEL?
14938: 99/02/26: <ibaggett@bagotronix.com>: Re: Xilinx ABEL?
14950: 99/02/26: Joel Kolstad: Re: Xilinx ABEL?
14954: 99/02/26: Austin Franklin: Re: Xilinx ABEL?
14941: 99/02/26: Mark Summerfield: Re: Xilinx ABEL?
14920: 99/02/25: Joel Kolstad: Where do I connect my reset pins to?
14924: 99/02/25: Jamie Sanderson: Re: Where do I connect my reset pins to?
14925: 99/02/25: Peter Alfke: Re: Where do I connect my reset pins to?
14930: 99/02/25: Joel Kolstad: Re: Where do I connect my reset pins to?
14961: 99/02/27: Andy Peters: Re: Where do I connect my reset pins to?
14933: 99/02/25: Bruce Nepple: Re: Where do I connect my reset pins to?
14923: 99/02/25: Jason Lohn: EH'99 deadline extended to March 10
14927: 99/02/25: L.O.S.: Where To FIND Info on Basic CPU Components
14942: 99/02/26: Charles F. Shelor: wanted: info about Fast Ethernet cores
14949: 99/02/26: Wiggo Olufsen: Re: wanted: info about Fast Ethernet cores
15054: 99/03/04: lior: Re: wanted: info about Fast Ethernet cores
14944: 99/02/26: Bill: Xilinx 9500XL
14953: 99/02/26: Stephanie Tapp: Re: Xilinx 9500XL
14946: 99/02/26: Matthias Brucke: pipelined multipliers for behavioral synthesis (->XC4062XL)
14951: 99/02/26: Larry Doolittle: Virtex multiplication
14955: 99/02/26: Ray Andraka: Re: Virtex multiplication
14957: 99/02/27: Ray Andraka: Re: Virtex multiplication
14958: 99/02/27: David Langmann: Foundation V1.5 Crash
14962: 99/02/27: Andy Peters: Re: Foundation V1.5 Crash
14964: 99/02/27: Jeff Hunsinger: Re: Foundation V1.5 Crash
15093: 99/03/05: Brian Boorman: Re: Foundation V1.5 Crash
15338: 99/03/19: Thomas LeMense: Re: Foundation V1.5 Crash
15350: 99/03/19: Bruce Nepple: Xilinx Makefile?
15366: 99/03/20: Peter: Re: Xilinx Makefile?
15387: 99/03/22: Bruce Nepple: Re: Xilinx Batchfile?
15420: 99/03/23: Rick: Re: Xilinx Batchfile?
15464: 99/03/24: Bruce Nepple: Re: Xilinx Version Control?
14959: 99/02/27: francesco l spadini: newbie questions
14967: 99/03/01: Sergio A. Cuenca Asensi: Re: newbie questions
14972: 99/03/01: Steven K. Knapp: Re: newbie questions
14980: 99/03/01: Jeff Iverson: Re: newbie questions
14965: 99/02/28: Bill Moffitt: MAXPlus Muti-chain JTAG problem
14966: 99/02/28: Webmaster: Over 1400 semiconductor links!
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