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Tximo, As a general rule you get inferred latches when you try to synthesize a design containing if- or case-statements with incomplete conditions, as you have below. In this case the synthesis tool implements a latch to hold values that are not changing. The remedy is to specify all possible conditions in if- and case-constructs. Wiggo. Tximo wrote: > Hi all, > I'm trying to synthesize in an XC4010E the module shown below, but F1.5 > gives me next message: > > Error: Sequential mapping has detected that the cell > '/ver1-Optimized/load_reg' uses both asynchronous > 'set' and 'clear' pins. The target architecture does not support both on > the same sequential device (FE-SEQMAP-2) > > After a lot of tests, if sentences with "-- ******" are commented, the > error dissappears, and from time to time I get next warning: > > Warning: Latch inferred in design 'generar_stuff_bis' read with > 'hdlin_check_no_latch' (HDL-307) > > My problems are that I am not using any latch, I don't know how to > access 'hdlin_check_no_latch' variable, and I don't know > the use of the inferred latch. > > Suggestions and ideas are welcome. Thanks in advance > > My e-mail: jgracia@disca.upv.es > > -- CODE: > > library IEEE; > use IEEE.std_logic_1164.all; > > entity generar_stuff_bis is > port (clock, reset, generar, trxon, error_contienda, bus_libre : in > STD_LOGIC; > linea_bus, parar : out std_logic > ); > end generar_stuff_bis; > > architecture generar_stuff_bis_arch of generar_stuff_bis is > > component contador1 > port (load, clock, reset : in std_logic; > c_in : in std_logic_vector(3 DOWNTO 0); > c_out : out std_logic_vector(3 DOWNTO 0)); > end component; > > signal dato_ant, load, linea_bus_int : std_logic; > signal c_in, c_out : std_logic_vector(3 DOWNTO 0); > > begin > > linea_bus <= linea_bus_int or error_contienda; > > cnt : contador1 port map ( > load => load, > clock => clock, > reset => reset, > c_in => c_in, > c_out => c_out); > > process (clock, reset) > begin > if reset='1' or bus_libre='1' > then > dato_ant <= '1'; > c_in <= "0000"; > linea_bus_int <= '1'; > parar <= '0'; > if reset='1' then > load <= '0'; > elsif bus_libre='1' then > load <= '1'; > end if; > > elsif clock='0' and clock'event then > if generar='1' and error_contienda='0' then > load <= '1'; > if c_out /= "0101" then > parar <= '0'; -- ****** > linea_bus_int <= trxon; -- ****** > if dato_ant /= trxon then > c_in <= "0000"; > dato_ant <= trxon; > else c_in <= c_out; > end if; > > elsif c_out = "0101" then > parar <= '1'; -- ****** > c_in <= "1111"; > if dato_ant /= trxon then linea_bus_int <= trxon; -- > ****** > else linea_bus_int <= not trxon; -- ****** > end if; > end if; > end if; > end if; > end process; > > end generar_stuff_bis_arch; -- +---------------------------------------------------------------+ | Wiggo Olufsen | | Cypress Software AS Phone : +47-73-52 46 59 | | P.O.Box 2668 Fax : +47-73-52 46 80 | | N-7001 TRONDHEIM E-mail: wiggo.olufsen@online.no | | NORWAY | +---------------------------------------------------------------+Article: 14726
Just a question. Why would you want to do that? If you have VHDL capapility then use it. Why lock yourself into a tool set by using AHDL? HAVE FUN!! Nick ali Benkhalil wrote: > Hi, > I am using MAX+plusII Ver. 8.2. > I want to know is it possible to write a mixed code AHDL (Altera HDL) > and VHDL > and compile it using MAX+plusII. (e.g. Call VHDL function from AHDL > code) > > Thanks. > > A.K. >Article: 14727
It is a propriatary tool AHDL. You either like what Altara did or go with an industry standard like VHDL or Verilog. HAVE FUN!! Nick Endric Schubert wrote: > while we're talking about AHDL vs. VHDL: > > does anybody know about any tools to work on AHDL files more > efficiently? like > > - source browsing tools or extensions to those (e.g. source navigator) > - tags file generators (ctags/etags dont work on AHDL) > - emacs ahdl mode > > i like to trace signals thru ahdl files more easily than just search for > their names in emacs... > > any help is appreciated > > endricArticle: 14728
You can NEVER!!! turst any simulator to show all real async-contitions. WHY? Because they have a limited timing parrameters. Mostly they are worst case numbers. If your actual real device runs faster then worst case, your simulation is invalid in an async situation. Want life to be easier? May I suggest syncronous design techniques? HAVE FUN!! Nick Lars Freund wrote: > Hi, > > I'm working with Altera Max+Plus II 8.3 and simulated my AHDL-Code. I > was able to avoid an error (wrong outpout for 1 clock period) by adding > another FlipFlop. > > But in real, on my FLEX8000-Chip, the problem is still there. (spikes in > PWM...) > > Does this mean that I can't trust the Simulator for signals < 1 clock > period? > > Bye, > > LarsArticle: 14729
Arrigo Benedetti wrote: > I just came across this: > > http://www.starbridgesystems.com/release.html > > Any thoughts? "Not found" said my browser to this URL Reiner Hartenstein University of Kaiserslautern http://xputers.informatik.uni-kl.de > > > -Arrigo > -- > Arrigo Benedetti o e-mail: arrigo@vision.caltech.edu > Caltech, MS 136-93 < > phone: (626) 395-3695 > Pasadena, CA 91125 / \ fax: (626) 795-8649 --Article: 14730
The site is under construction, try http://www.starbridgesystems.com/Pages/about.html Hans. In article <36C510AD.3F915D1C@rhrk.uni-kl.de>, hartenst@rhrk.uni-kl.de says... > > > >Arrigo Benedetti wrote: > >> I just came across this: >> >> http://www.starbridgesystems.com/release.html >> >> Any thoughts? > >"Not found" said my browser to this URL > >Reiner Hartenstein >University of Kaiserslautern >http://xputers.informatik.uni-kl.de > >> >> >> -Arrigo >> -- >> Arrigo Benedetti o e-mail: arrigo@vision.caltech.edu >> Caltech, MS 136-93 < > phone: (626) 395-3695 >> Pasadena, CA 91125 / \ fax: (626) 795-8649 > >-- > >Article: 14731
M1's DRC tells me that there are multiple pads for a logic net. I can't find more than one pad, however that one pad is the TDO pin. The TDO symbol is used, and its input is connected to the output of an OUTFFT. This design is a few years old and worked with XACT (not sure which version). Is there something special I need to do with M1? When I replaced TDO with an IOPAD with no fixed pin it passed the DRC. thanks Hamish -- Hamish Moffatt Mobile: +61 412 011 176 hamish@rising.com.au Rising Software Australia Pty. Ltd. Developers of music education software including Auralia & Musition. 31 Elmhurst Road, Blackburn, Victoria Australia, 3130 Phone: +61 3 9894 4788 Fax: +61 3 9894 3362 USA Toll Free: 1-888-667-7839 Internet: http://www.rising.com.au/Article: 14732
Hello
I have used Synplify to synthesize my design. In a first try I
selected the XC40150XV Xilinx FPGA as the target device. As my
design didn't fit in this one, I selected the V1000 Xilinx
Virtex FPGA. The problem is that from the second report I couldn't
conclude if the design does fit in this device (or in any other
Virtex family FPGA).
Bellow I included two pieces of the reports.
Any comment would be appreciated
Eduardo
--
E.A.Bezerra@sussex.ac.uk
-----------------------------------------------------------------
Report #1 - XC40150XV Xilinx FPGA
-----------------------------------------------------------------
Resource Usage Report
Mapping to part: 40150xvhq240-09
...
Logic Mapping Summary:
FMAPs: 31017 of 10952 (284%)
HMAPs: 14037 of 5476 (257%)
Total packed CLBs: 15509 of 5476 (284%)
(Packed CLBs is determined by the larger of three quantities:
Registers / 2, HMAPs, or FMAPs / 2.)
Mapper successful!
Process took 11212.6 seconds realtime, 11212.6 seconds cputime
-----------------------------------------------------------------
Report #2 - V1000 Xilinx Virtex FPGA
-----------------------------------------------------------------
Resource Usage Report
Mapping to part: v1000bg560-4
Cell usage:
MUXCY_L 82 uses
XORCY 93 uses
MULT_AND 13 uses
FDR 1 use
FDSE 1 use
MUXF5 5536 uses
MUXF6 2760 uses
FD_1 8 uses
FD 19 uses
LD 8 uses
FDC_1 32 uses
FDC 82 uses
FDCE_1 2560 uses
FDP 9 uses
FDPE 1 use
FDCE 8724 uses
I/O primitives:
IBUF 9 uses
OBUF 1 use
BUFGP 2 uses
BUFG 2 uses
I/O Register bits: 0
Register bits not including I/Os: 11437
Mapping Summary:
Total LUTs: 26625
Mapper successful!
Process took 5176.63 seconds realtime, 5176.63 seconds cputime
Article: 14733Hi! There is a way to have an internal oscillator in a cpld? I tried a inverter with input and output together, but Synario gives me an error, both with AHDL and Schematic Entry. Instead, if I use a NAND with the output and an input together and the other input to a pin pulled up, it's ok and oscillates, but I don't want to waste a pin for this use. Any idea? Thanks in advance. LuigiArticle: 14734
Ray Andraka wrote:
> For many data path applications, the design does break down quickly into a
> collection of small circuits, mostly less than 30 CLBs.
Data paths often require building the VHDL equalivant of a schematic.
If I built mostly data paths, such as I think is the case in signal
processing, with the careful side note that I have no experience with
practical signal processing, I can sure see why I would like VHDL less
and schematics more. My only problem with the mixed approach is that
you have two different tool sets for doing the same thing, that you must
maintain, keep up to date on, and find bugs in (gack!).
> As you say here, an experienced human can easily see the optimum solution, and
> too many times the HDL tools can't find it without a couple of good swift kicks,
> sweet talking, hand-holding and a couple of sweet-nothings or four letter words
> uttered. This is why I still advocate schematic entry for these types of
> problems. It would be really nice if it were a little easier to tell the HDLs
> exactly what you want constructed in cases like these.
It isn't very hard to do tell Synplicity exactly what to build.
Bascially what I do is to put what I want in a f-map or h-map into a
entity, decorate it with the correct magic properties, and use a
generate loop to tile it across the data path. Next is writing a .ucf
file to nail it all down to the correct locations. (Why the .ucf?
Xilinx's floorplanner always seems to be a step behind me in what it
supports. Virtex when?) Other worthwhile tactics include adding buf's
to break the logic into hunks that the tool can get right. Use of
bufg's (a predefined black box) for large fanout, time critical signals
(oe's for buses for example) can be important. I've even used the two
input omux in the output buffer. And the ever popular adding registers
when you can stand the extra cycle.
However, I've seen other methods of doing the exact same things. I'm
trying to learn how to get Exemplar to do the same sorts of things, as
the syntax that works well with Synplicity doesn't seem to work with
Exemplar. It would be nice to have a standardized common syntax. Which
brings me to:
My Major Wish list:
-----------------------------------------------
1) A high level floorplanner.
What I would like to do is to take a labeled statement (a process,
signal assignment or instantiated lower level block) and put it
into a physical form. The sorts of physical forms needed are
both absolute and relative, and would range from the very general
to the very specific, and both technology dependent and technology
independent forms would be desired.
2) A better way of doing physical VHDL.
While vendor independence is nice, when pushing parts to the limit
one must lose that to gain access to all the special features of a
part. It would be ok if the silicon vendors would just set up and
document a full set of physical VHDL "black boxes" for all of
their logic elements. The high level floorplanner might well fill
this need.
3) Quality of Results.
It's not great yet, guys and gals of the tools world. It can get
better, it should get better, it needs to get better.
--
Phil Hays
"Irritatingly, science claims to set limits on what
we can do, even in principle." Carl Sagan
Article: 14735Last quarters XCELL discussed a technique for clocking logic whereby a high frequency clock is divided down to form lower frequency clocks. In this technique the derived clocks are not used as clocks, but rather as clock enables to flip flops which are clocked with the original clock. This technique is supposed to be much better since timing constraints only need be specified for the one clock. My question is.. Does the time spec for the flip flop transfer to the clock enable line delay? In other words does the clock enable line delay get SPECed at the original clocks frequency as the data delay into the flip flop does. If it does not, I don't see any real advantage since the delay for each clock enable would have to be SPECed out separately. Also, how does one insure (in VHDL) that the clock enable is indeed being inferred? Thanks in Advance -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 14736
APS has two boards which will use 4085XLAs. The first is tha APS-X208. It is an ISA board with a programmable DDS clock and sep. Interface FPGA. The TEST FPGA is a socketed 208 pin QFP. The board has 64K SRAM. The second board (APS_X240) is a 240 pin QFP board which has a PC104/ISA/stand alone board. It has 512K SRAM option, on board oscillator socket, Wall transformer connector for stand alone power. The board can be stacked easily and is available with an ISA carrier which can hold upto 4 modules (4 4085's ..that's allot of FPGA horse power). Details can be seen at http://www.apsfpga.com. Sanjeev wrote: > I am looking for a good project board that will take a Xilinx XC4085XL (PGA > 559) FPGA. Anyone have any good suggestions? > > Thanks -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 14737
Check out http://www.apsfpga.com Apinetr Unakul wrote: > I'm also looking for a project board, but only with Xilinx XC4062XL (PG475) > FPGA. Any suggestion would greatly be appreciated. > > Thanx. > > Sanjeev wrote: > > > I am looking for a good project board that will take a Xilinx XC4085XL (PGA > > 559) FPGA. Anyone have any good suggestions? > > > > Thanks -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 14738
Two things to check. First , if you are using the Xpress constraints editor, insure
that the option under :
SYNTHESIS->OPTIONS->EXPORT TIMING CONSTRAINTS
is checked.
Then if the output clock is used anywhere in the circuit it should come up in the
Synopsys Constraints editor. It may be renamed to a new name (other than your HDL
signal name. You will have to search the synthesis XNF to be 100% sure that the new
clock name (usually Nxxx) is tied to your signal name. The problem is, that the
synthesis tool will reanme the signals in an HDL design to node names (ie. N23, N234
etc.) The same is true when using the M1 constraint editor. Any questions, just give
me a yell.
Farhad Abdolian wrote:
> Hi,
> I have a problem with a FPGA design (XC4036XL-1).
>
> I have 2 different clocks into the design and I use a MUX to choose
> between these two, but I can not set constraint to the clock after the
> MUX.
> I have defined my constraints for these 2 clocks but since these
> clocks are connectected to a block and my main clock is the one
> comming out of that block, synopsys does not sends the contraints to
> Xilinx which cause a lot of problem for me.
>
> I have mannaged to put constraints to the output of the MUX block, but
> this constraint does not apear in the .NCF file (which Xilinx uses as
> input).
>
> Is there anyone who have mannaged to do so? And how?
>
> I desperately need to know the answer to this question because it is
> the only part of my design which does not work as it should and I am
> having a lot of problem simulating the design after mapping (I use
> Modelsim 5.2a to simulate the time_sim.vhd by using the time_sim.sdf).
>
> I really appreciate any tips or help to solve this problem.
>
> Best regards,
> Farhad A.
> Stockhlm/Sweden
>
> PS: Here is the command I use to generate the clock in synopsys:
> /* first clock */
> create_clock -period sample_clk_period -waveform {0
> sample_clk_half_period} CLK_FPGA
> /* second clock */
> create_clock -period clk_period -waveform {0 clk_half_period} CTRL_CLK
>
> /* Clock output of the MUX */
> create_clock -name FPGA_REF_2_CLK -period 50 -waveform { 0 25 } {
> DDC_CORE_1/CLK_GEN_1/FPGA_REF_2_CLK }
>
> /* Clock input to the section that uses the above clock */
> create_clock -name CLK -period 50 -waveform { 0 25 } {
> DDC_CORE_1/dci_int_1/CLK }
>
> set_clock_skew -uncertainty clock_uncertainty -propagated { CTRL_CLK ,
> CLK_FPGA, CLK, FPGA_REF_2_CLK}
>
> /* And I can see that Synopsys has accepted the above statemtns and
> reports the clocks when I use the following commands: */
> all_clocks()
> report_clocks -attributes
>
> The result is:
>
> ****************************************
> Report : clocks
> Design : pad
> Version: 1998.08
> Date : Tue Feb 9 20:54:24 1999
> ****************************************
>
> Attributes:
> d - dont_touch_network
> f - fix_hold
> p - propagated_clock
>
> Clock Period Waveform Attrs Sources
> --------------------------------------------------------------------------------
> CLK 50.00 {0 25} p
> {DDC_CORE_1/dci_int_1/CLK}
> CLK_FPGA 38.00 {0 19} p {CLK_FPGA}
> CTRL_CLK 20.00 {0 10} p {CTRL_CLK}
> FPGA_REF_2_CLK
> 50.00 {0 25} p
> {DDC_CORE_1/CLK_GEN_1/FPGA_REF_2_CLK}
> --------------------------------------------------------------------------------
> 1
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President EDA & Engineering Tools
Associated Professional Systems (APS) http://www.associatedpro.com
3003 Latrobe Court richard@associatedpro.com
Abingdon, Maryland 21009
Phone: 410.569.5897 Fax:410.661.2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Article: 14739I recently saw a mailing from Lucent offering a "lite" (<30,000 gates) version of their Viewlogic-based tools for $95. Anyone have any experiences with this package you'd like to share? Scott ArmitageArticle: 14740
In article <36B88D66.46505A9D@hia.nrc.ca>, Tom Burgess <tom.burgess@hia.nrc.ca> wrote: >Gerd Beil wrote: >> >> Hi! >> >> Is there any serial EEPROM available to replace the OTP SPROMs >> XC17128E/XC17256E for configuring a Xilinx XC4k-device (XC4006/4010E)? >> What protocol dose it have to use (I^2C, Microwire, SPI,...)? >Yes, Atmel makes some XC17XXX compatible serial EEPROMs. See: Xilinx themselves also have a new series coming out, the XC1800. Available in sizes from 512K to 4 MB. These also support the all-important byte-wide configuration mode. These I think look like a good choice as well. Xilinx rep said they would begin shipping in March. Alex Rast arast@inficom.comArticle: 14741
Ooo, your design seems to be very big!
1. Which version of Synplify are you using? The version you are using
might result false reports, maybe a never version is correct.
2. Have you controlled all the codes to be targetted carefully?
Maybe you have unknowingly added a big core. Or duplicated source.
3. The process time of Synplify is very long. From there I get you
tried a very complex device to FPGA. Maybe a predesigned ASIC core?
Maybe your design is extremely big to fit into aFPGA. Maybe you
have been using plenty of macros (RAMs, for example). Then you can divide
the core into two chips, if possible. Maybe there is a coding style problem.
The amount is extremely big.
Suppose you succesfully fitted into a device like XC40250XV. Then there
might be insufficient net resources in Design Manager, since your logic
seems to be very complex. Maybe Floorplanner helps you.
AFAIK, Synplify supports only EDIF for Virtex devices. Maybe you have
selected XNF. So please verify at the Technical Support if
the version of Synplify you are using supports Virtex in EDIF or
XNF format. Also control license files.
If your design doesn't fit into a device, normally you target to
next larger device. But the larger the device, the greater the
net delays. You must then use more pipeline stages, which is
almost a redesign of the project.
Since you haven't given details here, my assumptions might be wrong.
If so, please excuse me.
Utku
Article: 14742On Sat, 13 Feb 1999 13:39:47 -0500, APS <resp@associatedpro.com> wrote: >Last quarters XCELL discussed a technique for clocking logic whereby a >high frequency clock is divided down to form lower frequency clocks. In >this technique the derived clocks are not used as clocks, but rather as >clock enables to flip flops which are clocked with the original clock. >This technique is supposed to be much better since timing constraints >only need be specified for the one clock. My question is.. Does the time >spec for the flip flop transfer to the clock enable line delay? In >other words does the clock enable line delay get SPECed at the original >clocks frequency as the data delay into the flip flop does. If it does >not, I don't see any real advantage since the delay for each clock >enable would have to be SPECed out separately. Also, how does one >insure (in VHDL) that the clock enable is indeed being inferred? > >Thanks in Advance I can't answer these beyond saying that (using Leonardo Spectrum and its Insight schematic viewer) clock enables are successfully inferred, so I see no reason why they shouldn't be (with this tool) with a clock divider. I have a supplementary question. One reason for lowering the clock frequency is to reduce power consumption. But in this scheme, the fast clock is being as widely distributed as it would be if the whole circuit was clocked from it, and therefore its CLKBUF must drive as much load. The FF's themselves however, are only enabled for one cycle in N (N=2,4,8, whatever). Does this give you anything like the full 1/N reduction in power consumption? - BrianArticle: 14743
Achim Gratz (gratz@ite.inf.tu-dresden.de) wrote: : David Kessner <davidk@peakaudio.com> writes: : > I've read this too, but I question it greatly. I question it for several : > reasons: : > : > 1. I doubt that the "FPGA based supercomputer" : > (http://www.starbridgesystems.com/release.html) : > uses Xilinx place/route/bitstream software. For a : > computer like that to be remotely useful, they would need : > something more integrated into their development tools. : They claim to use libraries, not compile on-the-fly. I suggest to take their claims with a big scoop of sceptism. They base their performance spec on the theoretical maximum number simultaneous 4 bit additions... That is not the way to benchmark a supercomputer. I don't think their system is a supercomputer at all, I think this is a "clueless venture capitalist magnet". Just take a look at their page, ther is very little real technical information, it doesn't cite any real-world benchmarks (where are they in the top500? (www.top500.org)), at what major trade shows did/will it show their product? For what real-life supercomputing task is their product being used successfully (successstories?), is there any tangible evidence of their expertise in FPGAs? There aren't even photo's of the claimed supercomputer machine... Take that in contrast to the o-so convenient form behind the 'investment' link -> "I am requesting information on Star Bridge Systems investment oppurtunities ...". Examine the material and just make your own conclusions. ...Article: 14744
Thanks for reading... I was asked to post my questions on this NEWSGROUP, I'm hoping someone can help me... I bought an E/EPROM programmer(new). I wanted to practice erasing an EEPROM, copy and write to it however, There is nothing in the literature that tells me how to electrically erase my EEPROM.Is there something that I can do to outside of my unit to erase some of the spare EEPROMS, electrically? HELP!!!! Thanks, DaveArticle: 14745
The EEPROMs I'm familiar with (e.g. from XICOR or Microchip) have a series of commands that one sends to the chip serially; including ERASE. Usually, these commands include some seemingly repetitive rules to insure that you truly want to erase the chip so that the chip isn't accidently erased during a brownout or system crash. Are you trying to do it from this Programmer or In-Circuit? I would've thought it'd have an ERASE command. Otherwise, look at the Datasheet under its command set and look for CLEAR or ERASE. Tell us what chip and what programmer you've got. >Thanks for reading... > >I was asked to post my questions on this NEWSGROUP, I'm >hoping someone can help me... > >I bought an E/EPROM programmer(new). I wanted to practice >erasing an EEPROM, copy and write to it however, There is >nothing in the literature that tells me how to electrically >erase my EEPROM.Is there something that I can do to outside >of my unit to erase some of the spare EEPROMS, electrically? > >HELP!!!! > >Thanks, > >DaveArticle: 14746
You seem to be using an insane number of flip flops, given the amount of logic you are implementing. Over 11000 flipflops and over 8000 muxF5/F6, almost no I/O, and almost no logic, ( I am asuming the Luts are doing route thru or more muxes, as there is no reported logic in the " Resource Usage Report" section.) Are you implementing a huge shifter, or maybe a memory, and it is being implemented in FFs???? Imagine how much more help people could give you, if you had actually described you application! Philip. In article <36C57C4D.A616A4AF@sussex.ac.uk> Eduardo Augusto Bezerra <E.A.Bezerra@sussex.ac.uk> writes: > >Hello > >I have used Synplify to synthesize my design. In a first try I >selected the XC40150XV Xilinx FPGA as the target device. As my >design didn't fit in this one, I selected the V1000 Xilinx >Virtex FPGA. The problem is that from the second report I couldn't >conclude if the design does fit in this device (or in any other >Virtex family FPGA). > >Bellow I included two pieces of the reports. > >Any comment would be appreciated > >Eduardo > >-- >E.A.Bezerra@sussex.ac.uk > >----------------------------------------------------------------- >Report #1 - XC40150XV Xilinx FPGA >----------------------------------------------------------------- > Resource Usage Report > > Mapping to part: 40150xvhq240-09 > ... > Logic Mapping Summary: > FMAPs: 31017 of 10952 (284%) > HMAPs: 14037 of 5476 (257%) > Total packed CLBs: 15509 of 5476 (284%) > (Packed CLBs is determined by the larger of three quantities: > Registers / 2, HMAPs, or FMAPs / 2.) > > Mapper successful! > Process took 11212.6 seconds realtime, 11212.6 seconds cputime > >----------------------------------------------------------------- >Report #2 - V1000 Xilinx Virtex FPGA >----------------------------------------------------------------- > Resource Usage Report > > Mapping to part: v1000bg560-4 > Cell usage: > MUXCY_L 82 uses > XORCY 93 uses > MULT_AND 13 uses > FDR 1 use > FDSE 1 use > MUXF5 5536 uses > MUXF6 2760 uses > FD_1 8 uses > FD 19 uses > LD 8 uses > FDC_1 32 uses > FDC 82 uses > FDCE_1 2560 uses > FDP 9 uses > FDPE 1 use > FDCE 8724 uses > > I/O primitives: > IBUF 9 uses > OBUF 1 use > BUFGP 2 uses > > BUFG 2 uses > > I/O Register bits: 0 > Register bits not including I/Os: 11437 > Mapping Summary: > Total LUTs: 26625 > > Mapper successful! > Process took 5176.63 seconds realtime, 5176.63 seconds cputimeArticle: 14747
Try writing FFh to all locations - this is what 'erasing' means with an EEPROM. > I bought an E/EPROM programmer(new). I wanted to practice > erasing an EEPROM, copy and write to it however, There is > nothing in the literature that tells me how to electrically > erase my EEPROM.Is there something that I can do to outside > of my unit to erase some of the spare EEPROMS, electrically?Article: 14748
OK, so it's not completely useless. Just the Aldec tools. They may work OK if you use them from start to finish, but if you enter your design using a different schematic/VHDL/Verilog package and try importing the netlist, you're probably going to run into the same troubles as I have. My experiences so far: 1. The schematic entry tool is horrible. It's OK for a very tiny, very simple example, but even that can be awkward to enter. I now use a different schematic entry program (Protel). 2. If you don't use the supplied toolset, the Project Manager refuses to play along. It won't allow me to launch the simulator until I create a dummy schematic with the supplied tool. 3. The simulator automatically loads a netlist (not the one I want) 95% of the time, bypassing the selection box (it flashes briefly on the screen). My workaround was to include a "load_edif filename" line to the start of my simulation script. 4. The simulator doesn't seem to be able to handle any design with hierarchy, whether the netlist is in XNF of EDIF format. 5. The simulator does not always recognize all signals in a design. Even though I can see one of the inputs to my design in the EDIF netlist, the simulator doesn't list it as a signal. 6. The Design Manager automatically assumes it knows which netlist to use. Trying to change this is not obvious. I figured out that I could create a custom template for my design, but this seemed awkward. My solution was to throw away the whole design manager and execute the tools from the command line using a make file. 7. More simulator complaints: The looping contructs are far too limited. Usually, I would create a test bench that would read in a set of vectors, execute, and compare to another set of vectors. If the test fails, it should stop and issue an error. I couldn't find a way to do this, mostly because of the lack of decent looping capabilities. Can anyone point me to another simulator? I'm looking for something low cost that can read in XNF or EDIF and have at least some compability for scripting. A full Verilog or VHDL simulator would be ideal, but I don't have the budget to support it yet. TIA, JeffArticle: 14749
On Sat, 13 Feb 1999 13:39:47 -0500, APS <resp@associatedpro.com>
wrote:
>Last quarters XCELL discussed a technique for clocking logic whereby a
>high frequency clock is divided down to form lower frequency clocks. In
>this technique the derived clocks are not used as clocks, but rather as
>clock enables to flip flops which are clocked with the original clock.
>This technique is supposed to be much better since timing constraints
>only need be specified for the one clock. My question is.. Does the time
>spec for the flip flop transfer to the clock enable line delay? In
>other words does the clock enable line delay get SPECed at the original
>clocks frequency as the data delay into the flip flop does. If it does
>not, I don't see any real advantage since the delay for each clock
>enable would have to be SPECed out separately.
if i understand you correctly, the answer is basically no. what if you
have some enables which are active on every second clock cycle, some
which are active on every third, and so on? the tools can't analyse
your hardware to find out what your clock enable waveform is, and so
they can't know what the allowable delay between two f/fs is - you
have to tell the tool.
this is a 'slow exception' problem. the procedure is:
1) give a TNM to your clock
2) specify a period for the clock, say PERIOD1
3) give a TNM to your clock enable net
4) put a timespec on your clock enable net, using a FROM:TO. this
timespec can use a multiple of the period on the clock net, for
example, PERIOD3 = n*PERIOD1.
an example, for a 20ns clock, and an enable which is active on every
third clock edge:
1) NET "CLOCK" TNM = MAIN_CLK;
2) TIMESPEC SPEC1 = PERIOD MAIN_CLK 20;
3) NET "ENABLE" TNM = CLK_EN;
4) TIMESPEC SPEC2 = FROM:CLK_EN:TO:CLK_EN:SPEC1 * 3;
this, in principle, covers all the required timespecs.
some pros and cons for lower-frequency enables:
1) for: in principle, it's (much) cleaner to have one clock, and lower
frequency enables
2) for: it's more difficult to design and timespec a multiple-clock
design (you have to keep track of all signals crossing clock domains,
and ensure that they're sampled correctly)
3) against: higher power consumption
4) watch out: if your clock enable operates a data-feedback mux, as it
does on xilinx, then there's a possibility that the tool may not use
the built-in feedback loop, but may route it externally. this can
cause timing to fail, and may be complex to fix
5) against: in real designs, you will have some parts of the chip that
must cycle quickly, and some that don't need to be fast. it can make
sense to have multiple clocks, as long as the number of signals
crossing domains is small, rather than routing a high-speed clock
everywhere, together with enables.
another (big) problem: you probably have a lot of logic that you need
to route your enable to. this means that, to meet timing, you may have
to route through a global buffer. there's a complex problem in 1.4
(and, i think, in 1.5, but i'm not sure), which i don't fully
understand, when you have timespecs on two buffers in the same chain
(ie. original clock -> clock buffer -> divided down -> enable buffer).
in short, IIRC, step 4 in the example above doesn't work correctly in
this case, and you have to identify all sources to the enabled f/f,
and you have to explicitly timespec all of them. note that you have
exactly the same problem when you directly use a lower-frequency clock
rather than an enable, since you then have two clock buffers in the
chain. it's some time since i looked at this and i've forgotten the
details, but i've got some notes somewhere.
> Also, how does one
>insure (in VHDL) that the clock enable is indeed being inferred?
the standard template for an enable is:
if (edge detect) then
if (enable active) then
...action on enabled clock
end if;
end if;
in other words, put the enable condition (ie. ENABLE = '1', or
whatever) right after the edge detection, on a line by itself. don't
be tempted to roll the enable condition into the edge detection (ie.
(CLK'event and CLK='1' and ENABLE='1')). this will give the correct
functionality with all tools, and should make sure that you use the CE
input for xilinx... see other threads for possible problems.
brian wrote:
>I have a supplementary question. One reason for lowering the clock
>frequency is to reduce power consumption. But in this scheme, the fast
>clock is being as widely distributed as it would be if the whole circuit
>was clocked from it, and therefore its CLKBUF must drive as much load.
>The FF's themselves however, are only enabled for one cycle in N
>(N=2,4,8, whatever).
>Does this give you anything like the full 1/N reduction in power
>consumption?
the f/fs still operate on every cycle, since xilinx's clock enable
operates a mux which controls data feedback, so there's little power
consumption advantage to using clock enables. there has to be some
reduction, since you don't have as many nodes changing, but i guess
that's it pretty minimal.
evan
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