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Greetings This is semimonthly announcement of Verilog FAQ. Verilog FAQ is located at http://www.angelfire.com/in/verilogfaq/ Alternate Verilog FAQ is an attempt to gather the answers to most Frequently Asked Questions about Verilog HDL in one place. It also contains list of publications, services, and products. Alternate Verilog FAQ is divided into three logical parts. Part 1 : Introduction and misc. questions Part 2 : Technical Topics Part 3 : Tools and Services What's New section outlines the changes in different versions and announcements. Links connects you to related informative links in internet. Rajesh Bawankule (Also Visit Verilog & EDA Page : http://www.angelfire.com/in/rajesh52/verilog.html ) -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15226
wgilles@my-dejanews.com wrote: > we are experiencing a problem with xilinx XC4010E FPGAs. > So far the problem > manifests itself as a stuck pin (Pin 126 of PQ208 package) > to VCC. I suggest a very simple test:Measure the pull-up impedance by pulling the "stuck" pin to ground with a 10 kilohm or a 100 Ohm resistor. The least likely case is a shortened pull-up transistor ( a hardware defect ) that would maintain Vout = Vcc even against a 10 Ohm pull-down. More likely is an activated pull-up ( n-channel to 3.8 V or p-channel to Vcc, that's a configuration option), which may be the result of wrong logic or misconfiguration, and it causes an internal pull-up impedance of about 30 Ohm, so the 100 Ohm pull-down has a noticeable effect. The most likely case is an inactive pull-up, combined with a weak pull-up to Vcc, impedance about 50 kilohm, so the 10 kilohm load will pull almost to ground. That is most likely the result of a misconfiguration, but could also be a logic or timing error. Peter Alfke, Xilinx ApplicationsArticle: 15227
A 128Kx18 (2Mbit) synchronous 100MHz SRAM should work, it costs less than $10 in small quantities. Use a standard clock doubler circuit, which has got to be more satisfying than an RC delay circuit, and you'll be home free. Assuming, of course, that this fits your application. Any more, it's hard to find SRAMs that are as slow as 60 nS access time! -- Bob Elkind fpgar@my-dejanews.com wrote: > > Thanks Peter > > The specific problem is: > > I need a write enable signal for a 100 ns RAM. > The clock of the system is 5-8 MHz, and i need write once per cycle. > > If i use the opposite clock-edge i must change the RAM to 60ns access time. > This memory is controlled something like that > > Wenable > --+ +--+ > ¦ ¦ ¦ > +------+ +---..... > -> <100n <- > > CLK > --+ +----+ > ¦ ¦ ¦ > +----+ +----..... > > With a 8 Mhz clock i thougth generating it as Wenable = /CLOCK*Clockdelayed > so i assure the minimun access time. > > Also I can delay the clock with external digital logic to avoid the slow rise > time, but i was looking for the easy and cheapest solution. > > Thanks for your help > > drp@lettera.net > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15228
In article <36E8A722.DBAB63FB@ee.princeton.edu>,
Zhen Luo <zhenluo@ee.princeton.edu> wrote:
>
>1. I have a global reset in my VHDL code. I used a STARTUP block to
>instantiate the GSR signal. Where should I put this GSR signals?
>Currently I am using ring[0] as a GSR signal. But I guess there is an
>error in my code (attached below) because all the internal FFs in LCAs
>are all 0s no matter how many cycles I run.
In principle this should work.
>2. What is meaning of the option -g GSRInactive:C3 in bitgen? Does this
>influence anything on the GSR?
For this you should read the doc in the xc4000 data sheet, but it
should not be affecting you here.
>3. when you write "PamDownloadBitstream(pam, &drc_pam, 30);"
> Does this function also set the user clock to be 33MHz as well?
Yes, the 3rd parameter to PamDownloadBitstream sets the user clock.
Since the user clock can take several milliseconds to reach a value
it is a good idea to overlap it with other timeconsuming operations
like download. But note that setting the user clock to some speed
doesn't activate it. You need to use the PamRT call:
PamClockOn(pam, 0);
By default after download the frequency is set, but the clock is gated
off. For testing you might also find
PamClockStep(pam, 0, n);
useful.
Looking at your code below, you might also have a problem of polarity.
Is your reset really active high?
>
>-- Zhen
>
> 49. /* using ring[0] to initiate a reset */
> 50. userport = &(PAMREGS(pam)->link);
> 51. *userport = 0; PamFlush();
> 52. // enable ring[0], disable ring[1]
> 53. PAMREGS(pam)->decode = (PAMREGS(pam)->decode & ~PPAMRING_ENABLES)
>| (0x1 << 8);
> 54. // force write
> 55. PamFlush();
> 56. // Set a '1' on ring[0]
> 57. PAMREGS(pam)->dwnld1 = (PAMREGS(pam)->dwnld1 & ~PPAMRINGS) | 0x1
><< 8;
> 58. // force write
> 59. PamFlush();
> 60. // Set a '0' on ring[0]
> 61. PAMREGS(pam)->dwnld1 = (PAMREGS(pam)->dwnld1 & ~PPAMRINGS) | 0x0
><< 8;
> 62. PamFlush();
>
>
Article: 15229This is just to announce my new book, "Programming Embedded Systems in C and C++" (ISBN 1-56592-354-5). I believe this title may be relevant to some of the readers of this group. The book is published by O'Reilly & Associates and available direct from them, in your local computer-friendly bookstore, and at Amazon.com: http://www.amazon.com/exec/obidos/ASIN/1565923545/netrino/ I've put the Table of Contents and Preface on my website to help potential readers get a feel for the book without buying it. I've also put copies of the Embedded Systems Glossary and Bibliography from the back of the book on the website as well: http://www.netrino.com/Books/EmbeddedC/ http://www.netrino.com/Publications/Glossary/ http://www.netrino.com/Publications/Bibliography/ It is my intention to make occasional changes and updates to the online version of the glossary and bibliography. So I would very much like to hear your constructive feedback. Please send comments and suggestions for new terms or books to <webmaster@netrino.com>. I have put a lot of work into the book, as well as the online versions of the glossary and bibliography. I sincerely hope that all three of them will be valuable contributions to the community of embedded systems developers. Enjoy, Michael BarrArticle: 15230
I just lost several days tracking down a Xilinx problem and thought I would pass it on so others don't have the same problem. We were having problems with an output being intermittent and finally found using epic that the router had created two copies of a flip flop used to sync an async input so we had the "same" signal both active and inactive depending on which flip flop the logic was connected to. The GUI button to prevent replicating logic doesn't prevent replicating flip flops in the same CLB. They have an solution record http://www.xilinx.com/techdocs/3813.htm that you set a special environment variable and it won't do this. set CM_EXCLUDE_XQYQ=TRUEArticle: 15231
On Mon, 15 Mar 1999 17:44:46 GMT, <mathai@ecf.toronto.edu> wrote: >Hi, I'm designing a small RISC on a Flex10k20 and have run into a problem >implementing my register file. > > >The register file I want is 16 regs deep, each with width 16 bits. I need >five data out (read) ports (two to the alu, three so I can do branch >condition detection and program counter loads on a branch), and one data >in (write) port. I tried to implement this as 16 registers with the output >ports as five huge 16:1 16 bit muxes. On compilation and fitting, I found >that this was must too large for the Flex10k20. > >My question ... is there a more efficient way to implement this kind of >functionality? > >Thanks for your advice, >Nebu If you have to have the speed of direct multiplexing, you may be out of luck. If your CPU clock is a factor of two or more down on the FPGA speed, you can use fewer multiplexers sequentially shared. Best case, if you can use the embedded array and cycle six addresses in one CPU cycle, you don't need any muxes at all! -- Steve Rencontre, Design Consultant http://www.rsn-tech.demon.co.uk/ -- remember to despam return addressArticle: 15232
On Fri, 05 Mar 1999 14:34:24 -0800, bob elkind <eteam@aracnet.com> wrote: >Is there a common, single solution set for hw and sw to program FPGAs and serial ROMs and CPLDs, from a PC parallel port to a >JTAG port? If there is, I bet it's expensive. The problem is not the download cable, it's the programming algorithms. Keeping up with these is the main reason why the likes of Data I/O can charge so much for their programmers. > >Xilinx has the Parallel Cable (with software modules that are proprietary to Xilinx)... > >Altera has the JAM language and Byte Blaster (and JAM is officially non-propietary, > but is there JAM support for non-Altera devices?)... > >Altera's ByteBlaster is very similar to Xilinx' Parallel Cable, except the pinouts are different. Hence the SW to drive them is >different. The most recent revision of Altera's JAM player also supports the Lattice ispDownload cable, which is a step in that direction. It would be a piece of piss to add support for yet another pinout (the source is available), but that doesn't help if there aren't any Xilinx JAM files. If you can get hold of the programming algorithms for all the devices you're interested in, the rest is easy! -- Steve Rencontre, Design Consultant http://www.rsn-tech.demon.co.uk/ -- remember to despam return addressArticle: 15233
I am currently trying to figure out how to improve an adder. An n-bit adder can be constructed by cascading n full adders in series, with the carry into stage i, Ci, coming from the output of stage i-1. The carry into stage 0, C0, is 0. If each stage takes T nsec to produce its sum and carry, the carry into stage i will not be valid until iT nsec after the start of the addition. For large n the time required for the carry to ripple through to the high-order stage may be unacceotably long. I want to design an adder that works faster. I believe that it has something to do with Ci being able to be expressed in terms of the operand bits Ai-1 and Bi-1 as wekk as the carry Ci-1. Using this relationship it is possible to express Ci as a function of the inputs to stages 0 to i-1, so all the carries can be generated simultaneously. Can anyone help to improve the adder?Article: 15234
On 15 Mar 1999 18:45:04 -0500, djg@drs-esg.com (David Gesswein) wrote: >I just lost several days tracking down a Xilinx problem and thought I would >pass it on so others don't have the same problem. > >We were having problems with an output being intermittent and finally found >using epic that the router had created two copies of a flip flop used to >sync an async input so we had the "same" signal both active and inactive >depending on which flip flop the logic was connected to. The GUI button to >prevent replicating logic doesn't prevent replicating flip flops in the >same CLB. They have an solution record >http://www.xilinx.com/techdocs/3813.htm that you set a special environment >variable and it won't do this. set CM_EXCLUDE_XQYQ=TRUE Wow! Thanks very much for posting this. I'd blithely assumed that flip-flop replication would be off as the default. Oh, well... Bob Perlman ----------------------------------------------------- Bob Perlman Cambrian Design Works Digital Design, Signal Integrity http://www.best.com/~bobperl/cdw.htm Send e-mail replies to best<dot>com, username bobperl -----------------------------------------------------Article: 15235
Sounds like a school problem to me! Go look for carry-lookahead adders in XILINX app notes on their WWW. >I am currently trying to figure out how to improve an adder. An n-bit >adder can be constructed by cascading n full adders in series, with the >carry into stage i, Ci, coming from the output of stage i-1. The carry >into stage 0, C0, is 0. If each stage takes T nsec to produce its sum >and carry, the carry into stage i will not be valid until iT nsec after >the start of the addition. For large n the time required for the carry >to ripple through to the high-order stage may be unacceotably long. I >want to design an adder that works faster. I believe that it has >something to do with Ci being able to be expressed in terms of the >operand bits Ai-1 and Bi-1 as wekk as the carry Ci-1. Using this >relationship it is possible to express Ci as a function of the inputs to >stages 0 to i-1, so all the carries can be generated simultaneously. >Can anyone help to improve the adder?Article: 15236
Indeed, you can get some rudimetary tools and get into at least some of the smaller FPGA devices for a couple hundred dollars. Those toolsets (the xilinx student edition comes to mind) generally have restrictions on the size of the design that can be implemented and may or may not have a usable design entry tool. The xilinx student version has the foundation schematic editor, which is reasonably good if you haven't used something better (such as viewlogic) yet. If you want to do VHDL entry, there is an additional cost. As far as what can you do with an FPGA goes, the sky is the limit. I run a business that is pretty much exclusively FPGA design. A majority of those designs are in signal processing applications in radar, communications and imaging areas and most run at data rates over 40 MSPS with some over 100MSPS. NO-SPAM damiano wrote: > Hi all, > > I just ended my studies to become an electronic engineer and I'd like > to start a few projects. > This is intended for learning purposes. > I heard that FPGA can be managed with a PC and a few hunred dollars, > is it true? > What can I do using FPGA at the moment? > > Damiano Rullo > Trezzano S/N > Milan, Italy > http://members.it.tripod.de/Damianoux/index.html > mailto: dmn@cheerful.com > mailto: damiano@mclink.it -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15237
Depends on the requirements for your clock. You can do it with an analog phase locked loop. If you want a digital solution you will need a higher frequency master clock (the higher it is the better the quality of your resulting clock) and then design either a direct digital synthesizer or a digital phase lock loop depending on your requirements. 10Hz to 2kHz output is well within the capability of any FPGA. For the DDS, worst case jitter will be 1 clock cycle of your master clock. Sven Svensson wrote: > Does anyone have a suggestion on how to make a clock multiplier > according to specs below: > > Fin: 10 Hz - 2000 Hz > Fout: Fin*100 > > I would like to use a FPGA but other ideas are also appreciated. > > Sven -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15238
what you are trying to do is called a carry look-ahead adder. Maybe you should go to your library and read some books/papers on fast adder design. This might also help in the midterm exams :-) Lisa Nangel <ln085137@sju.edu> wrote: >I am currently trying to figure out how to improve an adder. An n-bit >adder can be constructed by cascading n full adders in series, with the >carry into stage i, Ci, coming from the output of stage i-1. The carry >into stage 0, C0, is 0. If each stage takes T nsec to produce its sum >and carry, the carry into stage i will not be valid until iT nsec after >the start of the addition. For large n the time required for the carry >to ripple through to the high-order stage may be unacceotably long. I >want to design an adder that works faster. I believe that it has >something to do with Ci being able to be expressed in terms of the >operand bits Ai-1 and Bi-1 as wekk as the carry Ci-1. Using this >relationship it is possible to express Ci as a function of the inputs to >stages 0 to i-1, so all the carries can be generated simultaneously. >Can anyone help to improve the adder? muzo Verilog, ASIC/FPGA and NT Driver Development Consulting (remove nospam from email)Article: 15239
The xilinx lends itself well to testing for these types of faults due to it's reconfigurability. If you want a definitive answer as to whether there is a true stuck-at fault or a problem with the configuration, write a simple test configuration design to check out the I/O. If that shows a problem, then you have a physical problem that needs to be fixed. If not, then you have a problem with your design. For a more detailed treatment of using reconfiguration to enhance test, take a look at my paper "An FPGA based processor yields a real time high fidelity radar environment simulator " which is available on my web-site. wgilles@my-dejanews.com wrote: > we are experiencing a problem with xilinx XC4010E FPGAs. So far the problem > manifests itself as a stuck pin (Pin 126 of PQ208 package) to VCC. Two > XC4010E fpgas with different date codes (FPGA #1 = PQ208CKM9809 A105288A 4I, > FPGA #2 = PQ208CKJ9701 A105288A 4I) are programmed with the same image file. > FPGA #2 works properly but FPGA #1 with 9809 Date code has the stuck pin > problem. In the current design, Pin 126 is used as an external RAM data pin > which constantly being used. > > Per our xilinx rep, FPGA #2 has a smaller die than #1. Presently, we are not > sure whether if it is a timing problem with we are having with the latest > die. Since the fpga design was farmed out to an outside firm and they are > currently unavailable to aid us, we can't take a look at the timing > simulation to see whether we are border line or not, or, bring out test pins > to monitor the logics that affect pin 126. > > Has anyone out there experienced or heard of similar problems? If yes, how did > you overcome it? And if no, can you offer any advise? > > Thanks, > > gilles > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15240
This is one of the things I don't care for about the 10K architecture. In Xilinx 4k, spartan or virtex, you do this by using CLB ram. In Altera 10K, a register file either has to be implemented as a register per bit in the LEs (which as you have found eats up LE's quickly both for storage and selection) or in the EAB. If your clock cycle is small enough, you can use one or more EABs running at a multiple of the processor clock so that you get all your required reads sequentially in one cycle of the processor clock. Since you are doing a RISC, I suspect that that is not an option. You can also parallel EABs so that they all get written the same data and then get read out at different addresses. With the straight 10K, you still can't do concurrent read and write. Newer 10KE has a dual port EAB that will help. mathai@ecf.toronto.edu wrote: > Hi, I'm designing a small RISC on a Flex10k20 and have run into a problem > implementing my register file. > > The register file I want is 16 regs deep, each with width 16 bits. I need > five data out (read) ports (two to the alu, three so I can do branch > condition detection and program counter loads on a branch), and one data > in (write) port. I tried to implement this as 16 registers with the output > ports as five huge 16:1 16 bit muxes. On compilation and fitting, I found > that this was must too large for the Flex10k20. > > My question ... is there a more efficient way to implement this kind of > functionality? > > Thanks for your advice, > Nebu -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15241
This is a multi-part message in MIME format. --------------8AFB531CFA4E82CF4A604E5A Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit That's fine for Alrtera parts ....but I need a tool or method (preferably something automated) that supports different FPGA brands and devices. Thanks for the link though ... :-) Carlhermann Schlehaus wrote: > > Hi, > > ALTERA offers in their data book and as an application note (*.pdf) a > calculation sheet for power estimation. > > Ciao, CS > Richard Guerin <guerin2@home.com> schrieb in Nachricht > 36E9C804.13E88966@home.com.../// > >Can anyone suggest a good post-route power estimation method/tool for > >FPGA's ? (realize that this is highly dependent on frequency and > >probability of switching events .... Pav=CL*VDD^2*f) --------------8AFB531CFA4E82CF4A604E5A Content-Type: text/x-vcard; charset=us-ascii; name="guerin2.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Richard Guerin Content-Disposition: attachment; filename="guerin2.vcf" begin:vcard n:Guerin;Richard x-mozilla-html:TRUE adr:;;;;;; version:2.1 email;internet:GuerinRI@USA.net x-mozilla-cpt:;-1 fn:Richard Guerin end:vcard --------------8AFB531CFA4E82CF4A604E5A--Article: 15242
As far as I can tell, there is no way with Xilinx constraints to completely time a circuit that uses an internally generated clock. You have to guess, try, and do manual stuff to analyze what you have. pad to divider clock input (or even a comb. circuit) divider output to global net global net to input/output pins You can constrain the pad to divider (or pad to instantiated bufg if it's a comb. path) and the bufg to output separately. but you can't set a max over the whole thing. Have fun with hold time calculations. I've tried to explain this to Xilinx people, but they say "Well, you just can't do that!" and shrug it off as insignificant. Wait until you try removing all the false paths caused by a multicycle internal tri-state bus without eliminating the paths you care about. bruce hdl_fan@my-dejanews.com wrote in message <7c046k$k09$1@nnrp1.dejanews.com>... >1. Shall I give two OFFSET constraints for both directions of > an inout port in the SAME UCF file? I am using both directions > of these pads occasionally in the design. > > NET "ram_data_bus<*>" OFFSET=IN 10 BEFORE ram_if_clk ; > NET "ram_data_bus<*>" OFFSET=OUT 10 AFTER ram_if_clk ; > >2. Some pads are driven by logic triggered by an internal clock > but not external clock. I tried to constrain these pads with: > > NET "some_pin<*>" OFFSET=IN 10 BEFORE internal_clk ; > > where internal clock is running 12.5 MHz and derived from > 25 MHz. But Xilinx Design Manager gave error: > > ERROR:basts:168 - NET 'internal_clk' , which is the reference clock net > for the OFFSET 'some_pin<4> IN : 10000.000000 pS : BEFORE : internal_clk', > is not a pad related net (not driven by a pad). > > How can I give constraint to pad via internal clock??? > > Utku > >-----------== Posted via Deja News, The Discussion Network ==---------- >http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15243
Hi ! What about jitter ? if you not mined from jitter them i think i can help you. Sven Svensson wrote: > Does anyone have a suggestion on how to make a clock multiplier > according to specs below: > > Fin: 10 Hz - 2000 Hz > Fout: Fin*100 > > I would like to use a FPGA but other ideas are also appreciated. > > SvenArticle: 15244
Lisa Nangel wrote: > > I am currently trying to figure out how to improve an adder. An n-bit > adder can be constructed by cascading n full adders in series, with the > carry into stage i, Ci, coming from the output of stage i-1. The carry > into stage 0, C0, is 0. If each stage takes T nsec to produce its sum > and carry, the carry into stage i will not be valid until iT nsec after > the start of the addition. For large n the time required for the carry > to ripple through to the high-order stage may be unacceotably long. I > want to design an adder that works faster. I believe that it has > something to do with Ci being able to be expressed in terms of the > operand bits Ai-1 and Bi-1 as wekk as the carry Ci-1. Using this > relationship it is possible to express Ci as a function of the inputs to > stages 0 to i-1, so all the carries can be generated simultaneously. > Can anyone help to improve the adder? That what's called a carry look-ahead adder, and you are correct the idea is to divide the large adder into smaller adders, and calculate the carry-in directly from the lower input bits instead of waiting for the carry-out from the previous stage. Another way of making a fast adder is a carry select adder, in that you make two adders for all the higher sections, one that calculates the output with carry in = '1' and one with carry in ='0', and you then use the carry out from the lower stage to choose which output to use. (Sounds alot like a school problem, so you should be able to find it in your book ;)) --L2C --___--_-_-_-____--_-_--__---_-_--__---_-_-_-__--_---- Lasse Langwadt Christensen, MSEE (to be in 1999) Aalborg University, Department of communication tech. Applied Signal Processing and Implementation (ASPI) http://www.kom.auc.dk/~fuz , mailto:langwadt@ieee.orgArticle: 15245
In article <7ck620$dcr@moe.tas.drs.com>, David Gesswein <djg@drs- esg.com> writes >I just lost several days tracking down a Xilinx problem and thought I would >pass it on so others don't have the same problem. Wouldn't be necessary if there was a primitive synchronizer flip-flop, which could not be duplicated, allowed violations of setup and hold time, and which had a (possibly much) longer Tco than a normal FF. As Peter Afke has pointed out, the devices are excellent as synchronizers, and there is not much point in having 8 or 24 clocks if you don't have some synchronizers on chip. But it seems to be another case where the tools are a little behind the hardware. > >We were having problems with an output being intermittent and finally found >using epic that the router had created two copies of a flip flop used to >sync an async input so we had the "same" signal both active and inactive >depending on which flip flop the logic was connected to. The GUI button to >prevent replicating logic doesn't prevent replicating flip flops in the >same CLB. They have an solution record >http://www.xilinx.com/techdocs/3813.htm that you set a special environment >variable and it won't do this. set CM_EXCLUDE_XQYQ=TRUE -- Paul Walker 4Links phone/fax paul@4Links.co.uk P O Box 816, Two Mile Ash +44 1908 http://www.4Links.co.uk Milton Keynes MK8 8NS, UK 566253Article: 15246
Hi, I'm new to Foundation Express (just upgraded my Foundation Student Edition v1.3 to v1.4 with Foundation Express), so don't shoot me if this is a stupid question ;) The Esperan Master Class Lite tutorial states that you can either instantiate or infer IOBs in Foundation Express, but it doesn't really show you how to do this. I found out that if I instantiate IBUFs and OBUFs (this is not really technology independent VHDL, is it?), then the design synthesises as it should. However, if I don't instantiate these BUFs, then Foundation Express regards my top-level inputs and outputs as unconnected and optimizes them away (leaving me with an empty design). So, how do you correctly infer IOBs in VHDL? Thanks, -- name : Jo Depreitere | University of Ghent e-mail : jdp@elis.rug.ac.be | Electronics and Information Systems Dept. Phone : ++32+9/264 34 09 | Sint-Pietersnieuwstraat 41, B-9000 Ghent Fax : ++32+9/264 35 94 | http://www.elis.rug.ac.be/~jdpArticle: 15247
Jo Depreitere wrote:
> The Esperan Master Class Lite tutorial states that you can either instantiate
> or infer IOBs in Foundation Express, but it doesn't really show you how to
> do this. I found out that if I instantiate IBUFs and OBUFs (this is not
> really technology independent VHDL, is it?), then the design synthesises
> as it should.
No, it's not technology-independent, but then again neither is your finished
FPGA - you've got to freeze the pinout somewhere in the design flow...
but I agree that it can seem ugly, and loses the portability which is a
big win of using VHDL/Verilog.
> However, if I don't instantiate these BUFs, then Foundation Express regards
> my top-level inputs and outputs as unconnected and optimizes them away
> (leaving me with an empty design).
Hmmm. I use Synplify which automatically adds I/O pads to the ports
of the top-level entity by default. I thought FPGA Express did the same.
Maybe you have switched off a compiler option that does this? Or
maybe you have done something strange which prevents FPGA Express
from deciding correctly which is your top-level entity? Try it
with something very simple like a single gate, described in just
one entity/architecture, as a sanity check.
My own preference has always been to keep the VHDL/Verilog technology-
independent, build a schematic symbol to represent the top-level entity,
then drop that down in a top-level schematic which has I/O pads and
buffers as well. There are two drawbacks that I can see to this scheme:
(1) as we go to 300-pin and bigger packages, a schematic description of
the pinout will start to get unwieldy and error-prone;
(2) in some design environments, it is difficult or impossible to use
a HDL test bench on a schematic
Its big advantage is that the technology-independent HDL part is kept
separate from the messy practical device-dependent bit. You can
also conveniently tie-off various optional inputs on the HDL block
in the top level schematic, equivalent to "bond-out options".
HTH
Jonathan Bromley
Article: 15248Jonathan Bromley wrote: > > Hmmm. I use Synplify which automatically adds I/O pads to the ports > of the top-level entity by default. I thought FPGA Express did the same. > Maybe you have switched off a compiler option that does this? There is a checkbox which allows you to disable the insertion of I/O pads (for macros), but I didn't check this box. So, I guess that's not the problem. > Or maybe you have done something strange which prevents FPGA Express > from deciding correctly which is your top-level entity? How does a synthesiser decide what is the top-level entity? Should the inputs and outputs in the port-part of the entity have special attributes? I just have a top-level entity with input and output signals declared in the port section; what more should you do? > Try it with something very simple like a single gate, described in just > one entity/architecture, as a sanity check. It was a one-entity architecture (but with more than a single gate). Well, I'll try the one gate approach and see what happens. > My own preference has always been to keep the VHDL/Verilog technology- > independent, build a schematic symbol to represent the top-level entity, > then drop that down in a top-level schematic which has I/O pads and > buffers as well. Yes, that's what I've done first; and this works well. I just wanted to try all different aspects (full-VHDL, mixed VHDL/schematics, XNF-netlists instantiated in VHDL, and so on). >There are two drawbacks that I can see to this scheme: > (1) as we go to 300-pin and bigger packages, a schematic description of > the pinout will start to get unwieldy and error-prone; > (2) in some design environments, it is difficult or impossible to use > a HDL test bench on a schematic > Its big advantage is that the technology-independent HDL part is kept > separate from the messy practical device-dependent bit. You can > also conveniently tie-off various optional inputs on the HDL block > in the top level schematic, equivalent to "bond-out options". Yep, I agree with you. Thanks for your reaction, -- name : Jo Depreitere | University of Ghent e-mail : jdp@elis.rug.ac.be | Electronics and Information Systems Dept. Phone : ++32+9/264 34 09 | Sint-Pietersnieuwstraat 41, B-9000 Ghent Fax : ++32+9/264 35 94 | http://www.elis.rug.ac.be/~jdpArticle: 15249
Jo Depreitere wrote: > Jonathan Bromley wrote: > > > > Hmmm. I use Synplify which automatically adds I/O pads to the ports > > of the top-level entity by default. I thought FPGA Express did the same. > > Maybe you have switched off a compiler option that does this? > > There is a checkbox which allows you to disable the insertion of I/O pads > (for macros), but I didn't check this box. So, I guess that's not the > problem. > > > Or maybe you have done something strange which prevents FPGA Express > > from deciding correctly which is your top-level entity? > > How does a synthesiser decide what is the top-level entity? Should > the inputs and outputs in the port-part of the entity have special > attributes? I just have a top-level entity with input and output > signals declared in the port section; what more should you do? > The top level entity is the file wich containts the other files. And these files can contains files too. You can have multi level. The top level instantiates the level -1 components. The level -1 instantiates the level -2 components... and so on. You should not do more. > > Try it with something very simple like a single gate, described in just > > one entity/architecture, as a sanity check. > > It was a one-entity architecture (but with more than a single gate). > Well, I'll try the one gate approach and see what happens. > If all you have only one file, this file is your top level. You can instantiate components or/and write logic equations inside. > > > My own preference has always been to keep the VHDL/Verilog technology- > > independent, build a schematic symbol to represent the top-level entity, > > then drop that down in a top-level schematic which has I/O pads and > > buffers as well. > > Yes, that's what I've done first; and this works well. I just wanted > to try all different aspects (full-VHDL, mixed VHDL/schematics, XNF-netlists > instantiated in VHDL, and so on). > > >There are two drawbacks that I can see to this scheme: > > (1) as we go to 300-pin and bigger packages, a schematic description of > > the pinout will start to get unwieldy and error-prone; > > (2) in some design environments, it is difficult or impossible to use > > a HDL test bench on a schematic > > Its big advantage is that the technology-independent HDL part is kept > > separate from the messy practical device-dependent bit. You can > > also conveniently tie-off various optional inputs on the HDL block > > in the top level schematic, equivalent to "bond-out options". > > Yep, I agree with you. > > Thanks for your reaction, > > -- > name : Jo Depreitere | University of Ghent > e-mail : jdp@elis.rug.ac.be | Electronics and Information Systems Dept. > Phone : ++32+9/264 34 09 | Sint-Pietersnieuwstraat 41, B-9000 Ghent > Fax : ++32+9/264 35 94 | http://www.elis.rug.ac.be/~jdp Do you use vhdl or schematic entry? What is your error message exactly? Good luck. Michel Le Mer Gerpi sa (Xilinx Xpert) 3, rue du Bosphore Alma city 35000 Rennes France (02 99 51 17 18) http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htm
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