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We are looking for a USB Host IP core for an ASIC project. Can anybody help? If you have used one before did you have any problems integrating it ? Cheers Dave GlentonArticle: 15651
I agree with Don. Tri-State Busses are much more efficient. Muxes can suck up logic, fast. Also, if your muxes get wide, you might have to use multi-level muxes which add delays. Tri-state busses are also very fast and width-independent. Don Husby <husby@fnal.gov> wrote in message news:7eaguq$j3c$1@info3.fnal.gov... > Andreas Doering <doering@iti.mu-luebeck.de> wrote: > > The following are some ideas I got when doing > > a rather area intensive design with XILINX 40150XV/40250XV parts. > > My design is quite multiplexer intensive. > > Lucent's Orca 2Txx FPGAs are pretty good for multiplexing. > Without much effort, each logic block can be a 4-bit wide > 3-to-1 mux (1 logic level) or a 2-bit wide 4-to-1 mux > (1.5 logic levels) > > Using tristate busses for muxes is also more efficient. > The Orca part has 8 tristate drivers per PFU and can drive > horizontally or vertically. >Article: 15652
Richard, I think right now Altera is outpacing Xilinx. Still, for DSP applications, the Xilinx architecture is a hands down winner for reasons I've cited here before. If Georgi is looking to learn about FPGAs for DSP, he is well advised to use xilinx. On the other hand, Altera is a bit more tolerant to placement, so their device is more friendly to the novice user and to synthesis. Richard Schwarz wrote: > Georgi, > > There are many vendors out there as you have said. By far the most popular is > XILINX. Altera is coming up behind them, and is keeping them honest, but my > suggestion is to go with them. XILINX Foundation tools run on WIN95 and NT and > can be purchased with Synopsys VHDL and VERILOG as well as schematic capture. > The same package also supports their CPLD line. I suggest that you start out > with an HDL design environment. With this you should have the following > components: > > 1) Simulator Package > 2) Synthesis Tool > 3) Place and route software > 4) Test and Development Board > > These items can be costly. Buying the XILINX FOUNDATION series will satisfy > items 2 and 3. At APS you can get the Foundation Series software packaged with a > VHDL simulator and TEST and Development board also. Typically you would pay up > to $20,000 for complete packages like this. But if you are willing to settle for > medium size FPGAs you can get a complete package like this for as little as > $1700.00. This includes a PEakVHDL simulator, XILINX Router, Synopsys FPGA > Xpress synthesis, and the APS-X84 FPGA board. I actually reccomend that you get > this package with the APS-X240 board with a SPARTAN XCS40XL FPGA installed. The > APS-X240 board is in a nice small package, with a PC-104 port on it if you want > to develop download and control the design from the PC104(ISA) bus. An ISA > carrier board can be purchased to allow you access to the PC's suite of > developemnt tools to control the board. With a C compiler for example you can > configure your FPGA in circuit, and test and control it real time. Or, if you > want to use the board stand alone, you connect up the optional desktop or wall > power supply, and an XCHECKER or parallel download cable (comes with the kit) > and download the design from your PC parallel port or serial port. When the > design is finished, and stable you can then put your design in EPROM (we use > ATMELs reprogrammable serial proms) and remove the download cable. The board > also has optional on board RAM (256K), and an oscillator socket. The boards size > and standalone capabilty are really nice. > > If you are willing to spend a little more, the X240 can be purchased with a > PC104 computer board which has its own serial, parallel, and ETHERNET > connection. This board (which is not yet on our website). In this configuration > I have a laptop with Borland C and the XILINX Foundation software. I can > develop NETWORK or serial controllable FPGAs. The Computer board is an INTEL > based PC with on board FLASH which can hold the C programs I develop for > controlling my design. A reduced TCP/IP stack is already contained in the > computer, and so I can connect my FPGA right up to a network and control it, or > I can do control from one of the two on board serial ports. The X240 board can > take up to a Xc4085 currently, and will have a VIRTEX version ready shortly. > And, since the format is PC104, if I need more FPGA horsepower, I simply stack > on a second or third or more X240 card. Each card can be strapped for a > different address on the PC-104 card. You can get a lot of FPGA power this way. > > Anyway, you get sample code and examples with our development boards which > really help get you over the learning curve hump quick. And our FPGA boards are > flexible enough to actually become your product. > > Take a look at our packages at http://www.apsfpga.com and give me a yell if I > can be of any more help. > > Rick ( rick@apsfpga.com ) > > Georgi Beloev wrote: > > > Hi, > > > > I want to learn FPGA design and I have no experience in this field. I want > > to use FPGAs for DSP applications and simple RISC microprocessors. However > > there are many vendors out there - Xilinx, Atmel, Altera, etc. Which vendor > > and FPGA family are best in terms of good development environment (for PCs), > > free software, built-in schematic and VHDL/Verilog entry, on-chip SRAM, unit > > price, etc.? > > > > TIA > > -- > > Georgi Beloev > > gbeloev@iname.com > > -- > __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ > > Richard Schwarz, President > Associated Professional Systems Inc. (APS) > email: richard@associatedpro.com > web site: http://www.associatedpro.com > Phone: 410-569-5897 > Fax: 410-661-2760 > > __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15653
The key is to know the architecture and be aware how your design is going to map into it. In the case of combinatorial logic, limit the inputs to less than the number of inputs that can be implemented in the target number of levels. For instance, if you are designing for one level of logic in xilinx 4K, you generally want to keep the combinatorial inputs at each pipeline level to 5 or fewer inputs (4 inputs will allow denser packing, and there are a subset of functions up to 9 inputs that can be implemented in one level). For state machines, the same applies. One technique that usually works well for larger state machines is to use a one-hot encoding, which will limit the combinatorial inputs to each register. pandey@my-dejanews.com wrote: > Hello, I am designing a PCI bridge on Xilinx 4K series. What I have to > understand is the levels of logic mapping to the device. I have to see that I > design keeping in mind the safe levels of logic so as to leave minimum effort > to the Place and Route tool. This involves: 1> Breaking all the combinatorial > logic to a pipelined architecture 2> Making smaller state machines so as to > reduce number of inputs and thus levels of logic. This has been my approach > so far. Does anybody who designs FPGAs know of how these approaches are > exactly implemented. Is there some literature available on FPGA specific > designing. Thanks in advance Shardendu Pandey > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15654
--------------0A5136EC4DB0543A4301A76A Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit vanan wrote: > Hi! > > Anyone know about 8bit x 1K FIFO can implemented in FPGA ? > > If yes , Next after the size, you have to decide on the speed, and the synchronous or asynchronous nature of the read and write clocks. 8k bits of storage can be handled in Xilinx XC4000-series devices, require 256 CLBs just for storage, and would fit into an XC4008 ( 512 CLBs if dual-port RAM is required for speed reasons, which, including control, would fill an XC4013). In larger devices, you would of course have more logic left for other purposes. 50 MHz operation is reasonable to expect, 100 MHz is tricky. Xilinx Virtex has dual-ported BlockRAMs, each 4kbits. The smallest Virtex device (V50) has eight of these blocks. Two BlockRAMs are thus sufficient even for the most demanding application. An app note (XAPP131) describes a design that can run ( and has been demonstrated to run ) at 170 MHz with asynchronous read and write clocks, the most demanding case imaginable. At lower speed, the control can be drastically simplified. Generating glitch-free FULL and EMPTY control signals is the art in FIFO design. Everything else is trivial, especially since we now have large dual-ported RAMs. Click on http://www.xilinx.com/xapp/xapp131.pdf Peter Alfke, Xilinx Applications --------------0A5136EC4DB0543A4301A76A Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> <BODY BGCOLOR="#FFFFFF"> vanan wrote: <BLOCKQUOTE TYPE=CITE>Hi! <P>Anyone know about 8bit x 1K FIFO can implemented in FPGA ? <P>If yes ,</BLOCKQUOTE> Next after the size, you have to decide on the speed, and the synchronous or asynchronous nature of the read and write clocks. <P>8k bits of storage can be handled in Xilinx XC4000-series devices, require 256 CLBs just for storage, and would fit into an XC4008 ( 512 CLBs if dual-port RAM is required for speed reasons, which, including control, would fill an XC4013). In larger devices, you would of course have more logic left for other purposes. 50 MHz operation is reasonable to expect, 100 MHz is tricky. <P>Xilinx Virtex has dual-ported BlockRAMs, each 4kbits. The smallest Virtex device (V50) has eight of these blocks. Two BlockRAMs are thus sufficient even for the most demanding application. An app note (XAPP131) describes a design that can run ( and has been demonstrated to run ) at 170 MHz with asynchronous read and write clocks, the most demanding case imaginable. <BR>At lower speed, the control can be drastically simplified. <P>Generating glitch-free FULL and EMPTY control signals is the art in FIFO design. Everything else is trivial, especially since we now have large dual-ported RAMs. <P>Click on <P><U><A HREF="http://www.xilinx.com/xapp/xapp131.pdf">http://www.xilinx.com/xapp/xapp131.pdf</A></U><U></U> <P>Peter Alfke, Xilinx Applications </BODY> </HTML> --------------0A5136EC4DB0543A4301A76A--Article: 15655
--------------D861C676D187EFD0A14459A3 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit vanan wrote: > Hi! > > Anyone know about 8bit x 1K FIFO can implemented in FPGA ? > > If yes , Next after the size, you have to decide on the speed, and the synchronous or asynchronous nature of the read and write clocks. 8k bits of storage can be handled in Xilinx XC4000-series devices, require 256 CLBs just for storage, and would fit into an XC4008 ( 512 CLBs if dual-port RAM is required for speed reasons, which, including control, would fill an XC4013). In larger devices, you would of course have more logic left for other purposes. 50 MHz operation is reasonable to expect, 100 MHz is tricky. Xilinx Virtex has dual-ported BlockRAMs, each 4kbits. The smallest Virtex device (V50) has eight of these blocks. Two BlockRAMs are thus sufficient even for the most demanding application. An app note (XAPP131) describes a design that can run ( and has been demonstrated to run ) at 170 MHz with asynchronous read and write clocks, the most demanding case imaginable. At lower speed, the control can be drastically simplified. Generating glitch-free FULL and EMPTY control signals is the art in FIFO design. Everything else is trivial, especially since we now have large dual-ported RAMs. Click on http://www.xilinx.com/xapp/xapp131.pdf Peter Alfke, Xilinx Applications --------------D861C676D187EFD0A14459A3 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit <HTML> <BODY BGCOLOR="#FFFFFF"> vanan wrote: <BLOCKQUOTE TYPE=CITE>Hi! <P>Anyone know about 8bit x 1K FIFO can implemented in FPGA ? <P>If yes ,</BLOCKQUOTE> Next after the size, you have to decide on the speed, and the synchronous or asynchronous nature of the read and write clocks. <P>8k bits of storage can be handled in Xilinx XC4000-series devices, require 256 CLBs just for storage, and would fit into an XC4008 ( 512 CLBs if dual-port RAM is required for speed reasons, which, including control, would fill an XC4013). In larger devices, you would of course have more logic left for other purposes. 50 MHz operation is reasonable to expect, 100 MHz is tricky. <P>Xilinx Virtex has dual-ported BlockRAMs, each 4kbits. The smallest Virtex device (V50) has eight of these blocks. Two BlockRAMs are thus sufficient even for the most demanding application. An app note (XAPP131) describes a design that can run ( and has been demonstrated to run ) at 170 MHz with asynchronous read and write clocks, the most demanding case imaginable. <BR>At lower speed, the control can be drastically simplified. <P>Generating glitch-free FULL and EMPTY control signals is the art in FIFO design. Everything else is trivial, especially since we now have large dual-ported RAMs. <P>Click on <P><U><A HREF="http://www.xilinx.com/xapp/xapp131.pdf">http://www.xilinx.com/xapp/xapp131.pdf</A></U> <P>Peter Alfke, Xilinx Applications </BODY> </HTML> --------------D861C676D187EFD0A14459A3--Article: 15656
To fit it in the 10K70, there is a trick called serial distributed arithmetic that does the filtering bit-serially. One way of doing a serial by parallel multiply is to use a scaling accumulator so that the sum is shifted and recirculated. Then one multiplicand is added to the hisfted result for each one bit in the serial multiplicand. So the multiplier is simply an accumulator and a word-wide AND gate. Now if you wanted to do a 4 input multiply accumulate, you could put four of these scaling accumulator multpliers in parallel then add the results in a tree to get the sum of the 4 products. Since addition is associative, you can instead, add the one bit by word wide partial products in a tree and perform the scaling accumulate on the sum. That saves you several accumulators. More importantly, if you look at the 4 serial inputs and the adder tree, that logic can be realized as a 4 input by n bit output look-up table. Now you've got a 4 input (serial inputs) MAC with 4 unique constant coefficients implemented in a small look-up table and a scaling accumulator. The addition of a delay queue at the input gives you a 4 tap FIR filter. To expand it to more taps, you add the contributions of several 4 input LUTs together in an adder tree before doing the scaling accumulate. This makes for a quite compact filter, although it has to be clocked as many times as there are bits in the input for each sample. To speed things up at the cost of hardware, you can compute two bits at a time in parallel LUTs + adder trees, combine those results with the more significant bit shifted up by one with respect to the other and input to a scaling accumulator that shifts by two bits every clock. This is how you get lots of filter taps in the FPGA. Now, it does seem to me that you could get by with fairly small input widths and coefficient widths since you should have a significant processing gain through the matched filter. The input widths will not appreciably reduce the size of the filter if it is completely serial, but the coefficient widths will. batman2054@my-dejanews.com wrote: > Hello. Let me explain in more detail. I will construct two boards, both using > FPGA, say Altera 10K100. One is a CDMA transmitter, another is a CDMA > receiver. No RF nor IF, just baseband signal. :) The output of the > transmitter use a D/A convert while the input of the receiver use an A/D > convert. The chip rate is 4M cps, the sample rate for demodulation is 16M > sps, the sample rate for acquisition is 4M sps, the sample data width is > 6bits. The requirment is the acquisition must use Matched Filter. I think the > nature thought of of the implementation of a Digital Matched Filter is to > build a multi-bits delay line (parallel or serial, say using shift-regs.), a > lot of muliplier, then a very big adder. But I think it will cost too much > resourse (gates) and the time-delay of the adder is too long. So I want to > know does anyone have dealed with such case before and how they do it. Thanks > for your kind response to my question. And as for the so called environmental > limits is just my lab has purchased some Altera 10K100 several days ago. :) > And I have not used the Xilinx device for 2 or 3 years. Thanks again. > > Forest Niuman > niuman@263.net > > In article <37057F8B.C90AD922@ids.net>, > Ray Andraka <randraka@ids.net> wrote: > > Let's start from the top. > > > > Is there a specific Altera device you need to target? What is the precision needed > > .................. > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15657
ems@riverside-machines.com.NOSPAM wrote: > On Fri, 02 Apr 1999 09:27:10 -0500, Ray Andraka <randraka@ids.net> > wrote: > > >ems@riverside-machines.com.NOSPAM wrote: > > > >> Well, this is probably not the help you're looking for, but: > >> > >> (a) Are you actually trying to implement CDMA baseband in a 10K? You'd > >> need a large board full of them. Presumably you're just doing some > >> filtering? > > > >No true, You should be able to do a 256 tap 12 bit non-symmetric filter in a > >10K70 at the required 4MSPS, but Xilinx is still the better choice because of the > >delay queue implementation. > > my point was that he wants to implement CDMA baseband, as he said. > this takes a **lot** more than one 256-tap filter. True, but there are some other optimizations that can be done to help reduce the size. > > > >> (b) My first reaction to a 256-tap FIR, at 4 Meg, is that it may be > >> impossible in an Altera device. You need to run bit-serial, and that's > >> much easier in a Xilinx, using distributed memory. > > > >Only easier in Xilinx because of the implementation of the delay queue. The LUTs > >in the Altera are faster, but the global routing will keep both to roughly 8 MSPS > >max with 12 bit inputs. > > the issue here is area, not speed (since 4M is not a problem), and > what you can do to fit this into a reasonably sized device. i had > assumed that any xilinx advantage was due to both the delay queue > implemention, and the use of ROMs for partial product storage. at any > rate, we both appear to be agreed that this is easier, if not 'much' > easier, in a xilinx. > The altera LEs can also be used as ROMs for the partial product storage. I assumed the coefficients stay fixed in the matched filter (a reasonable assumption if the channel equalization is fixed). If the matched filter coefficients need to be updated, the xilinx RAM capability makes it possible to rewrite the partial products, where Altera requires the design to be recompiled (the LUTs in the Altera LE cannot be made to act like RAM). > >> (c) You need to do the matching in the analog front-end. Why do you > >> want to do it in digits? > > >Come again? The matched filter can be translated through the demodulator (the > >demod and the filters are all time invariant linear systems), and for that matter > >can be lumped with the demodulation filter and any decimating filters if you do > >the demodulation from IF digitally too. Doing the matched filter digitally at > >baseband has several advantages over doing an analog passband matched filter, > >although it will cost a bit more in power. > > ok, let me rephrase that. you can buy off-the-shelf components, > specifically for CDMA applications, which carry out any necessary I/Q > matching in analog. this saves you a lot of hassle in digital, meets > the specs and, by your estimate, saves you a 10K70. seems like a > pretty good reason to do it in analog to me. A digital matched filter gives you much much more flexibility in tailoring the filter response and depending on implementation can provide a lower noise floor. I've used digital matched filtering and demodulation to baseband in FPGAs for radar applications for this very reason. > > > evan -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15658
Hi: I want to find out a source who sells IP core for LCD display controller. HenryArticle: 15659
Try the Altera Baseline software, it has all you need to start off with and compiles quite a few parts (typically the smaller parts) but is an excellent starting point and it's totally FREE! All you need to do is design a prototyping board and build yourself a download cable of which the circuit is in the Altera Data book. Baseline also includes the simulator with Pd (about time too!) Georgi Beloev wrote in message <7eba1k$tlo$1@weber.techno-link.com>... >Hi, > >I want to learn FPGA design and I have no experience in this field. I want >to use FPGAs for DSP applications and simple RISC microprocessors. However >there are many vendors out there - Xilinx, Atmel, Altera, etc. Which vendor >and FPGA family are best in terms of good development environment (for PCs), >free software, built-in schematic and VHDL/Verilog entry, on-chip SRAM, unit >price, etc.? > >TIA >-- >Georgi Beloev >gbeloev@iname.com > > >Article: 15660
Hi, I'm trying to write some verilog code for a veterbi decoder (Trellis decoder) using 256-QAM which to be implemented on FPGA. It is my 4th year Electrical Engineering project. Is there anyone who has done any work on viterbi/trellis using verilog? Please e-mail me ASAP. Thanks. ACArticle: 15661
Georgi,
There are many vendors out there as you have said. By far the most popular is
XILINX. Altera is coming up behind them, and is keeping them honest, but my
suggestion is to go with them. XILINX Foundation tools run on WIN95 and NT and
can be purchased with Synopsys VHDL and VERILOG as well as schematic capture.
The same package also supports their CPLD line. I suggest that you start out
with an HDL design environment. With this you should have the following
components:
1) Simulator Package
2) Synthesis Tool
3) Place and route software
4) Test and Development Board
These items can be costly. Buying the XILINX FOUNDATION series will satisfy
items 2 and 3. At APS you can get the Foundation Series software packaged with a
VHDL simulator and TEST and Development board also. Typically you would pay up
to $20,000 for complete packages like this. But if you are willing to settle for
medium size FPGAs you can get a complete package like this for as little as
$1700.00. This includes a PEakVHDL simulator, XILINX Router, Synopsys FPGA
Xpress synthesis, and the APS-X84 FPGA board. I actually reccomend that you get
this package with the APS-X240 board with a SPARTAN XCS40XL FPGA installed. The
APS-X240 board is in a nice small package, with a PC-104 port on it if you want
to develop download and control the design from the PC104(ISA) bus. An ISA
carrier board can be purchased to allow you access to the PC's suite of
developemnt tools to control the board. With a C compiler for example you can
configure your FPGA in circuit, and test and control it real time. Or, if you
want to use the board stand alone, you connect up the optional desktop or wall
power supply, and an XCHECKER or parallel download cable (comes with the kit)
and download the design from your PC parallel port or serial port. When the
design is finished, and stable you can then put your design in EPROM (we use
ATMELs reprogrammable serial proms) and remove the download cable. The board
also has optional on board RAM (256K), and an oscillator socket. The boards size
and standalone capabilty are really nice.
If you are willing to spend a little more, the X240 can be purchased with a
PC104 computer board which has its own serial, parallel, and ETHERNET
connection. This board (which is not yet on our website). In this configuration
I have a laptop with Borland C and the XILINX Foundation software. I can
develop NETWORK or serial controllable FPGAs. The Computer board is an INTEL
based PC with on board FLASH which can hold the C programs I develop for
controlling my design. A reduced TCP/IP stack is already contained in the
computer, and so I can connect my FPGA right up to a network and control it, or
I can do control from one of the two on board serial ports. The X240 board can
take up to a Xc4085 currently, and will have a VIRTEX version ready shortly.
And, since the format is PC104, if I need more FPGA horsepower, I simply stack
on a second or third or more X240 card. Each card can be strapped for a
different address on the PC-104 card. You can get a lot of FPGA power this way.
Anyway, you get sample code and examples with our development boards which
really help get you over the learning curve hump quick. And our FPGA boards are
flexible enough to actually become your product.
Take a look at our packages at http://www.apsfpga.com and give me a yell if I
can be of any more help.
Rick ( rick@apsfpga.com )
Georgi Beloev wrote:
> Hi,
>
> I want to learn FPGA design and I have no experience in this field. I want
> to use FPGAs for DSP applications and simple RISC microprocessors. However
> there are many vendors out there - Xilinx, Atmel, Altera, etc. Which vendor
> and FPGA family are best in terms of good development environment (for PCs),
> free software, built-in schematic and VHDL/Verilog entry, on-chip SRAM, unit
> price, etc.?
>
> TIA
> --
> Georgi Beloev
> gbeloev@iname.com
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President
Associated Professional Systems Inc. (APS)
email: richard@associatedpro.com
web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Article: 15662
The APS-X240 boards will soon be available with VIRTEX and on board
RS232 drivers as well
as being available with an INTEL based TCP/IP network PC104 carrier
card. The kits will be
offered with XILINX Foundation software. The X240 PC-104 boards are
stackable and each
board can be addressed independently. And with the low cost PC104
carrier card the APS-X240s
are network programmable and controllable.
The APS-X240 board is in a nice small package, with a PC-104 port on it
if you want
to develop download and control the design from the PC104(ISA) bus. An
ISA
carrier board can be purchased to allow you access to the PC's suite of
developemnt tools to control the board. With a C compiler for example
you can
configure your FPGA in circuit, and test and control it real time. Or,
if you want
to use the board stand alone, you connect up the optional desktop or
wall
power supply, and an XCHECKER or parallel download cable (comes with the
Foundation kit) and download the design from your PC parallel port or
serial port. When the
design is finished, and stable you can then put your design in EPROM (we
use
ATMELs reprogrammable serial proms) and remove the download cable. The
board
also has optional on board RAM (256K), and an oscillator socket. The
board's size
and standalone capabilty are really nice.
If you are willing to spend a little more, the X240 can be purchased
with a
PC104 computer board which has its own serial, parallel, and ETHERNET
connection. This board (which is not yet on our website) in this
configuration
can , for example, use a laptop with Borland C and the XILINX
Foundation software to
fully synthesize, route, test, debug and control your designs. The
optional Computer board is
an INTEL based PC with on board FLASH which can hold the C programs
developed for
controlling the design. A reduced TCP/IP stack and DOS operating system
is already contained in the
computer board. FPGA code can be developed and loaded and C control code
can be developed and saved
in the computer board's on board FLASH. I can connect my FPGA right up
to a network and control it, or
I can do control from one of the two on board serial ports. Example
designs are included.
The X240 board can take up to a XC4085 currently, and will have a VIRTEX
version ready shortly.
And, since the format is PC104, if I need more FPGA horsepower, I simply
stack
on a second or third or more X240 card. Each card can be strapped for a
different address on the PC-104 bus. You can get a lot of FPGA power
this way.
You get sample code and examples with our development boards which
really help get you over the learning curve hump quick. And our FPGA
boards are
flexible enough to actually become your product.
Currently an 8 bit version can be purchased with any flavor and size
FPGA in
the XILINX SPARTAN, 4000E/XL/XLA and 5200 seriesFPGAs in the 240pinQFP
The newer 16bit board (with on board RS232 tranceivers) will be
available within a month
followed by the VIRTEX versions. The boards will be available with
XILINX Foundation
kits and download cables.
Take a look at this an our other FPGA packages at
http://www.apsfpga.com.
Rick ( rick@apsfpga.com )
--
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Richard Schwarz, President
Associated Professional Systems Inc. (APS)
email: richard@associatedpro.com
web site: http://www.associatedpro.com
Phone: 410-569-5897
Fax: 410-661-2760
__/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/
Article: 15663>Hi, I'm trying to write some verilog code for a veterbi decoder (Trellis >decoder) using 256-QAM which to be implemented on FPGA. It is my 4th >year Electrical Engineering project. > >Is there anyone who has done any work on viterbi/trellis using verilog? Yes. It is non-trivial, and not something that you should expect can just be given away. Did you have any specific question? I, of course, assume you expected to actually implement it yourself for your 4th year Electrical Engineering project. >Please e-mail me ASAP. > >Thanks. >AC >Article: 15664
Me too... Peter Dennett Email: pdennett@padsoft.com 61 Harbor Lane Web: www.padsoft.com Kemah, TX 77565 Voice: 281 334 3800 Fax: 281 521 1033 G Henry Yogendran wrote in message <370A6FA2.4D0038F1@airwire.com>... > >Hi: > >I want to find out a source who sells IP core for LCD display >controller. > > >Henry >Article: 15665
Hello, Could somone please tell me is there any FPGA for voltage working range 3...6 V? Thanks in advance, AndrewArticle: 15666
Hello, I need a EEPROM to program a Xilinx XC4010XL FPGA. This device requires a 283,424 bits memory for full programming. Atmel has "FPGA Configuration Memories" with 512Kbit and 1Mbit but the package I need is not available (PDIP8). Could someone please tell me the names of other companies which supply these memories in a PDIP8 package? Thanks. Arnaldo -------------------------------------------------------------------- Arnaldo Oliveira Dep. de Electronica e Telec. - Univ. de Aveiro Campus Universitario 3810 Aveiro Portugal tel.: +351 34 370200 fax.: +351 34 381128 email: arnaldo@ua.pt -------------------------------------------------------------------- begin 666 Arnaldo Oliveira.vcf M0D5'24XZ5D-!4D0-"E9%4E-)3TXZ,BXQ#0I..D]L:79E:7)A.T%R;F%L9&\- M"D9..D%R;F%L9&\@3VQI=F5I<F$-"D]21SI5;FEV97)S:61A9&4@9&4@079E M:7)O.T5L96-T<O-N:6-A(&4@5&5L96-O;75N:6-AY_5E<PT*5$E43$4Z16YG M+B!D92!%;&5C='+S;FEC82!E(%1E;&5C;VUU;FEC8>?U97,-"E1%3#M73U)+ M.U9/24-%.C,U,2TS-"TS-S R,# -"E1%3#M#14Q,.U9/24-%.C Y,S$M-#<R M.#@T-PT*5$5,.U=/4DL[1D%8.C,U,2TS-"TS.#$Q,C@-"D%$4CM73U)+.CLS M,#<[0V%M<'5S(%5N:79E<G-I=&%R:6\[079E:7)O.SLS.#$P.U!O<G1U9V%L M#0I,04)%3#M73U)+.T5.0T]$24Y'/5%53U1%1"U04DE.5$%"3$4Z,S W/3!$ M/3!!0V%M<'5S(%5N:79E<G-I=&%R:6\],$0],$%!=F5I<F\@,S@Q,#TP1#TP M05!O<G1U9V%L#0I%34%)3#M04D5&.TE.5$523D54.F%R;F%L9&] =6$N<'0- B"E)%5CHQ.3DY,#0P-U0Q-#0X,S=:#0I%3D0Z5D-!4D0-"@`` ` endArticle: 15667
Modern FPGAs are fast and large enough to handle complex designs. Add HDL
design methods and in-system reconfiguration and you have hardware that can
be developed and managed like software. Software developers take full
advantage of language features to simplify development and support. An
important technique that is largely ignored for synthesis is the use of
descriptive data types. Aside from user defined types for state machine
description, I don't see any encouragement from the press or tool vendors to
use any VHDL type other than std_logic.
The sample VHDL below seems like an obvious example of how to use a VHDL
record. Any number of fields can be added to the signal_stats_t without
changing the top-level code. Consider adding a strobe field (of type
std_logic or maybe boolean) to the record that indicates when the sample
data is valid. Without the record, signals like the data-valid strobe
contribute to code clutter and, even with appropriate names, are hard to
associate with the related data.
Are designers writing code like this and I just don't know it? If not, why
not?
--
Paul Butler
Paul.Butler@natinst.com
National Instruments
Austin, TX
===============================================================
library ieee;
use ieee.std_logic_1164.all;
package type_pack is
subtype cpu_data_t is std_logic_vector(31 downto 0);
subtype address_t is std_logic_vector(2 downto 0);
subtype adc_data_t is std_logic_vector(11 downto 0);
type signal_stats_t is
record
min_sample,
max_sample,
median_sample : adc_data_t;
end record;
end type_pack;
library ieee;
use ieee.std_logic_1164.all;
use work.type_pack.all;
entity adc_example is
port(
clk,
cs,
rd : in std_logic;
address : in address_t;
adc_din : in adc_data_t;
cpu_dout : out cpu_data_t
);
end adc_example;
architecture struct of adc_example is
component adc_measurements
port(
clk : in std_logic;
adc_din : in adc_data_t;
signal_stats : out signal_stats_t
);
end component;
component cpu_interface
port(
clk, cs, rd : in std_logic;
address : in address_t;
signal_stats : in signal_stats_t;
cpu_dout : out cpu_data_t
);
end component;
signal signal_stats : signal_stats_t;
begin
cpux: cpu_interface
port map(
clk => clk,
cs => cs,
rd => rd,
address => address,
signal_stats => signal_stats,
cpu_dout => cpu_dout
);
adcx: adc_measurements
port map(
clk => clk,
adc_din => adc_din,
signal_stats => signal_stats
);
end struct;
Article: 15668Try these links to Celestial Design. http://celestial.ne.mediaone.net/index.html http://celestial.ne.mediaone.net/ip.htm On Tue, 06 Apr 1999 15:33:39 -0500, G Henry Yogendran <yogi@airwire.com> wrote: > >Hi: > >I want to find out a source who sells IP core for LCD display >controller. > > >Henry > Visit Paul's Virtual Garage Sale: http://www.aimnet.com/~pjwhite/virtual_garage_sale.htmlArticle: 15669
The various companies that sell serial configuration PROMs for FPGAs is listed on The Programmable Logic Jump Station at http://www.optimagic.com/companies.html#SPROM. If you need EEPROM instead of one-time programmable (OTP) EPROM, your choices are fairly limited at the moment. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Arnaldo Oliveira wrote in message <370b7033.0@news.ua.pt>... >Hello, > >I need a EEPROM to program a Xilinx XC4010XL FPGA. >This device requires a 283,424 bits memory for full programming. >Atmel has "FPGA Configuration Memories" with 512Kbit and 1Mbit but the >package I need is not available (PDIP8). >Could someone please tell me the names of other companies which supply these >memories in a PDIP8 package? >Thanks. > >Arnaldo > >-------------------------------------------------------------------- >Arnaldo Oliveira >Dep. de Electronica e Telec. - Univ. de Aveiro >Campus Universitario >3810 Aveiro >Portugal >tel.: +351 34 370200 fax.: +351 34 381128 >email: arnaldo@ua.pt >-------------------------------------------------------------------- > > > >Article: 15670
We are designing a MMDS wireless transceiver using 256 QAM which we would like to operate at 200Mbps. Now most of the parts are done. However, I do have problem implementing viterbi decoder part of it. I am following a flow chart provided by Mansoor Chistie of Texas Instrument in IEEE journal. But as you might know it is little difficult to implement in h/w because algorithm is originally done for C and to work with TI DSP processors. Did you work with any existing algorithm/flow chart? Or did you find any reference book helpful? Thanks. Asif "Thomas A. Coonan" wrote: > >Hi, I'm trying to write some verilog code for a veterbi decoder (Trellis > >decoder) using 256-QAM which to be implemented on FPGA. It is my 4th > >year Electrical Engineering project. > > > >Is there anyone who has done any work on viterbi/trellis using verilog? > Yes. > > It is non-trivial, and not something that you should expect can just > be given away. Did you have any specific question? I, of course, > assume you expected to actually implement it yourself for your 4th > year Electrical Engineering project. > >Please e-mail me ASAP. > > > >Thanks. > >AC > >Article: 15671
Hello My problem is not exactly related to FPGAs, but perhaps someone in this news group can help me. I've just finished the implementation of an 8051 application, using only FPGAs. Now I'm writing a report, and I would like to include some comments about the area usage. From the PAR reports I can get everything I need for the FPGA, but I have no idea about the microcontroler. Does anybody know where to find this information? In the original design it was used a DS87C520 microcontroler, but any information about the number of gates of any 8051 family member is welcome. I haven't implemented an 8051 device. I implemented the 8051 application (software + hardware) in VHDL. I'm not interested in the space used by 8051 cores in FPGAs or ASICs. I'm looking for the gate counting of a standard 8051 device. Thanks Eduardo.Article: 15672
There are some papers/information on Viterbi decoding freely available on the Web (although not specifically in Verilog). If these will be of help please let me know and I will try to dig up the info. Tony **** Posted from RemarQ - http://www.remarq.com - Discussions Start Here (tm) ****Article: 15673
There seems to be more support/usage of Xilinx than Altera Devices for DSP Designs (FIRs, FFTs, Cordic, etc). My company already has Altera tools but I don't want to be limited by that choice. Please let me know if you think Altera is better or equivalent for DSP designs (or if you Xilinx is definitely superior). Thanks, I'll sumarise later for the group. Tony **** Posted from RemarQ - http://www.remarq.com - Discussions Start Here (tm) ****Article: 15674
If your looking for background information on Viterbi decoding I can send you some web links. I doubt if you'll find anything specific about Verilog or FPGAs related to Viterbi decoding, but there is information available about Viterbi decoding in VLSI. Good luck Tony **** Posted from RemarQ - http://www.remarq.com - Discussions Start Here (tm) ****
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