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Tony Kirke wrote:
> There seems to be more support/usage of Xilinx than Altera Devices for =
DSP
> Designs (FIRs, FFTs, Cordic, etc).
> My company already has Altera tools but I don't want to be limited by t=
hat
> choice.
> Please let me know if you think Altera is better or equivalent for DSP
> designs (or if you Xilinx is definitely superior).
> Thanks,
> I'll sumarise later for the group.
> Tony
>
> **** Posted from RemarQ - http://www.remarq.com - Discussions Start Her=
e (tm) ****
First of all, you CAN do large DSP designs in Altera 10K. I've successful=
ly
implemented +100 MHz 32 tap FIR filters synthesized from generic VHDL cod=
e ( Synplify)
( 16 bit Cordic at 40 MHz, 16 bit FFT at 50 MHz)
There are some limitations worth taking note of:
Lack of local interconnect slows down your design considerably when filli=
ng up the
device.
If you need to use clock enable for stalling pipelines, you are out of lu=
ck since the
CE input is shared with the LUT input needed for arithmetic mode. (This i=
s fixed in
20K)
The I/O cell has only one register making external bi-directional interfa=
ces (high
speed RAM) hard to accomplish. (You will need two pins tied together for =
each data
signal).
Lack of PLLs (or DLLs) make multirate filtering designs dependent on exte=
rnal timing
resources.
On the positive side:
The architecture synthesizes well, little floorplanning is needed. This c=
an have a
large impact on designer productivity and is probably the biggest advanta=
ge over
Xilinx (at least 4k family)
Opinion:
Xilinx 4k may give you a performance edge if you are willing to invest mo=
re time in
floorplanning.
The Virtex family with its vector based interconnect has the potential to=
be synthesis
friendly. It also adds resources enabling multipliers to run at higher sp=
eeds.
Givens good synthesis tool support, the Xilinx Virtex family seems most a=
pt to DSP
development.
--
Hans Christian L=F8nstad Data Respons AS
Sandviksveien 26
Real Time 1322 H=F8vik
Professionals Norway
mailto:Hans.Christian.Lonstad@datarespons.no
http://www.datarespons.no
Article: 15701Although there's no "official" nor "registered" FAQ for this newsgroup, Steven K Knapp's optimagic Website comes close and includes a FAQ at <http://www.optimagic.com/faq.html>. Maybe some kind person (Steve?) could post a pointer to that site at monthly or fortnightly intervals, with a suitable "subject" such as "Attention, newbies" or "Welcome to comp.arch.fpga"? That way anyone unsure of the reaction to asking a simple or possibly trivial question could at least check out the FAQ. -- Tim Forcer tmf@ecs.soton.ac.uk The University of Southampton, UK The University is not responsible for my opinionsArticle: 15702
Hervé Echelard wrote:
>
> I want use Xchecker to download program into Xilinx
> (serial cable), and with the same interface, exchange
> data with the computer (like Terminal into Windows).
>
> Then, I search plan about the xilinx serial download cable.
Nice idea, but I think you'll find it quite a challange!
The Xilinx serial download cable has a 9-way D-type using pins 2, 3, 5
and 6 (there may be linking of other pins), and terminates in a pod
which contains the following:
LT1181 TTL/RS232 transceiver
556 dual timer
Serial EEPROM
XC3042 FPGA
CXK581000M 1Mbit SRAM
74HC74A
and a few other bits and pieces.
Cloning doesn't seem like a task for the fainthearted, and I'd have
thought starting a custom DIY design from scratch might be easier?
--
Tim Forcer tmf@ecs.soton.ac.uk
The University of Southampton, UK
The University is not responsible for my opinions
Article: 15703Octavian Florea schrieb: > > I work with Xilinx FPGAs. > Does anyone use or heard about a testing board for FPGAs from Xilinx, > because I want to test a criptography chip and I wanna introduce data in > the chip and to test the outputs. > I can't only with the 7 LEDS and the pins from the borders. Take a look at my list of boards, that contains also European manufacturers: http://www.fernuni-hagen.de/IT/FPGA/boards.html Markus WannemacherArticle: 15704
Dave, According to my UK FAE, Xilinx have run a Virtex with a ZBT SSRAM at 140MHz. I don't know the details, perhaps ask your FAE. Cheers, Mark. On Wed, 07 Apr 1999 15:13:48 -0700, David Reid <dreid@corp.atl.com> wrote: >Has anyone yet put together a Virtex part and a ZBT (any manufacturer) >memory to work at 100Mhz or beyond? > > >Dave >Article: 15705
A good place to start is on The Programmable Logic Jump Station at http://www.optimagic.com. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Kirton Morris wrote in message <7ejsdo$7fn$1@dailyplanet.wam.umd.edu>... >Hello, >I'm writing a paper on FPGA's and PGA's and would like any links to >technical info on the above. Links to the architectual design of >the above will also be helpful > >trini@wam.umd.edu > >Article: 15706
I have been given a design to program into an isp1016E in the form of *.LDF files - I have Ver 5.0 of PDSPLUS Starter and I can't find a way of getting PDSPLUS to read the files. PDSPLUS it will look for a .LIF file, but the file format expected is different from what I have been given. I need to compile the .LDF file to .JED for the down-loader. Can someone enlighten me as to where I'm going wrong and point me in the right direction. Thanks Peter -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15707
mark.luscombe@lineone.net (Mark Luscombe) writes: > Dave, > > According to my UK FAE, Xilinx have run a Virtex with a ZBT SSRAM at > 140MHz. > > I don't know the details, perhaps ask your FAE. > > Cheers, Mark. > > > On Wed, 07 Apr 1999 15:13:48 -0700, David Reid <dreid@corp.atl.com> > wrote: > > >Has anyone yet put together a Virtex part and a ZBT (any manufacturer) > >memory to work at 100Mhz or beyond? > > > > > >Dave > > Xilinx has just posted an application note on interfacing Virtex to ZBT SRAM on their web site. -Arrigo -- Dr. Arrigo Benedetti o e-mail: arrigo@vision.caltech.edu Caltech, MS 136-93 < > phone: (626) 395-3695 Pasadena, CA 91125 / \ fax: (626) 795-8649Article: 15708
Try http://www.xilinx.com/xapp/xapp136.pdf -- Shekhar Bapat Steve Casselman wrote: > http://www.xilinx.com/apps/virtexapp.htm > > One more shot > > -- > Steve Casselman, President > Virtual Computer Corporation > http://www.vcc.comArticle: 15709
On Thu, 08 Apr 1999 13:26:53 -0400, Ray Andraka <randraka@ids.net> wrote: >Are you proposing to create and maintain a FAQ? D'oh (smacks forhead with open hand) Maybe I should. It's not so hard once it's done, and it would give me a reason to use some of this web space I get from my ISP for "additional material" relating to the group. Anyone care to provide input as to what it should contain? Cheers Stuart For Email remove "NOSPAM" from the addressArticle: 15710
In message <370e4e1b.121762@nntp.netcomuk.co.uk>
s_clubb@NOSPAMnetcomuk.co.uk (Stuart Clubb) wrote:
> On Thu, 08 Apr 1999 13:26:53 -0400, Ray Andraka <randraka@ids.net>
> wrote:
>
> >Are you proposing to create and maintain a FAQ?
>
> D'oh (smacks forhead with open hand)
>
> Maybe I should. It's not so hard once it's done, and it would give me
> a reason to use some of this web space I get from my ISP for
> "additional material" relating to the group. Anyone care to provide
> input as to what it should contain?
Libraries of useful generic bits.
References to on-line primers for ABEL-HDL, VHDL, Verilog.
Comparative reviews of programming software, and chip architectures.
Zero-cost software availability.
Free software availability.
Interesting design tricks.
cheers,Rich.
>
> Cheers
> Stuart
>
> For Email remove "NOSPAM" from the address
--
Rich Walker: rw@shadow.org.uk (Shadow Robot Project)
http://www.shadow.org.uk 251 Liverpool Road
+44(0)171 700 2487 London N1 1LX
"Sometimes after an electrical storm I see in 5 dimensions"
-- Cornfed Pig, Duckman.
Article: 15711Richard Guerin wrote: > > > Just curious how others handle the 2^N-N illegal states that are > possible in a one-hot (or zero-hot) encoded state variable ... Does > anyone else have horror stories regarding synthesys tools that totally > ignored the 2^N-N "when others =>" cases ? It is surprisingly easy and cheap to detect all >1 states with just a few look-up tables. So you get at least an error indication, while in an encoded machine you get no error indication at all. So, surprisingly, the one-hot method is more reliable, at a vey small extra cost. Peter Alfke, Xilinx ApplicationsArticle: 15712
Bruce Nepple wrote: > A one hot state machine has a real problem if it gets into an illegal state > (2 flip-flops set). I tell the compiler to ignore all of these > possibilities with a //synopsys full_case parallel_case pragma. > > I suppose you could implement special logic to detect whether 2 states ever > exist and use that to reset your state machine. For example, when in state > 0 if any other state is set, force it into state 0. I don't expect the > compiler to deal with this auto-magically. > > A 20 state one-hot machine would eat a lot of logic (and speed) trying to > detect all the illegal states, perhaps losing its advantage over a binary > coding. Not really "a lot of logic".For 16 states, it takes five 4-input LUTs = less than three CLBs to detect all 65000+ illegal states, and flag the error on one common output. Similarily, for 32 states, it takes less than seven LUTs to detect all 4 billion illegal states. Look-up tables are very powerful. Peter AlfkeArticle: 15713
Mandeep Singh wrote: > > Could someone please recommend a website or a book for a general > introduction to Reconfigurable Computing? > > Thanks > > Paul You can visit my FPGA page you will find lot of links http://www.geocities.com/SiliconValley/Pines/6639/fpgaArticle: 15714
Hi, Anyone using the FPGA Express 'Time Tracker' option? If so, is it a useful option? It's almost the same price as the base product! Opinions (on this subject ;-) greatly appreciated! Thanks, Austin Franklin austin@darkroom.comArticle: 15715
Bourguiba Riad wrote: > > Does any one want to talk about Dynamic Configuration? > > Here is my ICQ # : 33301195 > > Contact me. > > Riad Bourguiba Yes I am very intrested in this topic but I prefer the Email I do not like the ICQ you can visit my page www.geocities.com/SiliconValley/Pines/6639/fpgaArticle: 15716
vanan wrote: > > Hi! > > Anyone know about 8bit x 1K FIFO can implemented in FPGA ? > > If yes , Pls give me the vendor and part number. > > Any application note ? will be great . > > Thanks > > Svana visit www.geocities.com/SiliconValley/Pines/6639/ip/fifo.htmlArticle: 15717
Peter wrote: >I have been given a design to program into an isp1016E in the form of >*.LDF files - I have Ver 5.0 of PDSPLUS Starter Peter - Your best bet is to contact your local Lattice FAE. *.LDF files are generated as intermediate Boolean files either in PDS or PDSPLUS. There is no way for the PDSPLUS fitter to read and compile the design. (darn it!) LDF is a viable input file for PDS - an older design tool which is no longer supported, but your local FAE will have a copy. If the design is strictly Boolean equations (no Lattice Macros found in the design) it can be used as an ABEL design file, but that is quite a bit of work also. Lacking a local FAE to have arm-wrestle the design, you can email it to applications@latticesemi.com this is the email for the PLSI Hotline in Milpitas CA. They can help you convert/compile the design. If these options don't bear quick fruit - contact me! Michael Thomas LSC FAE - NY michael_thomas@latticesemi.comArticle: 15718
Peter Alfke wrote: > Not really "a lot of logic".For 16 states, it takes five 4-input LUTs = less > than three CLBs to detect all 65000+ illegal states, and flag the error on one > > common output. Sorry, I was off by a factor of two: You need 6.5 CLB to monitor 16 inputs: Each group of 4 inputs drives two parallel LUTs, one detects zero active inputs, the other one detects exactly one active input. On the next level, you do the same, and the third level gives you the result. Sorry for the overenthusiastic error. Look-up table are powerful, nevertheless. Peter AlfkeArticle: 15719
I've also used the carry logic in the 4K for a one and only one detect circuit which will detect a one-hot problem at little cost and with reasonable delay for medium sized machines. It does require the statemachine to be floorplanned though. Peter Alfke wrote: > Richard Guerin wrote: > > > > > > > Just curious how others handle the 2^N-N illegal states that are > > possible in a one-hot (or zero-hot) encoded state variable ... Does > > anyone else have horror stories regarding synthesys tools that totally > > ignored the 2^N-N "when others =>" cases ? > > It is surprisingly easy and cheap to detect all >1 states with just a few > look-up tables. So you get at least an error indication, while in an encoded > machine you get no error indication at all. So, surprisingly, the one-hot method > is more reliable, at a vey small extra cost. > > Peter Alfke, Xilinx Applications -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15720
In article <JXNO2.11292$LX.4591393@WReNphoon3>, sakdas@earthlink.net (Tony Kirke) wrote: > There seems to be more support/usage of Xilinx than Altera Devices for DSP > Designs (FIRs, FFTs, Cordic, etc). > My company already has Altera tools but I don't want to be limited by that > choice. > Please let me know if you think Altera is better or equivalent for DSP > designs (or if you Xilinx is definitely superior). > Thanks, > I'll sumarise later for the group. > Tony > > **** Posted from RemarQ - http://www.remarq.com - Discussions Start Here (tm) **** > Altera has really been getting its act together on DSP. Altera now has the coolest FIR filter compiler around and supports many complex high performance DSP functions from 3rd parties. -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15721
Has anyone tried using Virtex PULLDOWNs? When I instantiate a few they appear OK in the EDIF, but ngdbuild complains about PULLDOWN and PULLUP on the same pin and bails out. If I change the PULLDOWNs to PULLUPs, all proceeds OK so I guess there is some magic for disabling the default (!) PULLUPs. The ngdbuild version is M1.5.25. -- Simon (simon @ tile dot demon.co.uk) -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 15722
Never thought of that. Seems like a good tool feature! Xilinx take note.... bruce Ray Andraka wrote in message <370E7092.70065A2C@ids.net>... >I've also used the carry logic in the 4K for a one and only one detect circuit which >will detect a one-hot problem at little cost and with reasonable delay for medium >sized machines. It does require the statemachine to be floorplanned though. > >Peter Alfke wrote: > >> Richard Guerin wrote: >> >> > >> > >> > Just curious how others handle the 2^N-N illegal states that are >> > possible in a one-hot (or zero-hot) encoded state variable ... Does >> > anyone else have horror stories regarding synthesys tools that totally >> > ignored the 2^N-N "when others =>" cases ? >> >> It is surprisingly easy and cheap to detect all >1 states with just a few >> look-up tables. So you get at least an error indication, while in an encoded >> machine you get no error indication at all. So, surprisingly, the one-hot method >> is more reliable, at a vey small extra cost. >> >> Peter Alfke, Xilinx Applications > > > >-- >-Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email randraka@ids.net >http://users.ids.net/~randraka > >Article: 15723
jrf0@my-dejanews.com wrote: > In article <JXNO2.11292$LX.4591393@WReNphoon3>, > sakdas@earthlink.net (Tony Kirke) wrote: > > There seems to be more support/usage of Xilinx than Altera Devices for DSP > > Designs (FIRs, FFTs, Cordic, etc). > > My company already has Altera tools but I don't want to be limited by that > > choice. > > Please let me know if you think Altera is better or equivalent for DSP > > designs (or if you Xilinx is definitely superior). > > Thanks, > > I'll sumarise later for the group. > > Tony > > > > **** Posted from RemarQ - http://www.remarq.com - Discussions Start Here (tm) > **** > > Altera has really been getting its act together on DSP. Altera now has the > coolest FIR filter compiler around and supports many complex high performance > DSP functions from 3rd parties. I agree, altera's IP program is well endowed. On technical merits, I stand by my assertion that Xilinx is the better device for the general class of digital signal processing. > > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 15724
Bruce Nepple wrote: > Never thought of that. Seems like a good tool feature! Xilinx take > note.... The 4K carry chain can be used for all sorts of things once you get out of the arithmetic only mindset. The carry chain in Virtex is less flexible, so it doesn't handle many of the non-arithmetic apps as nicely, but it still can be useful in this type of problem. > bruce > > Ray Andraka wrote in message <370E7092.70065A2C@ids.net>... > >I've also used the carry logic in the 4K for a one and only one detect > circuit which > >will detect a one-hot problem at little cost and with reasonable delay for > medium > >sized machines. It does require the statemachine to be floorplanned > though. > > > >Peter Alfke wrote: > > > >> Richard Guerin wrote: > >> > >> > > >> > > >> > Just curious how others handle the 2^N-N illegal states that are > >> > possible in a one-hot (or zero-hot) encoded state variable ... Does > >> > anyone else have horror stories regarding synthesys tools that totally > >> > ignored the 2^N-N "when others =>" cases ? > >> > >> It is surprisingly easy and cheap to detect all >1 states with just a > few > >> look-up tables. So you get at least an error indication, while in an > encoded > >> machine you get no error indication at all. So, surprisingly, the one-hot > method > >> is more reliable, at a vey small extra cost. > >> > >> Peter Alfke, Xilinx Applications > > > > > > > >-- > >-Ray Andraka, P.E. > >President, the Andraka Consulting Group, Inc. > >401/884-7930 Fax 401/884-7950 > >email randraka@ids.net > >http://users.ids.net/~randraka > > > > -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka
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