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I have been struggling with this for some time, as I get the documentation (help file) completed for the design tools I will be releasing soon. Rather than detail all the false paths that wasted about 2 months of time (other than to say that screen images suck when pushed throught to PDF), here is what I am using now: Either: ctrl-PrtScreen to get the image of a window into the clipboard, then paste into MS-Word, and crop/resize as needed. or PaintShop Pro (V5.0) to do the screen capture. Crop as needed. Then save in any of dozens of formats (maybe also changing some colors, and bits per pixel). Import picture into MS-Word. PaintShop Pro is a great program, and is less than $80. Excelent for all types of image manipulations, and format conversions. For some examples of schematic pages pasted into a web page, you could look at http://www.fliptronics.com/flibgen.html which is a product description for one of my new products. You will also see some screen shots of a program menu. Philip Freidin. The following seems somewhat more tedious. There is the issue that my method limits you to what the schematic looks like on the screen, so if the screen image is poor (because you are using a D size sheet, and displaying the whole sheet), so is the captured image. If you zoom in and make it look nice before capture, the results are also just as good. In article <3754CE50.A7F54AE@yahoo.com> Rickman <spamgoeshere4@yahoo.com> writes: >Thierry Garrel wrote: >> >> Rick, >> >> I've done it with Viewlogic Workview Office 7.5 + Ghosscript 5.2 + Paint >> Shop Pro 3 + Word 6 >> In Viewlogic : export schematic individually in Poscript format (.PS) >> then go to ghoscript >> In Ghostcript : load the .PS file, zoom to the maximum, copy entire >> image to the clipboard the >> go to Paint Shop Pto >> In Paint Shop Pro : load the image from the clipboard and save it to a >> Word 6 compatible format >> (.GIF or .TIF) >> In Word 6 : insert the image in full page format the print the document >> >> When printing the document to Poscript Printer the resolution of images >> is pretty good >>Article: 16676
Hi, You can try the HPGL format. E. JOLLY On Tue, 01 Jun 1999 23:37:29 -0400, Rickman <spamgoeshere4@yahoo.com> wrote: >Steve Rencontre wrote: >> >> In article <3752C959.B6A78501@yahoo.com>, spamgoeshere4@yahoo.com said... >> > I am working on documentaion for my last design and I would like to >> > include schematic pages in the document. I could just print them out and >> > add the pages. But I was tring to add them electronically so that >> > everything is in one file. >> > >> > I am writing this in Word 97 and using Xilinx Foundation 1.5i for the >> > schematic capture. I was able to print to a PDF file, but Word won't >> > accept that as a picture. I also tried printing Postscript to a file, >> > but Word won't show that on the screen. It will only print it to a >> > Postscript printer. >> > >> > Does anyone have an idea of how to do this? Are there any programs that >> > will let me print the schematic to a picture file without a big loss of >> > resolution? I found that I could cut and paste from Acrobat to Word. But >> > the intermediate file format was a bit mapped file of some type and most >> > of the text blurred a great deal. >> >> Have you tried copying your schematic to the clipboard in Foundation and >> then pasting into Word? I was pleasantly surprised to find that this >> technique worked with Rational Rose diagrams, even though I could find no >> way of generating a useful graphic file format. >> >> -- >> Steve Rencontre - Design Consultant >> http://www.rsn-tech.demon.co.uk/ > >Good idea, but it didn't work. It is not a big deal. I have finished the >docs and will simply add the schematics as an appendix. But it would >have been nice to have been able to put the pictures into the doc file >so that it was self contained rather than to have to print out the >schematics and add them as paper copies. > >Does anyone know if Viewlogic is better at this? > > >-- > >Rick Collins > >rick.collins@XYarius.com > >remove the XY to email me. > > > >Arius - A Signal Processing Solutions Company >Specializing in DSP and FPGA design > >Arius >4 King Ave >Frederick, MD 21701-3110 >301-682-7772 Voice >301-682-7666 FAX > >Internet URL http://www.arius.comArticle: 16677
Hi Does anyone know of bookstores in central London that are likely to have a decent selection of this 'light' reading. rgds Mike Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16678
I am new to Xilinx cpld components and learning how to use it for real
applications.
I have two questions on tPTTS of XC9500 that I can't understand.
The datasheet shows that the tPTTS of XC95144-7 is 4.5ns, while the
tPTTS of XC95144-10 is 3.5ns. I am curious about why the faster
device get a longer delay? Any comment.
What' more, the tPTTS value is even higher in the "Post Layout Timing
Report". The tPTTS of XC95144-7 is 7.0ns, not 4.5ns. See the segment
of timing report file below.
Detailed Path Analysis Report
-----------------------------
Design: vdnet
Device: XC95144-7-PQ100
Program: Timing Report Generator: version M1.5.25
Date: Tue Jun 01 11:38:49 1999
Output will be sorted by decreasing path delays.
Logical Path Delay Type Delay
Cumulative
------------ ---------- -----
----------
********************
* Pad to Pad (tPD) *
********************
From: DSPRENA - : 0.0ns
(0.0ns)
Thru: $Net00139_ tIN : 2.5ns
(2.5ns)
Thru: DD<0>.OE tPTTS : 7.0ns
(9.5ns)
To: DD<0> tEN : 0.0ns
(9.5ns)
From: DSPRENA - : 0.0ns
(0.0ns)
Thru: $Net00139_ tIN : 2.5ns
(2.5ns)
Thru: DD<10>.OE tPTTS : 7.0ns
(9.5ns)
To: DD<10> tEN : 0.0ns
(9.5ns)
Article: 16679Dear All, I am learning to design with the Xilinx XC9500 cpld. Owning to the MCU's processing speed, I need to set up the pin to pin time delay to less than 7ns. What is the best approach to achieve this? By using VHDL, ABel, or Schematic entry etc.. Any suggestion is appreciated. Thanks and regards.Article: 16680
Hi Jamil, Try replacing "array (integer range <>)" with "array (natural range <>)". Stephen Fraleigh stephen.fraleigh@ericsson.com Jamil Khatib wrote: > > TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(7 DOWNTO > 0); > -- Memory Type > SIGNAL data : data_array(0 TO 7); -- Local data > >Article: 16681
Hi Jamil, Try replacing "array (integer range <>)" with "array (natural range <>)". Stephen Fraleigh stephen.fraleigh@ericsson.com Jamil Khatib wrote: > > TYPE data_array IS ARRAY (integer range <>) OF std_logic_vector(7 DOWNTO > 0); > -- Memory Type > SIGNAL data : data_array(0 TO 7); -- Local data > >Article: 16682
Workview Office is OLE enabled. You can simply copy your schematic to the clipboard (Select_all + Copy) and paste it into Word using "Paste Special". It pastes it as a bitmap.Article: 16683
More than books you can get a good idea by going through older (pre 94) proceedings of FCCMs and FPGA(90s). They have some architecture basics and implementation examples. Another place to look for papers is DAC. www.dac.com. Company websites give little but important information. Hope this helps -- Pranav n article <7j3ao2$nii@dfw-ixnews7.ix.netcom.com>, "Steven K. Knapp" <sknapp@optimagic.com> wrote: > There's a fairly comprehensive list of books on The Programmable Logic Jump > Station at http://www.optimagic.com/books.html -- many arranged by subject > matter. > > ----------------------------------------------------------- > Steven K. Knapp > OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" > E-mail: sknapp@optimagic.com > Web: http://www.optimagic.com > ----------------------------------------------------------- > > username@dso.org.sg wrote in message <37522363.124D@dso.org.sg>... > >Hello, > > > >Does anyone out there have any good recommendations on books about > >FPGA which contains a good explanation of how FPGA works and > >its physical construction, LCA/LCB design analysis, programming > >circuit and logic etc.? > > > >Not the usual data sheets though. > >Thanks in advance. > > > >email: csoolan@dso.org.sg > > Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 16684
Don Husby wrote: > Workview Office is OLE enabled. You can simply copy your schematic to the > clipboard (Select_all + Copy) and paste it into Word using "Paste Special". > It pastes it as a bitmap. Yes, it does. You better set your colors first though, because it copies the colors right out of the schematic. If you work with the classic colors (black background, green symbols, red wires & busses) that is what you get when you paste it into your text document too. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16685
Jonathan Feifarek <feifarek@removethis.ieee.org> wrote: : Tim Tyler wrote: :> A number of researchers in the area use FPGAs which are designed to try to :> avoid contention issues in all but the I/O stage - you can send a :> random bitstream to them without much fear that contention issues will :> arise. The Xilinx 6200 series is one family which exhibits this type of :> safety. : I wonder how many projects will be affected by Xilinx decision to : discontinue the part. When Xilinx sais they were going to fold the family, they didn't have any real reconfigurable alternative and pledged that they would continue to manufacture the chip and make samples of it available to academics and researchers for as long as there was demand for it. Now that Xilinx presumably want to channel people towards their Virtex part, which appears to have at least some of the functionality of the 6200 series, I don't know what their position is any more. By all accounts the 6200 was a pretty weird beast, and was without some of the software support it really needed. Most other Xilinx chips are "island style" FPGAs (as opposed to "cellular style") and have a less uniform structure, with patches of processing surrounded by interconnect. Such components appear less useful than they might be to those looking at cellular automata approaches. Most FPGAs have too much space devoted to look-up tables, and not enough space devoted to flip-flops, as well - for my taste. This is partly because they are used to prototype VLSI chips, which are generally designed to be used in conjunction with external RAM. The whole legacy VN-architecture idea of having RAM physically separated from the processor seems like a real problem to me. /All/ my applications seem to require that the RAM be physically situated right next to the logic elements, and distributed uniformly among the processing elements. There are some other ways in which I'd like to see the FPGA market develop. Currently the LUTs in FPGAs are too large and take up too much space. I would like to see simpler components more closely packed. Then there's reversibility. Current FPGAs can eat power and run hot. In the next ten years this will become a significant limiting factor, and it is /largely/ an unnecessary one. I would like to see *reversible* FPGAs, composed of large numbers of Fredkin gates - or equivalent reversible logic. I think this is a completely fundamental step, one which is inevitable, and consequently one which FPGA manufacturers should be looking at today. -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com Excuse me, while I whip out one of these!Article: 16686
Tim Tyler wrote: > > I would like to see *reversible* FPGAs, composed of large numbers of > Fredkin gates - or equivalent reversible logic. I think this is a > completely fundamental step, one which is inevitable, and consequently one > which FPGA manufacturers should be looking at today. My first time to across this term. After a quick search, I came across this site [ http://www.vxm.com/21R.30.html ] which (after discussing bacteria as switching devices) makes this statement: "The question then becomes how to commercially build this Fredkin device. It may be possible to create it out of semiconductor materials, but Toffolli thinks that a Fredkin gate would be 'very tough to implement in silicon.'" Then of course, this site [ http://www.nano.xerox.com/nanotech/electroTextOnly.html ] refutes this by discussing possible circuitry powered by FET-type switches, though I didn't see a reference to an actual working gate. Jonathan -- Jonathan F. Feifarek Consulting and design Programmable logic solutionsArticle: 16687
"news.pcnet.com" wrote: > > I was thinking about putting up a page devoted to new engineers entering the > FPGA market. > ...Other than the differences between CPLD/FPGA, the > programming, vendors, languages (VHDL or simple ABEL), what other things > would be appropriate for this type of page? It would useful to describe typical applications of FPGA (general prototyping, high speed reconfiguration, custom computers, etc.), as well the technology areas (networks, DSP, graphics, computation). Of course, discussion of the tools is a must, along with related topics like mapping, floorplanning, placement, and routing. Much knowledge is based on hands-on experience, so up-to-date information written by FPGA users would be helpful (perhaps some of it gleaned from newsgroups like this if there are no copyright issues). To make it interesting, add stories about unusual or novel applications, "gotchas" to watch out for, or trends in the industry (this will also attract veterans). This area is more for early users rather than complete novices, and may be outside your scope. Lastly, I would recommend lots of links. The http://www.optimagic.com site does an excellent job of this. Good luck! Jonathan -- Jonathan F. Feifarek Consulting and design Programmable logic solutionsArticle: 16688
I attended a seminar in (1985, 1986?) by the late, great, physicist Richard Feynman, where he discussed reversible logic, and why this would absolutely be required for quantum computation. It seems that destroying information requires energy, and making the computation reversible permits (in principle) performing a computation at zero energy cost. The fly in the ointment, or course, is that zero energy computations take an infinite amount of time to compute, since they randomly reverse as much as they go forward. The more energy you put into the computation, the faster you can make it go. Another thing that we took away from that seminar was the realization that we are still a *long* way from hitting the physical limits of computation. Moore's law has still quite a bit of steam left in it, even today. John McCluskey j.mccluskey@nospam.ieee.org ---------------------------------------------------------------- Jonathan Feifarek wrote: > Tim Tyler wrote: > > > > I would like to see *reversible* FPGAs, composed of large numbers of > > Fredkin gates - or equivalent reversible logic. I think this is a > > completely fundamental step, one which is inevitable, and consequently one > > which FPGA manufacturers should be looking at today. > > My first time to across this term. After a quick search, I came across > this site [ http://www.vxm.com/21R.30.html ] which (after discussing > bacteria as switching devices) makes this statement: > > "The question then becomes how to commercially build this Fredkin > device. It may be possible to create it out of semiconductor materials, > but Toffolli thinks that a Fredkin gate would be 'very tough to > implement in silicon.'" > > Then of course, this site [ > http://www.nano.xerox.com/nanotech/electroTextOnly.html ] refutes this > by discussing possible circuitry powered by FET-type switches, though I > didn't see a reference to an actual working gate. > > Jonathan > -- > Jonathan F. Feifarek > Consulting and design > Programmable logic solutionsArticle: 16689
Does anyone know of a company that makes a Rice Image Decompression core
that
runs on a Virtex or Apex chip?
Thanks,
Rich
--
Richard D. Hunt
_/_/_/ _/ _/ _/ SANDIA NATIONAL LABORATORIES _/_/_/
_/ _/_/ _/ _/ P.O. Box 5800 M/S 0965 _/_/
_/_/_/ _/ _/ _/ _/ Albuquerque, NM 87185-0965 _/_/_/_/_/_/
/ _/ _/_/ _/ Voice: (505)844-3193 _/ _/_/ _/
_/_/_/ _/ _/ _/_/_/_/ Fax: (505)844-5993 _/ _/_/ _/
mailto:rdhunt@sandia.gov _/_/_/
Article: 16690You might look at the Atmel devices, especially the AT40K. These are capable of partial reconfiguration and have a finer grained structure (ie a larger ratio of flip-flops to logic) than the competition. The AT6K cell is basically a half adder with a flip-flop on the sum output and some extra gates which allow it to handle many (but not all) 2 input logic function and a couple of 3 input logic functions. The incomplete 2 input logic coverage and relatively sparse routing can make the 6K hard to work with. The AT40K replaces the gated logic with a 4 LUT, so each cell is basically a 4-LUT with a flip-flop on the output. It is a different structure than the 6200, but it might be worth a look if reconfigurability is your game. Tim Tyler wrote: > Jonathan Feifarek <feifarek@removethis.ieee.org> wrote: > : Tim Tyler wrote: > > :> A number of researchers in the area use FPGAs which are designed to try to > :> avoid contention issues in all but the I/O stage - you can send a > :> random bitstream to them without much fear that contention issues will > :> arise. The Xilinx 6200 series is one family which exhibits this type of > :> safety. > > : I wonder how many projects will be affected by Xilinx decision to > : discontinue the part. > > When Xilinx sais they were going to fold the family, they didn't have > any real reconfigurable alternative and pledged that they would continue > to manufacture the chip and make samples of it available to academics > and researchers for as long as there was demand for it. Now that Xilinx > presumably want to channel people towards their Virtex part, which appears > to have at least some of the functionality of the 6200 series, I don't > know what their position is any more. By all accounts the 6200 was > a pretty weird beast, and was without some of the software support it > really needed. > > Most other Xilinx chips are "island style" FPGAs (as opposed to "cellular > style") and have a less uniform structure, with patches of processing > surrounded by interconnect. Such components appear less useful than > they might be to those looking at cellular automata approaches. > > Most FPGAs have too much space devoted to look-up tables, and not enough > space devoted to flip-flops, as well - for my taste. This is partly > because they are used to prototype VLSI chips, which are generally > designed to be used in conjunction with external RAM. > > The whole legacy VN-architecture idea of having RAM physically separated > from the processor seems like a real problem to me. /All/ my applications > seem to require that the RAM be physically situated right next to the > logic elements, and distributed uniformly among the processing elements. > > There are some other ways in which I'd like to see the FPGA market > develop. Currently the LUTs in FPGAs are too large and take up too much > space. I would like to see simpler components more closely packed. > > Then there's reversibility. Current FPGAs can eat power and run hot. In > the next ten years this will become a significant limiting factor, and it > is /largely/ an unnecessary one. > > I would like to see *reversible* FPGAs, composed of large numbers of > Fredkin gates - or equivalent reversible logic. I think this is a > completely fundamental step, one which is inevitable, and consequently one > which FPGA manufacturers should be looking at today. > -- > __________ > |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com > > Excuse me, while I whip out one of these! -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16691
In article <7j0hrd$3jl$1@nnrp1.deja.com>,
andi_carmon@my-deja.com wrote:
> Swapnajit,
>
> I finally got the book above. Congratulations.
> The section about inter-process communications was very helpful.
> Regarding this issue, I need an advice on the following :
> The 'accept' call of the server is blocking by default. It will not
> return until a connection is available. I know that it is possible to
> define the socket as non-blocking. Can you advise me how? Actually I
> want to achieve the effect of the server 'visiting' the socket and if
> there is no connection of the client to let it continue.
> Thank you,
> Andi Carmon
> andi@orckit.com
>
Andi,
I am glad that the example in the book
has encouraged you to do further research
on the topic; after all, that is one of the
main objective of the book.
Regarding your question, you can create a
non-blocking socket (by default, all sockets
are blocking) by using fcntl() system call.
An example of this is :
fcntl(s, F_SETFL, FNONBLK);
where s is the socket created by socket().
The names of the integer constants may be
slightly different depending on your version of
UNIX. For example, when FNONBLK is POSIX
compliant, IRIX uses a native FNONBLOCK.
Also, there are other ways to do the same. Some
flavors of UNIX (and BeOS) does this using
setsockopt(), but it is not implemented
in all OS'.
Thanks,
- Swapnajit Mittra
--
=-=-=-=-=-= 100% pure Verilog PLI - go, get it ! =-=-=-=-=-=
Principles of Verilog PLI -By- Swapnajit Mittra
Kluwer Academic Publishers. ISBN: 0-7923-8477-6
http://www.angelfire.com/ca/verilog/
Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 16692Hi, I'm using Xilinx foundation tools for a design in a 4010E. Trying to get a clock going from a normal IOB, I need to put it through an IBUF, but it keeps getting optimised out. The design is written in VHDL and if I put the clock through an AND gate all is fine, But that way I need an extra pin tied to Vdd and this is not very satisfactory. One of the Xilinx FAQs tells me to add a 'dont touch' attribute for the IBUF, but I don't know where to access the Synopsus scripts from the Foundation 1.5 Tools and what exactly I should put in once I find them. Can anyone help me out? Thanks, Ties.Article: 16693
We have two lots of EPC1 PROMs, one we can program and one we cannot. Would it be because of a change in the programmation algorithm made by Altera without notice (I know the PROM makers often do that) ? Or maybe the lot is defective? Maybe an older version of the ChipWriter would do with the old EPC1 ? Any help is welcome (we don't want to throw 30 EPC1 away like that) Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel 00 33 1 46 67 51 11 92400 COURBEVOIE Fax 00 33 1 46 67 51 01 FRANCE Mail reply : remove one dot from my addressArticle: 16694
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Article: 16695
In message <7j2sld$f77$1@nnrp1.deja.com>
micheal_thompson@my-deja.com wrote:
> Hi
> Does anyone know of bookstores in central London that are likely to
> have a decent selection of this 'light' reading.
Dillons on Gower Street have some interesting stuff,ISTR...
cheers,Rich.
--
Rich Walker: rw@shadow.org.uk (Shadow Robot Project)
http://www.shadow.org.uk 251 Liverpool Road
+44(0)171 700 2487 London N1 1LX
"Sometimes after an electrical storm I see in 5 dimensions"
-- Cornfed Pig, Duckman.
Article: 16696Despite the possibilities of contention, it turns out that XC4000X and Virtex type FPGAs can be used for evolvable hardware. Xilinx has developed a JBits based toolkit that demonstrates this capability on commercial of the shelf Xilinx based RC boards. We've also resolved how to create stable digital circuits. We will soon release the software on a Beta program to researchers. Delon Jonathan Feifarek <feifarek@removethis.ieee.org> wrote in message news:374F004F.20A46383@removethis.ieee.org... > OK, time for a new thread from "Re: High Speed Reconfigurability". > > I've been interested in Reconfigurable Computing in general, but know > very little about the area of Evolutionary Computation. I, for one, > would like to learn more. > > Tim Tyler wrote: > > > > Evolutionary computations parallelise /extremely/ well. The field offers > > applications for which there's no practical limit on how much parallelism > > is desirable - the more the merrier. Further, typically it eats > > processing power like there's no tomorrow. There are few applications > > *more* suitable for implementation on FPGAs than this one. > > > > I assume that evolution computation is the same thing as evolvable > hardware (plus the 'software'). Doesn't this process involve 'mutating' > configurations in successive generations, and evaluating the offspring > from each generation to determine their degree of success in meeting the > goal of the design? (Please excuse the imprecise terminology). > > My question is this: if the mutations are truly random alterations in > the logic, doesn't the possibility of logic contention arise where two > output stages are driven to opposite states at the same time? I've > heard of damaged hardware from this - indeed, J-Bits comes with a > prominent warning to beware of it. To check each offspring for this > possibility sounds like it would be an enormous task for a reasonably > sized circuit. > > Perhaps this is one of the areas where the technology "eats processing > power like there's no tomorrow". > > Jonathan > -- > Jonathan F. Feifarek > Consulting and design > Programmable logic solutionsArticle: 16697
How to make more money by going into Business instead :)
Seriously,
A websight that has links like:
Begginner Links:
link1
link2
etc...
Intermediate Links:
link1
link2
etc..
Advanced Links:
link1
link2
etc.
Plus all of the suggestions so far are good.
news.pcnet.com <desrosi@pcnet.com> wrote in message
news:DBZ43.5$9i6.6192@news.pcnet.com...
> I was thinking about putting up a page devoted to new engineers entering
the
> FPGA market.
>
> It was somewhat difficult for me to get started and I'd like to ease the
> pain for anyone just getting into this technology.
>
> My question is this...Other than the differences between CPLD/FPGA, the
> programming, vendors, languages (VHDL or simple ABEL), what other things
> would be appropriate for this type of page?
>
> Your input could benefit future designers.
>
> ---
>
>
>
Article: 16698Hello, I am trying implement a very low level design on Virtex. I want to use the MULT_AND and LUT components in my design. At the moment I can do it in schematics but I can't do it in VHDL. The LUT is removed and then the MULT_AND doesn't work. Can anyone help? Dimitris -- Dimitrios Siganos <d.siganos@ic.ac.uk> Dept. of Computing, Imperial College, London SW7 2BZ Work Tel: 0171 589 5111 ext 58439, Home Tel: 0181 446 8841 Homepage: www.doc.ic.ac.uk/~ds12Article: 16699
Unfortunately the EDIF that Max+plus gave you uses parts available for the
particular
chip family that was selected by the Max tools and the Xilinx part you want
to use
does not have the same parts (i.e. AND1 for instance). If you get this to
actually work
I would be amazed.
If you have the original VHDL code (that is if you didnt use Max's AHDL or
some
schematic entry) then I would use that instead by either compiling it in
Xilinx or some
"better" tool like leonardo or synplicity.
Good luck... maybe someone else has a suggestion as to how to edit the edif
file
or something to that nature.
Vitolo <setel@mx3.redestb.es> wrote in message
news:7j0s18$h9b29@SGI3651ef0...
> Hi, all:
>
> I need convert a ALTERA design(MAX+PLUSII) into a XILINX design
(Foundation
> F1.3). I try export a Edif 200 file from MAX+PLUS and import netlist into
> Schematic Editor of Foundation. I complet the design with the new
component
> (IBUF, OBUF, pads) and save. When i try export the netlist in a XNF file,
> ihave a error message ("Missing AND1 model or library error") then i
export
> in a VHD file and have ("Cannot read pin descriptors for AND1") error.
>
> I want to generate a VHDL file (XILINX Foundation compatible) from a EDIF
> ,or other, ALTERA file. How i can to do?
>
>
>
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