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You may wish to look at the examples provided at the following URL : http://www.altera.com/html/atlas/examples/ged/tri_state.html Hope it helps Stuart In article <37C0A132.A59ED9B7@auckland.ac.nz>, Grant Sargent <g.sargent@auckland.ac.nz> wrote: > Hi All, > I'm sure there's something simple that I'm just not getting, but I'm > having this problem with getting a BIDIR port working as I'd expect. > I'm simply trying to get a multiplexed Address/Data port to provide > seperate address and data inputs, and a data output. > Now, it's easy with glue logic to do this, but MAX2PLUS is complaining > that I need to connect a BIDIR tri-state buffer to a bidir port (It > is... I Think.) > I'm using a custom LPM function created via the Megafunction wizard. > Max2plus is ver 9.23 baseline. > > Thanks in advance, Cheers, > Grant > > Some days you're the dog, some days you're the hydrant. > Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17676
We have a product which might work for this application. Our main bussiness is PC based test equipment like Logic analyzers, test pattern generators, digital video equipment, and analog grabbers and generators. Our analog solution which is in development only goes to 40MHz, so that wouldn't help. However, we sell a version of our logic analyzer/test pattern generator in which we provide schematics and technicall information in which you can use our product to create your own product. This is the JumpShot board. The Logic Analyzer (and JumpShot) is 32 bits wide, currently 80MHz (should be able to run at 100MHz, but hasn't been tested yet), and has 4 Meg per channel of storage. We also offer a 8 Meg per channel upgrade. The JumpShot option is two boards which include 4Meg x 32, or 8Mex x 32 SDRAM, 10k30E, Parallel port interface, and the PFGA board which has a 10k50E or Virtex 300. The FPGA board is used to preprocess data being captured, or post process data being driven out. You can find more information at our website, or feel free to either call or email me. Brad Ree Director of Engineering Programmable Products www.programmable-products.com brad.ree@programmable-products.com 770-736-8932Article: 17677
Phil Hays wrote: > muzo wrote: > > just check-out http://www.free-ip.com/DES/index.htm and look for the > > comparisons between Synplify and FPGA express. > > This comparison just isn't very meaningful. It's based on a single flaw > in FPGA Express. > From the above URL: > > "This was traced down to the S-Boxes, which are implemented as 64x4 > ROM's. Under FPGA Express, these took about 33 slices where Synplify > took 10 slices." Seeing as I wrote that statement (from the above URL), I guess I should put my two cents worth in here... The comparison of FPGA Express and Synplify, with respect to the Free-DES core, is very meaningful but only in applications where ROM's are implemented (which I admit is limited). This has a huge impact for DES since there are so many ROM's, but it can also have an impact for some CPU (microcode rom), and DSP (coefficient tables) applications. I did a comparison between Synplify and FPGA Express and Synplify was better in all applications that I tried-- but the DES code was the most drastic. Ignoring the Free-DES core for the moment, typical improvements for Synplify was 10 to 20% less logic _OR_ a 10 to 60% improvement in speed. This was based on UART, CPU, and Ethernet controller designs. Of course, your mileage will vary. My only complaint about Synplify is that their way to do constraints seems awful to me. It may work, but I like what FPGA Express does much better. > If the team at Synopsis is serious about staying in business, this flaw > will be fixed in a matter of months. The latest version of FPGA Express (I forget the version #, but it is what's shipping this month with Xilinx Foundation/Alliance 2.1) does not fix this problem. > I'm tempted to update my evaluation license for Exemplar (which I think > has averaged as the number two tool in my past evaluations) just to try > this design. That would be good. Try the Free-6502 as well. I'd like to put those results up on the Free-IP Project web site... Thanks. David Kessner davidk@free-ip.com http://www.free-ip.comArticle: 17678
On Sat, 21 Aug 1999 13:43:01 +0200, Daniel Figuerola Estrada
<pfa@tinet.fut.es> wrote:
>I am making a project in wich I compare advantages and disadvantages in
>using microcontrollers and FPGA in the design of a digital system.
>
>Has anyone worked with those two technologies and could give his opinion
>of them?
>
>
>------------------------------------------------------------------------
> ////////////////////////////////\ ("`-''-/").___..--''"`-.__
> // Marcel Figuerola Estrada // `6_ 6 ) `-. ( ).`-.__.`)
> // pfa@tinet.fut.es // (_Y_.)' ._ ) `._ `.``-..-'
> // Valls - Catalunya - Europe // _..`--'_..-_/ /--'_.' ,'
> \//////////////////////////////// (il),-'' (li),' ((!.-'
>------------------------------------------------------------------------
When a microcontroller can do the job, it is always more maintainable,
(fewer or no nasty wires after the design is reworked) less costly
(small FPGA costs what 10 microcontrollers cost) less costly to
develop (tools cost 1% or thereabouts, as much as 10% of what the
least costly FPGA support tools cost) and more likely to stand the
test of time (FPGA types are changed often enough that a redesign is
warranted each time the FPGA is enhanced, since the earlier version
will likely be discontinued).
I still use microcontrollers I used 20 years ago, with as much
success, and, if need be, I can put the processor core in an FPGA and
use it there.
Dick
Article: 17679Gidday there, Can anyone give me some useful pointers to information required to be able to make my own JTAG 1149 programmer? I need to take raw binary data and program an Altera Serial Configurator (EPC2). Should I just get the IEEE spec and start from scratch, or are there some other decent docs? Thanks in advance Joshua Lamorie Systems Designer Xiphos Technologies Inc.Article: 17680
I believe in using FPGAs as microcontrollers.
See my sig below.
Simon
==============================
On Sat, 21 Aug 1999 13:43:01 +0200, Daniel Figuerola Estrada
<pfa@tinet.fut.es> wrote:
>I am making a project in wich I compare advantages and disadvantages in
>using microcontrollers and FPGA in the design of a digital system.
>
>Has anyone worked with those two technologies and could give his opinion
>of them?
>
>
>------------------------------------------------------------------------
> ////////////////////////////////\ ("`-''-/").___..--''"`-.__
> // Marcel Figuerola Estrada // `6_ 6 ) `-. ( ).`-.__.`)
> // pfa@tinet.fut.es // (_Y_.)' ._ ) `._ `.``-..-'
> // Valls - Catalunya - Europe // _..`--'_..-_/ /--'_.' ,'
> \//////////////////////////////// (il),-'' (li),' ((!.-'
>------------------------------------------------------------------------
Simon - http://www.spacetimepro.com Free CNC machine tool software
Article: 17681In article <37C172EE.CCA74D8D@xiphos.ca>, Joshua Lamorie <jpl@xiphos.ca> wrote: > Gidday there, > > Can anyone give me some useful pointers to information required to be > able to make my own JTAG 1149 programmer? I need to take raw binary > data and program an Altera Serial Configurator (EPC2). Should I just > get the IEEE spec and start from scratch, or are there some other decent > docs? Motorola's WEB site had a JTAG uploader with C source. I looked it over and ended up just writing my own from scratch. The JTAG state machine is simple enough to impliment. Are you just trying to avoid buying a programmer for the serial ROM? > > Thanks in advance > > Joshua Lamorie > Systems Designer > Xiphos Technologies Inc. > Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17682
David Kessner wrote: > The comparison of FPGA Express and Synplify, with respect to the > Free-DES core, is very meaningful but only in applications where ROM's > are implemented (which I admit is limited). We are mostly in agreement on this issue. One additional point is that implementing the ROM in the Virtex block rams might provide for vastly improved speed. > > I'm tempted to update my evaluation license for Exemplar (which I think > > has averaged as the number two tool in my past evaluations) just to try > > this design. > > That would be good. Try the Free-6502 as well. I'd like to put those > results up on the Free-IP Project web site... I'm in the process of downloading the files now. -- Phil Hays "Irritatingly, science claims to set limits on what we can do, even in principle." Carl SaganArticle: 17683
I need a fast scalable correlator. I would like to use an FPGA, and perhaps the XILINX correlator core, but it looks as if it would take up alot of 4000 series space (3 4085s?). Has anyone used the XILINX correlator core. Are there any ASICs out there better/smaller than the LOGIC Devices one?Article: 17684
On Mon, 23 Aug 1999 12:12:30 -0400, in <37C172EE.CCA74D8D@xiphos.ca> Joshua Lamorie <jpl@xiphos.ca> wrote: >Gidday there, > > Can anyone give me some useful pointers to information required to be >able to make my own JTAG 1149 programmer? I need to take raw binary >data and program an Altera Serial Configurator (EPC2). Should I just >get the IEEE spec and start from scratch, or are there some other decent >docs? The JTAG controller state machine is easy. What's difficult is knowing the commands and data structures used by a given device. Altera don't publish their private programming data, but it's possible to reverse-engineer it by decoding the JAM output from MaxPlus2. Everything you need can be found on Altera's web site, although collating it and making the necessary deductions isn't so straightforward. I can do the job for you, but I'll have to charge you for it :-) -- Steve Rencontre, Design Consultant http://www.rsn-tech.demon.co.uk/ -- remember to despam return addressArticle: 17685
How else do you know P&R has put the FFS in the IOB? Applying timing constraints to the input bus allows you to confirm this has been done. Darrin Utku Ozcan wrote in message <37B7B962.31A766E2@netas.com.tr>... > >Design Entry: Verilog >Synthesis: Synplify >P&R: Xilinx Design Manager >Technology: Xilinx > >I have 8-bit data input, say "data<*>", which is clocked by >"clock". I use following UCF command: > >NET "data<*>" OFFSET=IN 50 BEFORE clock ; > >But Placement&Routing report leaves time values empty for >this command. I have used following option: > >Pack I/O Register/Latches into IOBs for: Input/Output > >And Synplify directly connects this data bus to a register >set triggered by "clock". The name of these registers end >with "_inff", i.e. Synplify assumes that these can be mapped >to IOB's, which overlaps with the router option above. > >1. Since the IOB's are fixed to the pads, does it make any >sense to give timing constraints? I think, to have 50 ns >offset or 30 ns offset do not change the timing, since the >path from pad to IOB's are always the same, and thus always >have the same delay, tough. > >2. When a logic is mapped to an IOB, is it unnecessary to >use OFFSET constraints? > >-- >I feel better than James Brown. > >Article: 17686
Hello I just saw your message about JTAG, I'am also on the search for the IEEE 1149 document. If yo have an information were to get it would be very helpfull for me. If you would search how to use the Tap-Unit of an Intel 386ex Processor i could help you because i wrote a programm that uses the TAP to Programm a Flash Memory Thanks Gorkw In article <7pscoj$meg$1@nnrp1.deja.com>, ar679deja@my-deja.com wrote: > In article <37C172EE.CCA74D8D@xiphos.ca>, > Joshua Lamorie <jpl@xiphos.ca> wrote: > > Gidday there, > > > > Can anyone give me some useful pointers to information required > to be > > able to make my own JTAG 1149 programmer? I need to take raw binary > > data and program an Altera Serial Configurator (EPC2). Should I just > > get the IEEE spec and start from scratch, or are there some other > decent > > docs? > > Motorola's WEB site had a JTAG uploader with C source. I looked it > over and ended up just writing my own from scratch. The JTAG state > machine is simple enough to impliment. Are you just trying to avoid > buying a programmer for the serial ROM? > > > > > Thanks in advance > > > > Joshua Lamorie > > Systems Designer > > Xiphos Technologies Inc. > > > > Sent via Deja.com http://www.deja.com/ > Share what you know. Learn what you don't. > Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17687
Hi All,
I am hoping someone can help me out. I need to implement a memory element
the accepts a 72 bit input (9 bytes) and outputs 1 byte at a time each time
an input enable goes high. I would like a Verilog behavioural model and it
has to be synthesizeable. I had a design that simulated right but when I
synthesized it there we errors because more then one always block is
assigning a given variable.
This is what I had before:
module mem9_1 ( iCLK,
iRST,
iWR,
iRD,
iDIN,
oDOUT,
oDONE,
oEMPTY );
input iCLK;
input iRST;
input iWR;
input iRD;
input [71:0] iDIN;
output [7:0] oDOUT;
output oDONE;
output oEMPTY;
wire iCLK;
wire iRST;
wire iWR;
wire iRD;
wire [7:0] mem8 = iDIN[71:64];
wire [7:0] mem7 = iDIN[63:56];
wire [7:0] mem6 = iDIN[55:48];
wire [7:0] mem5 = iDIN[47:40];
wire [7:0] mem4 = iDIN[39:32];
wire [7:0] mem3 = iDIN[31:24];
wire [7:0] mem2 = iDIN[23:16];
wire [7:0] mem1 = iDIN[15:8];
wire [7:0] mem0 = iDIN[7:0];
reg [7:0] memory [8:0];
reg [7:0] oDOUT;
reg oDONE;
reg oEMPTY;
reg [3:0] pointer;
always @(negedge iCLK)
begin
if (!iRST)
begin
if (iRD)
begin
oDONE = 1'b1;
end
else
begin
oDONE = 1'b0;
end
end
else
begin
oDONE = 1'b0;
pointer = 4'h0;
oDOUT = 8'h00;
oEMPTY = 1'b1;
memory[8] = 8'h00;
memory[7] = 8'h00;
memory[6] = 8'h00;
memory[5] = 8'h00;
memory[4] = 8'h00;
memory[3] = 8'h00;
memory[2] = 8'h00;
memory[1] = 8'h00;
memory[0] = 8'h00;
end
end
always @(posedge iWR)
begin : write_block
memory[8] = mem8;
memory[7] = mem7;
memory[6] = mem6;
memory[5] = mem5;
memory[4] = mem4;
memory[3] = mem3;
memory[2] = mem2;
memory[1] = mem1;
memory[0] = mem0;
oEMPTY = 1'b0;
end
always @(posedge iRD)
begin : read_block
oDOUT = memory[pointer];
oDONE = 1'b1;
pointer = pointer + 1;
if (pointer == 9)
begin
pointer = 4'h0;
oEMPTY = 1'b1;
end
end
endmodule
Please point out anything else that could be done more efficiently or
whatever.
Cheers,
Tim
Article: 17688Rickman wrote: > Or perhaps I don't understand what you are asking. Are you looking for a > PLD type device to do the configuration of the Xilinx? I would not have > thought that was necessary since the Xilnx part can boot itself from > either a serial PROM or an addressable byte wide (E)EPROM. What exactly > is the "configurator" doing? A 'configurator' appears to be the standard name to describe the serial device that is manufactured by Xilinx, Atmel, or Altera with a dumb serial output. We have decided to go with an Altera device, because it is the smallest. The only question remaining is converting the output from the Xilinx software (some sort of bit file) into an SVF, or JAM file required by the Altera JTAG programmer. Or, I hack together a JTAG programmer of my own. Any hints? I'm sure this topic is of interest to many people, I will keep this newsgroup informed of my progress, and any suggestions about future use of this combination. Let me know if you want email rather than newsgroup. Joshua Lamorie Systems Designer Xiphos Technologies Inc.Article: 17689
Hi Tim, I think your problems arise because many signals in your module are edge triggered - but off more than one edge. For example your memory elements are reset to 0 on the clock negative edge as befits a synchronously reset register file, but are updated to new values on the edge of iWR as befits an asynchronous memory. Your oEMPTY signal is reset to 0 on the clock edge, cleared on a write by the edge of iWR and set on the final read by the edge of iRD. My suggestion would be to use only the clock edge and design a fully synchronous module. The behaviour would change slightly, ie new data would get written to the memory on the clock edge during which iWR was asserted rather than on the trailing edge of iWR, and new output would be asserted after the clock edge during which iRD was asserted rather than on the trailing edge of iRD. I would be happy to rework your design to reflect this if that is of interest to you. Regards, Robert. Tim Warnes wrote: > > Hi All, > > I am hoping someone can help me out. I need to implement a memory element > the accepts a 72 bit input (9 bytes) and outputs 1 byte at a time each time > an input enable goes high. I would like a Verilog behavioural model and it > has to be synthesizeable. I had a design that simulated right but when I > synthesized it there we errors because more then one always block is > assigning a given variable. > > This is what I had before: > > module mem9_1 ( iCLK, > iRST, > iWR, > iRD, > iDIN, > oDOUT, > oDONE, > oEMPTY ); > > input iCLK; > input iRST; > input iWR; > input iRD; > input [71:0] iDIN; > > output [7:0] oDOUT; > output oDONE; > output oEMPTY; > > wire iCLK; > wire iRST; > wire iWR; > wire iRD; > > wire [7:0] mem8 = iDIN[71:64]; > wire [7:0] mem7 = iDIN[63:56]; > wire [7:0] mem6 = iDIN[55:48]; > wire [7:0] mem5 = iDIN[47:40]; > wire [7:0] mem4 = iDIN[39:32]; > wire [7:0] mem3 = iDIN[31:24]; > wire [7:0] mem2 = iDIN[23:16]; > wire [7:0] mem1 = iDIN[15:8]; > wire [7:0] mem0 = iDIN[7:0]; > > reg [7:0] memory [8:0]; > reg [7:0] oDOUT; > reg oDONE; > reg oEMPTY; > reg [3:0] pointer; > > always @(negedge iCLK) > begin > if (!iRST) > begin > if (iRD) > begin > oDONE = 1'b1; > end > > else > begin > oDONE = 1'b0; > end > end > > else > begin > oDONE = 1'b0; > pointer = 4'h0; > oDOUT = 8'h00; > oEMPTY = 1'b1; > > memory[8] = 8'h00; > memory[7] = 8'h00; > memory[6] = 8'h00; > memory[5] = 8'h00; > memory[4] = 8'h00; > memory[3] = 8'h00; > memory[2] = 8'h00; > memory[1] = 8'h00; > memory[0] = 8'h00; > end > end > > always @(posedge iWR) > begin : write_block > memory[8] = mem8; > memory[7] = mem7; > memory[6] = mem6; > memory[5] = mem5; > memory[4] = mem4; > memory[3] = mem3; > memory[2] = mem2; > memory[1] = mem1; > memory[0] = mem0; > oEMPTY = 1'b0; > end > > always @(posedge iRD) > begin : read_block > oDOUT = memory[pointer]; > oDONE = 1'b1; > pointer = pointer + 1; > if (pointer == 9) > begin > pointer = 4'h0; > oEMPTY = 1'b1; > end > end > endmodule > > Please point out anything else that could be done more efficiently or > whatever. > > Cheers, > Tim -- ========================================================================= Robert R Fairlie - IC Design, Motorola, Scotland, Tel. - +44 1355 356039 =========================================================================Article: 17690
FPGA 2000
Call for Papers
Eighth ACM International Symposium on Field-Programmable Gate Arrays
Monterey, California
February 10-11, 2000
Submissions Due: October 1, 1999
The annual ACM/SIGDA International Symposium on Field-Programmable
Gate Arrays is the premier conference for presentation of advances in
all areas related to FPGA technology. For FPGA 2000, we are
soliciting submissions describing novel research and development in
the following (and related) areas of interest:
* FPGA Architecture: Logic block & routing architectures, I/O
structures and circuits, new architectures, Field-Programmable
Interconnect Chips and Devices (FPIC/FPID), Field-Programmable Analog
Arrays (FPAA).
* CAD for FPGAs: Placement, routing, logic optimization, technology
mapping, system-level partitioning, logic generators, testing and
verification. CAD for FPGA-based accelerators.
* Applications: Innovative use of FPGAs, exploitation of FPGA
features, novel circuits, high-performance and
low-power/mission-critical applications, DSP techniques, uses of
reconfiguration, FPGA-based cores.
* FPGA-based computing engines: Compiled accelerators, reconfigurable
computing, adaptive computing devices, systems and software.
* Rapid-prototyping: Fast prototyping for system level design,
Multi-Chip Modules (MCMs), logic emulation.
Authors are invited to submit PDF of their paper (12 pages maximum) by
October 1, 1999 via E-mail to hauck@ee.washington.edu. Notification
of acceptance will be sent by November 17, 1999. The authors of the
accepted papers will be required to submit the final camera-ready copy
by December 1, 1999. A proceedings of the accepted papers will be
published by ACM, and included in the Annual ACM/SIGDA CD-ROM
Compendium publication. Address questions to:
Scott Hauck
Program Chair, FPGA 2000
Dept. of EE, University of Washington
Box 352500
Seattle, WA 98195-2500
Phone: (206) 543-2150
Fax: (206) 543-3842
Email: hauck@ee.washington.edu
General Chair: Steve Trimberger, Xilinx
Program Chair: Scott Hauck, U. of Washington
Finance Chair: Sinan Kaptanoglu
Publicity Chair: Herman Schmit, Carnegie Mellon
Program Committee:
Miron Abramovici, Lucent David Lewis, U. of Toronto
Ray Andraka, Andraka Consulting Fabrizio Lombardi, Northeastern U.
Mike Bershteyn, Quickturn Wayne Luk, Imperial College
Michael Butts, Synopsys Margaret Marek-Sadowska, UCSB
Jason Cong, UCLA Jan Rabaey, UCB
Eugene Ding, Lucent Jonathan Rose, U. of Toronto
Carl Ebeling, U. of Washington Martine Schlag, UCSC
Reiner Hartenstein, U. Kaiserslautern Herman Schmit, Carnegie Mellon
Scott Hauck, U. of Washington Tim Southgate, Altera
Brad Hutchings, BYU Russ Tessier, U. Mass. - Amherst
Sinan Kaptanoglu, Actel Steve Trimberger, Xilinx
Tom Kean, Algotronix John Wawrzynek, UCB
Martin Wong, UT at Austin
Sponsored by ACM SIGDA, with support from Xilinx, Altera, Actel,
Lucent, Vantis and Cypress.
Please visit the web site <http://www.ece.cmu.edu/~fpga2000> for more
information.
Article: 17691Joshua Lamorie <jpl@xiphos.ca> wrote in message news:37C172EE.CCA74D8D@xiphos.ca... > Gidday there, > > Can anyone give me some useful pointers to information required to be > able to make my own JTAG 1149 programmer? I need to take raw binary > data and program an Altera Serial Configurator (EPC2). Should I just > get the IEEE spec and start from scratch, or are there some other decent > docs? For training how Boundary Scan works: try the trainer from Texas Instruments (scanedu.exe to be found somewhere on their webside - it's not new, it's not a graphical wonder BUT (I found it) VERY HELPFULL for learning about Bound.Scan - certainly for 'experiments' like you wish to do) I don't know the exact web-page ; and I don't find it back right away, I look if I can find it on another HD, and I'll let know then. Alain > > Thanks in advance > > Joshua Lamorie > Systems Designer > Xiphos Technologies Inc.Article: 17692
Hi Robert, Yes I would be very interested in this. After I posted my problem I looked at what I had and changed the code to operate off of one single clock but I am still having problems. For some guidelines I need the module to perform the following: - the write operation should write all 9 bytes in one clock cycle (not very critical but would help) - a byte should only be outputted when the RD line is inserted - only one byte should be outputted at one time Thanks for you help and I look forward to seeing what you come up with. Cheers, Tim Robert Fairlie wrote in message <37C2B9BA.53813DE1@mekb2.sps.mot.com>... [snip] > >My suggestion would be to use only the clock edge and design a fully >synchronous module. The behaviour would change slightly, ie new data would >get written to the memory on the clock edge during which iWR was asserted >rather than on the trailing edge of iWR, and new output would be asserted >after the clock edge during which iRD was asserted rather than on the >trailing edge of iRD. > >I would be happy to rework your design to reflect this if that is of interest >to you. > >Regards, Robert. >Article: 17693
Hi all, I am looking for APEX20K boards (or gerber files). Does anybody know where I can get this It would be great if the board has the possibility to connect SDRAM to the PLD Thank you for your help -- Jean-Luc DANGER email : danger@enst.fr ENST/dpt ComElec 46 rue Barrault 75013 PARIS Phone : 01 45 81 81 17 Fax : 01 45 80 40 36Article: 17694
Tim,
This may not be perfect, but it should get you pretty close.
module mem9_1 ( iCLK,
iRST,
iWR,
iRD,
iDIN,
oDOUT,
oDONE,
oEMPTY );
input iCLK;
input iRST;
input iWR;
input iRD;
input [71:0] iDIN;
output [7:0] oDOUT;
output oDONE;
output oEMPTY;
reg [7:0] oDOUT;
reg [71:0] mem;
reg [3:0] pointer;
reg oDONE;
always @ (posedge iCLK or negedge iRST)
if (~iRST)
mem <= 72'h000000000000000000;
else if (iWR)
mem <= iDIN;
always @ (posedge iCLK or negedge iRST)
if (~iRST) begin
pointer <= 4'h0;
oDONE <= 1'b1;
end
else if ((iWR) || (pointer == 4'h8)) begin
pointer <= 4'h0;
oDONE <= iWR ? 1'b0 : 1'b1;
end
else if (iRD) begin
pointer <= pointer + 1'b1;
oDONE <= 1'b0;
end
assign oEMPTY = oDONE;
always @ (pointer or iRD or mem)
if (~iRD)
oDOUT <= 8'hzz;
else
case (pointer)
4'h0: oDOUT <= mem[7:0];
4'h1: oDOUT <= mem[15:8];
4'h2: oDOUT <= mem[23:16];
4'h3: oDOUT <= mem[31:24];
4'h4: oDOUT <= mem[39:32];
4'h5: oDOUT <= mem[47:40];
4'h6: oDOUT <= mem[55:48];
4'h7: oDOUT <= mem[63:56];
4'h8: oDOUT <= mem[71:64];
default: oDOUT <= 8'h00;
endcase
--
Mark Lancaster email: mark.lancaster@motorola.com
Motorola WSSG M/S: CH275 phone: (480)814-4920
1300 N. Alma School Rd. fax: (480)814-3107
Chandler, AZ 85224
Article: 17695You can find TI's Boundary Scan Educator at this link: http://www.ti.com/sc/docs/jtag/educ.htm#sedu It is an invaluable tool. There is a good deal of useful information about boundary-scan on the TI web site at http://www.ti.com/sc/docs/jtag/educ.htm An actual copy of the standard can be purchased from the IEEE at either: http://standards.ieee.org/catalog/olis/gr_testtech.html or http://standards.ieee.org/catalog/test.html Hope this helps. Alain Cloet wrote: > Joshua Lamorie <jpl@xiphos.ca> wrote in message > news:37C172EE.CCA74D8D@xiphos.ca... > > Gidday there, > > > > Can anyone give me some useful pointers to information required to be > > able to make my own JTAG 1149 programmer? I need to take raw binary > > data and program an Altera Serial Configurator (EPC2). Should I just > > get the IEEE spec and start from scratch, or are there some other decent > > docs? > > For training how Boundary Scan works: try the trainer from Texas Instruments > (scanedu.exe to be found somewhere on their webside - it's not new, it's not > a graphical wonder BUT (I found it) VERY HELPFULL for learning about > Bound.Scan - certainly for 'experiments' like you wish to do) > > I don't know the exact web-page ; and I don't find it back right away, I > look if I can find it on another HD, and I'll let know then. > > Alain > > > > > Thanks in advance > > > > Joshua Lamorie > > Systems Designer > > Xiphos Technologies Inc.Article: 17696
Project VeriPage: http://www.angelfire.com/ca/verilog/ I. What's new ? 1. Couple of new examples have been added. 2. The "(For the rest of us who want it FREE)" section has been revised and new projects are added. 3. A site search has been added for easy surfing. II. About Project VeriPage: This is a free informative site on Verilog PLI with a growing number of articles on Verilog in general. Although there are few sites available for Verilog related information, this is the only site in my knowledge, which has been focussed on Verilog PLI. It has a number of resources on the subject including a FAQ, a tutorial and several examples on Verilog PLI. If you are a novice, take a look if it can help you in breaking the ice; if you are a guru, stop by and impart your knowledge to others. -- =-=-= 100% pure Verilog PLI - go, get it ! =-=-= Principles of Verilog PLI -By- Swapnajit Mittra Kluwer Academic Publishers. ISBN: 0-7923-8477-6 http://www.angelfire.com/ca/verilog/ Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17697
To all, We are using the block RAM in the Xilinx Virtex devices. We intialize the RAM using the UCF. Has anyone tried to changed the contents of the Xilinx Virtex Block RAM without going through place and route? If we want to change it's contents, we don't want to have to run through a full place and route. Clearly we can use the -g option (guide file) and read in the reviously placed and routed design, but has anyone done this another way? Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17698
Anyone has develop/modify Jbits to support XS40 board from Xess Corp. ? Thank you.Article: 17699
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microcontrollers - used for low-speed I/O (KHz range) and algorithms with complicated control flow.
FPGAs - used for high-speed I/O (MHz range) and algorithms with simple control flow.
Daniel Figuerola Estrada wrote:
> I am making a project in wich I compare advantages and disadvantages in
> using microcontrollers and FPGA in the design of a digital system.
>
> Has anyone worked with those two technologies and could give his opinion
> of them?
>
> ------------------------------------------------------------------------
> ////////////////////////////////\ ("`-''-/").___..--''"`-.__
> // Marcel Figuerola Estrada // `6_ 6 ) `-. ( ).`-.__.`)
> // pfa@tinet.fut.es // (_Y_.)' ._ ) `._ `.``-..-'
> // Valls - Catalunya - Europe // _..`--'_..-_/ /--'_.' ,'
> \//////////////////////////////// (il),-'' (li),' ((!.-'
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Content-Type: text/x-vcard; charset=us-ascii;
name="devb.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Dave Vanden Bout
Content-Disposition: attachment;
filename="devb.vcf"
begin:vcard
n:Vanden Bout;David
tel;fax:(919) 387-1302
tel;work:(919) 387-0076
x-mozilla-html:FALSE
url:http://www.xess.com
org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;28560
fn:Dave Vanden Bout
end:vcard
--------------7F5BCFECDC6651C06E1602D3--
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