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Dongho Chung wrote: > > LPM is written by AHDL not VHDL. If you are using LPM, your design is no > more VHDL desing. > That was a "letter of the law" vs. "spirit of the law" reply. I am sure the original poster appreciates your "helpful advice". The question really was "is it necessary to use paramaterized functions" to optimize a design in VHDL. Now we know that LPM is an Altera acronym used with their AHDL language, but we also know that VHDL supports generics to make parameterized components, and this is (probably) what he was asking. The answer to the original question is 'maybe'. Depends upon your particular application, i.e. speed, size, functionality. I personally have never needed hand crafted functions. But then again I generally do medium speed control applications and not high speed data path stuff. BTW, I am sure glad that US Actel support people aren't as "helpful" as the Korean Actel team. -- Brian C. Boorman Harris RF Communications Rochester, NY 14610 XYZ.bboorman@harris.com <Remove the XYZ. for valid address>Article: 17651
ATTENTION:
- SoC Designers
- IP Developers and Integrators
- SoC Tool and Service Providers
- Engineering Management and Executives
On September 30, 1999
Silicon Valley is the site for the VSI Alliance's
"OPEN SOC FORUM and VSIA WORLDWIDE MEMBER MEETING"
Featuring Keynote Speech by Hector Ruiz
President of Motorola's Semiconductor Products Sector
"MOTOROLA'S SYSTEM-ON-A-CHIP DEVELOPMENT ECOSYSTEM"
This event is open to all VSIA members at no cost!
For the first time, non-members may also attend for a fee of $200.
TO REGISTER:
Members go to:
http://216.15.112.114:80/member.htm
Non-members go to
http://216.15.112.114:80/non-member.htm
(To check if your company is a VSIA member, please go to
http://www.vsi.org/members.htm.)
OR call 408-356-8800
Seating is limited.
Ensure yourself a seat by registering today!
PROGRAM:
- 7:30 - 9:00 Registration and complimentary breakfast buffet
- 8:00 - 9:00 A special "Meet VSIA" meeting for those unfamiliar with
VSIA, its charter, and vision for the future of SoC.
- 9:00 Keynote Address
"MOTOROLA'S SYSTEM-ON-A-CHIP DEVELOPMENT ECOSYSTEM"
Hector Ruiz, President of Motorola's Semiconductor Products
Sector
- Technical Sessions beginning at 11:00 a.m.
1. "YOU CAN'T PULL QUALITY OUT OF A HAT"
Janick Bergeron, VP of Technical Wisdom
Qualis Design Corporation
2. "VERIFICATION: THE NEXT BIG CHALLENGE FOR VIRTUAL OMPONENTS"
Robin Bhagat, Organizing Chairman
VSIA Functional Verification Development Working Group
3. "VC INTEGRATION AT SYSTEM-LEVEL SPEEDS SOC DESIGN!"
Chris Lennard, Chairman,
VSIA System-Level Design Development Working Group
4. "MULTI-CORE INTEGRATION UTILIZING
THE VIRTUAL CHIP INTERFACE (VCI) STANDARD"
Ajit Deora, Director of Engineering, Semiconductor IP Group
Phoenix Technologies
- 5:00 Cocktail/Networking Reception
TIME & PLACE:
Santa Clara Marriott Hotel
2700 Mission College Blvd.
Santa Clara, California
8:00 a.m. - 5:00 p.m.
Breakfast and Lunch will be provided
We hope you can join us for this enlightening and educational
opportunity.
Stan Baker
Executive Director
VSI Alliance, Inc.
Article: 17652I am using v1.5 student edition. That means it doesn't support VHDL'93, am I right? Andy Peters wrote in message <7pemcp$1tm2$1@noao.edu>... >>Can somebody tell me how can I enable VHDL'93 on Xilinx Foundation >>(student ed)? (or, perhaps, it doesn't support '93 at all!). Thanks for >>help. > >you can't "enable" it. What version of Foundation are you using? > >Some support for '93 was added in FPGA Express 3.1; it's supposed to be >better in 3.2. >-- >----------------------------------------- >Andy Peters >Sr Electrical Engineer >National Optical Astronomy Observatories >950 N Cherry Ave >Tucson, AZ 85719 >apeters (at) noao.edu > >The Republican Party: "We've upped our standards. Now, up yours!" >Chi Fung wrote in message <37ba25bf.0@scctn03.sp.edu.sg>... > > >Article: 17653
z0rbaf@newsguy.com wrote in message <7ov6s7$1bnd@edrn.newsguy.com>... >Does anyone here have any experence with the XILINX >4000 series logic? I am attempting to parrallel load >a 4020 and the load is failing. I'm using the same >bits as would program the chip in serial mod through >the Xchecker cable. any help here? & thanks much. When you went into the PROM formatter tool, did you: 1) Tell it that you're doing a parallel load? It's different from the serial mode! 2) Tell it that you're starting from address 0 in the EPROM or from the top? 3) Tell it the right EPROM size? Also: Do you have the FPGA's mode pins pulled up and down correctly? Make sure it's set for master parallel (I don't have the datasheet right here). Make sure all of the other configuration pins are in the proper state (read the databook). Parallel loading should just "work" assuming the mode pins are set right and the EPROM is formatted correctly. -- a ---------------------------------------------------------------------------- -- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories apeters (at) noao.edu The Repulican Party: "We've upped our standards. Now, up yours!"Article: 17654
Hi. I recently started using a new browser because they said they would pay me for using it. It's completely legit, so I want to share this with you. GoToWorld.com is a search engine that is offering a cool Web browser. All I have to do is use there browser which has an advertising bar on it. The bar can be turned on or off, and when it's on I get paid money to surf the Web (which I do any way!!). You really have to check this out! It's great! http://www.gotoworld.com/getpaid/default.asp?rid=1022693393 You can download your copy of the browser and to start making money for browsing. Also, the more friends you tell about this, the more money you will make. MAKE MONEY!Article: 17655
In article <7pevu4$2pvf$1@obiwan.pmr.com>, "Bob Pearson" <bpearson@pmr.com> wrote: > Hi, > > Has any one encountered a situation where M1.5i > map get hung apparently in an infinite loop? And > if so what was the cause? I had a problem with it bombing out with a GPF due to a faulty VC++ runtime DLL. I copied the DLL from another PC and it then worked OK. Xilinx support confirmed that this is a common problem and told me that some people had difficulties running the software under Win98. Apparently, it is only intended for Win95. I find this hard to believe, though. Leon Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17656
Hi, can somebody tell me how to constrain two FFs that synchronize two different signals with the same clock followed by a simple or-gate to be implemented into one Xilinx XC4005 CLB. I use schematic entry from OrCAD and the usage of constraints is very similar to that of Xilinx Foundation entry. I also use an UCF-file. Regards, Heinrich FonfaraArticle: 17657
New Millennium Inc., a leading supplier of Software, Hardware and IT professionals to end clients around the world, has the following position open. Please take the time to peruse the below description and, if interested, please contact me at the numbers/email address at the end of this message. Location: Stevenage, Herts, UK Duration: 3 months+ Description: Our client is looking for an experienced Digital Design Engineer to work on product areas of development across engineering. The successful candidate would be educated to degree level or equivalent in a similar role. The main responsibilities will include FPGA detail design (Xilinx and/or Lattice), digital detail design, plus embedded systems specifications and designs. An understanding of processors, FPGA tools, VHDL design and C/Assembler languages are essential, previous experience of Veribest tools is desirable. The role demands excellent communication skills, the ability to work on your own or part of a team and some supervisory skills would be desirable. Thanks for taking the time to examine this position. I'm available at the numbers below to answer any additional questions. -- Michael Murphy New Millennium Inc. 401-792-0997 (V) 800-381-9507 (V) 800-381-8708 (F) mmurphy@newmill.comArticle: 17658
Has anyone any experience using the Virtex development board from Nallatech ? My impression from the web presentation, data sheets... is that the boards are quite good. Any advice or comments on pro's and con's of the boards would be much appreciated before I start to consider buying them. Regards Alexander SchwarzArticle: 17659
The Free-IP Project announces the availability of the Free-6502 8-bit CPU core, and the Free-DES data encryption core. They are available at: http://www.free-ip.com David Kessner davidk@free-ip.comArticle: 17660
Anybody writting any firmware using JBits? I could do with some help!!! GordonArticle: 17661
Gidday there,
I have a Xilinx FPGA going into a PCMCIA card. The problem, is that
none of the in-system reprogrammable parts from Atmel are small enough
to fit (less than 2.51mm tall).
Anyone done this before? I'm currently looking at using an Altera
Flash based configurator in a TQFP. Any problems with this?
Joshua Lamorie
Article: 17662Hi, I am trying to explicitly instantiate a LUT3 in Verilog in Foundation Express 1.5i so that I can attach a LOC attribute. F-E seems to think that LUTS don't have an output (which was true of FMAPS but not LUTS). Has anyone ever done this before? Bob Pearson bpearson@pmr.comArticle: 17663
I am making a project in wich I compare advantages and disadvantages in
using microcontrollers and FPGA in the design of a digital system.
Has anyone worked with those two technologies and could give his opinion
of them?
------------------------------------------------------------------------
////////////////////////////////\ ("`-''-/").___..--''"`-.__
// Marcel Figuerola Estrada // `6_ 6 ) `-. ( ).`-.__.`)
// pfa@tinet.fut.es // (_Y_.)' ._ ) `._ `.``-..-'
// Valls - Catalunya - Europe // _..`--'_..-_/ /--'_.' ,'
\//////////////////////////////// (il),-'' (li),' ((!.-'
------------------------------------------------------------------------
Article: 17664
Daniel Figuerola Estrada <pfa@tinet.fut.es> wrote in message
news:37BE90C5.D41BA8EF@tinet.fut.es...
> I am making a project in wich I compare advantages and disadvantages in
> using microcontrollers and FPGA in the design of a digital system.
>
> Has anyone worked with those two technologies and could give his opinion
> of them?
>
>
> ------------------------------------------------------------------------
> ////////////////////////////////\ ("`-''-/").___..--''"`-.__
> // Marcel Figuerola Estrada // `6_ 6 ) `-. ( ).`-.__.`)
> // pfa@tinet.fut.es // (_Y_.)' ._ ) `._ `.``-..-'
> // Valls - Catalunya - Europe // _..`--'_..-_/ /--'_.' ,'
> \//////////////////////////////// (il),-'' (li),' ((!.-'
> ------------------------------------------------------------------------
This is a very complicated matter and cannot be answered in just a few
sentences. But you might start your investigation by checking out the
following item: www.cs.berkeley.edu/~amd/reconfig_com_roundtable_oct96
This presentation is rather "scientific", but explains very well where to
use and not use FPGAs and microcontrollers, respectively. It all depends on
the type of algorithms you want to execute; there is definitely a role for
either approach.
Regards,
Krister Wikström
Article: 17665Pieter, Check out our APS-X240 boards at http://www.associatedpro.com they have PC104 connectors 2 128K by SRAMs an osc socket, 6 50 pin connectors, and can be ordered with any xilinx 4000 or 5000 series (XLA/XL/E/EX) 240 pin QFP, The 50 pin connectors are .1 inch centered connectors with 25 signals and 25 grounds so you could connect an AtoD demo board from Analog devices for example right ot the board. (We have done this before). Also the X240 board can be used in a PC ISA slot (with an optional carrier board) IN A pc104 STACK, OR STAND ALONE. A 2.4 amp wall transformer is available for stand alone operation. Pieter Op de Beeck wrote: > Hi, > > Currently I find myself in a position where I have to decide whether I > should buy or make an fpga based board. To give more details : it > should contain a modest fpga (XC4025) and possibly an A/D converter. > That's it, not even external ram or anything. > So, what would you suggest? > > By the way, where can I find pricelists for the Xilinx devices? > > Kind regards, > Pieter > > Pieter Op de Beeck > K.U.Leuven - ESAT - PSI/ACCA > Kardinaal Mercierlaan 94 > 3001 Heverlee > pieter.opdebeeck@esat.kuleuven.ac.beArticle: 17666
just check-out http://www.free-ip.com/DES/index.htm and look for the comparisons between Synplify and FPGA express. muzo Verilog, ASIC/FPGA and NT Driver Development Consulting (remove nospam from email)Article: 17667
Utku Ozcan wrote: > > Design Entry: Verilog > Synthesis: Synplify > P&R: Xilinx Design Manager > Technology: Xilinx > > I have 8-bit data input, say "data<*>", which is clocked by > "clock". I use following UCF command: > > NET "data<*>" OFFSET=IN 50 BEFORE clock ; > > But Placement&Routing report leaves time values empty for > this command. I have used following option: > > Pack I/O Register/Latches into IOBs for: Input/Output > > And Synplify directly connects this data bus to a register > set triggered by "clock". The name of these registers end > with "_inff", i.e. Synplify assumes that these can be mapped > to IOB's, which overlaps with the router option above. > > 1. Since the IOB's are fixed to the pads, does it make any > sense to give timing constraints? I think, to have 50 ns > offset or 30 ns offset do not change the timing, since the > path from pad to IOB's are always the same, and thus always > have the same delay, tough. > > 2. When a logic is mapped to an IOB, is it unnecessary to > use OFFSET constraints? > > -- > I feel better than James Brown. If I understand what you are asking, I believe the answer is: no, you don't need OFFSET constraints for signals that are clocked into the IOB flipflop. The same on outputs. The only control you have over the IO timing for IOB registers is to add delay to the input or to change the edge rate for outputs. This is done with specific constraints which formats I don't quite remember. They might be something like NET FAST <name>. Look up the DELAY, FAST and SLOW keywords in the manuals. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 17668
muzo wrote: > > just check-out http://www.free-ip.com/DES/index.htm and look for the > comparisons between Synplify and FPGA express. This comparison just isn't very meaningful. It's based on a single flaw in FPGA Express. Don't misunderstand this: I think Synplify is currently the best synthesis tool on the market today. They have generally given the best results (meaning smaller and faster) for most of the past couple of years with the least amount of engineering effort. It's just that other tools are just not as far behind as this comparison would imply. From the above URL: "This was traced down to the S-Boxes, which are implemented as 64x4 ROM's. Under FPGA Express, these took about 33 slices where Synplify took 10 slices." If the team at Synopsis is serious about staying in business, this flaw will be fixed in a matter of months. Suppose this flaw is fixed in a new release in few months. Then the small case for FPGA express will decrease from 905 by 184 to 721 slices, slightly smaller than Synplify at 731 slices. But wait, the Synplicity team is pretty unlikely to stand still. While we are at it, FPGA Express is a better tool for learning, as it generally has better compiler error and warning messages. Not everyone is driven only by smaller and faster designs, sometimes faster learning is important as well. I'm tempted to update my evaluation license for Exemplar (which I think has averaged as the number two tool in my past evaluations) just to try this design. -- Phil HaysArticle: 17669
Hi everybody, I'm looking for a DSP/FPGA development system to do the following: Capture the RGB output (1280x1024, 75Hz, 24bit) of a standard PC (Mac, SGI, etc.), do some processing, then output RGB again. (btw, there is a reason why I don't do the processing within the PC) Processing: 2D spatial transformations like zooms and shifts but also more complex according to displacement maps. Plus 4pt. bilinear interpolation In particular I couldn't find any frame grabbers that can handle the high pixelrates of almost 100Mpixel/s. Usually they're targeted at video capturing with max. 40Mpixel/s. Also, most frame grabbers are PCI cards - I'm looking for an embedded system solution. Another problem is memory bandwitdh. Apart from accessing the image buffer at least 4 times (for the interpolation) I also have to pipe in the displacement and interpolation data. What I did find is an ADC from AD (AD9884) that might at least be suited for the converting, although it's mainly targeted at LCD monitors. However, I'd really like to avoid messing too much with the hardware. In general I'd prefer a "one-supplier-solution" rather than buying components from different companies. I'd also be willing to spent some money on a nice software environmant rather than doing everything from scratch in assembler. Finally, does anyone know a newsgroup that specializes on image processing (like the music-dsp list does for sound) ?? Thanks, Sukandar sk@zkm.deArticle: 17670
Joshua Lamorie wrote: > > Gidday there, > > I have a Xilinx FPGA going into a PCMCIA card. The problem, is that > none of the in-system reprogrammable parts from Atmel are small enough > to fit (less than 2.51mm tall). > > Anyone done this before? I'm currently looking at using an Altera > Flash based configurator in a TQFP. Any problems with this? > > Joshua Lamorie I am not sure that you looked at all the parts that Atmel makes. They have the AT40K series of parts which come in several packages including the VQ100 and the TQ144, both of which are well under 0.1" as well as a couple of BGA packages with 225 pins and up. The older AT6000 series parts also come in the VQ100 and TQ144 packages. Or perhaps I don't understand what you are asking. Are you looking for a PLD type device to do the configuration of the Xilinx? I would not have thought that was necessary since the Xilnx part can boot itself from either a serial PROM or an addressable byte wide (E)EPROM. What exactly is the "configurator" doing? -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 17671
Joshua Lamorie wrote: > > Gidday there, > > I have a Xilinx FPGA going into a PCMCIA card. The problem, is that > none of the in-system reprogrammable parts from Atmel are small enough > to fit (less than 2.51mm tall). > > Anyone done this before? I'm currently looking at using an Altera > Flash based configurator in a TQFP. Any problems with this? > > Joshua Lamorie I checked some of the Atmel data sheets I have on hand and both of the PLD type parts I have data on come in a TSSOP package that is only about 1 mm high. These are the ATF16V8C, and the ATF20V8C (preliminary). Are these parts not what you call in system reprogrammable? I have not worked with them yet. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 17672
Hi All, I'm sure there's something simple that I'm just not getting, but I'm having this problem with getting a BIDIR port working as I'd expect. I'm simply trying to get a multiplexed Address/Data port to provide seperate address and data inputs, and a data output. Now, it's easy with glue logic to do this, but MAX2PLUS is complaining that I need to connect a BIDIR tri-state buffer to a bidir port (It is... I Think.) I'm using a custom LPM function created via the Megafunction wizard. Max2plus is ver 9.23 baseline. Thanks in advance, Cheers, Grant > Some days you're the dog, some days you're the hydrant.Article: 17673
Sorry guys, The Xilinx part is based on SRAM, In order to configure the part, you need to upload the FPGA from a Non Volatile Memory Joshua is asking for the NVM in a thin package, not the PLD/FPGA etc as such. As far as I know, there are only PLCC and DIP Atmel configurators available, but as normal this view may not be shared by Atmel, so Joshua, I suggest you drop configurator@atmel.com a mail and ask them. There may be someting in the works that I do not know about. -- This is a personal view which may or may not be shared by my employer Atmel Sweden Ulf Samuelsson ulf 'a't atmel 'd'o't com Rickman skrev i meddelandet <37C08303.8C4BEF11@yahoo.com>... >Joshua Lamorie wrote: >> >> Gidday there, >> >> I have a Xilinx FPGA going into a PCMCIA card. The problem, is that >> none of the in-system reprogrammable parts from Atmel are small enough >> to fit (less than 2.51mm tall). >> >> Anyone done this before? I'm currently looking at using an Altera >> Flash based configurator in a TQFP. Any problems with this? >> >> Joshua Lamorie > >I am not sure that you looked at all the parts that Atmel makes. They >have the AT40K series of parts which come in several packages including >the VQ100 and the TQ144, both of which are well under 0.1" as well as a >couple of BGA packages with 225 pins and up. > >The older AT6000 series parts also come in the VQ100 and TQ144 packages. > >Or perhaps I don't understand what you are asking. Are you looking for a >PLD type device to do the configuration of the Xilinx? I would not have >thought that was necessary since the Xilnx part can boot itself from >either a serial PROM or an addressable byte wide (E)EPROM. What exactly >is the "configurator" doing? > > >-- > >Rick Collins > >rick.collins@XYarius.com > >remove the XY to email me. > > > >Arius - A Signal Processing Solutions Company >Specializing in DSP and FPGA design > >Arius >4 King Ave >Frederick, MD 21701-3110 >301-682-7772 Voice >301-682-7666 FAX > >Internet URL http://www.arius.comArticle: 17674
Dear friends,
Can any one explain how to pass constraints( Including the
constraints given to the inner level blocks of a design) from SYNOPSYS
FPGA compiler to XILINX m1 implementation tools? The problem goes like
this. Synopsys FPGA compiler writes the constraints given to a design in
a .DC file. But the constraints given to the inner level blocks are not
written to .DC. I tried the "propagate_constraints -all"
command. I also tried "write_script -heirarchy > TOP + ".dc" " while
writing
the .DC file in SYNOPSYS FPGA compiler.
Since I am not able to write the constraints(of the inner level
blocks of a design) to .DC file SYNOPSYS FPGA compiler level in the
appropiate format, I am not able to use dc2ncf script of xilinx
efficiently, to transfer the constraints to .NCF format. Please help..
Thanks in advance.
Regards
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z