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In article <37C6A794.EA82B0AA@xiphos.ca>, Joshua Lamorie <jpl@xiphos.ca> wrote:
>Gidday there,
>
> I'm currently climbing up the learning curve with FPGA Express, and
>porting my VHDL (isn't that a silly statement) from Cypress Warp. I
>keep getting the following error on my code.
>
>Error L-1/C0:#0 Not enough storage is available to complete this
>operation.
>
> According to the Xilinx Answer #5301, this is due to underscores within
>binary strings. However, though I am using binary strings, I do not
>have any underscores. You can find the answer at:
>
>http://www.xilinx.com/techdocs/5301.htm
>
> Actually, it can't be anything with the strings, I just can't get past
>this step. Is there a patch somewhere? The software was installed by a
>Xilinx FAE, with about 30 CDs (exageration). So, maybe he missed one.
>
> Any hints would be greatly appreciated.
>
>Joshua Lamorie
>Systems Designer
>Xiphos Technologies Inc.
>
>ps. Some specs
>
>PC: P-II 350 w/128MB RAM 270MB Virtual
>OS: NT4 SP5
>Foundation: F1.5 Build 3.1.140
>FPGA Express: 3.1.1.0w
There is a major bug in the Synopsis stuff included with F1.5 (any version
AFAIK; SP2 still has it) that could cause this error. A few weeks after
I posted this to the XIlinx "hotline", they replied something like: "we've
confirmed this is a bug in Synopsis, and we can only wait for Synopsis to fix
it".
The bug shows up when using nested loop statements. The compiler keeps
allocating memory until all of it is gone (real + virtual) and then it bails
out with a message similar to what you've seen. This may take a LONG time.
All other compilers I tested (even the crappy Altera VHDL compiler) have no
idea why this is so difficult :-)
Small exploit appended. Don't shoot me if your compiler doesn't crash. Mine
and the xilinx hotline one did...
K.
-----------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package Output_Handling_pack is
component Output_Handling
port (Clock: in std_logic;
Inc: in std_logic;
Start: in std_logic;
DataIn: in std_logic_vector( 0 to 10);
Outg: out std_logic;
DataOut: out std_logic_vector(15 downto 0));
end component;
end package;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity Output_Handling is
port (Clock: in std_logic;
Inc: in std_logic;
Start: in std_logic;
DataIn: in std_logic_vector( 0 to 10);
Outg: out std_logic;
DataOut: out std_logic_vector(15 downto 0));
end output_handling;
architecture behav of Output_Handling is
begin
p1:
process (Inc, DataIn, Clock, Start)
variable Count, Sum: unsigned( 4 downto 0);
variable Addr, Spare: unsigned( 4 downto 0);
variable OutBuff: std_logic_vector(31 downto 0);
begin
if (Start='0') then
Addr := (others => '0');
Outg <= '0';
DataOut <= (others => '-');
elsif (rising_edge(Clock)) then
Outg <= '0';
if (Inc='1') then
if (DataIn(0)='0') then
Count := conv_unsigned(9,Count'length);
else
Count := conv_unsigned(11,Count'length);
end if;
Spare := Addr + Count;
for I in 0 to 10 loop
for II in 0 to 31 loop
if (II=Addr) then
Sum:=conv_unsigned(I,5)+conv_unsigned(II,5);
Outbuff(conv_integer(Sum)) := DataIn(I);
end if;
end loop;
end loop;
if (Addr(4)/=Spare(4)) then
Outg <= '1';
if (Spare(4)='1') then
DataOut(15 downto 0) <= OutBuff(15 downto 0);
else
DataOut(15 downto 0) <= OutBuff(31 downto 16);
end if;
end if;
Addr := Spare;
end if;
end if;
end process;
end behav;
Article: 17751Can anybody tell me what the LPCILOGIC site in the Virtex does? It is apparently for PCI apps, but could someone elaborate?Article: 17752
I am using VHDL with MAX+plus II version 8.0. I have three component,
two with a inout port and one with a out port. I would like to link the
three port with the same signal.
Part of the program body is show below. It make me wrong when
assign more than one signal to the same wire (error messaje: Signal
BDataBus/BDataRam has multiple sources
The process is used to control the bidirectional bus access. The
component can not assign more than one signal to the bus at the same
time, it is control by the ce_eprom,read_mem signal
Architecture mia is Procesador of
signal Bce_eprom : std_logic;
signal Bread_mem : std_logic;
signal Bdatabus : std_logic_vector(7 DOWNTO 0);
signal BDataRom : std_logic_vector(7 DOWNTO 0);
signal BDataRam : std_logic_vector(7 DOWNTO 0);
...
begin
...
Activa_CPU:cpu
port map(...
ce_eprom => Bce_eprom,
read_mem => BRead_mem,
databus => BdataBus --inout port(1 assign to BDataBus)
...);
Memoria_RAM:ram2
port map (...
databu2 => BDataRam, --inout port(1 assign to BDataRam)
...);
Memoria_EPROM:eprom2
port map (...
databu => BDataRom, --out port
...);
process(clock)
begin
if clock'event and clock='1' then
if Bce_eprom='0' then
BDataBus<=BDataRom; --(2 assign to BDataBus)
else
if Bread_mem = '1' then
BDataBus<=BDataRam;
else
BDataRam<=BDataBus; --(assign to BDataRam)
end if;
end if;
end if;
end process;
...
end mia;
Germán Acosta
Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.
Article: 17753I got this reply from Xilinx, This block contains a couple of simple and/or gates and a dedicated route to the CE pins of IOBs along that edge (there are two in a device on the left and right edges). This block was designed to work with the Xilinx PCI interface at 66MHz. What I don't know is how to instantiate it! Bill In article <37caa4c8.234020955@client.sw.news.psi.net>, steves@traclabs.com wrote: > Can anybody tell me what the LPCILOGIC site in the Virtex does? It is > apparently for PCI apps, but could someone elaborate? > > -- ----------------------------- Alpha Data ----------------------------- Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17754
Hi, I am using a Xilinx Spartan Configuration Prom xc17s40 which theoretically is not cascadable, now I have also used the 17256D which is cascadable as the first device, this has a CEO output to cascade this I have connected to the 17S40 device's OE, I feel that it should work but it doesn't. I get a configuration error after approx 64k bits have been read from the 17s40 device (after the 17256 is completely read). Does anyone know why its happening or is there a way to cascade these devices? Any help will be appreciated. Regards Sharad sharad@bisquare.com Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17755
Hi, well, the problem should be located in the > process(clock) > begin > if clock'event and clock='1' then > if Bce_eprom='0' then > BDataBus<=BDataRom; --(2 assign to BDataBus) > else > if Bread_mem = '1' then > BDataBus<=BDataRam; > else > BDataRam<=BDataBus; --(assign to BDataRam) > end if; > end if; > end if; > end process; > ... > end mia; > part of your file. In this process you assign the signals to BDataBus. I assume, that the BDataBus is an inout port to the external hardware, isn't it? First I wouldn't write ... else if use elsif to declare the 'else' clause of the first 'if' advisement. Try to write it that way. Another possibility could be, that you have to assign "ZZZZZZZZ" to the BDataBus if you reach the final else clause. This would put the output buffers in TriState. I use it in conjunction with an FSM and an Selected State Signal assignment (With state select...) this usage works fine on my Max+PlusII. CU, CSArticle: 17756
Hi Phil, Could you please share some more ideas and experiences on the high-speed FPGA design? Based on your opinions, what is the best synthesis tool in the market for the FPGA design? I am going to use the Altera tool for a project at 125Mhz. As you may have already known, Altera did a poor job on synthesizing the Verilog code. Because of that, we will use the Synopsys Design Compiler (targeting on the Altera liberary), synthesis the Verilog code and save the result as an EDIF file, then use Altera to do the placement and routing. Do you think the above methodology works? Or, we have to buy another synthesis tools? Thanks in Advance! In article <37C78660.E301C7C9@sprynet.com>, Phil Hays <spampostmaster@sprynet.com> wrote: > thiru1457@my-deja.com wrote: > > > I intend to implement a logic in FPGA (roughly > > 12K logic gates complexity), running at 200 MHz. > > > > Is it possible to implement the above design, > > with the current FPGA technology?. > > It is impossible to estimate practicality or effort needed without any > more information. > > The size is no problem. > > The speed might be a problem. The path from flip flop, through any > routing and/or logic, to setup into the next flip flop needs to be 5 ns > or less for all paths (with a few exceptions) for a design running at > 200 MHz. To route a signal a significant distance may well take several > ns. To get a design to work at such speeds there can be at most only a > few levels of logic between each flip flop, and not much routing, or > perhaps a longer route (or a route with large fanout), and a single > 4in-LUT (four input look up table). > > The layout of the design also matters because longer routes take more > time. If the design is regular and needs to communicate only to a few > of the nearest neighbor logic cells then it might be made to run very > fast. If communication needs to be very general, it might be very hard > to make run fast. If the design is regular and rectangular it might be > made to run very fast. Very irregular logic is very difficult to place. > Some non rectangular logic is hard to place, and some is fairly easy. > > If your design is already structured into simple logic between pipeline > stages that can be easily floorplanned into a regular rectangular > structure, a design like this might be done in 2 to 6 person weeks by an > experienced FPGA designer. > > It also might take a few person years of effort to fit the design into > the next generation of FGPAs, defined for this statement as twice as > fast as the current generation. > > It's also very possible that your design can't be done with existing > FPGAs at all, even assuming a factor of two speedup for the next > generation, regardless of effort, regardless of experience. > > The questions you need to ask are: > 1) can the design be pipelined "enough"? (How much time will this > take?) > 2) what is the "shape" of the parts of design? How can they be > floorplanned to minimize route lengths and delays? > > Best of luck. > > -- > Phil Hays > "Irritatingly, science claims to set limits on what > we can do, even in principle." Carl Sagan > Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17757
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JUST LIKE YOU are now!! So, can you afford $6.00 and see if it really works?? I think so... People have said, "what if the plan is played out and no one sends you the money? So what! What are the chances of that Happening when there are tons of new honest users and new honest people who are joining the internet and newsgroups everyday and are willing to give it a try? Anyway, it is only $6.00 for a chance at thousands. Estimates are at 20,000 to 50,000 new users, every day, with thousands of those joining the actual internet. Remember, play FAIRLY and HONESTLY and this will really work. You wouldn't want someone to cheat you the same way you may be cheating!Article: 17758
I read the phase "Partial Evaluation" from many papers but I don't know the exact meaning of it. Who can tell me the meaning or where I can find the meaning. Thanks! Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17759
My penny's worth here. For a 12K gate design the answer is NO!. thiru1457@my-deja.com wrote in message <7q5r3b$bi4$1@nnrp1.deja.com>... >Hi, > > I intend to implement a logic in FPGA (roughly >12K logic gates complexity), running at 200 MHz. > > Is it possible to implement the above design, >with the current FPGA technology?. > > How difficult it would be (interms of manweeks) > for synthesis and "place and route" the above >design. > >Thanks in advance for your response. > >-Regards > >Thiru > > > > > > > > > >Sent via Deja.com http://www.deja.com/ >Share what you know. Learn what you don't.Article: 17760
vermon1055@my-deja.com wrote:
> Based on your opinions, what is the best synthesis tool in the
> market for the FPGA design?
> I am going to use the Altera tool for a project at 125Mhz. As
> you may have already known, Altera did a poor job on synthesizing the
> Verilog code. Because of that, we will use the Synopsys Design
> Compiler (targeting on the Altera liberary), synthesis the Verilog code
> and save the result as an EDIF file, then use Altera to do the
> placement and routing.
> Do you think the above methodology works? Or, we have to buy
> another synthesis tools?
I think that the best tool is Synplicity's Synplify. Second is
Exemplar's Leonardo Spectrum. Last is Synopsys's FPGA Express. There
are many other tools I have not tried. Other Important Notes and
Warnings: I was targeting Xilinx 4000 and Virtex, code written in
VHDL. Different designs and design styles will give different results.
Different tools will give different results for different target parts.
The differences between versions of tools can be greater than the
differences between different tools. Tools differ in other ways as
well: FPGA Express has the best error messages, Exemplar targets more
parts, Synplify runs faster.
I think that the above methodology will work. How well it will work
I do not know, as I have never used Synopsys Design Compiler, which I
have heard is mainly aimed at the ASIC market. Perhaps a Synopsys user
or rep will comment? Also, my Altera experience is mostly a few years
old. (I have played with Apex.)
As for buying another synthesis tool, I suggest that you get
evaluation copies of at least two other tools and check them out with
your designs: I suggest Synplify and Exemplar LS. Also, ask your local
Altera FAE about what tool they would use if Altera parts were being
benchmarked against the dreaded "Brand-X". I've seen a difference
between the best and the worst on the order of 20% for both speed and
area over a range of designs.
Floorplanning can gain speed, and can improve packing. Hand mapping key
bits of logic can gain a lot of speed (instantiate target family
primitives) at the cost of design portability. You will probably need
to both floorplanning and hand mapping to meet your design goal of 125
MHz. It will not be easy. Good luck.
--
Phil Hays
"Irritatingly, science claims to set limits on what
we can do, even in principle." Carl Sagan
Article: 17761Hello You can see an example by using the coregen tool to create a memory with a pre-loaded value. The variable STARTUP is used for simulation. Good luck. Michel Le Mer Gerpi sa Steve Kinkead <stevek@cts.com> a écrit dans le message : 7q12p0$1tt9$1@thoth.cts.com... > A related question: How do you initialize the Block RAM during simulation? > The contents > default to X's but I would like to initialize it to 0's. (I'm using > Modelsim). > > Paul Butler <c_paul_butler@yahoo.com> wrote in message > news:rs7ql0cs7r88@corp.supernews.com... > > > > chadlamb@my-deja.com wrote in message <7pvd76$pv5$1@nnrp1.deja.com>... > > >To all, > > > > > >We are using the block RAM in the Xilinx Virtex > > >devices. We intialize the RAM using the UCF. > > > > > >Has anyone tried to changed the contents of the > > >Xilinx Virtex Block RAM without going through > > >place and route? If we want to change it's > > >contents, we don't want to have to run through > > >a full place and route. Clearly we can use the > > >-g option (guide file) and read in the reviously > > >placed and routed design, but has anyone done > > >this another way? > > > > > > > > > > > > > > > Jbits might be what you're looking for: > > > > http://www.xilinx.com/xilinxonline/jbits.htm > > > > Paul Butler > > > > Paul.Butler@natinst.com > > National Instruments > > Austin, TX > > > > > > > >Article: 17762
sharad@bisquare.com wrote: > > Hi, > > I am using a Xilinx Spartan Configuration Prom xc17s40 which > theoretically is not cascadable, now I have also used the 17256D which > is cascadable as the first device, this has a CEO output to cascade this > I have connected to the 17S40 device's OE, I feel that it should work > but it doesn't. > <snip> Depends on how you have the rest of it connected. If you have the second device's CE and CLK to the same lines as the first device and just rely on the output enable, then the second device could be clocking data the whole time that the first one is but just not placing it on the shared data pin. Then when it finally gets to spit out data, it is at some unknown address and thus the data is wrong and thus your configuration error. I would try running the cascaded CEO to the second device'c CE line, and connecting the OE line to the Spartan LDC or HDC (depending on active high/low sense of OE). The second device won't activate the data out line until both CE and OE are active, and it also won't be clocking the internal address counter. -- Brian C. Boorman Harris RF Communications Rochester, NY 14610 XYZ.bboorman@harris.com <Remove the XYZ. for valid address>Article: 17763
On Wed, 25 Aug 1999 09:32:29 +0200, Joshua Schwartz <josh@iccd.co.il>
wrote:
>
>
>Richard Erlacher wrote:
>
>> On Sat, 21 Aug 1999 13:43:01 +0200, Daniel Figuerola Estrada
>> <pfa@tinet.fut.es> wrote:
>>
>> >I am making a project in wich I compare advantages and disadvantages in
>> >using microcontrollers and FPGA in the design of a digital system.
>> >
>> >Has anyone worked with those two technologies and could give his opinion
>> >of them?
>> >
>> >
>> >------------------------------------------------------------------------
>> > ////////////////////////////////\ ("`-''-/").___..--''"`-.__
>> > // Marcel Figuerola Estrada // `6_ 6 ) `-. ( ).`-.__.`)
>> > // pfa@tinet.fut.es // (_Y_.)' ._ ) `._ `.``-..-'
>> > // Valls - Catalunya - Europe // _..`--'_..-_/ /--'_.' ,'
>> > \//////////////////////////////// (il),-'' (li),' ((!.-'
>> >------------------------------------------------------------------------
>>
>> warranted each time the FPGA is enhanced, since the earlier version
>> will likely be discontinued).
>
>I don't agree most of the Xilinx line for instance is still available. I think that
>only the 2000 series has been discontinued. In the latest release of their software
>I still see support for the 3000 family which is quite old.
>
What you see, I believe, is support for their current 3000A or 3100
series, which addresses the same overall device type requirement but
does not support the "real" 3000-series parts.
I have a number of these old 3000-series parts, which were quite
costly back in the early '90's, and since I used my client's tools to
develop code for them, I was hoping to use them up in my lab, yet
can't because they're not compatible with the 3000A and -XL families
which are supported by the current software.
Now, if only there were a way to migrate the configuration files back
for the benefit of those old parts, which, BTW, are still available in
distribution.
>
>>
>>
>> I still use microcontrollers I used 20 years ago, with as much
>> success, and, if need be, I can put the processor core in an FPGA and
>> use it there.
>>
>> Dick
>
Article: 17764Nallatech's Ballyblue DIME module, has 2Mx64 of SDRAM on board, as well as a 16Mbit FIFO. We also have a module that will be shortly available with 16Mx64 (128 MB), if that is of interest. The ballynuey motherboard carrier can support 4 DIME modules so you can expand memory by using several modules. See www.nallatech.com/dime regards Allan. -----Original Message----- From: Sukandar Kartadinata [mailto:sk@zkm.de] Posted At: 25 August 1999 12:47 Posted To: fpga Conversation: Virtex dev boards Subject: Virtex dev boards I'm looking for a Virtex development board that has (supports) at least 16MBytes (or rather 4Mwords with 32bits word width, or 2Mx64bits) of fast SDRAM. Even better would be a board with two memory interfaces. Thanks for any suggestions Sukandar Kartadinata sk@zkm.deArticle: 17765
I have several designs where we only have 17mm x 17 mm or so for a FPGA or PLD. I am looking for various Chip Scale and fine pitch BGA FPGA/PLD devices. So far Xilinx seems to be the only vendor who has parts available now and that are on a cost parity with normally packaged parts. (e.g. XC95144XL in a chip scale package for less than $10 or XCV50 Virtex in 256 fine-pitch BGA for $45) Am I missing any others ??? Thanks, Stuart sja@world.std.comArticle: 17766
When doing a hierarchical HDL design in F1.5 (I'm using FPGA Express), how do you decide when to dissolve hierarchy or not? I know that preserving hierarchy preserves the bus structures in the PPR timing simulation netlist so it makes it easier to check against the behavioral and post synthesis simulations. On the other hand, if you have registered I/O but the registers are embedded inside hierarchical blocks, then FPGA Express cannot infer IFFs or OFFs unless you dissolve those blocks. Besides these obvious reasons, if you are doing a highly pipelined datapath and you know the logic cannot be minimized any further between registers, are there any good reasons to dissolve hierarchy? For example, does it improve the routing delays (after floorplanning)? Maybe someone with lots of designs under their belt can give some input here. Ray? Thanks ***************************************************************** Sanjeev Gunawardena School of Electrical Engineering and Computer Science Ohio University Athens, OH 45701 email: sanjeev@NObobcat.ent.SPAMohiou.eduArticle: 17767
Hi all ! Try so. library IEEE; use IEEE.std_logic_1164.all; entity MYMEM is port (CLK, WE:in std_logic; ADDR: in std_logic_vector(8 downto 0); DIN: in std_logic_vector(7 downto 0); DOUT: out std_logic_vector(7 downto 0)); end MYMEM; architecture BEHAVE of MYMEM is signal logic0, logic1: std_logic; component RAMB4_S8 --synopsys translate_off generic( INIT_00,INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F : BIT_VECTOR(255 downto 0) := X“0000000000000000000000000000000000000000000000000000000000000000”); --synopsys translate_on port (WE, EN, RST, CLK: in STD_LOGIC; ADDR: in STD_LOGIC_VECTOR(8 downto 0); DI: in STD_LOGIC_VECTOR(7 downto 0); DO: out STD_LOGIC_VECTOR(7 downto 0)); end component; --synopsys dc_script_begin --set_attribute ram0 INIT_00 “0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF” -type string --set_attribute ram0 INIT_01 “FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210” -type string --synopsys dc_script_end begin logic0 <=’0’; logic1 <=’1’; ram0: RAMB4_S8 --synopsys translate_off generic map ( INIT_00 => X”0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF”, INIT_01 => X”FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210”) --synopsys translate_on port map (WE=>WE, EN=>logic1, RST=>logic0, CLK=>CLK,ADDR=>ADDR, DI=>DIN, DO=>DOUT); end BEHAVE;‰ Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17768
In article <7pvd76$pv5$1@nnrp1.deja.com>, chadlamb@my-deja.com wrote: > To all, > > We are using the block RAM in the Xilinx Virtex > devices. We intialize the RAM using the UCF. > > Has anyone tried to changed the contents of the > Xilinx Virtex Block RAM without going through > place and route? If we want to change it's > contents, we don't want to have to run through > a full place and route. Clearly we can use the > -g option (guide file) and read in the reviously > placed and routed design, but has anyone done > this another way? > > Sent via Deja.com http://www.deja.com/ > Share what you know. Learn what you don't. Hi ! Try so. library IEEE; use IEEE.std_logic_1164.all; entity MYMEM is port (CLK, WE:in std_logic; ADDR: in std_logic_vector(8 downto 0); DIN: in std_logic_vector(7 downto 0); DOUT: out std_logic_vector(7 downto 0)); end MYMEM; architecture BEHAVE of MYMEM is signal logic0, logic1: std_logic; component RAMB4_S8 --synopsys translate_off generic( INIT_00,INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F : BIT_VECTOR(255 downto 0) := X“0000000000000000000000000000000000000000000000000000000000000000”); --synopsys translate_on port (WE, EN, RST, CLK: in STD_LOGIC; ADDR: in STD_LOGIC_VECTOR(8 downto 0); DI: in STD_LOGIC_VECTOR(7 downto 0); DO: out STD_LOGIC_VECTOR(7 downto 0)); end component; --synopsys dc_script_begin --set_attribute ram0 INIT_00 “0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF” -type string --set_attribute ram0 INIT_01 “FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210” -type string --synopsys dc_script_end begin logic0 <=’0’; logic1 <=’1’; ram0: RAMB4_S8 --synopsys translate_off generic map ( INIT_00 => X”0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF”, INIT_01 => X”FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210FEDCBA9876543210”) --synopsys translate_on port map (WE=>WE, EN=>logic1, RST=>logic0, CLK=>CLK,ADDR=>ADDR, DI=>DIN, DO=>DOUT); end BEHAVE; > ‰ Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17769
Dear Colleague, You can provide an important impetus to the enhancement of VHDL by spending a few minutes of your valuable time completing a survey. The data collected by this survey will guide the VHDL 200x team in proposing the next round of extensions and modifications to VHDL. To participate, please visit http://www.vhdl200x.org/survey/surveyPart1.html. As you know, the IEEE requires that the VHDL standard be recertified at least every five years. There is currently underway a recertification and language refinement as a "maintenance release," which will conclude late this year or early next. The VHDL standards community is already working on the subsequent revision, a significant enhancement, entitled VHDL 200x. The VHDL 200x revision will dramatically reduce the impact of electronic system obsolescence and pave the way for future generations of CAD/EDA systems that support rapid and cost-effective development. The VHDL 200x team is sponsored and supported by the Air Force Research Laboratory. The work is being done in cooperation with the IEEE DASC VHDL Analysis and Standards Group (VASG). Team members include University of Virginia, Virginia Commonwealth University, Menchini & Associates, EDA Standards Consulting, and the Advanced Technology Institute. Please help the design community by completing the survey. We are requesting that the survey be completed by SEPTEMBER 10th. Initial results will be presented at the 1999 Fall VIUF Workshop. (The Workshop's preliminary program is at http://www.vhdl.org/viuf/conf/viuf99/index.html.) Again, the survey web address is: http://www.vhdl200x.org/survey/surveyPart1.html. Thanks in advance for participating. Sincerely, The VHDL-200x team -- Paul Menchini | mench@mench.com |"The last thing I want to do is Cadence Design Systems | www.orcad.com | spread fear, uncertainty and P.O. Box 71767 | 919-479-1670[v] | doubt in the users' minds." Durham, NC 27722-1767 | 919-479-1671[f] | --Don Jones, MS's Y2K Product MgrArticle: 17770
Designing to the architecture will have more bearing on whether or not you meet speed requirements than choice of tools. Your code needs to be written at the "pipeline" RTL level or lower so that the synthesizer has less guessing to do. By pipeline RTL level, I mean that the HDL code should describe the logic between each register in your pipelined design...For instance, A multiplier has to be described so that the synthesizer knows how to build it, which means you need to tell it how the partial products and adder architecture are constructed. The synthesizers really don't know too much more than simple carry chain structures and memory. Anything more complex needs to be laid out in detail. Phil, I'd like to know how you proposed to floorplan Altera? There is no way (other than the subtle hints provided by cliques and assigning pins) to embed floorplan info in an altera design that I know of. You can use the graphical floorplanner in the Maxplus tools, but if you iterate the design you have to start over. Fortunately, the routing structure in Altera does let you get away without floorplanning, even with high speed designs. Altera is capable of 125Mhz designs, but you do have to be careful to design to the FPGA architecture. Phil Hays wrote: > vermon1055@my-deja.com wrote: > > > Based on your opinions, what is the best synthesis tool in the > > market for the FPGA design? > > I am going to use the Altera tool for a project at 125Mhz. As > > you may have already known, Altera did a poor job on synthesizing the > > Verilog code. Because of that, we will use the Synopsys Design > > Compiler (targeting on the Altera liberary), synthesis the Verilog code > > and save the result as an EDIF file, then use Altera to do the > > placement and routing. > > Do you think the above methodology works? Or, we have to buy > > another synthesis tools? > > I think that the best tool is Synplicity's Synplify. Second is > Exemplar's Leonardo Spectrum. Last is Synopsys's FPGA Express. There > are many other tools I have not tried. Other Important Notes and > Warnings: I was targeting Xilinx 4000 and Virtex, code written in > VHDL. Different designs and design styles will give different results. > Different tools will give different results for different target parts. > The differences between versions of tools can be greater than the > differences between different tools. Tools differ in other ways as > well: FPGA Express has the best error messages, Exemplar targets more > parts, Synplify runs faster. > > I think that the above methodology will work. How well it will work > I do not know, as I have never used Synopsys Design Compiler, which I > have heard is mainly aimed at the ASIC market. Perhaps a Synopsys user > or rep will comment? Also, my Altera experience is mostly a few years > old. (I have played with Apex.) > > As for buying another synthesis tool, I suggest that you get > evaluation copies of at least two other tools and check them out with > your designs: I suggest Synplify and Exemplar LS. Also, ask your local > Altera FAE about what tool they would use if Altera parts were being > benchmarked against the dreaded "Brand-X". I've seen a difference > between the best and the worst on the order of 20% for both speed and > area over a range of designs. > > Floorplanning can gain speed, and can improve packing. Hand mapping key > bits of logic can gain a lot of speed (instantiate target family > primitives) at the cost of design portability. You will probably need > to both floorplanning and hand mapping to meet your design goal of 125 > MHz. It will not be easy. Good luck. > > -- > Phil Hays > "Irritatingly, science claims to set limits on what > we can do, even in principle." Carl Sagan -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17771
If you are doing floorplanning, you want to make sure you don't dissolve the hierarchy or you are going to have problems. If for instance, you embed RLOC= attributes in your code, the hierarchy has to stay intact for the RLOCs to stay relative. The older tools seemed to do better with heirarchy than without when doing place and route. I'm not sure on the M1, M2 tools, as I haven't done any designs with the hierarchy collapsed. Sanjeev Gunawardena wrote: > When doing a hierarchical HDL design in F1.5 (I'm using FPGA Express), how > do you decide when to dissolve hierarchy or not? > > I know that preserving hierarchy preserves the bus structures in the PPR > timing simulation netlist so it makes it easier to check against the > behavioral and post synthesis simulations. On the other hand, if you have > registered I/O but the registers are embedded inside hierarchical blocks, > then FPGA Express cannot infer IFFs or OFFs unless you dissolve those > blocks. > > Besides these obvious reasons, if you are doing a highly pipelined datapath > and you know the logic cannot be minimized any further between registers, > are there any good reasons to dissolve hierarchy? For example, does it > improve the routing delays (after floorplanning)? > > Maybe someone with lots of designs under their belt can give some input > here. Ray? > > Thanks > > ***************************************************************** > Sanjeev Gunawardena > School of Electrical Engineering and Computer Science > Ohio University > Athens, OH 45701 > email: sanjeev@NObobcat.ent.SPAMohiou.edu -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 17772
Anyone have any experience (good or bad) with FPGAs from QuickLogic?Article: 17773
In a previous article Wayne Miller <wayne@aerial-imaging.com> writes: : ;Anyone have any experience (good or bad) with FPGAs from QuickLogic? I have used QuickLogic FPGAs, and I found it to be more routable than FPGAs from other vendors. It is fast and it has the least amount of architectural gotchas when I was looking for FPGAs about a year ago. We shipped a whole lot of products containing QuickLogic FPGAs in the year, and we will use it to fill our antifuse need in future projects.Article: 17774
Why don't you try a bigger board ? or, Alternatively have a look at ALTERA parts. In article <FHE539.Bs9@world.std.com>, Stuart J Adams <sja@world.std.com> writes >I have several designs where we only have 17mm x 17 mm or so >for a FPGA or PLD. I am looking for various Chip Scale and >fine pitch BGA FPGA/PLD devices. So far Xilinx seems to be the >only vendor who has parts available now and that are on a cost >parity with normally packaged parts. (e.g. XC95144XL in a chip scale >package for less than $10 or XCV50 Virtex in 256 fine-pitch BGA >for $45) > >Am I missing any others ??? > >Thanks, > Stuart > sja@world.std.com -- Pat
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