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Richard Erlacher wrote:
> On Sat, 21 Aug 1999 13:43:01 +0200, Daniel Figuerola Estrada
> <pfa@tinet.fut.es> wrote:
>
> >I am making a project in wich I compare advantages and disadvantages in
> >using microcontrollers and FPGA in the design of a digital system.
> >
> >Has anyone worked with those two technologies and could give his opinion
> >of them?
> >
> >
> >------------------------------------------------------------------------
> > ////////////////////////////////\ ("`-''-/").___..--''"`-.__
> > // Marcel Figuerola Estrada // `6_ 6 ) `-. ( ).`-.__.`)
> > // pfa@tinet.fut.es // (_Y_.)' ._ ) `._ `.``-..-'
> > // Valls - Catalunya - Europe // _..`--'_..-_/ /--'_.' ,'
> > \//////////////////////////////// (il),-'' (li),' ((!.-'
> >------------------------------------------------------------------------
>
> warranted each time the FPGA is enhanced, since the earlier version
> will likely be discontinued).
I don't agree most of the Xilinx line for instance is still available. I think that
only the 2000 series has been discontinued. In the latest release of their software
I still see support for the 3000 family which is quite old.
>
>
> I still use microcontrollers I used 20 years ago, with as much
> success, and, if need be, I can put the processor core in an FPGA and
> use it there.
>
> Dick
Article: 17701I'm looking for a Virtex development board that has (supports) at least 16MBytes (or rather 4Mwords with 32bits word width, or 2Mx64bits) of fast SDRAM. Even better would be a board with two memory interfaces. Thanks for any suggestions Sukandar Kartadinata sk@zkm.deArticle: 17702
chadlamb@my-deja.com wrote in message <7pvd76$pv5$1@nnrp1.deja.com>... >To all, > >We are using the block RAM in the Xilinx Virtex >devices. We intialize the RAM using the UCF. > >Has anyone tried to changed the contents of the >Xilinx Virtex Block RAM without going through >place and route? If we want to change it's >contents, we don't want to have to run through >a full place and route. Clearly we can use the >-g option (guide file) and read in the reviously >placed and routed design, but has anyone done >this another way? > > > Jbits might be what you're looking for: http://www.xilinx.com/xilinxonline/jbits.htm Paul Butler Paul.Butler@natinst.com National Instruments Austin, TXArticle: 17703
Take a look at www.vcc.com The virtual workbench has 16meg on it in1Mb x 16 bits SDRAM (maybe ok for you?) Also has 2 meg flash memory And a funky alphanumeric display!!! Sukandar Kartadinata wrote in message <37C3D7A6.66CCFF9A@zkm.de>... >I'm looking for a Virtex development board that has (supports) at least >16MBytes (or rather 4Mwords with 32bits word width, or 2Mx64bits) of >fast SDRAM. >Even better would be a board with two memory interfaces. > >Thanks for any suggestions >Sukandar Kartadinata >sk@zkm.de > > >Article: 17704
Tim,
I was beaten to the draw !
That's what comes of living in a significantly different time zone.
Anyway, here's my attempt, for what it's worth...
module mem9_1 ( iCLK,
iRST,
iWR,
iRD,
iDIN,
oDOUT,
oDONE,
oEMPTY );
input iCLK;
input iRST;
input iWR;
input iRD;
input [71:0] iDIN;
output [7:0] oDOUT;
output oDONE;
output oEMPTY;
reg [7:0] oDOUT;
reg oDONE;
reg oEMPTY;
reg [71:0] mem;
reg [3:0] pointer;
// =======================================================================
// oDOUT
// =====
// The output of the memory has valid data when there is an active read
// strobe asserted, otherwise it is high impedance.
always @ (pointer or iRD or mem)
if (~iRD)
oDOUT <= 8'hzz;
else
case (pointer)
4'h0: oDOUT <= mem[7:0];
4'h1: oDOUT <= mem[15:8];
4'h2: oDOUT <= mem[23:16];
4'h3: oDOUT <= mem[31:24];
4'h4: oDOUT <= mem[39:32];
4'h5: oDOUT <= mem[47:40];
4'h6: oDOUT <= mem[55:48];
4'h7: oDOUT <= mem[63:56];
4'h8: oDOUT <= mem[71:64];
default: oDOUT <= 8'h00;
endcase // case(pointer)
// =======================================================================
// =======================================================================
// oDONE
// =====
// This output asserts in the clock cycle immediately following a read access
always @(posedge iCLK)
if (iRST)
oDONE <= 1'b0;
else if (iRD)
oDONE <= 1'b1;
else
oDONE <= 1'b0;
// =======================================================================
// =======================================================================
// oEMPTY
// ======
// This indicates that the last of the current memory contents has just been
// read, so it gets set on a read when the pointer points to the last entry,
// and cleared again on a write. If a write happens simultaneously with the
// final read (this is cool in a synchronous module) then the oEMPTY flag
// remains clear.
always @(posedge iCLK)
if (iRST)
oEMPTY <= 1'b1;
else if (iWR)
oEMPTY <= 1'b0;
else if (iRD == 1'b1 && pointer[3:0] == 4'b1000)
oEMPTY <= 1'b1;
// =======================================================================
// =======================================================================
// pointer
// =======
// This points to the memory byte that will appear on the output the next
// time iRD is asserted, after which it will be incremented. It wraps back
// from 8 to 0.
always @(posedge iCLK)
if (iRST)
pointer[3:0] <= 4'b0000;
else if (iRD)
begin
if (pointer[3:0] == 4'b1000)
pointer[3:0] <= 4'b0000;
else
pointer[3:0] <= pointer[3:0] + 1;
end // if (iRD)
// =======================================================================
// =======================================================================
// mem
// ===
// The actual memory.
always @(posedge iCLK)
if (iRST)
mem[71:0] <= 72'b0;
else if (iWR)
mem[71:0] <= iDIN[71:0];
// =======================================================================
// That's all, Folks!!!
endmodule // mem9_1
...plus a wee test bench...
module test_mem;
reg [71:0] iDIN;
reg iCLK,
iRST,
iRD,
iWR;
wire [7:0] oDOUT;
wire oDONE,
oEMPTY;
mem9_1 mem9_1 ( iCLK,
iRST,
iWR,
iRD,
iDIN,
oDOUT,
oDONE,
oEMPTY );
initial
begin
$signalscan;
$recordvars;
end
initial
begin
iCLK <= 1'b1;
iRST <= 1'b1;
iWR <= 1'b0;
iRD <= 1'b0;
end
always
#5 iCLK <= ~iCLK;
initial
begin
#15 iRST = 1'b0;
#10 iWR = 1'b1;
#0 iDIN = 72'h0123456789ABCDEF01; // some random rubbish!
#10 iWR = 1'b0;
#0 iRD = 1'b1;
#80 iWR = 1'b1;
#0 iDIN = 72'hfedcba9876543210fe;
#10 iWR = 1'b0;
#90 iRD = 1'b0;
#20 $stop;
end // initial begin
endmodule // test_mem
Note that my effort uses active high synchronous reset, whilst Mark's uses
active low asynchronous reset. That's just a matter of preference.
Regards, Robert.
Mark Lancaster wrote:
>
> Tim,
>
> This may not be perfect, but it should get you pretty close.
>
> module mem9_1 ( iCLK,
> iRST,
> iWR,
> iRD,
> iDIN,
> oDOUT,
> oDONE,
> oEMPTY );
>
> input iCLK;
> input iRST;
> input iWR;
> input iRD;
> input [71:0] iDIN;
>
> output [7:0] oDOUT;
> output oDONE;
> output oEMPTY;
>
> reg [7:0] oDOUT;
> reg [71:0] mem;
> reg [3:0] pointer;
> reg oDONE;
>
> always @ (posedge iCLK or negedge iRST)
> if (~iRST)
> mem <= 72'h000000000000000000;
> else if (iWR)
> mem <= iDIN;
>
> always @ (posedge iCLK or negedge iRST)
> if (~iRST) begin
> pointer <= 4'h0;
> oDONE <= 1'b1;
> end
> else if ((iWR) || (pointer == 4'h8)) begin
> pointer <= 4'h0;
> oDONE <= iWR ? 1'b0 : 1'b1;
> end
> else if (iRD) begin
> pointer <= pointer + 1'b1;
> oDONE <= 1'b0;
> end
>
> assign oEMPTY = oDONE;
>
> always @ (pointer or iRD or mem)
> if (~iRD)
> oDOUT <= 8'hzz;
> else
> case (pointer)
> 4'h0: oDOUT <= mem[7:0];
> 4'h1: oDOUT <= mem[15:8];
> 4'h2: oDOUT <= mem[23:16];
> 4'h3: oDOUT <= mem[31:24];
> 4'h4: oDOUT <= mem[39:32];
> 4'h5: oDOUT <= mem[47:40];
> 4'h6: oDOUT <= mem[55:48];
> 4'h7: oDOUT <= mem[63:56];
> 4'h8: oDOUT <= mem[71:64];
> default: oDOUT <= 8'h00;
> endcase
>
> --
> Mark Lancaster email: mark.lancaster@motorola.com
> Motorola WSSG M/S: CH275 phone: (480)814-4920
> 1300 N. Alma School Rd. fax: (480)814-3107
> Chandler, AZ 85224
--
=========================================================================
Robert R Fairlie - IC Design, Motorola, Scotland, Tel. - +44 1355 356039
=========================================================================
Article: 17705A related question: How do you initialize the Block RAM during simulation? The contents default to X's but I would like to initialize it to 0's. (I'm using Modelsim). Paul Butler <c_paul_butler@yahoo.com> wrote in message news:rs7ql0cs7r88@corp.supernews.com... > > chadlamb@my-deja.com wrote in message <7pvd76$pv5$1@nnrp1.deja.com>... > >To all, > > > >We are using the block RAM in the Xilinx Virtex > >devices. We intialize the RAM using the UCF. > > > >Has anyone tried to changed the contents of the > >Xilinx Virtex Block RAM without going through > >place and route? If we want to change it's > >contents, we don't want to have to run through > >a full place and route. Clearly we can use the > >-g option (guide file) and read in the reviously > >placed and routed design, but has anyone done > >this another way? > > > > > > > > > Jbits might be what you're looking for: > > http://www.xilinx.com/xilinxonline/jbits.htm > > Paul Butler > > Paul.Butler@natinst.com > National Instruments > Austin, TX > > >Article: 17706
Thanks to both of you. I slightly adapted the ideas presented but I think I finally have something that works. Can one of you guys tell me why between reads you tristate the bus? Is this something commonly done? Just a question. The code I wrote does not do this but I have seen this done on more then one occasion. Are both of you in ASIC design with Motorola? Or do you just know your verilog. You might have guessed that I have not been using Verilog for very long but I think I am starting to get a little clue. Thanks again, TimArticle: 17707
When you need to switch the direction of a tri-state bus, you have to take some measures against the possibility that both sides will drive the bus for a short while. If you turn-off one side and turn-on the other at the same clock edge, there is a chance that because of placement and other factors which effect the delays to the drivers, both drivers will be on, ie if the to-be-inactive side is slow and to-be-active side is fast. So it is always a good idea to put a clock cycle of tri-state bus to get around this issue. "Tim Warnes" <timwarn@nortelnetworks.com> wrote: >Thanks to both of you. I slightly adapted the ideas presented but I think I >finally have something that works. Can one of you guys tell me why between >reads you tristate the bus? Is this something commonly done? Just a >question. The code I wrote does not do this but I have seen this done on >more then one occasion. > >Are both of you in ASIC design with Motorola? Or do you just know your >verilog. You might have guessed that I have not been using Verilog for very >long but I think I am starting to get a little clue. > >Thanks again, >Tim > > muzo Verilog, ASIC/FPGA and NT Driver Development Consulting (remove nospam from email)Article: 17708
ModelSim solution. The block RAMs do not have a defualt value built into their model. During route time, it copies the values from the UCF and puts it into the design. The problem is that it is a waste to route everytime you change a little thing. Therefore, I put a precompiler command into the Verilog code so that during simulation I used a modified Xilinx model. The modefied model was nothing more than the Xilinx model with the init instruction inserted so that the RAMs would be whatever I needed them. The only problem was that I had to make sure a change in the RAM got reflected in both the UCF and my model. I know there is a slicker way to solve the problem, but I didn't have the time to try several solutions. Brad Ree Director of Engineering Programmable Products www.programmable-products.com brad.ree@programmable-products.com 770-736-8932Article: 17709
Tim Warnes wrote: > > Thanks to both of you. I slightly adapted the ideas presented but I think I > finally have something that works. Good! > Can one of you guys tell me why between > reads you tristate the bus? Is this something commonly done? Just a > question. The code I wrote does not do this but I have seen this done on > more then one occasion. > If there are no other drivers for whatever bus oDOUT is connected to, then there is no need to tri-state oDOUT. I guess Robert and I just assumed (bad mistake) that if you have a "read" signal then you only want to drive the bus when it's asserted. > Are both of you in ASIC design with Motorola? Or do you just know your > verilog. You might have guessed that I have not been using Verilog for very > long but I think I am starting to get a little clue. > I'm not sure of Robert's job function, but I do ASIC design. We have worked together to develop Moto's Verilog coding standards. MarkArticle: 17710
"Steve Kinkead" <stevek@cts.com> wrote: > A related question: How do you initialize the Block RAM during simulation? > The contents > default to X's but I would like to initialize it to 0's. (I'm using > Modelsim). > If you use the Xilinx v21_i tools this problem is fixed. See if record #6459 helps. If you want to initialize the RAM to something other than zeros, then you have two options: 1. use generics (painful) or 2. create a RAM model that will read a file. chad lamb Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17711
well, almost. but I need that 32bit access Daryl Bradley wrote: > Take a look at www.vcc.com > > The virtual workbench has 16meg on it in1Mb x 16 bits SDRAM (maybe ok for > you?) > > >I'm looking for a Virtex development board that has (supports) at least > >16MBytes (or rather 4Mwords with 32bits word width, or 2Mx64bits) of > >fast SDRAM. > >Even better would be a board with two memory interfaces.Article: 17712
have a look at www.xess.com THey have a virtex board coming soon with memory on it Haven't looked at the specs but maybe suitable? Sukandar Kartadinata wrote in message <37C4E4CA.DFC1D45C@zkm.de>... >well, almost. >but I need that 32bit access > >Daryl Bradley wrote: > >> Take a look at www.vcc.com >> >> The virtual workbench has 16meg on it in1Mb x 16 bits SDRAM (maybe ok for >> you?) >> >> >I'm looking for a Virtex development board that has (supports) at least >> >16MBytes (or rather 4Mwords with 32bits word width, or 2Mx64bits) of >> >fast SDRAM. >> >Even better would be a board with two memory interfaces. > > >Article: 17713
Utku Ozcan wrote in message <37B7B962.31A766E2@netas.com.tr>... > >Design Entry: Verilog >Synthesis: Synplify >P&R: Xilinx Design Manager >Technology: Xilinx > >I have 8-bit data input, say "data<*>", which is clocked by >"clock". I use following UCF command: > >NET "data<*>" OFFSET=IN 50 BEFORE clock ; > >But Placement&Routing report leaves time values empty for >this command. I have used following option: > >Pack I/O Register/Latches into IOBs for: Input/Output P&R doesn't give a timing report for FFs in IOB. It'll tell you if the timing fails, though. This has been fixed in Fondation and Alliance 2.1i. >And Synplify directly connects this data bus to a register >set triggered by "clock". The name of these registers end >with "_inff", i.e. Synplify assumes that these can be mapped >to IOB's, which overlaps with the router option above. I don't think the mapper cares about those things. I'll do whatever pleases it. >1. Since the IOB's are fixed to the pads, does it make any >sense to give timing constraints? I think, to have 50 ns >offset or 30 ns offset do not change the timing, since the >path from pad to IOB's are always the same, and thus always >have the same delay, tough. The timing from pad to INFF is always the same but the internal clock skew might change depending on your design. This is more important for OUTFF than for INFF, though. >2. When a logic is mapped to an IOB, is it unnecessary to >use OFFSET constraints? Always use OFFSET constraints. FROM TO constraints do not cover clock skews. -NickArticle: 17714
Hi, I want to buy Xilinx Foundation, version 1.5 with FPGA Express. Can you provide me with pricing, if someone is interested in? Regards - Adam A.Biniszkiewicz@pz.zgora.plArticle: 17715
Sukandar, One solution to consider is the Texas Instruments' TMS320C6x Evaluation Module with a third party plug-in board for video. Though it's not a one company solution, TI has an excellent software development environment and lots of options for add-on hardware. Signalware (www.signalware.com) makes several plug-in boards for this module with 8 to 12 bit converters (I assume 24 bits mean 8 bits per color channel), SAW type filters, and a breadboarding area. These boards have Xilinx FPGAs (including Virtex versions) for pre- or post-processing for video or cellular processing. We are designing a frame grabber using the Signalware board, to be followed by basic video processing cores hosted in Xilinx FPGAs. Jonathan ----- Jonathan F. Feifarek President, Beyond the Horizon Ent. PO Box 1342 Castle Rock, CO 80104 (303) 688-5737 feifarek@ieee.org http://clients.estreet.com/feifarek/Article: 17716
Look at xapp130. You can to create a .ncf file with just the memory initializations (both block and LUT ram). You could also download the data using the SelectMap port. -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 17717
Hi, I intend to implement a logic in FPGA (roughly 12K logic gates complexity), running at 200 MHz. Is it possible to implement the above design, with the current FPGA technology?. How difficult it would be (interms of manweeks) for synthesis and "place and route" the above design. Thanks in advance for your response. -Regards Thiru Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17718
In the Virtex family 4 clock buffers are available. They may be used for clock distribution with null skew .The Flip-flops hold time being 0 one can safely assumes that hold time violation are fixed by design for the clock domains fed with the clock buffers. However if there are more than 4 clock domains,it is necessary to make sure that no such hold time violations are possible. So far I have only found a command which reports the maximum skew for a clock domain.I could not find a command which checks for hold time. Is there any command available in the Xilinx flow for that ?. In the event that it exists both in GUI environment and in batch mode I am only interested in the batch mode one, since it is definitely something to run routinely. I found there is a constraint called MAXSKEW to control the net skew. Some clock nets have also logic connection which are not the clock input of a flip-flop.For these logic terminals the skew does not matter. I would like to exclude them from the constraint : Any idea ? Thanks, PierreArticle: 17719
The Virtex boards from Alpha Data have separate memory interfaces with SRAM and SSRAM. Size might be a problem. RC1000 has 4 x 512k x 32 SRAM. ADM-XRC has 4 x 128k(256,512) x 36. Try www.alphadata.co.uk. In article <37C3D7A6.66CCFF9A@zkm.de>, sk@zkm.de wrote: > I'm looking for a Virtex development board that has (supports) at least > 16MBytes (or rather 4Mwords with 32bits word width, or 2Mx64bits) of > fast SDRAM. > Even better would be a board with two memory interfaces. > > Thanks for any suggestions > Sukandar Kartadinata > sk@zkm.de > > -- ----------------------------- Alpha Data ----------------------------- Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17720
i got xilinx student edition v1.5, installed it on my windows NT machine, and it immediately started bombing at the "map" stage of implementation, with access violation at address 0x78001799. this happens even after i installed the service pack for 1.5. also, i do NOT have microsoft visual studio installed. it could be some other application installed a bad microsoft DLL. but i read in the xilinx tech notes that xilinx decided they did NOT think it was due to this DLL. anyhow, it is all very confusing and unsatisfying because i cannot even compile a simple AND gate to my nice, brand new 4010 XS40 XESS board. does anyone know the real fix to this, besides buying for $500 the university edition of 2.1? (assuming that fixed it). thanks! -tobi delbruck Bob Pearson wrote: > Hi, > > Has any one encountered a situation where M1.5i > map get hung apparently in an infinite loop? And > if so what was the cause? > > Thanks for any help > > Bob Pearson > bpearson@pmr.com -- Tobi Delbruck Institute of Neuroinformatics, UniZ/ETHZ Winterthurerstr. 190 8057 Zurich, Switzerland phone +41 1/635 30 38 fax +41 1/635 30 53 tobi@ini.phys.ethz.ch <http://www.ini.unizh.ch/~tobi>Article: 17721
In article <7q5r3b$bi4$1@nnrp1.deja.com>, thiru1457@my-deja.com wrote: > Hi, > > I intend to implement a logic in FPGA (roughly > 12K logic gates complexity), running at 200 MHz. > > Is it possible to implement the above design, > with the current FPGA technology?. > > How difficult it would be (interms of manweeks) > for synthesis and "place and route" the above > design. Maybe the -1 speed grade flex6k or flex10k or apex FPGAs will satisfy your needs, but at such speed it should be highly pipelined, because you can't place additional logic between flipflops to fit in 5 ns delay. 'how difficult' depends on... If your design is just 2K bit shift register, it will take some minutes ;-) Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17722
Daryl Bradley <dwb105@nospam.ohm.york.ac.uk> wrote: > have a look at www.xess.com > THey have a virtex board coming soon with memory on it > Haven't looked at the specs but maybe suitable? Hmm. Elastic Computing have always had pricing schemes that appeal to my baser intstincts - but I've always written them off until now due to my feeling the need for better I/O bandwidth than is provided by a parallel port. I observe that while thier "XSV Virtex Prototyping Board" still appears to lack anything resembling a PCI interface, it /does/ sport USB ports as well as serial and parallel ports, ethernet, PS/2, and some "expansion ports"... While "processing video and audio signals" is not my scene, this offereing /does/ look potentially interesting... -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com If it's stuck, force it. If it breaks, it needed replacing anyway.Article: 17723
Gidday there, I'm currently climbing up the learning curve with FPGA Express, and porting my VHDL (isn't that a silly statement) from Cypress Warp. I keep getting the following error on my code. Error L-1/C0:#0 Not enough storage is available to complete this operation. According to the Xilinx Answer #5301, this is due to underscores within binary strings. However, though I am using binary strings, I do not have any underscores. You can find the answer at: http://www.xilinx.com/techdocs/5301.htm Actually, it can't be anything with the strings, I just can't get past this step. Is there a patch somewhere? The software was installed by a Xilinx FAE, with about 30 CDs (exageration). So, maybe he missed one. Any hints would be greatly appreciated. Joshua Lamorie Systems Designer Xiphos Technologies Inc. ps. Some specs PC: P-II 350 w/128MB RAM 270MB Virtual OS: NT4 SP5 Foundation: F1.5 Build 3.1.140 FPGA Express: 3.1.1.0wArticle: 17724
If you want to change the RAM contents with minimal CAD effort you could try to change (i.e. patch) the bit-file for configuration. There is an application note from Xilinx, describing their data format. (Sorry, I don't know the number.) It looks complicated at first, but once you have understood the format, you (or your computer) have easy access to every single bit in the RAMs. I admit, that I have not tried to fumble with these bits. Has anybody out there done so? Has anybody out there done so with success? Regards, Marco --- Marco Winzker Liesegang electronics Gmbh, Hannover, Germany Only speaking for myself
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