Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Steve McDowell wrote: > I'm looking at utilizing the virtex 600 and larger devices. Does anyone have > any strong likes / dislikes for the various systhesis tools as applied to > the large Xilinx gate arrays? I use Synplicity's Synplify and am fairly happy with it. Other tools I would suggest evaluating are Exemplar's Spectrum and Synopsys's FPGA Express. http://www.synplicity.com/ http://www.exemplar.com/ http://www.synopsys.com/products/fpga/fpga_express.html -- Phil Hays "Irritatingly, science claims to set limits on what we can do, even in principle." Carl SaganArticle: 17626
Design Entry: Verilog Synthesis: Synplify P&R: Xilinx Design Manager Technology: Xilinx I have 8-bit data input, say "data<*>", which is clocked by "clock". I use following UCF command: NET "data<*>" OFFSET=IN 50 BEFORE clock ; But Placement&Routing report leaves time values empty for this command. I have used following option: Pack I/O Register/Latches into IOBs for: Input/Output And Synplify directly connects this data bus to a register set triggered by "clock". The name of these registers end with "_inff", i.e. Synplify assumes that these can be mapped to IOB's, which overlaps with the router option above. 1. Since the IOB's are fixed to the pads, does it make any sense to give timing constraints? I think, to have 50 ns offset or 30 ns offset do not change the timing, since the path from pad to IOB's are always the same, and thus always have the same delay, tough. 2. When a logic is mapped to an IOB, is it unnecessary to use OFFSET constraints? -- I feel better than James Brown.Article: 17627
<mx3000@my-deja.com> wrote in message news:7p65k0$4ts$1@nnrp1.deja.com... > Hey, > > I'm going to be starting on some hefty Virtex > FPGA designs, and I was trying to settle on > a HDL to use. I've briefly used VHDL and been > OK with it. (I don't see anything wrong with > the strong typing.) Other people around me are > saying that Verilog is a better choice for now > (more device models available for simulation, > easier) and the future (gaining market share over > VHDL). > > Are there any recent surveys indicating what > current trends are? > > Does it really matter? > > Thanks, > > Peter I'll put in my two-cents worth on this one. From the standpoint of getting the job done, both VHDL and Verilog(tm) work equally well. They both synthesize pretty efficiently into FPGA and ASIC devices. There are language differences, of course, but the end result is the same. The main reason for using either language is not so much for a design entry tool, but for a tool that allows portability between various brands and types of target devices. Furthermore, their use is a strategic way to protect your design investment. If a 'proprietary' tool vendor goes out of business or quits selling a product line (a fairly common event in the schematic based entry tools), then you can switch to another tool vendor. We've discovered that in the U.S., VHDL is more popular among FPGA developers, and Verilog(tm) is more popular among ASIC people. In Europe, they prefer VHDL across the board. As far as models go, I don't find that there are more models available on either language. If you want to lock yourself into a specific brand of tool (Synopsis, etc.), then you may find that there are more models available from that particular tool vendor. We are located in the U.S., and do more work on VHDL than in Verilog(tm). However, that choice is based on the knowledge that there are more colleges and Universities training engineers with VHDL. We've got a labor shortage here (< 2.5% unemployment), and it is our view that there is a larger labor pool associated with VHDL than Verilog(tm). Furthermore, we have found that there is a 5:1 more plentiful supply of VHDL training materials (such as books). Furthermore, there are more internationally recognized standards activity in VHDL than in Verilog. For example, there are quite a few IEEE standards based on the VHDL language, and only one or two on Verilog. This makes it easier to build compliant tools. Like I say...my 2 cents worth. Verilog(tm) is a trademark of Cadence Design Systems, Inc. -- Wade D. Peterson Silicore Corporation 3525 E. 27th St. No. 301, Minneapolis, MN USA 55406 TEL: (612) 722-3815, FAX: (612) 722-5841 URL: http://www.silicore.net/ E-MAIL: peter299@maroon.tc.umn.eduArticle: 17628
Hi, Currently I find myself in a position where I have to decide whether I should buy or make an fpga based board. To give more details : it should contain a modest fpga (XC4025) and possibly an A/D converter. That's it, not even external ram or anything. So, what would you suggest? By the way, where can I find pricelists for the Xilinx devices? Kind regards, Pieter Pieter Op de Beeck K.U.Leuven - ESAT - PSI/ACCA Kardinaal Mercierlaan 94 3001 Heverlee pieter.opdebeeck@esat.kuleuven.ac.beArticle: 17629
Can anyone tell me where to find vhdl code to debounce and latch a input from a momentary switch? Regards, KevinArticle: 17630
Pieter,
Why not simply go for it and make the board? If all involved are two
chips plus some resistors and capacitors, then I say it is an easy design.
Just make sure you follow good design rules inside the FPGA, like
synchronizing everything.
There was a time when you could get pricing on Xilinx FPGAs at
Marshall's (distributor) web site; however, they lost Xilinx on their line
card. I would call your local friendly Xilinx rep, FAE, or salesperson. I
know that they carry price lists around with them.
-Simon
Pieter Op de Beeck <pieter.opdebeeck@esat.kuleuven.ac.be> wrote in message
news:37b82570.1844080484@news.kulnet.kuleuven.ac.be...
> Hi,
>
> Currently I find myself in a position where I have to decide whether I
> should buy or make an fpga based board. To give more details : it
> should contain a modest fpga (XC4025) and possibly an A/D converter.
> That's it, not even external ram or anything.
> So, what would you suggest?
>
> By the way, where can I find pricelists for the Xilinx devices?
>
> Kind regards,
> Pieter
>
> Pieter Op de Beeck
> K.U.Leuven - ESAT - PSI/ACCA
> Kardinaal Mercierlaan 94
> 3001 Heverlee
> pieter.opdebeeck@esat.kuleuven.ac.be
Article: 17631We currently have a product which could fit your requirements. We developed a 80MHz state and timing logic analyzer which connects to a PC. Some of the option cards include D1 interfaces for video, but we also have a FPGA card. The FPGA card interfaces to the main board (Logic Analyzer/ Signal Generator). The FPGA card is ment to provide user interface to the front end of our equipment. Another board which we are still developing is both an A/D board and a DAC board. Both boards are 12 bit and run at 40MHz. If all you need is a A/D and a FPGA, you could take the FPGA board and connect it with the A/D board. The FPGA board supports both Xilinx Virtex parts, and Altera 10kE parts. You can see the base board, D1 boards, and FPGA boards at www.programmable-products.com. Brad Ree www.programmable-products.com brad.ree@programmable-products.com 770-736-8932 Pieter Op de Beeck wrote: > > Hi, > > Currently I find myself in a position where I have to decide whether I > should buy or make an fpga based board. To give more details : it > should contain a modest fpga (XC4025) and possibly an A/D converter. > That's it, not even external ram or anything. > So, what would you suggest? > > By the way, where can I find pricelists for the Xilinx devices? > > Kind regards, > Pieter > > Pieter Op de Beeck > K.U.Leuven - ESAT - PSI/ACCA > Kardinaal Mercierlaan 94 > 3001 Heverlee > pieter.opdebeeck@esat.kuleuven.ac.beArticle: 17632
Greetings This is semimonthly announcement of Verilog FAQ. Verilog FAQ is located at http://www.angelfire.com/in/verilogfaq/ Alternate Verilog FAQ is an attempt to gather the answers to most Frequently Asked Questions about Verilog HDL in one place. It also contains list of publications, services, and products. Alternate Verilog FAQ is divided into three logical parts. Part 1 : Introduction and misc. questions Part 2 : Technical Topics Part 3 : Tools and Services What's New section outlines the changes in different versions and announcements. Links connects you to related informative links in internet. Your suggestions to make this FAQ more informative are welcome. Rajesh Bawankule (Also Visit Verilog & EDA Page : http://www.angelfire.com/in/rajesh52/verilog.html ) Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17633
jtag don't work as far as I know. set all mode pins to "1" Slave-serial mode. Then use the regular download cable (DLC5). You have to set XIL_HWD_PCAB_FIX = 1 in autoexec.bat file or just set the above in the environment for NT. cuong wrote: > Hello, > > I tried to download my design to the xcv100_pq240. It runs correctly > sometimes. But after an new implementation, the configuration failed and > DONE signal doesn't go high. It happened in many times. > > My hardware configuration is: > > "M2 M1 M0" = "101" > > I selected the startup clock = Jtagclk. . > > the version of Design Manager is 1.5.25. > > With the new version of Design Manager 2.1i, there is no change. > > Can you show me exactly what to do ? > > Thanks. > > Best Regards -- Steve Casselman, President Virtual Computer Corporation http://www.vcc.comArticle: 17634
www.compu-medic.net www.compu-medic.net www.compu-medic.net If you are looking for computer parts then look no further. We now have a complete line of microsoft License software. We have price that are hard to beat. Also we have service that is hard to beat. We focus on you and what will best meet your needs. Compu-Medic where you get service with a smile. Here are a few prices to look at. Hope to see you soon. Processors AMD K6-II450MHz MMX $96 AMD K6-III400Mhz MMX $146 AMD K6-III450Mhz MMX $220 CPPC333PPGAOEM $77 INTEL CELERON 366Mhz PPGA OEM $89 INTEL CELERON 400Mhz OEM W/128 $134 INTEL CELERON 433Mhz PPGA OEM $114 INTEL PENTIUM II 400 MHz SECC2 OEM $202 INTEL PENTIUM II 450MHz OEM $280 INTEL PENTIUM II 450 MHz SECC2 $290 INTEL PENTIUM III 450MHz OEM $243 PENTIUM III 500Mhz RETAIL $444 INTEL PENTIUM III 500MHz OEM $438 PENTIUM III 550Mhz RETAIL $671 PENTIUM III 600Mhz RETAIL $750 INTEL XEON 450Mhz W/512K RETAIL $720 Modems Shark-OEM 56K PCI Int Box V80 VOICE $44 USROBOTICS- 56K ISA Int Voice $83 USROBOTICS- 56K PCI WIN MODEM Int Voice 2974 $58 Zoom-OEM 56K Ext V.90 Box $100 Zoom-OEM 56K ISA Int Box flex/V90-K56flex is the d $65 Zoom-OEM 56K PCI Int Box - Fully AT Command Set Co $54 Zoom-OEM 56K PCMCIA Box $107 Hard Drive MAXTOR-13.6G-IDE-UDMA- $173 MAXTOR-17.2G-EIDE-UDMA-<9MS-91728DA -ATA-4 $210 MAXTOR-4.3G-EIDE-UDMA-<10MS-84320D5 $115 MAXTOR-8.4G-EIDE-UDMA-<9.7MS-88455D8 $135 MAXTOR - 10.8 GB IDE 5400RPM QUASAR $170 MAXTOR - 13 GB IDE 5400RPM QUASAR $186 MAXTOR 20.40GB EIDE ULTRA-DMA/33 3.5LP 7200RPM DIA $300 QUANTUM-5.1G-IDE $125 SEAGATE-3.2G-IDE-<12MS-ST33232A $100 SEAGATE 10.2GB EIDE ULTRA DMA 10MS 5400RPM $163 SEAGATE 8.4 EIDE ULTRA DMA 3.5L 9MS 5400RPM $135 SEAGATE - 9.10GB SCSI ULTRA2 LVD 68 PIN 9.5MS 3.5L $332 WD-6.4GB-EIDE-ULTRA-DMA/33-9.5MS $127 WD-8.4GB-EIDE-ULTRA-DMA/33-11MS $135 WD-13.00GB EIDE ULTRA-ATA/66 3.5LP 9.5MS 5400RPM C $188 WD 10.20GB EIDE ULTRA-ATA/66 3.5LP 9.5MS 5400RPM C $158 This list was put up 08/16/99 Prices subject to change! Phone: 401-946-8827 Cell: 401-965-8306 Fax: 401-946-8719 Website: www.compu-medic.net E-mail: compumedi@aol.com E-mail: compmedsec@aol.com If you want a website let use know we have everything you need to get started. From a two page free website to a $130 website for a year special. We are your one stop place for everything you need online. We will ship any where in the world.Article: 17635
In article <37b82570.1844080484@news.kulnet.kuleuven.ac.be>, pieter.opdebeeck@esat.kuleuven.ac.be (Pieter Op de Beeck) wrote: > Hi, > > Currently I find myself in a position where I have to decide whether I > should buy or make an fpga based board. To give more details : it > should contain a modest fpga (XC4025) and possibly an A/D converter. > That's it, not even external ram or anything. > So, what would you suggest? > > By the way, where can I find pricelists for the Xilinx devices? > I'm putting together a simple prototyping board for the Spartan XS05XL in the PLCC84 package, using a round pad Eurocard. You could probably do something similar. I just phone my Xilinx distributor for price info. BTW, the Xilinx CPLD starter kit I've just bought includes a JTAG download cable and can be used for designs with the Virtex and Spartan devices. It only costs 60 punds in the UK. Leon leon_heller@hotmail.com Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17636
You should be able to download via JTAG at any time. It works for me on a V1000. Check you have the latest software. BTW I'm using DLC5 also. In article <37B86A40.AFAB4B32@vcc.com>, sc@vcc.com wrote: > jtag don't work as far as I know. > set all mode pins to "1" Slave-serial mode. > Then use the regular download cable (DLC5). > You have to > set XIL_HWD_PCAB_FIX = 1 > in autoexec.bat file or just set the above > in the environment for NT. > > cuong wrote: > > > Hello, > > > > I tried to download my design to the xcv100_pq240. It runs correctly > > sometimes. But after an new implementation, the configuration failed and > > DONE signal doesn't go high. It happened in many times. > > > > My hardware configuration is: > > > > "M2 M1 M0" = "101" > > > > I selected the startup clock = Jtagclk. . > > > > the version of Design Manager is 1.5.25. > > > > With the new version of Design Manager 2.1i, there is no change. > > > > Can you show me exactly what to do ? > > > > Thanks. > > > > Best Regards > > -- > Steve Casselman, President > Virtual Computer Corporation > http://www.vcc.com > > Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17637
z0rbaf@newsguy.com wrote: > > Does anyone here have any experence with the XILINX > 4000 series logic? I am attempting to parrallel load > a 4020 and the load is failing. I'm using the same > bits as would program the chip in serial mod through > the Xchecker cable. any help here? & thanks much. If I am not mistaken, don't you have to reverse the bits in the bytes to use the parallel load? I think the bit file is designed for serial downloading with the msb first. The XC4000 data sheet shows a table on page 44 with the bit fields. The fill byte and format code form the bytes FF 2x in the bit file (after the header stuff that you can rip out). The text of the data sheet says that the serial data is sent from this file format with msb first. A parallel load is sent with the first bit at D0. This effectively means that you have to bit reverse your bytes to send them in any parallel mode. I believe that if you use the prom generator to strip off the header, it can do the bit reversal for you. You might check it out. That is likely the most straight forward method. I am planning on leaving the header on the bit stream so that I can get version info on my bit stream in the embedded product since the header has target device, time, date and file name in it. So I will have to do bit reversal in the DSP, or hook up the bus bits reversed. I am not sure which way is best. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 17638
I believe this is a difference between VHDL 87 and 93.
87
temp <= '1';
port map(component_pin=> temp);
93
port map(component_pin=> '1');
Chi Fung wrote:
>
> I understand that the standard format for component instantiation
> using port map is
>
> U1: comp1
> port map(component_pin=>signal_node);
>
> where signal_node has been declared previously right
> below the currrent architecture.
>
> My problem is, let say, if I want to port map component_pin
> to a constant, e.g. '1' instead of signal_node, how am I
> suppose to code that? I have tried
>
> port map(component_pin=>'1');
>
> but it doesn't seem to work.
>
> Thanks for any hints.
--
Paulo //\\\\
| ~ ~ |
( O O )
__________________________________oOOo______( )_____oOOo_______
| . |
| / 7\'7 Paulo Dutra (paulo@xilinx.com) |
| \ \ ` Xilinx hotline@xilinx.com |
| / / 2100 Logic Drive (800) 255-7778 |
| \_\/.\ San Jose, California 95124-3450 USA |
| Oooo |
|________________________________________oooO______( )_________|
( ) ) /
\ ( (_/
\_)
Article: 17639If you have large or multiple FPGA's and want easy in-circuit re-configuration, check out the FLASH based XILINX FPGA Configurator at the following address: http://www.fpgaconfigurator.com/ In addition to the plug in version shown at the above address, a pod version will be available soon to ease your current FPGA developments. Thanks for looking......gregArticle: 17640
For those of you using the new Altera Quartus package, are you finding a lot of bugs? If so, could you please send me information about the kinds of problems you are seeing. I am trying to evaluate using it for a new design and have seen several problems and three different PC I have tried. As of yet, Altera's support has been unable to reproduce any of what I have found. The biggest problem I have found is when I select the EP20K100QC240-3 device, and try to simulate, the software appears to lock-up after the simulation begins initial setup at 25% complete. All three PCs exhibit this problem. Sent via Deja.com http://www.deja.com/ Share what you know. Learn what you don't.Article: 17641
Can somebody tell me how can I enable VHDL'93 on Xilinx Foundation (student ed)? (or, perhaps, it doesn't support '93 at all!). Thanks for help.Article: 17642
Hi ! I am new to the group (which I stumbled upon accidentally.) I am actually looking for newsgroups/discussion groups that discuss the above topic(s), represented by companies like EXCEL SWITCHING that got acquired by Lucent today for $1.5b (yes!) Any other resources/tutorials/people references would also be most welcome. Reply directly, if you wish. Regards, a.mian@ieee.org * Sent from RemarQ http://www.remarq.com The Internet's Discussion Network * The fastest and easiest way to search and participate in Usenet - Free!Article: 17643
Hi Anyone encountered error of above, can dispense some advise how to get rid of it. It displays this error FE-PADMAP-02 when I am synthesising the VHDL design using foundation v1.5. YeopArticle: 17644
LPM is written by AHDL not VHDL. If you are using LPM, your design is no more VHDL desing. "Asher C. Martin" wrote: > Greetings, > > Thanks for the advice... would anyone happen to know if LPM functions > are necessary to reduce the amount of space that VHDL takes up on an > FPGA? > > Best regards, > > >Asher< > > <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>> > Asher C. Martin > 805 West Oregon Street > Urbana, IL 61801-3825 > (217) 367-3877 > E-MAIL: martin2@acm.uiuc.edu > http://fermi.isdn.uiuc.edu > telnet://fermi.isdn.uiuc.edu > ftp://feynman.isdn.uiuc.edu > <<=>>=<<=>>=<<=>><<=>>=<<=>>=<<=>>Article: 17645
Hi, Can anyone give me the total number of CLBs for a multiplier (area or performance optimized) in a Virtex ? Is this the same as for the 4000 family (why not?)? Thanks, PieterArticle: 17646
I am trying to design a board for Xilinx XC9500 CPLD you can check the block diagram and later I'll update the page with all the design information www.geocities.com/SiliconValley/Pines/openip/board.html You are welcomed to join our OpenIP project for open hardware designs our temporary site is www.geocities.com/SiliconValley/Pines/6639/openip Jamil Khatib Pieter Op de Beeck wrote: > Hi, > > Currently I find myself in a position where I have to decide whether I > should buy or make an fpga based board. To give more details : it > should contain a modest fpga (XC4025) and possibly an A/D converter. > That's it, not even external ram or anything. > So, what would you suggest? > > By the way, where can I find pricelists for the Xilinx devices? > > Kind regards, > Pieter > > Pieter Op de Beeck > K.U.Leuven - ESAT - PSI/ACCA > Kardinaal Mercierlaan 94 > 3001 Heverlee > pieter.opdebeeck@esat.kuleuven.ac.beArticle: 17647
DesignPRO has a number of ASIC/FPGA Design Engineers available for contract service opportunities. DesignPRO is a contract engineering design organization based in Ottawa, Canada, specializing in Telecom Solutions in Silicon, and offering a complete spectrum of turnkey product development services, including: * system design; * chip and board specification; * FPGA and ASIC design and verification; * PCB design and manufacturing, * DSP coding; * firmware and software development; * hardware and software integration testing; With EXPERIENCE and REUSABLE BLOCKS in the following areas: * ATM & Packet over SONET/SDH - X@STS-1, X@STS-3c, X@STS-12c, X@STS-48c * High speed access products, xDSL, T1/E1, Cable Modem; * ATM, PPP, 8b10b, HDLC, SDLC, TCP/IP, UTOPIA (Level I, II & III), Ethernet, PCI, VME; * Wireless - CDMA, GPS, LMDS, PCS. DesignPRO is a proud member of the Altera Consultant Alliance Program (ACAP) and the Xilinx XPERT Program. DesignPRO is pleased to announce the release of a fully configurable suite of reusable cores (unencrypted IP), providing the building blocks for ATM and Packet over SONET/SDH for all of the possible configurations from STS-1 to STS-48c (i.e. X@STS-1, X@STS-3c, X@STS-12c, X@STS-48c). DesignPRO offers non-exclusive, non-transferable rights and licenses to reuse, modify and evolve the IP for the purpose of IC development for subsequent product sale. In addition, it would be our pleasure to provide contract engineering design services to assist with developments using the IP, which will facilitate knowledge transfer, while developing product. Our team of design engineers with experience and IP could be a great asset to any company using any one of a variety of business models. DesignPRO's list of customers includes many of the key communications companies in the world, including Nortel Networks, Newbridge Networks, Lucent Technologies - Ascend Communications, Motorola, and many other mid-size and smaller firms. For additional information about DesignPRO, visit our website at www.designpr.com or contact: Andrew Bunsick General Manager abunsick@designpr.com (613) 596-5030Article: 17648
>Can somebody tell me how can I enable VHDL'93 on Xilinx Foundation >(student ed)? (or, perhaps, it doesn't support '93 at all!). Thanks for >help. you can't "enable" it. What version of Foundation are you using? Some support for '93 was added in FPGA Express 3.1; it's supposed to be better in 3.2. -- ----------------------------------------- Andy Peters Sr Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters (at) noao.edu The Republican Party: "We've upped our standards. Now, up yours!" Chi Fung wrote in message <37ba25bf.0@scctn03.sp.edu.sg>...Article: 17649
Hi, Has any one encountered a situation where M1.5i map get hung apparently in an infinite loop? And if so what was the cause? Thanks for any help Bob Pearson bpearson@pmr.com
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z