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The adder is placed to take advantage of the carry chain, which requires it to be packed 2 bits per slice. The register is not placed at all, so the PAR software is spreading it out. If you look at the results in either the floorplanner (2.1) or EPIC, you'll see that the registers have been scattered around somewhat so that there are slices with only one flip-flop used. You can put placement constraints on the register if you instantiate flip-flop primitives or you can place them in the floor planner if you need them to be packed. martin_at_deja@my-deja.com wrote: > I am trying to estimate how many CLB's my design is going to need > and I have some interesting findings to share. > > Let me go through the assumptions first. > I use verilog, synplify 5.15, Xilinx Virtex v50pq240-4 (for the purpose > of the example - in reality I use the 1000), and M2.1i tools. > > I have done a very simplistic 32-bit adder design as > shown below: > > // Force i/o's into IOB's > if (reset) > begin > at <= 'h0; > bt <= 'h0; > q <= 'h0; > else > begin > at <= a; > bt <= b; > q <= qt; > end > > // 32-bit adder > if (reset) > qt <= 'h0 > else if (enable) > qt <= at + bt; // Comment out "+ bt" for the register example > > Comment out everything related to the "b" input and get a simple 32-bit > register. > > After mapping, the results strike me: > > adder: 16 slices > register: 21 slices > (exclude I/O's - just want core function) > > Why an adder (more complex) would need more slices than a simpler > design (register)??? I have done a 5 32-bit register design and > this scales almost linearly, i.e. 107 slices! Am I missing something? > > How come both dff slices not be utilized completely in > the register implementation cases, i.e. a 32-bit register should > map to 16 slices max. The "-c" switch does not seem to do anything. > > I have opened a case at xilinx, but I thought I'd share this > with you. > > Cheers > Martin > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18126
Hi, The short version is I have a 25Mhz clock and I'm trying to "reliably" get info from a fifo which has a 25ns access time and 10ns recovery time. I am trying to produce a signal from the 25Mhz clock (which is pretty close to 20ns on each phase) which is 25ns on one phase and 15 ns on the other in VHDL. I am using the XACT 6.0/Foundation software and I cannot figure out how to keep it from optimizing out my attempts to use a double inversion. Any help or other ways I could achieve the same results is greatly appreciated. Thanks for your time. Tyrone P.S. If you are interested here is some further background: The project is a high-speed networking card designed to run at 200Mbits. I could simply drop in a 20 Mhz crystal, which is how I have been testing it thus far, but then it would max out at 160 Mbits. I would change the fifo but it is soldered on the board. I am using the older tools because the main fpga on the board is an XC4008 which is not supported by the newer software. -- -------------- thompson@eecis.udel.edu University of Delaware Tyrone Thompson EE Graduate StudentArticle: 18127
This is well explained in the "Synthesis and Simulation Guide", Chap. 5.
http://toolbox.xilinx.com/docsan/2_1i
In the design code, declare GSR as a Verilog wire, however, it is not specified
in the port list for the module. Describe GSR to reset or set
every inferred register or latch in your design. GSR does not need to be
connected to any instantiated registers or latches, as shown in the
following example.
module my_counter (CLK, D, Q, COUT);
input CLK, D;
output Q;
output [3:0] COUT;
wire GSR;
reg [3:0] COUT;
always @(posedge GSR or posedge CLK)
begin
if (GSR == 1'b1)
COUT = 4'h0;
else
COUT = COUT + 1'b1;
end
// FDCE instantiation
// GSR is modeled as a wire within a global module. So,
// CLR does not need to be connected to GSR and the flop
// will still be reset with GSR.
FDCE U0 (.Q (Q), .D (D), .C (CLK), .CE (1'b1), .CLR (1'b0));
endmodule
Since GSR is declared as a floating wire and is not in the port list, the
synthesis tool optimizes the GSR signal out of the design. GSR is replaced later
by the implementation software for all post-implementation simulation netlists.
In the test fixture file, set GSR to test.uut.GSR (the name of the global
set/reset signal, qualified by the name of the design instantiation instance
name and the test fixture instance name). Since there is no STARTUP block, a
connection to GSR is made in the testfixture via an assign statement.
`timescale 1 ns / 1 ps
module test;
reg CLK, D;
wire Q;
wire [3:0] COUT;
reg GSR;
assign glbl.GSR = GSR;
assign test.uut.GSR = GSR;
my_counter uut (.CLK (CLK), .D (D), .Q (Q), .COUT (COUT));
initial begin
$timeformat(-9,1,"ns",12);
$display("\t T C G D Q C");
$display("\t i L S O");
$display("\t m K R U");
$display("\t e T");
$monitor("%t %b %b %b %b %h", $time, CLK, GSR, D, Q, COUT);
end
initial begin
CLK = 0;
forever #25 CLK = ~CLK;
end
initial begin
#0 {GSR, D} = 2'b11;
#100 {GSR, D} = 2'b10;
#100 {GSR, D} = 2'b00;
#100 {GSR, D} = 2'b01;
#100 $finish;
end
endmodule
In this example, the active high GSR signal in the XC4000 family device is
activated by driving it high. 100 ns later, it is deactivated by driving it low.
(100 ns is an arbitrarily chosen value.)
Joseph H Allen wrote:
>
> I don't need an explicit reset pin since all flip-flops are reset on
> initialization anyway, however I still want to define the global reset net
> in verilog. Is there a way to indicate that this net is being driven by the
> chip's internal reset generator without having to bring the net out to an
> external pin?
>
> For example, I can do this ok:
>
> module toplevel(clk,reset,in,out);
> input clk, reset, in;
> output out;
> reg out;
>
> STARTUP u1(.GSR(reset));
>
> always @(posedge clk or posedge reset)
> if(reset) out=0;
> else out=in;
>
> endmodule
>
> But I really want something like this, with no pin wasted on the reset
> signal:
>
> module toplevel(clk,in,out);
> input clk, in;
> output out;
> reg out;
>
> wire reset=BUILT_IN_RESET_GENERATOR;
>
> STARTUP u1(.GSR(reset));
>
> always @(posedge clk or posedge reset)
> if(reset) out=0;
> else out=in;
>
> endmodule
> --
> /* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
> int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
> +r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
> ]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
--
Paulo //\\\\
| ~ ~ |
( O O )
__________________________________oOOo______( )_____oOOo_______
| . |
| / 7\'7 Paulo Dutra (paulo@xilinx.com) |
| \ \ ` Xilinx hotline@xilinx.com |
| / / 2100 Logic Drive (800) 255-7778 |
| \_\/.\ San Jose, California 95124-3450 USA |
| Oooo |
|________________________________________oooO______( )_________|
( ) ) /
\ ( (_/
\_)
Article: 18128Try the Intel developers web site: http://developer.intel.com/design/strong/index.htm and here: http://developer.intel.com/design/strong/quicklist/eval-plat/ I can't vouch for University discounts though ;-) senget <sfmohdsa@engmail.uwaterloo.ca> wrote in article <bYWI3.6530$xJ4.327824@newscontent-01.sprint.ca>... > Hai all > > I am searching for evaluation/development board with StrongARM (SA-11XX) > processors. Anybody know where I can find such board and have uni. discount. > Your help is highly appreciated > > Thank you > > >Article: 18129
In article <37F531FA.C63E8448@xilinx.com>,
Paulo Dutra <paulo@xilinx.com> wrote:
>In the design code, declare GSR as a Verilog wire, however, it is not
>specified in the port list for the module. Describe GSR to reset or set
>every inferred register or latch in your design. GSR does not need to be
>connected to any instantiated registers or latches, as shown in the
>following example.
> module my_counter (CLK, D, Q, COUT);
> input CLK, D;
> output Q;
> output [3:0] COUT;
>
> wire GSR;
>
> reg [3:0] COUT;
>
> always @(posedge GSR or posedge CLK)
> begin
> if (GSR == 1'b1)
> COUT = 4'h0;
> else
> COUT = COUT + 1'b1;
> end
>
> // FDCE instantiation
> // GSR is modeled as a wire within a global module. So,
> // CLR does not need to be connected to GSR and the flop
> // will still be reset with GSR.
>
> FDCE U0 (.Q (Q), .D (D), .C (CLK), .CE (1'b1), .CLR (1'b0));
>
> endmodule
>
>Since GSR is declared as a floating wire and is not in the port list, the
>synthesis tool optimizes the GSR signal out of the design. GSR is replaced
>later by the implementation software for all post-implementation simulation
>netlists.
When I do this, the synthesizer says "there is no global reset net in this
design, so the GSR signal will not be used". Should I ignore this message?
Also will this always work correctly with inferred D flip flops? for
example if you do something like this:
module top(clk,in,out);
output out;
input in, clk;
reg x;
wire GSR=0;
always @(posedge CLK or posedge GSR)
if(GSR) x=0;
else x=~in;
assign out=~x;
endmodule
If GSR gets optimized out, there doesn't seem to be a reason for the
inverters to not be optimized out. Then on reset, output will be 0 instead
of 1. I don't know if this will happen, but it seems like it could. If
this optimization never happens I'll ignore the issue.
Also, I have another question (if you don't mind). Will foundation
express ever duplicate FFs? For example if you bring a signal from a flip
flop to an output pin, but also use the signal elsewhere in the design, will
two flip flops be created? One for the internal signal and one in the IOB
for the external signal? Or will only one flip flop be created, and the IOB
flip flop remain unused?
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 18130Tyrone Thompson <thompson@ren.eecis.udel.edu> wrote in message news:7t38lv$c3c$1@dewey.udel.edu... > The short version is I have a 25Mhz clock and I'm trying to "reliably" get info > from a fifo which has a 25ns access time and 10ns recovery time. I am trying to > produce a signal from the 25Mhz clock (which is pretty close to 20ns on each > phase) which is 25ns on one phase and 15 ns on the other in VHDL. I am using > the XACT 6.0/Foundation software and I cannot figure out how to keep it from > optimizing out my attempts to use a double inversion. Any help or other ways I > could achieve the same results is greatly appreciated. 60/40 phasing is possible to do, albeit a bit cumbersome. In your case, use a 250 Mhz (positive edge) input clock, and a state machine to divide by ten and generate the 60/40 duty cycle at the same time. For the most part, you probably won't be able to find 250 Mhz crystal oscillators. However, you could use a 25 Mhz input clock and a phase-lock-loop (PLL) to generate the 250 Mhz reference frequency. You may not be able to do this in the FPGA itself, unless they have a PLL clock generator internal to the device. I've done this trick before (in a different RF application), but it was with descrete ECL parts. This may be a kludgy solution, so you might want to consider something else. -- Wade D. Peterson Silicore Corporation 3525 E. 27th St. No. 301, Minneapolis, MN USA 55406 TEL: (612) 722-3815, FAX: (612) 722-5841 URL: http://www.silicore.net/ E-MAIL: peter299@maroon.tc.umn.eduArticle: 18131
RE: my last post about Lucent / PCI interface Xilinx also has a PCI core on their website. Has anybody tried that thing, and does it work? Any special problems with integrating 3rd party VHDL tools to the interface? -- Wade D. Peterson Silicore Corporation 3525 E. 27th St. No. 301, Minneapolis, MN USA 55406 TEL: (612) 722-3815, FAX: (612) 722-5841 URL: http://www.silicore.net/ E-MAIL: peter299@maroon.tc.umn.eduArticle: 18132
In article <FIyJ7v.2uv@world.std.com>,
Joseph H Allen <jhallen@world.std.com> wrote:
>Also will this always work correctly with inferred D flip flops?
In fact this method does not work correctly. For example, if I want a
flip-flop which is to be preset in a family which does not have a preset
option built into the CLB flip flops (like XC5000 series), this problem will
occur:
When you bring the reset signal out to a pin it works correctly, and
'out' is 1 after configuration.
module top(in,out,reset,clk)
input in,reset,clk;
output out;
reg out;
always @(posedge clk or posedge reset)
if(reset) out <= 1;
else out <= in;
endmodule
But when I follow the direction you suggest, it fails and out is 0 after
configuration:
module top(in,out,clk)
input in,clk;
output out;
reg out;
wire reset;
always @(posedge clk or posedge reset)
if(reset) out <= 1;
else out <= in;
endmodule
There really needs to be a module like 'ROC' for VHDL.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 18133steves@traclabs.com wrote: > > Hello. Sorry, this is not entirely FPGA related. Has anybody used a > 0.8mm pitch BGA on their board? I am using the CS280 package from > Xilinx and have some questions. What trace/via/pad and clearances > were used on the PCB? Any links to guidelines on using these devices > would be nice. My layout guy hasn't found anything on these devices > yet. Thanks for your time. I just had to change a part on my board from a microBGA to a TSSOP because of this. The part was a 64 pin 0.8 pitch BGA with no open space in the center. We could not get out from the center pads without using vias in between the pads. This would have required an annular ring around the via smaller than the 5 mil traces and much smaller than the other via pads we were using. I decided it was not worth it and switched packages. I can't find any info on the Xilinx web site about the CS280 package. If they are making it, they are hiding the information as usual. I am learning a lot about chip mounting by talking to the board fab and assembly people. I would recommend that you give your people a shout. -- Rick Collins rick.collins@XYarius.com remove the XY to email me. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 18134
Thank you for the information Is there any other company where can I purchase evaluation/development board with SA-11XX processor Austin Franklin wrote in message <01bf0c86$abde3240$247079c0@drt4>... >Try the Intel developers web site: > >http://developer.intel.com/design/strong/index.htm > >and here: > >http://developer.intel.com/design/strong/quicklist/eval-plat/ > >I can't vouch for University discounts though ;-) > >Article: 18135
You are confusing the time to load (reconfigure) the device with place and route, which the time to generate the bitstream. Place and route is usually done with the FPGA design tools and the results are stored for use in the FPGA device. The "blue" statement below is accurate for reconfiguration. The place and route can take anywhere from a few seconds to many hours depending on factors such as the complexity of the design, how much placement is stipulated in the design in the form of floorplanning, and routing congestion in the design. BTW, why the colored background? I don't know how to make it go away, and I suspect it may make it hard for some readers to read this. anup kumar raghavan wrote: > Hi, I was reading an article and have a doubt on this? > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > Virtex FPGAs support partial > reconfiguration, thus allowing new > circuitry to be downloaded while > standard operation continues within > the device. A fast 400Mb/second > reconfiguration rate ensures that a > full reconfiguration can be done in > milliseconds and a partial > reconfiguration can be done in > microseconds. > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > This article was from the site > > http://www.chipcenter.com > My doubt lies in the line I have marked with Blue > > Usually the internal connections to be routed in a FPGA take several > hours doesnt it? So when a > configuration is changing , how can the new configuration take effect > so rapidly on the device ? > > Thanks again .. > > > Regards > > Anup -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18136
Depending on delays in FPGAs is generally a bad practice, as the design becomes very sensitive to routing, as well as to process improvements. You might be able to reliably use the FPGA circuit delays by constructing a delay lock loop in the FPGA logic. It uses feedback to adjust how many delay elements are in the signal. You could probably use the carry chain as the delay line, as it has relatively short and consistent delays for each "tap". You will have to be careful about the routing off the taps though. I haven't tried this to see how well it works, but at 25 MHz, you might be able to pull it off. Tyrone Thompson wrote: > Hi, > > The short version is I have a 25Mhz clock and I'm trying to "reliably" get info > from a fifo which has a 25ns access time and 10ns recovery time. I am trying to > produce a signal from the 25Mhz clock (which is pretty close to 20ns on each > phase) which is 25ns on one phase and 15 ns on the other in VHDL. I am using > the XACT 6.0/Foundation software and I cannot figure out how to keep it from > optimizing out my attempts to use a double inversion. Any help or other ways I > could achieve the same results is greatly appreciated. > > Thanks for your time. > > Tyrone > > P.S. If you are interested here is some further background: > > The project is a high-speed networking card designed to run at 200Mbits. I > could simply drop in a 20 Mhz crystal, which is how I have been testing it > thus far, but then it would max out at 160 Mbits. I would change the fifo > but it is soldered on the board. I am using the older tools because the > main fpga on the board is an XC4008 which is not supported by the newer > software. > -- > -------------- > thompson@eecis.udel.edu University of Delaware > Tyrone Thompson EE Graduate Student -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18137
You are confusing the time to load (reconfigure) the device with place and route, which the time to generate the bitstream. Place and route is usually done with the FPGA design tools and the results are stored for use in the FPGA device. The "blue" statement below is accurate for reconfiguration. The place and route can take anywhere from a few seconds to many hours depending on factors such as the complexity of the design, how much placement is stipulated in the design in the form of floorplanning, and routing congestion in the design. BTW, why the colored background? I don't know how to make it go away, and I suspect it may make it hard for some readers to read this. anup kumar raghavan wrote: > Hi, I was reading an article and have a doubt on this? > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > Virtex FPGAs support partial > reconfiguration, thus allowing new > circuitry to be downloaded while > standard operation continues within > the device. A fast 400Mb/second > reconfiguration rate ensures that a > full reconfiguration can be done in > milliseconds and a partial > reconfiguration can be done in > microseconds. > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > This article was from the site > > http://www.chipcenter.com > My doubt lies in the line I have marked with Blue > > Usually the internal connections to be routed in a FPGA take several > hours doesnt it? So when a > configuration is changing , how can the new configuration take effect > so rapidly on the device ? > > Thanks again .. > > > Regards > > Anup -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18138
Depending on delays in FPGAs is generally a bad practice, as the design becomes very sensitive to routing, as well as to process improvements. You might be able to reliably use the FPGA circuit delays by constructing a delay lock loop in the FPGA logic. It uses feedback to adjust how many delay elements are in the signal. You could probably use the carry chain as the delay line, as it has relatively short and consistent delays for each "tap". You will have to be careful about the routing off the taps though. I haven't tried this to see how well it works, but at 25 MHz, you might be able to pull it off. Tyrone Thompson wrote: > Hi, > > The short version is I have a 25Mhz clock and I'm trying to "reliably" get info > from a fifo which has a 25ns access time and 10ns recovery time. I am trying to > produce a signal from the 25Mhz clock (which is pretty close to 20ns on each > phase) which is 25ns on one phase and 15 ns on the other in VHDL. I am using > the XACT 6.0/Foundation software and I cannot figure out how to keep it from > optimizing out my attempts to use a double inversion. Any help or other ways I > could achieve the same results is greatly appreciated. > > Thanks for your time. > > Tyrone > > P.S. If you are interested here is some further background: > > The project is a high-speed networking card designed to run at 200Mbits. I > could simply drop in a 20 Mhz crystal, which is how I have been testing it > thus far, but then it would max out at 160 Mbits. I would change the fifo > but it is soldered on the board. I am using the older tools because the > main fpga on the board is an XC4008 which is not supported by the newer > software. > -- > -------------- > thompson@eecis.udel.edu University of Delaware > Tyrone Thompson EE Graduate Student -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18139
Depending on delays in FPGAs is generally a bad practice, as the design becomes very sensitive to routing, as well as to process improvements. You might be able to reliably use the FPGA circuit delays by constructing a delay lock loop in the FPGA logic. It uses feedback to adjust how many delay elements are in the signal. You could probably use the carry chain as the delay line, as it has relatively short and consistent delays for each "tap". You will have to be careful about the routing off the taps though. I haven't tried this to see how well it works, but at 25 MHz, you might be able to pull it off. Tyrone Thompson wrote: > Hi, > > The short version is I have a 25Mhz clock and I'm trying to "reliably" get info > from a fifo which has a 25ns access time and 10ns recovery time. I am trying to > produce a signal from the 25Mhz clock (which is pretty close to 20ns on each > phase) which is 25ns on one phase and 15 ns on the other in VHDL. I am using > the XACT 6.0/Foundation software and I cannot figure out how to keep it from > optimizing out my attempts to use a double inversion. Any help or other ways I > could achieve the same results is greatly appreciated. > > Thanks for your time. > > Tyrone > > P.S. If you are interested here is some further background: > > The project is a high-speed networking card designed to run at 200Mbits. I > could simply drop in a 20 Mhz crystal, which is how I have been testing it > thus far, but then it would max out at 160 Mbits. I would change the fifo > but it is soldered on the board. I am using the older tools because the > main fpga on the board is an XC4008 which is not supported by the newer > software. > -- > -------------- > thompson@eecis.udel.edu University of Delaware > Tyrone Thompson EE Graduate Student -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18140
You are confusing the time to load (reconfigure) the device with place and route, which the time to generate the bitstream. Place and route is usually done with the FPGA design tools and the results are stored for use in the FPGA device. The "blue" statement below is accurate for reconfiguration. The place and route can take anywhere from a few seconds to many hours depending on factors such as the complexity of the design, how much placement is stipulated in the design in the form of floorplanning, and routing congestion in the design. BTW, why the colored background? I don't know how to make it go away, and I suspect it may make it hard for some readers to read this. anup kumar raghavan wrote: > Hi, I was reading an article and have a doubt on this? > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > Virtex FPGAs support partial > reconfiguration, thus allowing new > circuitry to be downloaded while > standard operation continues within > the device. A fast 400Mb/second > reconfiguration rate ensures that a > full reconfiguration can be done in > milliseconds and a partial > reconfiguration can be done in > microseconds. > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > This article was from the site > > http://www.chipcenter.com > My doubt lies in the line I have marked with Blue > > Usually the internal connections to be routed in a FPGA take several > hours doesnt it? So when a > configuration is changing , how can the new configuration take effect > so rapidly on the device ? > > Thanks again .. > > > Regards > > Anup -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18141
David Newman <celaban@yahoo.com> wrote in message news:37E73E1B.6E7F1827@yahoo.com... > Hi Greg, > > A decryption/encryption core can be found at : > > http://www.free-ip.com/DES/index.htm > > Good luck, Hi, is there a similar Web-side available for the European people? Thanks in advance, FranzArticle: 18142
anup kumar raghavan <anup@elec.uq.edu.au> wrote: [snip] : This article was from the site : http://www.chipcenter.com : My doubt lies in the line I have marked with Blue Comes out lovely in ASCII here ;-) /Please/ don't send messages with attached binary files to newsgroups. : Usually the internal connections to be routed in a FPGA take several : hours doesnt it? So when a configuration is changing , how can the new : configuration take effect so rapidly on the device ? Routing is different from downloading bitstreams - and reconfiguring these chips can genuinely happen as fast as the article says. -- __________ |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com I just got a dog for my girlfriend - what a trade.Article: 18143
Yes I strongly aggree with your definition of granularity in fpga's. The
routing archetecture is as important as the logic element especially when it
comes to synthesis. I have had very good luck synthesizing into Virtex parts
where the old xc4k parts failed miserably. I think the main difference is
the granularity of the routing resources.
Peter D.
George <g_roberts75@hotmail.com> wrote in message
news:7t0ce8$3eg$1@news.qub.ac.uk...
> >Ray Andraka <randraka@ids.net> wrote in message
> news:37F2B043.532A6FB8@ids.net...
> > Well, I've never considered the 4K ans anything but a course grained
> > architecture. I don't know of any real definitions, but for comparison
> sake
> > consider the atmel 6K or even the xilinx 6K. Those are what I'd call
fine
> grain
> > - each cell only handles a 2 or 3 input function, but the cell speeds
are
> > considerably higher than the 4K of the same time period. The 4 K cell
is
> a
> > conglomerate of smaller LUTs, flip-flops, carry logic etc. I haven't
come
> > across an architecture touted as medium grained. If you find a solid
> > definition, I'd like to hear it too.
>
> OK, that is how I would define it:
> I think the granularity of the the basic logic block (the number of I/O)
is
> not the only determing factor.
> I think the routing architecture is also very important.
> The fine logic granularity gives better logic utilisation (less wasted
logic
> resources). The coarse logic granularity allows the logic to be compacted
in
> one complex logic block resulting in a very high operating speed. From
> this side, we can say that XC6000 and Atmel6k for example are fine
grained.
> On the other hand, XC3000, XC4000, Virtex, Altra's Flex8000 etc. are
coarse
> grained.
> However, if the routing structure is hierarchical (i.e there are Local,
> Doubles, 4 length, 16 length etc. routings segments), the FPGA can be
> considered as both fine and coarse grained because it combines both the
> efficient logic utilisation and the high operating speed no matter what
the
> logic granularity is. That's why Virtex (and may be XC4000XL,XV) are
> sometimes decribed as fine grained (as well as coarse grained) because of
> the hierachical routing structure which means that a CLB can communicate
> with another distant CLB very quickly using long routing segments.
>
> Anybody agrees with that?
>
>
Article: 18144Hello, a question!!!! Anybody know about applications with fpga related with: **fuzzy logic **A/D converters or Operationals Amplifiers inside the FPGA. please, if someone have a suggest, send me a email, thanks!!!Article: 18145
Who is Norm? I'm not sure if the polynomial is correct for ATM or not. If the polynomial is x^43 + 1 then you need 43 delays, not the 42 you have shown. Think of 1 as x^0. In your drawing d0 should be e+q43. The '+' is the one bit sum, which is the exclusive OR of the serial data input and the feedback data path(s). The output can be taken off anywhere along the delay queue. You may want to take it from immediately AFTER the first register if the design is highly pipelined (as it would likely be for an FPGA implementation). This of course is the scrambler. The descrambler has feed-forward instead of feedback, also by 43 delays. Note that this scrambler is for serialized data, and as such may have too high a bit rate to be done in the FPGA. My guess is that you are using an external serializer, in which case you will need to transform this to the parallel form for the scrambler rather than this serial one. The translation to a parallel design is not trivial, and will take some time to derive. Rémi SEGLIE wrote: > I have to do an ATM scrambler in a FPGA and I wonder some questions : > Norm says that the polynome is x^43+1, it's enabled only during payload and > that the basic diagram is : > > ------------------------------- > | __ __ __ | > V | | | | | | | > Ei -->+-----| |-- | |-- ... --| |--| > | |__| |__| |__| > V > Yi > > (sorry for this poor draw) > In others words : > d0 = e + q42 > d1 = q0 > d2 = q1 > ... > d42 = q41 > > Is it right ? > > Thank you for your help. > > Rémi SEGLIE > Hardware Design Engineer > company : CELOGIC > www : http://www.celogic.com/ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18146
As I understand it, the INIT forces the FF to the state specified as the initial state in the device program, and REV forces it to the opposite state. Normally, the initial state is '0', but you can make it '1' using an INIT= attribute on the flip-flop. Peter, any comments? simon_bacon@my-deja.com wrote: > Does anyone have a definition of the REV on the Virtex flip-flops? > A search at Xilinx reveals nothing. This connection pairs with > INIT on each FF -- INIT seems to be set/reset. > > Many thanks. > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 18147
On Sun, 3 Oct 1999, Ray Andraka wrote: > Depending on delays in FPGAs is generally a bad practice, as the design becomes > very sensitive to routing, as well as to process improvements. You might be able > to reliably use the FPGA circuit delays by constructing a delay lock loop in the > FPGA logic. It uses feedback to adjust how many delay elements are in the signal. > You could probably use the carry chain as the delay line, as it has relatively > short and consistent delays for each "tap". You will have to be careful about the > routing off the taps though. I haven't tried this to see how well it works, but at > 25 MHz, you might be able to pull it off. It would seem that another consideration would be the amount of jitter on the clock edge that could be tolerated, since it would seems that switching between taps would produce such behavior. Perhaps since the clocking is only needed for a special device, that specific asynchronous logic be designed so that the sequencing of signals is always correct and IAW whatever signals come back from the device. --al toda ########################################################### Alvin E. Toda aet@lava.net sr. engineer Phone: 1-808-455-1331 2-Sigma WEB: http://www.lava.net/~aet/2-sigma.html 1363-A Hoowali St. Pearl City, Hawaii, USAArticle: 18148
Let me decribe it in more detail: What takes minutes or hours is the compilation of the design, where the software figures out how to place and interconnect the gates and flip-flops and how to to achieve the stipulated performance.. It's a bit like your effort when you design a pc-board "by hand". There has been a lot of progress, each recent software revision has cut the compile time in half, but it is still minutes and can be hours for a very big and demanding design. Once the design is compiled, the resulting configuration bitstream can be downloaded into the device pretty fast. In the old devices at 1 MHz, in XC4000 at up to 10 MHz, and in Virtex at up to 400 MHz ( 8 bits in parallel @50 MHz). So the downloading or reconfiguration takes only milliseconds if the new bitstream has been compiled beforehand. Peter Alfke, Xilinx Applications =================================== Tim Tyler wrote: > anup kumar raghavan <anup@elec.uq.edu.au> wrote: > > [snip] > > : This article was from the site > > : http://www.chipcenter.com > : My doubt lies in the line I have marked with Blue > > Comes out lovely in ASCII here ;-) > > /Please/ don't send messages with attached binary files to newsgroups. > > : Usually the internal connections to be routed in a FPGA take several > : hours doesnt it? So when a configuration is changing , how can the new > : configuration take effect so rapidly on the device ? > > Routing is different from downloading bitstreams - and reconfiguring > these chips can genuinely happen as fast as the article says. > -- > __________ > |im |yler The Mandala Centre http://www.mandala.co.uk/ tt@cryogen.com > > I just got a dog for my girlfriend - what a trade.Article: 18149
Hi, anyone knows of any free SDRAM and/or PCI controllers? regards, Damjan
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