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This is a multi-part message in MIME format. ------=_NextPart_000_0008_01BE92FB.345B5540 Content-Type: text/plain; charset="big5" Content-Transfer-Encoding: quoted-printable Hello ! Where can find 8255 programable I/O interface verilog core. thank you very much Email address is Willy_tsai@Smartchip.com.tw Thanks in advance. Any leads greatly appreciated. Home Web: http://www.cgw.163.net =20 */-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/ ------=_NextPart_000_0008_01BE92FB.345B5540 Content-Type: text/html; charset="big5" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD W3 HTML//EN"> <HTML> <HEAD> <META content=3Dtext/html;charset=3Dbig5 http-equiv=3DContent-Type> <META content=3D'"MSHTML 4.72.3110.7"' name=3DGENERATOR> </HEAD> <BODY bgColor=3D#ffffff> <DIV><FONT color=3D#000000 size=3D2>Hello !</FONT></DIV> <DIV><FONT color=3D#000000 size=3D2></FONT> </DIV> <DIV><FONT color=3D#000000 size=3D2>Where can find 8255 programable I/O = interface=20 verilog core.</FONT></DIV> <DIV><FONT color=3D#000000 size=3D2></FONT> </DIV> <DIV><FONT color=3D#000000 size=3D2>thank you very much</FONT></DIV> <DIV> </DIV> <DIV><FONT color=3D#000000 size=3D2>Email address is <A=20 href=3D"mailto:Willy_tsai@Smartchip.com.tw">Willy_tsai@Smartchip.com.tw</= A></FONT></DIV> <DIV><FONT color=3D#000000 size=3D2></FONT> </DIV> <DIV><FONT color=3D#000000 size=3D2>Thanks in advance.</FONT></DIV> <DIV><FONT color=3D#000000 size=3D2></FONT> </DIV> <DIV><FONT color=3D#000000 size=3D2>Any leads greatly = appreciated.</FONT></DIV> <DIV><FONT color=3D#000000 size=3D2></FONT> </DIV> <DIV><FONT color=3D#000000 size=3D2>Home Web: <A=20 href=3D"http://www.cgw.163.net">http://www.cgw.163.net</A> &nb= sp; =20 <BR>*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-= \*/</FONT></DIV></BODY></HTML> ------=_NextPart_000_0008_01BE92FB.345B5540--Article: 16051
I have had this idea too. I never actually had to do it though. But I don't see why you couldn't make a ring oscillator out of a bunch of inverters and then servo its length with a big mux. Your servo will need a bandwidth faster than what ever would make the ring delay change, Temp changes would be large and slow. Voltage changes could be fast, but you could control that, mostly with good bypassing. Xilinx is even specifying min delays, now so you can get an idea of the range of ring oscillator delay lengths you'll need. Please post your results. I think it will work. "Peter..."@t-online.de (Peter Lang) wrote: >Hi all, >i heard about the frequence doubling in the new virtix family. >But what I need if not twice the frequnce but nearly 20 times the input >clock frequence. >I now have a crazy idea: >Maybe it is possible to implement a Delayline with normal >CLBs and routing. By changing the numbers of CLB a signal is >travelling through an feed it back inverted it must be possible >to adjust the frequence like with a DCO. > >Has anybody experience with thing like that >please let me know >thanks peter > > Dave Decker Please use only one 'h' in mush. I'm trying to reduce the spam. "Animals . . . are not brethren they are not underlings; they are other nations, caught with ourselves in the net of life and time, fellow prisoners of the splendor and travail of the earth." Henry Beston - The Outermost HouseArticle: 16052
Hi, Does anyone know the metastability parameters for Xilinx Spartan and SpartanXL parts (with various speed grades)? Xilinx's web site only seems to have the numbers for the XC4005E-3 XC4005-6 XC3142A-09 XC3042-70 XC5200-5 parts, and for the XC7000 and XC9500 families. I'm designing a synchroniser... Please, I don't want anyone to reply with synchroniser designs or the theory of metastability. I just want the numbers (or URLs, etc). Thanks, Allan.Article: 16053
On Thu, 29 Apr 1999 09:59:39 +0200, "C. Mueller" <evil.moshi@gmx.de> wrote: >Hi, >I am looking for a interrupt controller >written in VHDL. > >regards > > Yeah, me too! Seriously, you didn't say which one you wanted. I suppose you want the 8259? I have contemplated designing an 8259 in an FPGA, but haven't actually done it yet. My preliminary analysis shows that there are some operational modes and features of the 8259 that are not usable in a PC architecture. This implies that the design could be greatly simplified by implementing only the necessary modes and features, and ignoring the rest (such as 8051 style interrupt acknowledging). The same is true of the 8237 DMA controller and the 8254 timer. So, has anyone done this before? If you have, are you willing to share it with the rest of us ;-) ? If you don't have to have a 8259 compatible, you can design your own interrupt controller as simple or as complex as you want it. I have designed "mini-controllers" which are used for sharing one 8259 interrupt among several requesters. It is a simple state machine that drives an 8259 IR input _/~ when one or more of the requests is active. When the ISR code executes, it sends an end-of-interrupt (EOI) to the 8259, then it sends an EOI to my "mini", which causes the output to go low. If any other requests are pending, the "mini" drives the IR input _/~ again after one clock cycle. It is kind of like cascaded 8259's but without the extra 8259. It works. Best regards, Ivan Baggett BagotronixArticle: 16054
can some one help to find the prices for Xilinx Virtex XV300 and XV800.? I can't find it in Xilinx web site! -- _____________ email: alsolaim@ieee.org ____________________________Article: 16055
Contact your local Distributor Avnet, Insight, or Nu Horizons or your local Xilinx Rep office Ahmad Alsolaim wrote: > > can some one help to find the prices for Xilinx Virtex XV300 and XV800.? I > can't find it in Xilinx web site! > > -- > _____________ > email: alsolaim@ieee.org > ____________________________Article: 16056
Hi I have seen where the length count is incorrect and so the device will not go high until the internal length counter wraps around (a 24 bit counter). To verify this either continue to send TCLK clocks 2^24 or add some additional length in the header. You can verify the device is trying to configure by looking at the Dout pin. You should see the header one clock delayed then it will stop until the device configuration memory is full ... then if you toggle TDI while sending extra TCLK clocks the device will pass the TDI one clock delayed. The only remianing thing is for the internal length counter to equal the length count in the bit stream. By continuously sending TCLK clocks the internal counter will wrap an equal. It seems that either the length count in the generated bit stream is too short or the internal counter is getting advanced preamaturely. I don't know which it is yet. You should be able to advance the length count in the header and eventualy get it to work. Best Regards Terry sgopalakrishnan@attotech.com wrote: > > Hi all, > > I have been trying to configure a XILINX 4036XL FPGA part on our board through > JTAG. I have written my own C code for doing this and ..I am having problems. > The "DONE" signal does not go high. I know there is a JTAG Programmer software > available from XILINX for doing this and I compared my test with theirs on the > analyzer ( looked at the signals). Everything looks the same except of course > when I run my code the DONE does not go high.I don't know what I am missing. > I was wondering if someone has written code for doing same and has been lucky > and also if they would share their code. I would really appreciate it. > > Thanks > Sucharita > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 16057
Hi If your Init pin is low then there is something fundamentaly wrong. Either the device is not ready for configuration or there was a data error while trying to configure and the device aborted. Try reviewing the configuration trouble shooter at the following location http://www.xilinx.com/support/techsup/journals/config/cps.htm Best Regards Terry wannarat wrote: > > hi > I have BIG problems. > I can't config FPGA XC4085XLA , Have Error about Init pin and Done pin. > Now it shows " Device can't config , Done is not high" > I check init pin but have "low signal" / > What's wrong with My FPGA.??? > Now i try to download FPGA from EPROM. > REgard > Please suggest me at > ksuwanna@kmitl.ac.th > ICQ - 7874501 > Immediately!!!!Article: 16058
The XC4000 and XC4000E devices are pin compatable Andy Peters wrote: > > Tyrone Thompson wrote in message <7g79ls$llu$1@dewey.udel.edu>... > >Help! > > > >I am looking for some help from someone who has made the transitions from > >XACT 5.2 to 6.0 to Foundation. I have been trying unsuccessfully to > >produce a working binary file for a XC4008 (no extensions!) chip using the > >Foundation 1.3 (Metamor) front end and XACT 6.0.2 routing under Win95. > > Ooops. You're SOL: the Foundation tools don't support your chip. You have > to use a 4008E or later device. I'm not sure about pin compatibilty. > > -- adny > ------------------------------------------ > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters@noao.edu > > "Space, reconnaissance, weather, communications - you name it. We use space > a lot today." > -- Vice President Dan QuayleArticle: 16059
Hi ! Student is required help. For want of information and time. Needed source code on VHDL language or Verilog for scholastic whole following devices: 1. Ethernet controller; 2. T1/E1 Framer; 3. Synchronous controller for instance one channel 85C30 Thanks. AlekseyArticle: 16060
I keep getting an error when Xact tries to map in the larger 4013 and above fpga's. It states that the lock map feature is no available. I am using the M1 ver.1.4 software schematic capture. When I use a smaller device such has the 4010, Xact runs fine. My design is using simple logic gates. If anyone else had this problem, please let me know how to correct it. Thanks, Evan evansamuel@earthlink.netArticle: 16061
XC6200-based board wanted (used/new). Pls email offer to me, Lawrence Chai <chaimj@singnet.com.sg>Article: 16062
David Decker wrote: > > I have had this idea too. I never actually had to do it though. But I > don't see why you couldn't make a ring oscillator out of a bunch of > inverters and then servo its length with a big mux. Your servo will > need a bandwidth faster than what ever would make the ring delay > change, Temp changes would be large and slow. Voltage changes could be > fast, but you could control that, mostly with good bypassing. I think you will find that the edge-locking device made by Kraias behaves in this way. Some high-end video capture cards use it for locking the phase of a local crystal oscillator (for the pixel clock) on to the line sync timing, line by line, so you don't suffer the jitter problems associated with a phase-locked loop. They use it as a delay-lock device, not as a digitally-variable oscillator. Sadly, I first got data on this device many years ago and I have lost it. But I think I have the manufacturer's name right. One potential problem with doing this in an FPGA is that the routing delays from the taps on your delay line to the mux inputs, and the delays through the mux itself, might be comparable with the delay line inter-tap delays. This could result in a non-monotonic relationship between tap number and delay, which would seriously screw up the servo. The trick would be to make each stage have a delay at least as long as the longest possible routing delays. Still, it's an interesting idea and well worth trying. Jonathan BromleyArticle: 16063
You can try... CAST at http://www.cast-inc.com/cores/index.htm Macrocad at http://www.macrocad.com/products/prodindex.html For other core providers check out VSI Alliance at http://www.vsi.org/Article: 16064
Jonathan Bromley wrote: > One potential problem with doing this in an FPGA is that the routing > delays from the taps on your delay line to the mux inputs, and the > delays through the mux itself, might be comparable with the delay line > inter-tap delays. This could result in a non-monotonic relationship > between tap number and delay, which would seriously screw up the servo. > The trick would be to make each stage have a delay at least as long as > the longest possible routing delays. > > Still, it's an interesting idea and well worth trying. > This is what I was trying to say a few days ago when this first came up. I looked at doing this a whileback using the carry chains for the delay elements. The problem I ran into was that it was extremely difficult to match the delays for each of the taps thru the feedback mux, so the delay selection was not monotonic. If you can accept a large granularity in the delay steps, (so that the delay differences through the mux are swamped by the incremental delays in the delay chain), then you should be able to do it. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16065
The 10K EAB is not a dual port RAM. You can make a psuedo dual port synchronous ram out of it if you can provide a 2x clock. Each EAB will give you 2048x1, so you will have to cascade 5 EABs. Depending on your speed requirements, you may find that you have to pipeline to get the desired clock rate, in which case you may have an unacceptable latency. The 10KE devices have a dual port capability, so they would be more appropriate. (they also give twice twice the bits per EAB). You might also look at Xilinx Virtex, as they have fast dual port 4K blocks with async capability. Eli Keren wrote: > Hello ! > > I think it's possible by cascading few RAM's but you must calculate the > number of memory cell inside 10K20. > Do you real DPR with to separate clocks write/read ? then use 10K50E > > vertige69@hotmail.com wrote: > > > Hello! > > > > I am a beginner in the design of FPGA, and I want to know whether it is > > possible to create a 9000*1bit Dual-Port Ram on an EPF10K20 in internal > > (with the EABs).... or must I add an external one??? > > > > Thanks for your response, > > Best regards, > > Eric Trinh, an humble student. > > etrinh@ifhamy.insa-lyon.fr > > etrinh@cri.ens-lyon.fr > > trinh@rfv.insa-lyon.fr -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16066
Sounds like you are using the student version, which I think is constrained to smaller designs. somebody wrote: > I keep getting an error when Xact tries to map in the larger 4013 and above > fpga's. It states that the lock map feature is no available. I am using > the M1 ver.1.4 software schematic capture. When I use a smaller device such > has the 4010, Xact runs fine. My design is using simple logic gates. If > anyone else had this problem, please let me know how to correct it. > > Thanks, > Evan > evansamuel@earthlink.net -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16067
Good luck. People pay good money for these cores (many thousands of dollars US). I seriously doubt you'll find someone willing to provide it at no cost. Aleksey Starikov wrote: > Hi ! > > Student is required help. > For want of information and time. > Needed source code on VHDL language or Verilog for scholastic whole > following devices: > > 1. Ethernet controller; > 2. T1/E1 Framer; > 3. Synchronous controller for instance one channel 85C30 > > Thanks. > > Aleksey -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16068
The 8259 controller really isn't very complex. You should be able to roll your own with relatively little effort. Alternatively, I believe Memec has an 8259 Core available, although the price may be too high. Ivan Baggett (Ivan Baggett) wrote: > On Thu, 29 Apr 1999 09:59:39 +0200, "C. Mueller" <evil.moshi@gmx.de> > wrote: > > >Hi, > >I am looking for a interrupt controller > >written in VHDL. > > > >regards > > > > > > Yeah, me too! > > Seriously, you didn't say which one you wanted. I suppose you want > the 8259? > > I have contemplated designing an 8259 in an FPGA, but haven't actually > done it yet. My preliminary analysis shows that there are some > operational modes and features of the 8259 that are not usable in a PC > architecture. This implies that the design could be greatly > simplified by implementing only the necessary modes and features, and > ignoring the rest (such as 8051 style interrupt acknowledging). The > same is true of the 8237 DMA controller and the 8254 timer. > > So, has anyone done this before? If you have, are you willing to > share it with the rest of us ;-) ? > > If you don't have to have a 8259 compatible, you can design your own > interrupt controller as simple or as complex as you want it. I have > designed "mini-controllers" which are used for sharing one 8259 > interrupt among several requesters. It is a simple state machine that > drives an 8259 IR input _/~ when one or more of the requests is > active. When the ISR code executes, it sends an end-of-interrupt > (EOI) to the 8259, then it sends an EOI to my "mini", which causes the > output to go low. If any other requests are pending, the "mini" > drives the IR input _/~ again after one clock cycle. It is kind of > like cascaded 8259's but without the extra 8259. It works. > > Best regards, > Ivan Baggett > Bagotronix -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16069
--------------3919CD4F080C3C8CDD00B5C3 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit You can try memec, I think they may have an 8255 core for xilinx, although I think it is probably schematics. The 8255 is not very complicated. You could probably sit down and write one yourself in a day or two. You'll have to find one of the old PC texts that describe the detailed architecture of the 8255. Willy_Tsai wrote: > Hello ! Where can find 8255 programable I/O interface verilog > core. thank you very much Email address is > Willy_tsai@Smartchip.com.tw Thanks in advance. Any leads greatly > appreciated. Home Web: http://www.cgw.163.net > > /-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka --------------3919CD4F080C3C8CDD00B5C3 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <HTML> <BODY BGCOLOR="#FFFFFF"> You can try memec, I think they may have an 8255 core for xilinx, although I think it is probably schematics. The 8255 is not very complicated. You could probably sit down and write one yourself in a day or two. You'll have to find one of the old PC texts that describe the detailed architecture of the 8255. <P>Willy_Tsai wrote: <BLOCKQUOTE TYPE=CITE> <FONT COLOR="#000000"><FONT SIZE=-1>Hello !</FONT></FONT> <FONT COLOR="#000000"><FONT SIZE=-1>Where can find 8255 programable I/O interface verilog core.</FONT></FONT> <FONT COLOR="#000000"><FONT SIZE=-1>thank you very much</FONT></FONT> <FONT COLOR="#000000"><FONT SIZE=-1>Email address is <A HREF="mailto:Willy_tsai@Smartchip.com.tw">Willy_tsai@Smartchip.com.tw</A></FONT></FONT> <FONT COLOR="#000000"><FONT SIZE=-1>Thanks in advance.</FONT></FONT> <FONT COLOR="#000000"><FONT SIZE=-1>Any leads greatly appreciated.</FONT></FONT> <FONT COLOR="#000000"><FONT SIZE=-1>Home Web: <A HREF="http://www.cgw.163.net">http://www.cgw.163.net</A></FONT></FONT> <BR><FONT COLOR="#000000"><FONT SIZE=-1>*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/*/-\*/</FONT></FONT></BLOCKQUOTE> <P>-- <BR>-Ray Andraka, P.E. <BR>President, the Andraka Consulting Group, Inc. <BR>401/884-7930 Fax 401/884-7950 <BR>email randraka@ids.net <BR><A HREF="http://users.ids.net/~randraka">http://users.ids.net/~randraka</A> <BR> </BODY> </HTML> --------------3919CD4F080C3C8CDD00B5C3--Article: 16070
NuHorizons: http://www.nuhorizons.com/ Avnet: http://www.em.avnet.com/cgi-bin/sc.cgi Avent had sample pricing for the XCV300 ranging from $344 to $562 for low volumes, depending on the package and speed grade. NuHorizons had "call". I didn't see anything for the XCV800 yet. It must just be sampling. I'd also recommend contacting your local Xilinx sales person. The prices that you find on the web are usually only for small quantities for immediate delivery. If you're planning on a larger-volume project, especially for production down the road, it's best to get more realistic pricing from your sales person. ----------------------------------------------------------- Steven K. Knapp OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally" E-mail: sknapp@optimagic.com Web: http://www.optimagic.com ----------------------------------------------------------- Ahmad Alsolaim wrote in message ... >can some one help to find the prices for Xilinx Virtex XV300 and XV800.? I >can't find it in Xilinx web site! > >-- >_____________ >email: alsolaim@ieee.org >____________________________ > > > >Article: 16071
I've developed a digital system with xilinx xc4005 but there aren't some function generators. The biggest component supported by my development system is XC4013. i need to fit my design into XC4020 or 4025, but my system does not support them. How can i do? Thanks. ALXArticle: 16072
How about stringing the delay CLBs along a horizontal longline and using TBUFs for the delay mux? Should be predictably monotonic. Don't seem to see horizontal longline switching characteristics anymore in recent Xilinx data sheets, so I don't what kind of bandwidth you would get. Tracking between identical delay lines on different rows should be pretty good, so it might be possible to get reasonably stable relative delays with granularity of a CLB delay plus a short local interconnect. regards, tom Jonathan Bromley wrote: > > > One potential problem with doing this in an FPGA is that the routing > delays from the taps on your delay line to the mux inputs, and the > delays through the mux itself, might be comparable with the delay line > inter-tap delays. This could result in a non-monotonic relationship > between tap number and delay, which would seriously screw up the servo. -- Tom Burgess Digital Engineer National Research Council of Canada Herzberg Institute of Astrophysics Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3 Email: tom.burgess@hia.nrc.ca Office: (250) 490-4360 Switch Board: (250) 493-2277 Fax: (250) 493-7767Article: 16073
Hi! I am planning to use an EPC2 for ISP programming. Has somebody experience on how to configure and set up the circuit such that the EPC2 can be configured using the Bitblaster? I want to configure a FLEX10K50E in circuit with it. Thanks a lot, Henning TrispelArticle: 16074
Unfortunately, the chip is soldered onto the board I am using. I realize the latest foundations do not support the XC4008, but I was assuming that the earlier versions, which included the libraries might work. Am I wrong here? Also, after a little digging I noticed that the defaults for configuring the chip (i.e. the settings for MAKEBITS) are different between XACT 5.2 and 6.0. For instance the default for the DONE line in 5.2 is for it to have an internal pullup, but not for 6.0. I'm thinking that this may be a more likely problem, especially since the chip doesn't seem to doing the same thing every time I load it. Any suggestions on the configuration settings? I know I need a pullup for the DONE line internally, but I have no idea about the MODE lines or the timing for the release of GSR, etc. I am programming the chip in Master serial mode if that is helpful. Thanks again, Tyrone -- -------------- thompson@eecis.udel.edu University of Delaware Tyrone Thompson EE Graduate Student
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