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On 28 Apr 1999 08:26:35 -0700, mcgett@feynman.xsj.xilinx.com (Ed Mcgettigan) wrote: >In article <3726BD1D.519D18DF@ago.fr>, >Le mer Michel <michel.lemer@ago.fr> wrote: >> >>You have 4 DLLs inside a virtex, so you can have your input frequency x2 >>x2 x2 x2 = 16. >>If it is enough, you can see the XAPP132 (xilinx web site). >> > >It is not possible to multiply the clock frequency by more than >4X within Virtex using two internal CLKDLLs. Creating a 8X or 16X >would violate either the minimum or maximum clock input frequency >for the CLKDLL. problem: when cascading two DLLs to give a x4 multiply, the jitter spec on the input to the 2nd DLL is violated...... any comment? thanks evanArticle: 16026
In article <3726F3A7.79A5DDD5@kmitl.ac.th>, wannarat <ksuwanna@kmitl.ac.th> wrote: > hi > I have BIG problems. >I can't config FPGA XC4085XLA , Have Error about Init pin and Done pin. >Now it shows " Device can't config , Done is not high" >I check init pin but have "low signal" / >What's wrong with My FPGA.??? >Now i try to download FPGA from EPROM. >REgard Are you compiling for the correct part? This usually occurs when you are trying to load a bitfile compiled for a different part. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 16027
In article <37276cea.4477006@news.dial.pipex.com>, <ems@riverside-machines.com.NOSPAM> wrote: > >problem: when cascading two DLLs to give a x4 multiply, the jitter >spec on the input to the 2nd DLL is violated...... > >any comment? > This is a common misperception of the clock input jitter item in the DLL Timing Parameters table in XAPP132. The Tijit 50ps value should not have been listed in the table with the other min/max specs. As Note 3 states this is only a testing parameter for the Tojit 200ps max jitter value. This of course must be the case or we not have specified the Clock Input Frequency Tolerance (Tiftol) as 25000 PPM (+/-2.5%). This item, along with the BUFGIO typo, has been updated in the next revision of this application note which will be available shortly. EdArticle: 16028
My application requires data to be converted to a 32 bit floating point format (IEEE) in the FPGA before being serially transferred into a DSP for further processing. I'm not too sure of what is involved in implementing this kind of a block in a FPGA...the size and complexity. I would appreciate any insights on this. Are there any 'cores' available for this from vendors? I plan to use a Xilinx Virtex part for the application. Thanks Bhaskar -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 16029
Hi everyone, Can Synplicity and Leonardo automatically optimize large binary counters to be fast? Or do I have to recode them? Any help will be highly appreciated. Thanks MicheleArticle: 16030
Article: 16031
I normally cascade large counters in the code so as to ensure an efficient/fast synthesis. They're may be another way, but this was I am usually safe. PJ In article <7g83r2$ion@freenet-news.carleton.ca>, cr795@FreeNet.Carleton.CA (C. Michele Rogers) wrote: > > Hi everyone, > > Can Synplicity and Leonardo automatically optimize large binary counters to be > fast? Or do I have to recode them? > > Any help will be highly appreciated. > > Thanks > Michele > -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 16032
I'm assuming your input data is fixed point? If it is, you need to shift the data left until the two msb's are different. The exponent is derived from the number of shifts performed (just a bit of simple arithmetic or a LUT to apply the bias (+127) and any fixed implied exponent in the input...also this bit of arithmetic might have to reverse the shift count depending on the shifter implementation). The IEEE format has a sign bit at the front and the mantissa is unsigned with a hidden one. After shifting, the MSB can be used directly as the sign. Take the absolute value of the output from the shifter, drop the top two bits (the sign, which is now zero and the lsb which should always be 1). The next 23 most significant bits become the 23 LSBs (the mantissa without the hidden 1 bit) of the floating point output. This should occupy approximately 50 clbs in Virtex, and completely pipelined should be no more than 6 clocks at around 100MHz for a 32 bit fixed point input. I've done several floating point converters in both xilinx and altera. I currently do not have a core for sale that will do this, but could turn a custom design in a short time. bhaskart@my-dejanews.com wrote: > My application requires data to be converted to a 32 bit floating point format > (IEEE) in the FPGA before being serially transferred into a DSP for further > processing. > I'm not too sure of what is involved in implementing this kind of a block > in a FPGA...the size and complexity. I would appreciate any insights on this. > > Are there any 'cores' available for this from vendors? I plan to use a Xilinx > Virtex part for the application. > > Thanks > Bhaskar > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16033
This is a multi-part message in MIME format. --------------69AED717C418426FD7C48EED Content-Type: multipart/alternative; boundary="------------7BDB6BF35C94181AE999B8D0" --------------7BDB6BF35C94181AE999B8D0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Have you tried the Configuration Problem Solver on our web site? You can find it at: http://support.xilinx.com/support/techsup/journals/config/cps.htm More information can be found in the FPGA Configuration Expert Journal as well: http://support.xilinx.com/support/techsup/journals/config/index.htm Hopefully this information will help you detect your problem. -- Brian wannarat wrote: > hi > I have BIG problems. > I can't config FPGA XC4085XLA , Have Error about Init pin and Done pin. > Now it shows " Device can't config , Done is not high" > I check init pin but have "low signal" / > What's wrong with My FPGA.??? > Now i try to download FPGA from EPROM. > REgard > Please suggest me at > ksuwanna@kmitl.ac.th > ICQ - 7874501 > Immediately!!!! -- ------------------------------------------------------------------- / 7\'7 Brian Philofsky (brian.philofsky@xilinx.com) \ \ ` Xilinx Applications Engineer hotline@xilinx.com / / 2100 Logic Drive 1-800-255-7778 \_\/.\ San Jose, California 95124-3450 1-408-879-5199 ------------------------------------------------------------------- --------------7BDB6BF35C94181AE999B8D0 Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> <p>Have you tried the Configuration Problem Solver on our web site? You can find it at: <A HREF="http://support.xilinx.com/support/techsup/journals/config/cps.htm">http://support.xilinx.com/support/techsup/journals/config/cps.htm</A> <p>More information can be found in the FPGA Configuration Expert Journal as well: <br><A HREF="http://support.xilinx.com/support/techsup/journals/config/index.htm">http://support.xilinx.com/support/techsup/journals/config/index.htm</A> <p>Hopefully this information will help you detect your problem. <br> <p>-- Brian <br> <p>wannarat wrote: <blockquote TYPE=CITE> hi <br> I have BIG problems. <br>I can't config FPGA XC4085XLA , Have Error about Init pin and Done pin. <br>Now it shows " Device can't config , Done is not high" <br>I check init pin but have "low signal" / <br>What's wrong with My FPGA.??? <br>Now i try to download FPGA from EPROM. <br>REgard <br>Please suggest me at <br>ksuwanna@kmitl.ac.th <br>ICQ - 7874501 <br>Immediately!!!!</blockquote> <pre>-- ------------------------------------------------------------------- / 7\'7 Brian Philofsky (brian.philofsky@xilinx.com) \ \ ` Xilinx Applications Engineer hotline@xilinx.com / / 2100 Logic Drive 1-800-255-7778 \_\/.\ San Jose, California 95124-3450 1-408-879-5199 -------------------------------------------------------------------</pre> </html> --------------7BDB6BF35C94181AE999B8D0-- --------------69AED717C418426FD7C48EED Content-Type: text/x-vcard; charset=us-ascii; name="brianp.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Brian Philofsky Content-Disposition: attachment; filename="brianp.vcf" begin:vcard n:Philofsky;Brian tel;fax:(408) 879-4442 tel;work:1-800-255-7778 x-mozilla-html:TRUE org:<br><img src="http://www.xilinx.com/images/xlogoc.gif" alt="Xilinx"><BR><BR>;Xilinx Design Center version:2.1 email;internet:brianp@xilinx.com title:Application Engineer adr;quoted-printable:;;2100 Logic Drive=0D=0ADept. 2510;San Jose;CA;95124-3450;USA x-mozilla-cpt:;-12504 fn:Brian Philofsky end:vcard --------------69AED717C418426FD7C48EED--Article: 16034
ems@riverside-machines.com.NOSPAM wrote: >On Tue, 27 Apr 1999 00:52:42 GMT, Bob Sefton <rsefton@home.com> wrote: > ><snip> >> I agree that it takes a lot >>of work to completely spec some designs, but you have to do that >>anyway. If a timing sim reveals a broken path the only way to fix >>it is to constrain the path correctly. > >agreed. i'm not meaning to imply that a timing sim is better than a >static analysis, or can replace it; only that, if you have a >complicated (or any) set of constraints, then the only way to check >them is with a timing sim. > >evan > Experts agree that Timing Simulation is never necessary or useful in any way if you: 1) Do synchronous design 2) Use functional (unit delay) simulation to prove the function is correct 3) Achieve 100% coverage of all nets with timing specifications (not easy, agreed) 4) Run Static timing analysis to prove your timing specs were met. The above procedure proves that 100% of your nets meet timing. Timing simulation shows the careful observer that those nets that were exercised, did meet timing under the specific conditions covered by the test vectors. Dave Decker Diablo Research Co. LLC diabloresearch.com Please use only one 'h' in mush. I'm trying to reduce the spam. "Animals . . . are not brethren they are not underlings; they are other nations, caught with ourselves in the net of life and time, fellow prisoners of the splendor and travail of the earth." Henry Beston - The Outermost HouseArticle: 16035
>pasquale wrote in message <371A1D1F.2E618F3C@zoran.com>...
>>
>>My altera flex10k200e design takes about 8 hours to place and route.
>>I needed to change one gate in my design (and inverter to a buffer)
>>and Altera tech support told me I had to start the place and route
>>(i.e. "recompile") from scratch. They said that there was no way
>>to make a minor change like this and that there was no way
>>to directly edit the LUT equations by hand.
>>They say that this capbility may be available by year end.
>>
>>Is this true?
On Sun, 18 Apr 1999 13:45:34 -0500, "Tom Meagher" <tomm@icshou.com>
wrote:
>Yes, it is true. Get used to it.
>
>There is no way to edit any post P&R logic equation using the Altera MAX
>Plus + II software ("MP2"). If you want to change an inverter to a buffer,
>you have to start over.
Five years ago, I was using the FLEX 8000 series, and I was able to
make small, specific changes like you are wanting. I haven't really
used MP2 since then -- so I don't know if my procedures would still
work, or if they work on other device families. This came about
because I was using the largest available device, had 83% LE
utilization, and boards in customer hands, when I needed to fix a bug.
The normal flow was verilog to synopsys via edif to maxplus2.
Patching the verilog or patching the edif resulted in maxplus2 being
unable to fit the design.
I wrote a program in Perl to convert the .rpt file to a .tdf file;
with everything given specific location assignments. Most of the
EQUATION section consisted of valid AHDL constructs; and the row and
column location of each LCELL was given in either the signal name, the
comment, or in the .fit file.
I can't share the code, but the rough outline was:
read basename.fit to get design and device sections
put in basename.tdes
copy sans pin assignments to create subdesign port list
put in basename.tsbp
read basename.rpt to get a list of _LCs that feed CASCADE
read basename.rpt to get equation section
put in basename.teqn
find all lvalues and declare as nodes
put in basename.tnod
find lcell locations for the lcell nodes for device
assignment
put in basename.tass
cat the pieces together
make needed changes
One example of the changes that I made (two LEs):
% diff orig.tdf edit.tdf
3699c3699,3700
< # !_LC8_A6 & !bit_19_;
---
> # !_LC8_A6 & !bit_19_
> # _LC3_B20;
7892c7893
< _LC6_F8 = DFF( fifo_rdy, GLOBAL( CLK), VCC, VCC);
---
> _LC6_F8 = LCELL( fifo_rdy);
Your mileage may vary
jeff
Article: 16036Hi, I am looking for a interrupt controller written in VHDL. regardsArticle: 16037
Hello ! From my experience in Xilinx or other FPGA i suggest you not try to do delays inside FPGA because they will not be predictable on every compilation(they will change). Please look for other idea. Peter Lang wrote: > Hi all, > i heard about the frequence doubling in the new virtix family. > But what I need if not twice the frequnce but nearly 20 times the input > clock frequence. > I now have a crazy idea: > Maybe it is possible to implement a Delayline with normal > CLBs and routing. By changing the numbers of CLB a signal is > travelling through an feed it back inverted it must be possible > to adjust the frequence like with a DCO. > > Has anybody experience with thing like that > please let me know > thanks peterArticle: 16038
Hello ! From my experience in Xilinx or other FPGA i suggest you not try to do delays inside FPGA because they will not be predictable on every compilation(they will change). Please look for other idea. Peter Lang wrote: > Hi all, > i heard about the frequence doubling in the new virtix family. > But what I need if not twice the frequnce but nearly 20 times the input > clock frequence. > I now have a crazy idea: > Maybe it is possible to implement a Delayline with normal > CLBs and routing. By changing the numbers of CLB a signal is > travelling through an feed it back inverted it must be possible > to adjust the frequence like with a DCO. > > Has anybody experience with thing like that > please let me know > thanks peterArticle: 16039
Hello ! I think it's possible by cascading few RAM's but you must calculate the number of memory cell inside 10K20. Do you real DPR with to separate clocks write/read ? then use 10K50E vertige69@hotmail.com wrote: > Hello! > > I am a beginner in the design of FPGA, and I want to know whether it is > possible to create a 9000*1bit Dual-Port Ram on an EPF10K20 in internal > (with the EABs).... or must I add an external one??? > > Thanks for your response, > Best regards, > Eric Trinh, an humble student. > etrinh@ifhamy.insa-lyon.fr > etrinh@cri.ens-lyon.fr > trinh@rfv.insa-lyon.frArticle: 16040
Hi thereArticle: 16041
Oops sorry. Blush. Martin Duffy wrote in message <7g9ptd$do5$1@news6.svr.pol.co.uk>... >Hi there > >Article: 16042
Here's one to consider: Field-Programmable Gate Arrays : Reconfigurable Logic for Rapid Prototyping and Implementation of Digital Systems http://www.amazon.com/exec/obidos/ASIN/0471556653/iversonsoftwarecA On Wed, 31 Mar 1999 23:19:31 -0500, Mandeep Singh <msingh@ececs.uc.edu> wrote: >Could someone please recommend a website or a book for a general >introduction to Reconfigurable Computing? > >Thanks > >Paul Kind Regards, Jeff Iverson -- Iverson Software Co. 507-235-9209 - voice 418 N. State St. #7 507-235-8835 - fax Fairmont MN 56001 http://www.iversonsoftware.com/Article: 16043
phil_jackson@my-dejanews.com writes: > I normally cascade large counters in the code so as to ensure an > efficient/fast synthesis. They're may be another way, but this was I am > usually safe. What is the target? Xilinx produced a couple of application notes for designing fast counters by making best use of the carry logic. Other manufacturers probably produce similar app notes. -- ------------------------------------------------------------------------------- David Miller Tel: +44 (0)131 343 4963 Development Engineer Fax: +44 (0)131 343 4091 Marconi Avionics, RCS Division Email : david.miller@gecm.com Crewe Toll, Edinburgh EH5 2XS -------------------------------------------------------------------------------Article: 16044
Kolaga Xiuhtecuhtli wrote: > > What is a good eval board for a hobbyist? I'm talking > about the daydreamer sort of electronics fan. The kind > who wants to realize a CPU out of a FPGA. But actually > something easy on the wallet and ego... You can find a free very simple design with PCB to make your own for Xilinx XC52xx in PLCC84, in the url of the signature. -- 73's de Luis mail: melus@esi.us.es Ampr: eb7gwl.ampr.org (sorry shut down) AX25: (sorry shut down) http://www.esi.us.es/~melus/ <- Homebrewed Hardware Projects with PCBsArticle: 16045
Hi all, I have been trying to configure a XILINX 4036XL FPGA part on our board through JTAG. I have written my own C code for doing this and ..I am having problems. The "DONE" signal does not go high. I know there is a JTAG Programmer software available from XILINX for doing this and I compared my test with theirs on the analyzer ( looked at the signals). Everything looks the same except of course when I run my code the DONE does not go high.I don't know what I am missing. I was wondering if someone has written code for doing same and has been lucky and also if they would share their code. I would really appreciate it. Thanks Sucharita -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 16046
Willy_Tsai wrote in message <7g6ce4$9e5@netnews.hinet.net>...
"I am develope a project. It need Z80 and Z80-CTC and Z80-PIO."
Uh, pick up a digikey, mouser, or JDR catalog and order the chips?
Should be pretty cheap.
--
------------------------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters@noao.edu
Space, reconnaissance, weather, communications - you name it. We use
space a lot today."
-- Vice President Dan Quayle
Article: 16047Tyrone Thompson wrote in message <7g79ls$llu$1@dewey.udel.edu>... >Help! > >I am looking for some help from someone who has made the transitions from >XACT 5.2 to 6.0 to Foundation. I have been trying unsuccessfully to >produce a working binary file for a XC4008 (no extensions!) chip using the >Foundation 1.3 (Metamor) front end and XACT 6.0.2 routing under Win95. Ooops. You're SOL: the Foundation tools don't support your chip. You have to use a 4008E or later device. I'm not sure about pin compatibilty. -- adny ------------------------------------------ Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters@noao.edu "Space, reconnaissance, weather, communications - you name it. We use space a lot today." -- Vice President Dan QuayleArticle: 16048
Hello,
I am trying to write a process that give me and internal clk. My
idea is that the external clock drives this process, and the processor
gives a '1' every time the process counts to a certain number (here it
is 3000). However, the compiler gives me a "ignored unnecessary INPUT
pin 'clk_0' when this is the signal in the sensitivity list and the
entire process waits for a rising edge! What am I missing??
I am using the latest Altera compiler.
....
signal pulse_int : std_logic;
begin
pulse_chk: process (clk_0)
variable int_cnt : natural := 0;
begin
if rising_edge(clk_0) then
int_cnt := int_cnt + 1;
if int_cnt < 3000 then
pulse_int <= '0';
else
pulse_int <= '1';
int_cnt := 0;
end if;
end if;
end process pulse_chk;
...
This should be pretty standard. Any ideas?
Garrick Kremesec
University of Illinois
gkremese@ews.uiuc.edu
Article: 16049
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / "One Sheep Farmer's Impressions Of SNUG'99"
_] [_ (plus what 23 other engineers saw there, too.)
by John Cooley
Moderator Of The E-mail Synopsys Users Group (ESNUG)
The 9th Annual Synopsys (& EPIC) Users Group Meeting (SNUG'99)
at the Doubletree Inn, San Jose, CA, March 29th - 31st, 1999
First Impressions
-----------------
"One thing I liked better about this conference than I did the previous
time I went was that since Synopsys has a greater range of products,
the presentations cover a greater range of topics and seem to cover
almost every aspect of ASIC design."
- Brad Sonksen of Vixel Corp.
The Numbers
-----------
Because EDA salesdroids and marketeers are known to distort/exaggerate
what other customers are doing/saying about a particular tool they're
trying to get you to buy, over the years I've found it necessary to get
the hard data myself -- whether it be the ratio of Verilog users to VHDL
users or how many customers attended a specific talk. This year, the
numbers controversy was around how many attended Aart's speech. My
count at the 30 minute mark was 367. Immediately after the speech, one of
the Synopsys people told me: "John, I had two CAE's count the room. They
counted 385." Roughly half an hour after Aart's speech was over, the
very *same* Synopsys employee told me: "John, I had two CAE's count the
room. They counted 470." I stand by my original 367.
Monday, March 29 Number Of Attendees
9:00 - 12:15 (MA1) Tutorial on Synthesis Coding Styles 239
9:00 - 12:15 (MA2) Tutorial of FPGA Compiler II 51
9:00 - 12:15 (MA4) Tutorial on Behavioral Compiler 44
9:00 - 12:15 (MA5) IP Vendor Reuse Stories & SPINE'99 69
1:30 - 3:00 (MB1) DC Wire Models & 2 Power Talks 214 + 11 standees
1:30 - 3:00 (MB2) Eagle, COSSAP, Cyclone, VERA Talks 63
1:30 - 3:00 (MB3) PrimeTime 128 + 8 standees
3:15 - 4:45 (MC1) Make, MIN/MAX Synth, Clk Gating 227 + 17 standees
3:15 - 4:45 (MC2) BFM Testing, Test Compiler 58
3:15 - 4:45 (MC3) Large FPGAs, FPGA Express 43
5:00 - 8:00 Synopsys R&D Cocktail Party Est. 600
Tuesday, March 30
9:00 - 10:15 Keynote Address (Aart's Speech) 367 or (385) or (470)
10:30 - 11:45 (TA1) Dc_shell, Verilog, VHDL, ECO Compiler 166
10:30 - 11:45 (TA2) VCS, sim/syn mismatch, LFSRS 128 + 13 standees
10:30 - 11:45 (TA3) IP Cores, IP w/ PathMill & PrimeTime 101
10:30 - 11:45 (TA4) EPIC TimeMill, Arcadia, RailMill, ACE 34
1:30 - 3:00 (TB1) Tcl, Clear Case, FSM_PERL, "Modes" 227
1:30 - 3:00 (TB2) IP Cores / Design Reuse Talks 96
3:15 - 4:45 (TC1) Make files, SMART 2.0, RUN_PROJ 161
3:15 - 4:45 (TC2) Behavioral Compiler Experiences 93
3:15 - 4:45 (TC3) Formality Experiences 83
5:00 - 5:45 SNUG'99 Wrap-Up & Best Papers Awards 216
6:00 - 8:00 Non-Synopsys EDA Vendor Fair Party over 400
Wednesday, March 31
8:00 - 11:15 (WA1) Tutorial of New Stuff in DC 99.05 178
8:00 - 11:15 (WA2) Tutorial on EPIC PathMill 25
8:00 - 11:15 (WA3) Tutorial on Design Reuse 61
8:00 - 11:15 (WA4) Tutorial on Functional Verification 33
1:00 - 4:00 (WB1) Tutorial on PrimeTime & PathMill 43
1:00 - 4:00 (WB2) Tutorial on Scan Test w/ DC Expert 31
1:00 - 4:00 (WB3) Tutorial on TimeMill & PowerMill 11
1:00 - 4:00 (WB4) Tutorial Module Compiler/BOA/BRT 135 + 7 Standees
1:00 - 4:00 (WB5) Tutorial on VCS & VERA 63
The overall user attendance for SNUG'99 was 528 customers. Compared to
the SNUG'98 numbers, 590, this is an 11 percent drop in attendance. But
that's no big surprise because SNUG normally 'partners' with OVI/VIUF
on opposite ends of a particular weekend. It just so happens that this
year, that weekend was Easter/Spring Break Weekend -- forcing the two
conferences to have 5 dead days between them. As a result, this meant
that the out-of-towners choose *either* SNUG *or* OVI/VIUF rather than
their usually going to both.
On the technical side, last year SNUG'98 had 15 tutorials and 30 user
papers. This year, SNUG'99 had 12 tutorials and 35 user papers. Last
year, SNUG'98 was 2 1/2 days; this year, SNUG'99 was 3 full days.
"The presenter gave some interesting statistics for design effort
at Intel
Spec Development 30%
Coding 10%
Synthesis 15%
Design Validation 25%
Layout 20%
I am not sure about the sample size within Intel. Their initial
design took 3 months, adding reusability took about 3 weeks, and
the first re-use of the block took 1 month"
- Anon
The Bigwig's Big Speech
-----------------------
"I think Aart must be renovating his house these days because his big
thing this year was comparing every problem the industry is facing to
various home renovation disasters encountered by 'one of my friends'."
- Paul Chenard of Hewlett-Packard
The SNUG'99 keynote address was given, as it always has been, by Aart de
Geus, the CEO of Synopsys. This year's speech was very odd in that it was
a System-On-A-Chip CEO Talk instead of Aart's usual State of the Synopsys
Union Address. An awful lot was very conspicuous by its absence from
Aart's speech. (For example, *NONE* of the following were mentioned:
Design Compiler, VSS, behavioral synthesis, LMC, Module Compiler, scan
or ATPG, PrimeTime, MOTIVE, libraries, FPGA synthesis, Formality, ECO
Compiler, buying/reselling ViewLogic, Protocol Compiler, nor EPIC tools.)
Here's his speech with all the 'Home Improvement' stories removed.
About 50% of all semiconductors go into PC's, and the next kill apps for
semi's are probably Digital TV, Phones, and Internet appliances. Reuse is
a big topic since design cannot keep up with Moore's Law of gaining 10X
gate density every 6 years. Most systems on a chip (SoC) require both HW
and SW. The design of these IC's are beginning to merge the styles of ASIC
flows and Full Custom flows.
The 3 biggest design challeges are
1. Specifications and Verification
2. Timing and Power Closure
3. IP Reuse
Here are his views on how each will be solved
1) Specs and Verification are a big issue with verification being 50% or
more of the design process. HW/SW co-simulation will help test SoC.
Synopsys has a tool called Eagle that is designed for this.
2) Timing and Power Closure -- Timing is being solved by moving to
physical synthesis. A new tool "Chip Architect" is being released
this year to use placement info in synthesis. Synopsy has purchased
a company called Everest, which deleveloped a top level router tool.
Tool capacity for large chips may be an issue in this area. Power
is being solved by Power Compiler and other related tools.
3) IP reuse is one way to gain productivity. There are 3 kinds of IP
a) Building Block IP - such as DesignWare
b) Complex Commodity IP - this is a difficult model to have
a business around.
c) Star IP - parts like an ARM core that has great IP content.
Synopsys has published the RMM book and has a MORE rating to gauge
the goodness of IP. Some IP companies are having a hard time making
a business model for commodity IP. Synopsys wants the DesignWare
Foundation to always grow over time.
Synosys also has 2 new testbench tools ( VERA and CoverMeter). Radiant
VCS is 3X faster w/ 50% less memory. There are new IP delivery tools
called CoreBuilder & CoreConsultant.
In general, Synopsys 1998 was a $720 M company (3X of its 1993 size) that
invests 22% back into R&D. Revenues broke out by
North America : #################### 55 - 60 %
Europe : ###### 15 - 20 %
Japan : ###### 15 - 20 %
Asia/Pacific : ## 5 - 10 %
In a 1998 "EE Times" survey, Synopsys was ranked #1 for customer support,
Mentor #2, OrCAD #3, Cadence #4. At the bottom of the 12 company list
were Summit Design and IKOS.
"I will forgive not getting to market on time if the reason was to
make the core reuseable."
- Brian Halla, CEO of National Semiconductor (as cited by Aart.)
"WE WANT YOUR FIRST BORN CHILD!" It's rumored that a woman lawyer inside
of Synopsys, named Sylvia, who used to work in Licensing Enforcement is
now heading the Synopsys High School Outreach Program. "We want to get
the kids interested in engineering early on. They're our employees of
tomorrow!", Sylvia told me. (And no, I'm not making this up!)
SELLING ICE TO ESKIMOS Most companies that do chip design have internal
networks, internal web sites, with data management and rev control -- yet
at the Vendor Faire, "Synchronicity" was selling just that. Selling ice
to Eskimos? Wanna buy the Brooklyn bridge? See www.syncinc.com
WHY DO THEY WEAR "KICK ME" SIGNS? At the SNUG R&D faire, Synopsys Customer
Support had a table with a sign: "Stump The Engineer". OK, so it looks
like we customers get to stump them with our tricky Synopsys questions
face-to-face instead of on the phone. WRONG! We were only allowed to
ask them questions from pre-printed Trivial Pursuit cards! ("I guess you
guys still have just as many problems with my bugs whether we're on the
phone or face-to-face, eh?! Should we e-mail in a test case with this?")
"We saw a real need for HW/SW co-design. We had the Mentor Seamless
and Synopsys Eaglei guys come in to pitch their tools. As a test,
we set up two teams in house using both tools. Each team consisted
of two HW engineers and one SW engineer. For a few weeks, they used
either Eaglei or Seamless to develope a PowerPC based testbench. We
then had each team switch to using the other tool. In the end, the
two tools were very close but our conclusion was to choose Mentor
Seamless because it was more mature, it allowed granular and dynamic
optimization control of memories, they had working Denali memory
models (Synopsys MemPro was yet unworkable), and it ran on HPUX
(Eaglei only runs on Suns and we're a HP house.) Price was a
non-issue because they were so close."
- Hugh Blair of Honeywell Space Systems
RESISTANCE IS FUTILE! <yawn> As usual, independant consultant Steve Golson
won the first place award for Best Paper at SNUG this year. (There's talk
of renaming it the 'Golson Award' because he's won 3 Best Papers so far!)
In his paper, Golson points out the problems associated with the seven
common myths surrounding wireload models plus a related graphical techique.
The 2nd place SNUG'99 paper was "FPGA Express Coding Techniques" by David
Nye of Xilinx. The 3rd place paper was "Using ACE to Simulate a Complex
PLL" by Kevin McCollough of Motorola. To see any of the SNUG'99 papers
on-line, go to www.snug-universal.org.
"Wireload models are like the weather. Many people talk about them,
but not many people *do* anything about them! This paper will explore
some of the myths and realities of wireload models:
- why wireload models are important, and why *nobody*
understands them
- why your intuition is wrong
- why you shouldn't trust your silicon vendor
- why floorplanning sometimes doesn't matter
- why having an accurate wireload model is a *bad* idea
A technique for measuring the quality of wireload models will be
described. Real-world results will be discussed. Cool graphics
will be shown. A desperate plea for future work will be given."
- the abstract to Steve Golson's 1st place SNUG'99 paper
titled "Resistance is Futile! Building Better Wireload Models"
ELVIS HAS LEFT THE BUILDING: The fact that SNUGs are (virtually) devoid
of any Synopsys marketing presentations is something greatly appreciated
by most users. And not only are SNUGs a great place to get all sorts
of useful user tips, you can also get solutions to your really tricky
Synopsys problems there, too, (because of all the experienced users,
Synopsys CAEs, Synopsys R&D, and other techo-nitpickers are there.) And,
you can also get help on more serious (what I call "infrastructural")
problems, too.
Solving "infrastructural problems" requires having a Synopsys bigwig from
upstairs and a lowly customer meeting face to face (because the bigwigs
are the only ones with the real authority to create "infrastructural
change". An example of this was during the Q&A part of Aart's speech,
Kurt Baty (a chip designer) openly complained about Design Compiler not
being able it to handle very large designs. At first, Aart understandably
tried to pooh-pooh Kurt's problem as being very specific to his design
because it was 10 million gates. Kurt countered that he didn't think he
was the only one dealing with DC Capacity Fatals and asked any other users
facing this to raise their hand. Approximately 60 out of the 367 people
in the room (~16 percent) raised their hands. Suddenly the conversation
then shifted to moving DC from its 32-bit (4 Gigabit limit) implementation
to a 64-bit (a *much* bigger 1.8 x 10^19 bit limit). And you can bet that
more effort will be brought to bear on Kurt's problem pretty damn soon.
Conversely, if Kurt had handled this through accepted channels, his
"problem" would have been classified by the techno-nitpickers as not even
being a bug but as a low priority "enhancement request" from a kook doing
an absurdly large design. ("Uh... We'll do the 'enhancement requests'
sometime in 2005 -- after we get *all* the bugs out! Hahahahaha!")
"What's this 'Elvis Has Left The Building' stuff, John?," you ask. It's
because at this year's SNUG'99, other than a cameo appearance by Aart,
virtually *none* of the Synopsys bigwigs (the VP's and GM's) deigned
meet the lowly end users this year. This is a very dangerous precedence.
Instead only the techno-nitpickers (Synopsys CAE's, R&D, tech support)
plus a number of middle managers, and a few observing marketeers came.
Bad idea. It not only leaves the Synopsys "infrastructural problems"
unfixable by customers, it also recklessly leaves Synopsys management
vulnerable to their own soothsaying Marketeers, yes-men, and Rasputins.
And many times these weaselly flatterers are more caught up in their own
Palace Intrigues than presenting the Real Truths their customers are
facing. Is a VSS (VHDL) Marketing Manager ever going to say "Hey, let's
dump our internally developed VHDL simulator, buy Chronologic, and sell
the world's fastest Verilog simulator instead!"? (And you tell me: would
*you* bet *your* livelihood on a Collett Market Forecast???)
"I spend a good bit of my time listening to marketing presentations.
They are almost all exactly alike: a marketing guy drones through a
series of PowerPoint slides. Invariably, they quote market
predictions by "analysts." As nearly as I can tell, what these
analysts do is poll all their customers (i.e., marketing guys), get
some data, massage it, and sell the data back to the marketing guys
for a couple of thousand dollars a pop."
- Chuck Small, Senior Tech Editor at "Electronic Systems" magazine
"The telephone has too many shortcomings to be seriously considered
as a means of communication."
- an 1876 corporate memo from Western Union (a telegraph company.)
"An island of stability."
- President Jimmy Carter (1979) describing the Shah of Iran. The
Shah was overthrown a few months later.
"I share your view that the urgent problem of species extinction and
the conservation of biological diversity should be addressed. The
first step in saving any plant or animal from extinction is to become
aware of and respect the fragile ecosystems that make up our
environment."
- a 1996 letter from Vice President Al Gore to a Dallas couple who
complained about the elimination of the "Texas Eagle". The
"Texas Eagle" was an Amtrack train connecting Dallas to Chicago.
"Beyond a doubt, all stories about large bodies of Indians being
here are the merest bosh."
- General George Armstrong Custer, 1876, a few weeks before being
massacred by a large body of Indians at Little Big Horn
"Don't worry about it. It's nothing."
- U.S. Navy Lt. Tyler, Dec. 7, 1941, upon being informed that radar
had just picked a large formation of planes heading for Pearl
Harbor, Hawaii.
"I think Synopsys is facing some real challenges next year. I've got
Design Compiler blowing out on my current design. As a user and a
stockholder I'm concerned. Design Compiler is using too much memory."
- chip designer and consultant Kurt Baty at Aart's speech
"I second Kurt's problems. We, at HP, are seeing this, too."
- an anon voice in the crowd at Aart's speech
THE BASEMENT IS FLOODING: One of the bigger announcements Synopsys
made at SNUG'99 was the how they intended to keep adding more and more
parts to the basic Designware Foundation library. That is, as a piece
of IP becomes more mainstream in useage, Synopsys is just going to
automatically add it to the Foundation at no extra cost to users. In
this vein, Aart annouced that the DW PCI core and the DW 8051 were now
part of the DW Foundation library -- free to anyone already using that
library. This effectively means it's free to anyone using Design
Compiler due to its close ties to the DW Foundation lib! Way cool!
"We use Ambit with Synopsys. Right now the Ambit equivalent to a
DesignWare library is very weak. It didn't exist two revs ago
and it currently only contains three parts. This is why we used
Synopsys in conjunction with Ambit because of the huge DW library.
For example, we had some blocks that needed a binary encoder and
DesignWare had it."
- Thomas Tomazin of Analog Devices
"Design Reuse is myth. It's this year's EDA hobby. They're trendy
industry buzzwords that'll be long forgotten 2 to 3 years from now.
Engineers do not want to reuse somebody else's design. Engineers
want to 'create' and they do _not_ want to modify another engineers
code to do it."
- Cliff Cummings of Sunburst Design
"I feel a little betrayed. I was asked to come into SNUG to talk
about the strides Synopsys has made in interoperability. I even
wrote an article specifically about this in EE Times. Now, this
flies in the face of mix and match IP. It's really been buging me."
- Rita Glover, an analyst at EDA Today about CoreBuilder and
CoreConsultant delivering encrypted IP to customers via a
proprietary algorithm that only works with Design Compiler
"Those little Mom & Pop IP start-ups? The French have a term for
IP. It's 'I pee on you.' At one point we counted 167 of these
little IP companies, but they're dropping like flies."
- Gary Smith, Dataquest analyst
"I am told that there is a tool which allows you to put a wrapper
around Verilog code to allow it to be simulated with VHDL in VSS.
Essentially the wrapper means that the Verilog will be simulated
under VCS within the VSS simulation. The tool is free. This could
give us a free route to simulations involving VHDL and Verilog IP
(such as is required on [Project Name Deleted].) I am asking our
local support for more info."
- Euro Anon
IT'S NOT LUCY'S YOUNGER BROTHER ANY MORE: Yielding more credibility to
the anti-Windows movement, Synopsys annouced at SNUG'99 that VCS and
CoverMeter will be available to customers on Red Hat Linux in July 1999.
Avant! already ported Polaris over to Linux. Even little EDA start-ups
like Stanza Systems ported their full-custom editor (SLE) and DRC tool
(PolarVerify) over to Linux. ModelTech is making Linux noises. Linux
is a comin' thang! "I was delighted with how quickly and smoothly VCS
came up on Linux," said Lee Jones of Silicon Graphics. "We are very
pleased that Synopsys responded to our request. Our initial testing of
this version indicates that VCS on Linux is rock solid and ready for
production work."
"One World, One Web, One Program"
- Microsoft Ad
"Ein Volk, Ein Reich, Ein Fuhrer"
- Adolf Hitler
"After my first experience hearing Ron Collet's VHDL presentation, I
was always very skeptical of his market analysis. In 1996, it hit
directly in my realm when he avoided the VHDL-versus-Verilog topic
and began to harp on the demise of the UNIX workstation platform
in favor of Windows NT."
- Clay Degenhardt of Systems Science in ESNUG 286
"We're adopting a wait and see attitude on this. We've found that the
UNIX workstation is still the platform of choice for our customers.
Less than 10 percent have switched over to Windows NT PCs. If Linux is
10 percent of that, it's still pretty small. We'll just have to see."
- Synopsys CEO, Aart de Geus, in the Q&A at SNUG'99
"VCS on Linux was announced just before SNUG. They are not sure if
they're going to port the synthesis tools to Linux, it will depend on
user feedback. I vote YES."
- Oren Rubinstein of Gigapixel
MAKING "VICTORIA'S SECRET" BETTER FOR EVERYONE!: If you're a guy, I'm
sure you'll remember the fashion show "Victoria's Secret" had on the web
at half-time during the Super Bowl. It crashed because too many men
were trying to access that web site simultaneously -- the web server
couldn't handle the demand! It turns out that there's an EDA start-up
that may make such disappoints a thing of the past. (Yes, you're about
to hear another scoop.) It's called "LavaLogic" and word is that they're
working on a Java-to-Synthesizable-Verilog translator called "Forge".
The story is that they're a bunch of ex-NASA technonerds who used to do
contract work for the NASA Goddard Space Center and that Sun Microsystems
is beta testing Forge on the FPU of the Sun picoJAVA embedded uP. This,
when taken altogether, means that the zillions of Internet software Java
applets will be easily synthesized onto FPGAs or ASICs -- and that means
web sites will run with 1,000 to 1,000,000 times more effective CPU!
"Yay, Naiomi Campbell!!! You go, girl!" (Check out www.lavalogic.com)
TELL THEM "COOLEY SENT YOU" Yup, I hate creating functional testbenches
as much as the next guy. Go check out www.surefirev.com. The whizkids
there who created Chrono's VCS say they have a new tool ("SureSolve")
that's supposed to take *whatever* Verilog RTL you've created 'as is' and
it *automatically* creates a set of functional test vectors for it. (It
supposedly somehow magically figures out everything from analyzing your
datapaths and control flow.) And there's also supposed to be an easy GUI
that lets you direct it to functionally test the parts that it initially
missed. If this works, please e-mail me ASAP at "jcooley@world.std.com".
I really do hate creating functional test vectors.
"I want more automatic testbench tools. I believe companies like
Surefire Verification, 0-in, and Silicon Forest Research are
addressing the real design problems of rapid verification."
- Cliff Cummings of Sunburst Design
SEWARD'S FOLLY (PART DEUX?): In 1867, the U.S. Secretary of State, William
Seward bought Alaska from the Russians for $7 million. At the time, this
purchase was called "Seward's Folly" because it was popularly felt that
the U.S. would never get $7 million worth of return out of Alaska. (In a
sense, public opinion at the time was right, because it's estimated that
it took about 35 years to recoup $7 million of surplus taxes from the
Alaska economy.) The Synopsys equivalent of this came when they bought
System Science (VERA) for $26 million. It's well known that verification
and functional testbench generation is something that we engineers drool
at because we *hate* creating testbenches, so the need is there for VERA
and Specman. (Specman is a competing functional testbench generation tool
from Verisity.) Functional verification (sim done in Verilog or VHDL) is
supposedly taking over 50 percent of design efforts these days. If you go
to DejaNews, you'll find there are around 5,300 posts every year on either
Verilog or VHDL. And it's growing. Yet you'll only find 6 VERA posts and
2 Specman posts in DejaNews, and only 7 posts on each if you grep an ESNUG
archive! Yes, Synopsys recently announced VeraCore (VERA being used with
IP) and, yes, it's integrating VERA with the Eagle HW/SW co-simulator,
but if VERA is an up-and-coming widely used tool, shouldn't there be more
posts from users on it? Is Synopsys going to have to wait 35 years to
recoup its VERA investment?
"VERA - Mehdi Mohtashem (mr VERA). Most stuff in files. Sales pitch
that was very technical and example laden.
- Can reuse existing verilog or C. Can call routines/tasks inVERA
- Interfaces to simulator via PLI . Going direct with VCS to speed
it up.
- Can handle re-entrant calls without multiple instantiation. Fully
recursive via virtual ports. Can call multiple times at anytime.
- Cyclebasedwith event driven options
- random and directed random constructs to produce stimulus
- Self checking with floating expects.
- User defined functional coverages (not line code coverage) of
stuff like fsms. Gives reports. Can react to coverage and
dynamically redirect sim on the fly.
- 2 to 10x reduction in overal verification: Speeds up verification
development, verification debug, and result review(regression).
IP released with VERAcore gives verification test suite that can run
without VERA license."
- Peet James of Qualis Design
"Whenever I teach Verilog and Verilog synthesis classes, I always
take a short poll. The question: 'How many engineers in this room
prefer writing testbenches over doing ASIC design work?' Of more
than 600 engineers taught in the last two years, fewer than five
preferred writing testbenches."
- Cliff Cummings of Sunburst Design
WALLY'S FOLLY: For quite a few years within the test community, Mentor's
Fast Scan and Flex test tools have been known as the best in their class.
When Test Compiler first came out, it was a dog with too many bugs to be
useful. (Even on the personal side, TC had some tough times with the R&D
manager dying from brain cancer and another R&D person later commiting
suicide.) Instead of capitalizing on this ideal situation to completely
dominate the test market, Mentor now only owns 27 percent of the market
compared to Synopsys owning 51 percent (from the 1997 Dataquest numbers;
it's rumored the 1998 numbers are 55 to 60 percent market share.) To make
matters worst for Wally, Synopsys bought Sunrise (grabing that market
share and partial scan technology) plus Test Compiler and DC Expert are
now debugged, robust, fully functional tools.
"The present opportunities are not to be neglected; they rarely
visit us twice."
- French philosopher and wit, Francois Arouet Voltaire, 1694-1778
"Mentor's Fast Scan and Flex test tools, in my experience, seem to
need less support than the Sunrise tools. Online documentation and
tool maturity with some of the larger chips has made these tool quite
a bit robust and easy to use. My experience with Mentor's tools is
limited. But I certainly like to use them and they do a good job."
- Shankar Hemmady of Guru Technologies in ESNUG 300
"Right now Synopsys scan insertion and ATPG works at the gate level.
They're working on tools that will automatically fix testability
problems at the RTL level with no gates needed."
- Anon
THE MORE THINGS CHANGE, THE MORE THEY STAY THE SAME: Back in the medieval
ages of EDA (oh, about 5 years ago), two bloated companies (who possessed
all the spry agility of drunken elephants) had two mutually exclusive yet
critical monopolies in the chip design world. The queen with a plain face,
Cadence, owned Verilog simulation. The queen with a fair face, Synopsys,
owned synthesis. Of course, dear Cadence dabbled in synthesis with her
Synergy, but everyone knew it was a joke not to be taken seriously. And,
dear Synopsys also toyed with her VSS simulation, but everyone laughed
at how VSS was the base unit in the benchmarks. (That is, all the other
simulators were measured as "2.3X faster than VSS" or "5.4X faster than
VSS". Poor, poor VSS.)
Then, about two year ago, a small young upstart named Ambit started messing
with the Synopsys monopoly. Ambit was young, lean, and hungry for a nice
tasty chunk of the Synopsys monoply. (Gosh, in those days, Synopsys *upper
management* would even meet with the *lowly users* of Design Compiler at
SNUGs and ask users what they thought about Ambit, DC, and how to make DC
better! (I know, hard to believe, but it's true!)) Ambit staged little
raiding parties at SNUGs to show users their BuildGates synthesizer.
Synopsys upper managment got scared and pushed their R&D to completely
revamp Design Compiler to be faster, get better results, and use less
memory. And the customers always won because that pesky competition caused
*both* EDA tools to get better!
Then, like the Dooms Day Asteroid, our big bloated Cadence came crashing
in, bought Ambit for the princely sum of $260 million CASH (with all
the Ambit employees being fully vested!) and destroyed our world. Within
picoseconds all those nouveau riche Ambit employees (who had caused such
trouble for Synopsys), in unison, threw up their hands, said "well, our
job's done here!", and ran laughing all the way to the bank.
In addition, much drinking and merrymaking secretly went on at Synopsys,
too. Why? Because this purchase meant we're mostly back to "the good
olde days" of Cadence/Synergy. Sigh.... It's true. The more things
change, the more things stay the same.
"I am in absolute awe of him. I just want to fall at his feet and
say 'We're not worthy! We're not worthy!'. He got $260 million
in cash for a $10 million, maybe $20 million company. I'm in awe."
- a Synopsys marketingdroid describing Ambit CEO Prakash Bhalerao
"The 1997 synthesis market breaks out to:
Synopsys: 94.91100 percent
Ambit: 0.01314 percent
Mentor: 5.07586 percent
Yes, those old Mentor Autologics seats in the military outsold Ambit's
commercial seats by a ratio of around 380 to one."
- Analyst Gary Smith of Dataquest
Pissing and moaning aside, the DC'99 we're seeing right now in the Synopsys
roadshows is a direct result of competing with that pesky Ambit.
"Design Compiler speed improvements in 1999.05: they claim 2x for
normal compilations (I've seen over 3x) and 8x for chip-level (with
-top). DC will do placement AND global routing in a future version.
They are changing all the tools to 64-bit binaries, because people
are running into memory limits (currently, 3.7 Gbytes). They are
starting with the tools which typically work on a full chip: Design
Compiler, PrimeTime, layout optimizations, etc. The conversion
to 64 bits will take time and SNPS is concerned the tools will be
slower in that mode. In the meantime, they are working on reducing
the amount of memory they use."
- Oren Rubinstein of Gigapixel
"New in DC99: read-f verilog -netlist ( -netlist ignores syntax and
some other checking, but speeds up reading 2x)."
- Anon
"In Synopsys 99.05 the VHDL construct rising_edge(clk), "alias databit :
std_logic is data(5)" and all of "use ieee.numeric_std.all;" are fully
supported. In order to use the designware components with the numeric
standard package, you need to do "use dware.dw_foundation.all;", not
the individual "use dw01" constructs. The only way to use the "/",
"mod", and "rem" constructs is with the "dware" package.
A few new variables available in 99.05 are "hdlin_bussed_clock = true"
which allows you to buss clock signals. "hdlin_keep_feedback_netnames
= true" will use the internal VHDL netname rather than the "_port" for
internal signal connections. "hdl_report_inferred_module = verbose"
will report and give the names of module inferred by VHDL constructs.
If you find yourself reading a VHDL netlist back into Synopsys, it will
read 2X faster with the following "read -f vhdl -netlist filename.vhd".
See the "HDL Coding style synthesis application notes" for more updates
which can be found in 99.05.
TCL Interface: TCL version 7.6 has been integrated into Synopsys 99.05.
It can be invoked with "dc_shell -tcl_mode" and "dc_shell-t" commands.
NOTE that the default $SYNOPSYS/admin/setup/synopsys_dc.setup file is
now written in TCL!!! A "#" needs to be the first character on the
first line of any dc_shell TCL script. A web page can be found at
http://www.scriptics.com which explains TCL and TCL constructs. Many
of the standard commands had to be changed because the conflicted with
TCL reserved words. A list can be found on Page 68 in the notes.
Other Notes: TCL normally works with list, however all of the Synospys
tools produce "collections". There is a nice little script in the
handouts which will convert a collection to a list.
(from outside the meeting)
Synopsys 99.08 has some ugly bugs in it. It tends to crash, it runs
faster, but gives you a worse result. PT2 (primetime) is unstable,
there are patch releases available.
(back at the meeting)
DC99 is 2x faster than 98, which is 3x faster than 97.
Reoptomize_design is 2.5x faster. Use the command "compile -top" to
fix constraints from the top level.
There is now a "checkpoint" option. It now takes 3 '^C's to kill a
dc_shell script. A unix "kill" will cause a "checkpoint" file to be
created before it actually dies. "compile_checkpoint_cpu_interval",
a new variable, will periodically checkpoint your design as you are
running. The "compile_new_boolean_structure" compiler knows about
all of the "don't care" feature that are built into the language and
will optimize around them. Try the following: "set_structure -true
-boolean true -boolean_effort medium".
DC99 can only use 2.0 gig of memory. Under solaris 2.6 it can use
4.0 gig of memory if you do a "limit database unlimited".
"simplify_constraints" - new command which opomized tied signals.
The "reoptomize_design" command has changed, so old scripts won't
work. (See page 61 in the handout for a nice list of obsoleted
commands going back to V3.0.)
There are scripts available to convert transcripts into TCL."
- [ Kenny from South Park ]
"Although some nice user enhancements were added, no 'Earth Shattering'
features were added."
- Anon
"Along with Steve Golson, Kurt, several other big chip people and some
Synopsys folks we pow wow'd under NDA on DC limits on large designs
and their new ACS. Can't give details, but I'd like to throw it at a
big chip soon."
- Anon
TICKLE ME ELMO: Damn Ambit. Damn PrimeTime. It's because of tools like
these that we're now all moving (kicking and screaming I might add) over
to TCL scripting. Means all those old & working dc_shell scripts will
need translating or complete rewrites. Damn! SNUG'99 had its first TCL
tutorial. There will be more to come, I'm sure.
"Tcl is a bit better than the current dc_shell language, but only a
small bit. Why couldn't Synopsys have picked perl or one of the other
higher level scripting languages? I tried to write a histogram routine
in tcl, for PrimeTime, it was ugly and slow. Perl did most of the work
in one line with an associatve array (hash)."
- Don Reid of Hewlett-Packard in ESNUG 310
A SEA CHANGE IN DESIGN: Think of a chip world where scan is automatically
built in, no lengthy validation schemes are needed, and troublesome parts
(like a PCI interface) is already built in? Then you're thinking about
the Brave New World of Bigger FPGAs like Vertex (Xilinx), ORCA (Lucent),
and APEX (Altera). They even have their own DesignWare-like libraries
like CoreWare (Altera) and XBLOX (Xilinx) plus some fabs like ChipExpress,
Toshiba, and AMI are offering a quick and easy FPGA-to-ASIC migration path
once your design's debugged. Yea, alot of this is still problematic
(like Altera's flakey PCI part, or the fact that ORCA has *still* yet to
deliver on that 66 Mhz hard macro PCI interface that it promised *two*
years ago, or that 150 ASIC kgates equals 1 Million Vertex gates...)
But, headaches aside, the writing is on the wall and it says 'F-P-G-A'.
YOU'RE TAKING YOUR CHANCES WITH US! To foster an image of competence
and quality at the SNUG R&D faire, Synopsys Customer Education had a sign
saying "Take A Closer Look At Synopsys Customer Education" while they were
running a roulette at their table. What are they saying? "Is our VHDL
training worthwile? Well,... we'll give you 2 to 1 odds it might be!" ?
"Interoperability: Panel took alotted time (plus 15 min into lunch) to
give their presentations. No time for Q&A. Mostly yadda, yadda,
yadda party line stuff.
Gary Smith - Dataquest - Moderator
Dinesh Better - Intel - Good overview.
Rich Collman??? - Synopsys - Sales pitch on TAP-IN (insync
multi-vendor partnering) and SPINE99
Michael ????? - Cadence - SPINE99 details. Warm fuzzies about
new Synopsys and Cadence partnering
Priti Vijayragiya - Synopsys - TAP-IN details. Have a lab for
joint EDA usage, No Synopsys regulars aloud. Multi vendor
teams to work on interoperabilities. Need testcases, have
teams and interoperability points defined.
?????? - ULTIMA - Small eda backend (parasitic and delay
generator) company. Early TAPin. Warm fuzzies about first
date with Synopsys.
Rita Glover - Analyst (formerly Silc and Mentor). Good history
of interoperbility & EDA vendor blunders. Defined problem.
That last person, Rita Glover, gave some much needed fresh air, by
talking a little about Synopsys' past record in this area."
- Peet James of Qualis Design
"They're talking a good line but they're not doing it. They're the
only ones who can do it. The whole industry is depending on them to
become interoperable. It's very frustrating. I've even moderated
panel discussions where, at the last minute, one of them would
threaten to pull out if the other was going to mention some specific
item. I'm stuck being the peace broker behind the scenes. What I'd
really like to do is to have all of them come to Phoenix. I have a
pool. I'll buy an extra picnic table and I already have a blender.
They could sip margaritas and work out their differences. Anyone
who gets too pigheaded about anything gets pushed into the pool to
cool off! I'd really like to do that."
- Rita Glover, an analyst at EDA Today, talking about how Cadence
Synopsys, and Avant! give great lipservice to interoperability
in public yet scratch and claw about it in private
COKE BRINGS THE DEAD BACK TO LIFE: There are some fairly famous gaffes in
international marketing. The Chevy Nova in South America is one. "Nova"
is very close to "No va" which in Spanish translates to "it doesn't go".
On the week preceding HDL Con (OVI/VIUF), Avant!, with its predominately
Chinese management, mailed *broken* mousetraps to a good part of the EE
Times readership. What this means in Chinese, I have *no* clue, but in
American culture there's the famous saying of "Build a better mousetrap
and the world will beat a path to your door." What is Avant! trying to
say? "Don't bother coming our way because all our ideas are broken?"
Huh? And to make matters worst, Avant! then mass-mailed pieces of cheese
out on the following week! Huh? Is it poisoned because their mousetrap
technology is so broken? Huh??? I are engineer and I are confused.
"Coke Brings The Dead Back To Life!"
- the "Coke Adds Life!" slogan when its was literally translated
on the Coca Cola ads in the Chinese speaking markets.
THE GREAT LEAP FORWARD: Although many people understandably disagree with
what Mao Tse Tung did to the individual liberty and lives of hundreds of
millions of Chinese citizens, Mao can take credit for, in one generation,
converting a China of peasants and shopkeepers that was regularly invaded
by foreign powers into a technologically advanced China that now stands as
a nuclear superpower in her own right. My own pissing and moaning aside,
Synopsys has been very wisely focused on moving synthesis down into the
physical domain because there's only so much one can do to improve a tool
that goes from Verilog/VHDL down to gates only using front-annotated, best
guestimated wire load models. Like Mao's "Great Leap Forward", Synopsys
is re-inventing itself into a beastie focused on something called "physical
synthesis" to slay all the evil Metal-Migration, Signal Integrity, EMI,
and Wire Model dragons that lurk in the sinister depths below 0.5 micron.
1.0 0.8 0.7 0.5 0.35 0.25 0.18
----------------------------------------
Area | X X X X X X
Speed | X X X X X X X
Power | X X X X X
Metal-Migration | X X X
Signal Integrity | X X
EMI | X
The first of the New Weapons that Synopsys is carting out to deal with
these issues is a new tool called 'Chip Architect'. Chip Architect does
hierarchical floor planning, timing analysis, timing budgeting, power
planning, global routing, and congestion analysis on RTL level source
code. (And Aart says they'll be adding top-level routing soon, too.)
Rather than having their marketing spin-doctors woo us with the praises of
this new tool, Synopsys rolled out three beta customers and let them talk.
Benchmarking The New Chip Architect Placement Algorithm
-------------------------------------------------------
The first odd feature of Chip Architect that Synopsys does is to split
away placement from routing. That is, they're moving 'placement' earlier
into RTL synthesis while keeping 'routing' as a post-synthesis process.
In that vein, Synopsys claims Chip Architect uses a proprietary
breakthrough in timing driven placement algorithms. To prove this, they
brought out the following customer benchmarks.
CPU Wire Percent Clock
Name (Co or Type) Gates Time Reduct. Util. Period Process
------- ------------ ----- ---- ------ ------- ------ -------
Block A (multimedia) 750K 6 hr 17% 82% 8 ns .35u
Block B (multimedia) 250K 1.5 hr 13% 95% 8 ns .35
Block C (ST Micro) 150K 1 hr 16% 80% N/A .35
Block D (ST Micro) 20K 2 min 0% 97% 7 ns .35
The Results: "Wire Reduction" is the percentage difference between the
total wire-length after detailed routing using Synopsys Chip Architect
placement with Cadence routing as compared to using purely Cadence P&R.
(Ironically, what these wire reductions indicate is that Cadence Silicon
Ensemble did *better* routing w/ Chip Architect placed designs *than
with* Cadence placed designs!
The Details: Cadence Silicon Ensemble was used for final routing of *all*
four blocks. The pin-out and placement area was fixed by the end user and
the only variable was the use of the new Synopsys placement engine. The
netlists were placed using the timing and congestion driven placement
capability in Chip Architect. That placement was compared to results
achieved using Qplace and Silicon Ensemble from Cadence for timing driven
placement and routing. All designs routed without routing violation.
Based on customer feedback the Synopsys and Cadence placement runtimes
were comparable. The major difference was in the wire-length reported
after detailed routing.
The Toshiba Evaluation
----------------------
Tomohisa Shigematsu reported that they took three already finished Toshiba
designs that had timing closure problems and ran their source Verilog RTL
through the Chip Architect design flow. The three designs and results:
Old Style Chip Arch
Size Tech Type Clock Iterations Iterations
------- ------- ------- ------ ---------- ----------
PC chip A 170 k 0.35 um gt array 66 Mhz 2 1, no viol.
PC chip B 170 k 0.25 um std cell 66 mhz 2 1, no viol.
Multimedia 1,000 k 0.30 um embedded 50 mhz 5 1, 44 viol.
The first two designs made their desired timing specs on their first try
at the Verilog-RTL-to-final-routing through Chip Architect design flow.
The million gate multimedia chip ran into 44 paths with timing violations
doing the same flow.
His flow consisted of three basic parts:
1.) To get the block wireload models for each block in a chip:
Verilog RTL -> CA RTL Estimator -> CA Floorplanner ->
CA create_placement -eff low -> CA create_wire_load (makes .db)
2.) To get each individual block's timing:
Verilog RTL -> CA RTL Estimator ->
CA Floorplan (write_sdf) -> PrimeTime (allocate_budgets)
3.) The final block stitch together:
Blk Wire Models + Blk Timing + DC + CA Place -> CND Cell3 or Gate Ensemble
Tomohisa reported that when they further examined the Chip Architect
output for the million gate multimedia design, the final-routed paths
had a timing histogram of
Chip Architect +
DC + Gate Ensemble DC + Gate Ensemble
------------------ ------------------
| . | .
number | *****. number | .
of | ***** .* of | .
paths |* . * paths | **.**
| . * | ****** . ****
| . * |*** . **
| . * | . **
------------+---- ------------+-----------+--
delay 20 nsec delay 20 40 nsec
With a spec of 20 nsec, the worst of the 44 violators cut off at around
20.96 nsec. That is, w/ Chip Architect, he had a 4.8 percent Delay Error
Delay Error == ((Worst Delay - Spec Delay) / Spec Delay) x 100 %
4.8 percent == (( 20.96 nsec - 20.0 nsec ) / 20.0 nsec) x 100 %
while his normal flow created a widely flattened histogram with many
paths having delays going up to roughly to 40 nsec (i.e. with Delay
Errors going up in the 100 percent range!)
The Panasonic Evaluation
------------------------
Keith Hirayama of Panasonic reported that they took the Verilog RTL from
two designs they already completed:
digital video camera chip (0.35 um / 3 metal / 80 Mhz)
mobile phone chip (0.25 um / 4 metal / 55 Mhz)
and compared what Chip Architect *estimated* from their source Verilog RTL
to the actual Avant! P&R final results. They were surprized to find
that Chip Architect estimates were highly accurate for long wires, even
when the wires went around intervening blocks and that 75 percent of all
nets were within +/- 10 percent of their estimates.
Keith did complain that the "RTL -> Chip Architect -> DC" run time only
averaged being 1.4 times faster than just doing the standard "RTL -> DC"
run time and wanted Synopsys to work on that. But Keith also found enough
early accuracy in Chip Architect to easily justify his customers using it
to eliminate the "Panasonic P&R <-> Customer Synthesizes" interations.
The ST Microelectronics Evaluation
----------------------------------
Marco Casale-Rossi of ST Microelectronics reported using Chip Architect on
parts of a 2 million gate, 0.25 um, 200 Mhz multimedia chip that had 80 to
90 utilization and more than 120 embedded RAMs. The chip was a design in
progress. It was broken up into 12 blocks and two of them were analyzed
in detail to evaluate the Chip Architect Verilog RTL-to-Placement path.
In one case, the block flow went:
Verilog RTL -> Chip Arch Placement + DC -> Cadence Silicon Ensemble Routing
In another case, the same block would go
Verilog RTL -> Design Compiler -> Cadence Silicon Ensemble Place & Routing
The results were:
Cell Routing Viol. Routing CPU Avg. Wire
RAMs Inst Gates Cdnc ChipArch Cdnc ChipArch Reduction
---- ---- ----- ---- -------- ----- -------- ---------
Blk 1 22 100K ~350K ~1800 ~900 4.3 hr 2.5 hr 7 percent
Blk 2 0 90K ~300K 0 0 19 min 38 min 12 percent
The Avg Wire Reduction was how much the Chip Architect placement reduced
the average wire length compared to using the Cadence Silicon Ensemble
placement. That is, for example in Blk 1, Cadence Silicon Ensemble found
the Chip Architect placements routed 7 percent shorter than using purely
Cadence place and route. Marco also reports that, for both blocks, he
found the post-P&R Silicon Ensemble congestion map and the Chip Architect
predicted congestion map to be virtually identical.
"Technology is part of our fundamental DNA."
- Aart De Geus, CEO of Synopsys
GOD HELPS THOSE WHO HELP THEMSELVES: Employees from both IBM and Ford
Microelectronics presented papers on using makefile and perl scripts to
automate synthesis. The set of scripts from Ford, called SMART 2.0, was
the most automated. Basically, you just provide SMART 2.0 with a top level
set of constraints and the name of the top level module, and it figures out
the entire hierarchy of your design and does as many iterations as you want
of characterize/synthesize commands (top-down, bottom-up strategy). It
also has support for the new design budgeting feature of Synopsys. SMART
is available for free from Ford, and they will even provide phone and email
support to get you started. ("rramsay1@ford.com" or "tharring@ford.com")
Focus and Qualis created a simular tool called RUN_PROJ that's available
at www.qualis.com/cig-bin/qualis/library.pl
Cliff Cummings of Sunburst Design presented fsm_perl, a perl script that
generates Verilog code for Finite State Machines (FSMs). The designer
writes a description of a state machine in a simple format that the perl
script can read. The advantages of using the perl script are that it is
easy to maintain, it has the ability to generate Verilog in multiple FSM
styles, and it automatically generates a Synopsys synthesis script for the
FSM, that uses the Synopsys FSM tool. www.sunburst-design.com
Robert Wiegand of Ensoniq Corporation presented a unique MIN/MAX method
to stop the ping pong effect which is common when using the characterize
command to optimize the timing of a design. (The ping pong effect is
where the synthesize/characterize iterations cause worst case delays to
alternate, or hop, between two modules that contain the path.) Robert's
technique requires three synthesis/compile passes. The first pass
compiles the RTL with default constraints, the second pass compiles with
the constraints derived from the characterize, and the third pass does an
incremental compile with the constraints derived from the characterize.
The key difference from the "normal" methodology is the incremental
compile, which is supposed to put a stop to the ping pong effect.
"Cooley, Golson, and Baty were really going at it in the bar over
that MIN/MAX compile technique. Golson and Baty hated it because
it created designs with overly conservative wireloading. Cooley
loved it because it completed designs quickly. Those three
squabbled for a good half hour. Brainy little kids, actually."
- Anon
"Weigand's MIN/MAX paper was well researched, well written, and well
presented. Even the slides were well done. It was perfect in every
way. I would have given it a 5.0 rating [the highest] in the user
survey. I just completely disagreed with what it was saying."
- consultant Kurt Baty
"Virtually every presentation that I attended dealt with at least one
aspect of reuse. Core reuse, test bench reuse, HW/SW co-sim, grading
3rd Party IP, coding standards, timing convergence and a new term
'Meta-Quality' all centered around the reuse theme. (No, I haven't
figured out what meta-quality *really* means)"
- Anon
WHERE THERE'S SMOKE, THERE'S FIRE: With Deeeeeeep Sub Micron now coming
in vogue, all those transistor-level EPIC tools appear to be the Synopsys
equivalent of discovering the Lost Continent of EDA Atlantis. And even
though at SNUG'99, the EPIC user talks only drew 34 users, the Customer
Education Workshop Calendar at www.synopsys.com has 98 classes scheduled
in EPIC tools!! (What?! Comparitively, they had 89 general synthesis,
33 advanced synthesis, 17 VHDL, and 30 Verilog classes scheduled in the
same months.) A hefty 98 classes indicates a *LOT* of hidden EPIC
customers. It's said that you can't see the true size of an iceberg
because 90 percent of it is underwater. Hmmm...
The 'Other' Numbers
-------------------
For a nosely bastard like myself, class schedules can tell a *lot* about
what tools are hot and what are not. Here's a summary of what I found:
Class Number Scheduled
------------------------ ----------------
General Synthesis 89
Advanced Synthesis 33
Verilog for Synthesis 13
VHDL for Synthesis 14
Basic Verilog/VCS 20
Adv. Verilog/VCS 10
Basic VHDL/VSS 14
Adv. VHDL/VSS 3
Hardware Modeling 8
Behavioral Synthesis 6
Module Compiler 18
Test Synth / TestGen 26
PrimeTime 46
VERA 5
PCI Bus Protocol 3
Library Compiler 2
FPGA Synthesis (Verilog) 3
FPGA Synthesis (VHDL) 3
ECO Compiler 0
Formality 1
EPIC Tools 98
I've already commented on the EPIC surprise. Everything seemed to make
sense (twice as many Verilog classes than VHDL, a high number of PrimeTime
classes, Module Compiler beating Behavioral Compiler by 3-to-1, only two
Library Compiler classes, 5 VERA classes, etc.) Only one other surprise...
DAVE? DAVE'S NOT HERE! Formality-The-Big-New-Change-In-The-Way-Designs-
Are-Verified has only *one* class scheduled??! Huh? Do a DejaNews
on Formality and you get lots of weird unrelated alt.religion.scientology
quotes. In the ESNUG archives, Formality is only mentioned in 5 letters;
and that was after it was announced. After that, nada, no bugs, no usual
user gripes, nothing. (In contrast, Module Compiler generated 21 user
letters in ESNUG and MC is a specialized tool for a niche market. Commonly
used EDA like Verilog or VHDL generates thousands of user letters.) For a
tool that's supposedly being used by so many different companies, Formality
should have generated more than a grand total of 5 user letters. At the
recent DAC'98, ten other EDA companies announced formal verification
products (along with Formality) to go against Chrysalis. The New Darling
at the time was the FV tool from Bell Labs EDA -- which Cadence later
bought. Maybe Chrysalis still mostly owns the formal verification market
with their Design Verifier equivalency checker? (See www.chrysalis.com)
Or maybe formal verification is more of an expensive EDA toy than a
required tool. All I know is that there is no external evidence that
Formality is being used by very many customers.
"Formal Verification:
A) Mike Barrett of ST Microelectronics - Formality
Good talk on applying Formality to 6 kinds of design problems (basic
synth, datapaths, backend, libraries, signoff, and migration).
Backend and migration are highest benefit. For migration, they
started with library cell compares and then higher level compares.
Positive feedback that formaility is easy to set up and use,
and debug. Still need tool experts on most runs he said, and
especially for debug. Worth it overall. Reduces gate level sims.
B) Chrystian Roy of LSI Logic - Formality
Wonder if he is any relation to Patrick Roy, the fabulous goalie of
my blessed Colorado Avalanche. Formality is the recommeded tool for
LSI's FlexStream process releases. Not required. 15 min to learn
gui. Good for gate to gate. RTL coming along. Scan bypass worked.
Clock tree bypass worked. Buffersize stuff worked. 650K gates with
hier took 3 hours & 1.16Meg mem. 800K gates flat took 30 min, but
tons of memory. Limits: multipliers, matching/finding compare
points, rtl to rtl.
C) ditched on 3rd guy. He was from ST Microelectronics as well. Looked
same talks. Saw a bit of David Black's Behavioral Compiler pitch.
Great as usual. Also saw some of Focus Enhancment pitch on run_proj
script. Great auto harness for simulation with hooks to cvs.
The one cool thing at the vendor faire was a new formal Verification
company called Verplex. Supose to blow the others away for speed and
memory uses."
- Peet James of Qualis Design
VOTING WITH THEIR FEET ON "SYNOPSYS II" A few years ago, Aart made a
lot of noise about chip designers needing to "move up to higher levels of
abstraction", which was a not-so-indirect pitch for customers to start
using Behavioral Compiler on top of Design Compiler. The idea was for
Synopsys to make scads of money from BC. The problem was that BC was, from
a customer point of view, a real 'dog' to use. I took the 5 day training
class for BC and half of it was spent managing DesignWare wrappers and
crap like that -- all to get a tool that would juggle around some adders
and multipliers for me. Jeez! It was far more easier to just structure
my Verilog/VHDL by hand to do the right thing, or, if I had time (and cash)
to tweak a design, I'd use the easy-to-run datapath compiler from Synopsys
called 'Module Compiler'. (To boot, no one back in Boston wanted to risk
using BC in their project!!) The Big Shiney Plastic Prize one was
supposed to get for opening the BC breakfast cereal box was BOA and BRT;
two very nice come-ons, but not worth the hassles & headaches of BC/DW.
So, like hiding the idiot uncle in the basement when guests visit, Synopsys
has wisely de-emphasized BC, moved BOA/BRT into DC-Ultra, and you now see
there are 18 Module Compiler classes for every 6 BC classes given at
Synopsys Corporate. At SNUG'99, for every 1 user in the BC tutorial, there
were 5.4 users in the DC tutorial. (This year Aart didn't mention BC.
Inside Synopsys, he's been hailing "Physical Synthesis" as the new
'Synopsys II'. He's wrong. BC was 'Synopsys II'. "Physical Synthesis"
is actually a 'Synopsys III'. BC didn't fail as a tool. It has its gaggle
of cult devotees, faithfully using it for their designs. BC just didn't
conquer the mainstream chip design world as it was supposed to.)
"A man's errors are what make him amiable."
- Wolfgang von Goethe, German poet/philosopher, 1749 - 1832
"BC analyzes the design based on user-specified throughput and latency
constraints, and will automatically generate state machines, muxes,
registers and other logic necessary to implement the desired behavior.
The tool also analyzes register longevity to minimize unnecessary
register usage by resource sharing, and also has the ability to map
a storage array to different types of memories, both on-chip and
off-chip. Control logic is automatically generated to accommodate
user-specified memory widths and access characteristics, as well as
automatically scheduling access to shared memories. With increasing
time-to-market pressures and increasing design complexity, a tool like
BC has the potential to significantly reduce our design cycle."
- Anon
"Their BC people tried some of that pushing up the abstraction level
in their talk. Success in this area still appears to be limited to
those companies w/ large amounts of time to devote to paving the way."
- Anon
"In my previous company, SGI, several designers, including myself,
evaluated Module Compiler for 6 months, and we came to the conclusion
that it was years ahead of any other similar tools on the market.
This is why we opted to purchase many licenses right away. It was
targeted for multi-million gates design with speed equivalent to
today's processors."
- Jean-Didier Allegrucci of Alpine Semiconductors in ESNUG 280
"I have been using Module Compiler since its early days (known back then
as SiArc's DataPath Architect) to build fast arithmetic and various
data paths structures. Something that Design Compiler was not, in my
experience, very good at achieving. The tool has improved a great deal
since then and has become an indispensable part of my design flow. MC
has been a great help in getting the best performance out of my
arithmetic structures (short of hand-designing it gate-by-gate). In
addition, it's great for analyzing precision vs. gate-count trade-offs
early in the design phase."
- Adrian Jeday of SGI in ESNUG 280
"In an ASIC design environment where time to market is top priority,
Module Compiler is *THE* tool to use for arithmetic pipeline designs.
It allows for very fast architectural exploration & early convergence
on an optimal design solution. While at SGI doing 3-D graphics chip
design, the team's use of MC helped to cut months off our design
cycle. ( We're using it for the same reasons here at NVidia.)"
- Bob Prevett of NVidia in ESNUG 280
WHERE'S WALDO? Remember 'HDL Advisor', that tool from a few years ago
that helped designers write better Verilog or VHDL for synthesis? It's
nowhere to be seen anymore. Guess it's a now forgotten One Hit Wonder.
DIVORCED? WE WERE NEVER MARRIED! Two years ago, like a beachcombing
sea gull, Synopsys gulped down the ViewLogic fish. This year (after
having digested Chrono VCS, Sunrise test, the MOTIVE customer base,
Roadrunner, and Quad Design), Synopsys has regurgitated the bones of a
stunted little ViewLogic that now only sells PCB and cheapie PC EDA.
TRAPPED IN YUGOSLAVIA There are two Synopsys product lines that are
trapped in ugly EDA war zones with lots of unfriendly 'questionable'
characters surrounding them. FPGA Express is trapped in a world where
it's fighting Synplicity and Exemplar for the 'high end' of an FPGA
market that's flooded with free (or virtually free) synthesis tools
from Xilinx and Altera. Synopsys VSS is trapped fighting Cadence
Leapfrog and a cheaper Model Tech for the 'high end' of an ever
cheapening VHDL sim market. (It's constantly being undermined by
the super-cheap/free VHDL simulators from Aldec, or ViewLogic, or the
$99 Cypress Warp.) You can't make a hell of a lot of money selling
cows when everyone is giving milk away for free.
"Right now we've got over 100,000 design sites (MaxPlusII & Quartus)
with customers. On a rough order of magnitude, Xilinx has a simular
number of seats. Fifty percent of our seats are 'free' and the other
fifty percent are 'purchased' seats. The 'free' versions only support
our proprietary Altera-HDL (A-HDL). Of the 50,000 'purchased' seats
about 15,000 of them support VHDL or Verilog. (All have A-HDL.) To
be honest, I couldn't tell you the exact split between VHDL or Verilog
with any certainty, because we really don't care, and support both
equally. However, qualitatively, I'd say 10,000 (10% overall) are
VHDL vs. 5,000 (5% overall) are Verilog."
- Robert Beachler, Sr. Director of Development Tools, Altera
HELP WANTED: Two years ago, ECO Compiler was a Secret Project that was
shown under NDA only to an exclusive group of Synopsys users at SNUG'97.
Last year, ECO Compiler was announced as a product. And since then, it's
been having some troubles in trying to help customers respin large
already placed & routed chips. Someone call 911!
"Our design process is to freeze everything for timing and to only
isolate one small part of the chip for ECO Compiler. We're talking
million gate designs here; re-synthesizing for small changes is
very costly. It took us 3 months to get ECO Compiler to work with
20 ECOs. Our problems were:
1.) Most of the tricks and effective ways to use it aren't
documented. It's a 20 Questions game to find this info.
2.) We regularly got fatal errors and it took a full day to
isolate and package the error before a Synopsys engineer
would work on it. Very time consuming.
3.) Designs won't align and we're stuck with no report why!
4.) Directives live forever. We'd sequentially process ECOs
and any old directive from the prior design would mess
with the design currently being ECO-ed.
5.) One case generated bad logic with two gate outputs tied
together. Synopsys has the test case.
6.) ECOs that involve hierarchy changes won't work. You have
have to create dummy cells to match old & new hierarchies.
7.) They can't handle multiple instances of sub-designs!
8.) There's no feedback about alignment statements being accepted
or doing anything. Statements don't always "take" so we have
to run eco_align 3 times to get them all.
9.) The eco_process cannot be scripted to run successfully from
start to finish. It requires too much manual intervention
and trial & error to get alignment scripts built for all of
the special cases encountered.
10.) Design Compiler gets indigestion doing an incremental compile
on designs output by ECO Compiler. We'd dont_touch everything
but the ECO itself and DC would triple buffer non-critical
paths (adding 200 ps) to improve a critical path by 20 ps
making the ECO unworkable.
We used ECO Compiler on a million gate chip. It worked and it was
worth it for that specific chip, but we didn't use it for any of our
other designs. It was too painful to use. Another division of Unisys
tried ECO Compiler and failed. They bit the bullet & had to re-synth
everything by hand. We've met w/ Synopsys R&D a few times over this.
They'd say that it would be easy to fix certain issues. I wished I
had written them down then, because a year later nothing changed. My
boss parlayed our ECO Compiler headaches into a PrimeTime license."
- Ken Merryman of Unisys
AN UNEXPECTED POWER SURGE: Tools for power analysis and even optimization
are coming of age in the EDA world. Power Compiler, Design Power, PowerGate
(all from Synopsys) and WattWatcher (Sente') are some of the gate level
power tools. Go to transisters and you can find EPIC's PowerMill and
ACE or Simplex's 'Fire & Ice' tools. Power is no longer a quirky, back
door problem -- it's become mainstream.
"I have used Power Compiler and saw substantial power reduction.
Briefly, one could get 15% power reduction but at substantial area
cost. By manipulating the cost function one could limit area penalty
for a lower power saving. For my test cases, I was able to get 10%
power reduction for 2% area penalty."
- Zia Khan of Intel in ESNUG 306
"This user paper was given by an employee of Motorola (Austin) and
described this user's experience using the Synopsys EPIC PowerMill,
with the ACE option, to simulate a PLL. This user paper won 2nd place
overall and was an excellent presentation of this user's "real world"
experiences using a new tool on a project with an extremely tight
schedule (he said he had 8 months to tapeout his PLL design). The
author presented what features of the tool he found useful, how the
tool compared in accuracy to MSSPICE (Motorola's version of Spice) - he
said the tools were within 5% of each other, and many lessons learned
using the tool. Knowing nothing about this tool, but knowing the
gotcha's of using any new tool, I found his presentation extremely
insightful as he clearly described to the audience the dangers of using
certain modes and switches of the ACE tool, and the consequences of
using these modes/switches. He described that the ACE tool was faster
than Spice by several orders of magnitude, but to achieve this
performance, the tool "ignores" certain capacitors and resistors whose
values are below some preset number. He told the users how to modify
these preset values so that they can properly simulate circuits which
may have elements that would otherwise be automatically deleted by the
tool. This was just one example of many useful tips the author
presented. The bottom line is that the author said that after he
learned how to use this tool, it allowed him to "almost" meet his
original schedule, a schedule he said he would have had NO chance of
meeting if he had to use Spice.
Although I don't plan on using ACE anytime in the near future, I
appreciated the usefulness of this paper to anyone who may be planning
on using the tool."
- Ken Banas of Basis Communications Corp.
"Zia Kahn (Intel) gave a Power Compiler presentation. One useful
idea was to measure the frequency of the nodes that toggle per clock
cycle. This is probably good for measuring the activity of a model
w.r.t. simulation speeds."
- Anon
"Lots of talk about Power Compiler and its ability to replace the
enable/disable of flip-flops with gated clocks. Real experiences
from users, what you need to do (i.e. you need a special cell in
the library). They reported power savings between 20% to 50%,
which is mouth watering."
- Oren Rubinstein of Gigapixel
"Power comes from the barrel of a gun."
- Mao Tse Tung, communist revolutionary, Chinese Emperor '49 - '76
IF YOU CAN'T BEAT THEM, BUY THEM: To understand the static timing analysis
market that PrimeTime lives in, just look at these Dataquest numbers:
Revenue ($M) Growth Market Share
1995 1996 1997 (%) (%)
-------------------- ------ ------------
Synopsys - 0.3 9.8 28.7 49.4
ViewLogic 5.0 7.3 - -
Cadence 2.3 5.0 6.4 29.1 32.4
Chronology 0.0 1.8 2.0 11.1 10.1
Mentor Graphics 1.0 0.4 0.1 -72.1 0.5
Other Companies 1.0 1.0 1.5 52.1 7.5
All Companies 9.3 15.7 19.8 25.8 100.0
(And these are just the 1997 numbers; it's rumored that the unreleased
1998 numbers give Synopsys a 55 to 65 percent market share!) With a
clever one-two punch, Synopsys grabbed the lion's share of this market by
developing PrimeTime plus buying the MOTIVE market share when it aquired
ViewLogic. The foundries are also backing PrimeTime with 6 of them (IBM,
LSI, TI, NEC, Fujitsu, Toshiba, and Samsung) publically accepting design
timing sign-off with PrimeTime. (Do a web search and you'll see them.
What's odd is that I couldn't find *any* foundries accepting Cadence Pearl
static timing sign-off. What's up with that?) The fact that there were
136 users at the SNUG'99 PrimeTime tutorial (with 8 of them standees)
plus the fact that PrimeTime comes up regularly in ESNUG discussions
confirms that there's quite a bit of customer interest in this tool.
"There's a general dissatisfaction with static timing analysis tools.
Users complain about the lack of asynch support. Pearl is getting
better reviews than PrimeTime but Cadence doesn't seem to be pushing
it, since Kuhoo [the Pearl mktng mgr] went on maternity leave.
There's a lot of interest, especially from the Nokias and Erickssons,
in the new Mentor offering (called Velocity SST, weird name) because
it can handle non-synchronous designs."
- Analyst Gary Smith of Dataquest
"Overall, I'm fairly happy with PrimeTime. Tcl isn't my favorite
language, and PrimeTime does fatal occasionally, but it is much better
than DesignTime. Also, I've been impressed with the hotline team's
knowledge and responsiveness. Whoever is running the PrimeTime show
over at Synopsys seems to really care about getting it right."
- Paul Zimmer of Cerent in ESNUG 315
HERE COMES THE SUN: Tirelessly feeding the demands of speed junkies,
along with a number of cycle-based ideas from Viewlogic's Roadrunner
technology, VCS 5.0 now incorporates a front-end parser that analyses
your entire design and performs global optimizations via flattening,
structuring, and more clever ticks to create a faster functional
equivalent of your simulation run. It's called "Radiant" and one
historically reliable source within Synopsys has told me that "with
the radiant in vcs 5.0 we see speedups from 10% to 6x at customer sites,
with a common ranges of 40% to 2x. these numbers are very design
dependant and work equally well for both rtl and gate level designs."
"Improvements Synopsys has made to VCS over the last eight months,
most notably the 5.0 version integrated with Radiant Design
technology, have sped up our simulations around 3X while requiring
no modifications to our Verilog source."
- Alex Silbey of SGI
"The paper was by 2 guys from Gigapixel (www.gigapixel.com) who
had a novel way of driving VCS simulations from a C test bench.
They were designing large graphics engines. They also had a unique
way of specifying the chip such that the drivers, hardware and
software could use the same programming model specification.
Their design environment consisted of dual Pentium II PC's running
Linux and some SUN's for VCS simulations."
- Anon
"By the year 2000, there'll no cycle-based simulators; they'll all be
incorporated within your standard Verilog/VHDL simulator. By the
the year 2001, there will be no Verilog/VHDL simulators, they'll
all be dual language, single kernal, sims like Model Tech's V-system."
- Analyst Gary Smith of Dataquest at DesignCon'99
"VCS : Mark Warren of Synopsys
- Great pitch on new VCS radiant technolgy. Basically VCS
is reducing and moving stuff all around to speed stuff up.
- Lots of great switches for VCS (here is a few)
-xrace-0x11 parses design and then makes a race.out file
during run to give list of possible race condition.
+alwaystrigger parses design and sets up sensitivity list
first to fix intializatioin compile ordering mismatches
dumpvar scripts (free inside $VCS_home/{system}/util
vcat perl to parse (vcat dump1.vcd -scope top.dut.moda)
gives ascii list of signal changes. Very useful on laptop
with no signalscan.
vcdiff compares two dumpvars.
Mark gave lots of code examples of classic Verilog problems with
solutions. He also admitted where VCS fell short."
- Peet James of Qualis Design
HISTORY REPEATS ITSELF: Towards the end of SNUG'99 there was serious talk
about doing another design contest like the infamous 'Verilog vs. VHDL'
contest I held back in SNUG'95. In it contestants "were given 90 minutes
using either Verilog or VHDL to create a gate netlist for the fastest fully
synchronous loadable 9-bit increment-by-3 decrement-by-5 up/down counter
that generated even parity, carry and borrow." Of the 9 Verilog designers
in the contest, only one, Oren Rubenstein, didn't get a final gate level
netlist because he tried to code a look-ahead parity generator. Of the 8
remaining, 3 had netlists that missed on functional test vectors. (Kurt
Baty "claims" he "misfiled" his final results.) The 5 Verilog designers
who got fully functional gate-level designs were:
Larry Fiedler NVidea 3.90 nsec 1147 gates
Steve Golson Trilobyte Systems 4.30 nsec 1909 gates
Howard Landman HaL Computer 5.49 nsec 1495 gates
Mark Papamarcos EDA Associates 5.97 nsec 1180 gates
Ed Paluch Paluch & Assoc. 7.85 nsec 1514 gates
Of the 5 VHDL designers in the contest, *none* of the 5 succeeded in
getting their VHDL based designs to gates. -- and this caused all sorts
of reactions in the Verilog vs. VHDL wars.
What's being kicked around now is doing *another* 90-minute design
contest next year at SNUG'00. My problem is exactly *what* would be
a good, interesting problem for that contest?
"Yea! I want another chance to redeem my honor!"
- Oren Rubinstein of Gigapixel
"A followup on our lunchtime discussion. The problem is too little
time to work on an interesting design. But how about giving a
design that needs to go faster and has bugs in it? This may make
up for the difficulty in describing complex designs.
Maybe not bugs, but enhancements, more filter coefficients, more
memory or something like that. It would represent some of the
support issues that happen in real life.
To be really authentic, the testbench should have bugs too; but
that may be too hard again."
- Larry Fiedler of NVidea
"Those who cannot remember the past are condemned to repeat it."
- George Santayana, American philosopher, 1863 - 1952
The 1999 Synopsys Report Card
-----------------------------
So, from a customer's viewpoint, Synopsys appears to only be messing up on
mostly small potatoes. VERA needs more user exposure. VSS, FPGA Express,
(and apparently Formality) are in a ugly fragmented markets. Behavioral
Compiler didn't conquer the world as it was supposed to. ECO Compiler
needs 911. Protocol Compiler and HDL Advisor are playing "Where's Waldo?".
The Synopsys upper management decided to blow-off hobnobbing with the lowly
end users at SNUG this year. And we all grumble about Tcl.
On the upside, Synopsys seems to be doing very well with the big ticket
issues. Design Compiler is wildly popular and DC'99 is better than ever.
PrimeTime and Test Compiler dominate their markets. Module Compiler
groupies are ecstatic. VCS is bitch'n hot with 3X speed-up Radiant and
going to Linux. Power tools are undergoing a surge with customers. There
appears to be far more EPIC users than any of us ever expected. Eaglei
seems to be matching it's biggest rival, Seamless. The DW Foundation
library is growing. They just announced some new IP delivery tools. The
techno-nitpickers (Synopsys CAE's, R&D, tech support) were seen everywhere
at SNUG. And we have three serious customer benchmarks confirming that
'physical synthesis' is something *real* with the new Chip Architect tool.
Overall, Synopsys seems to be doing very well technologically this year.
I wish to publically thank Renae Cunningham of Synopsys (who did all the
behind the scenes organizing within Synopsys, Inc. to make SNUG'99 happen)
and the SNUG'99 Chair, Don Mills of L3 (who made sure everything in SNUG'99
was user-driven instead of Synopsys-Marketing-driven!) These two did an
awful lot to make SNUG successful this year. Great job!
And I'm now stuck brainstorming a new Design Contest for next year... :(
- John Cooley
the ESNUG guy
P.S. If you agree/disagree/have-violent-reactions with anything in this
trip report, please feel free to send me a reply! I love reader feedback!
===========================================================================
Trying to figure out a Synopsys bug? Want to hear how 6,000+ other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
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