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Rolf Aengenendt wrote: > We have the following problem concerning configuring Xilinx FPGA's > (XC4000E): > > We have a pcb using one main LCA Xc4010 and an additional (optinonal) LCA > device, which is only used and mounted in special cases. The devices are > configured in slave daisy chain mode by a microcontroller, so the "dout" of > the main LCA is connected to the "din" of the optinonal LCA and the other > controll-lines (done, prog, cclk) are connected together and routed to one > port of the mic. > > Until now, only the main LCA was placed on the pcb and so the mic saw only > one device. However, when you use two devices in chain, the xilinx prom > formatter builds *one* program mcs-file. But what we want to have are two > independent files, so while the system startup is going on, the mic could > decide weather to program only the main LCA, or -when present- build the > data stream for the main and the optional LCA on its own and program the > both devices. > > So we would link two independent mcs or binary LCA-files to our mic-code > (firmware) > > Does anybody have an idea how to create the combined bitstream? > > Thx a lot > > Rolf Aengenendt > > _______________________________________________________________ > Rolf Aengenendt, Lumino GmbH, Krefeld, Germany > fon: +49-2151-8196-76 fax: +49-2151-8196-6676 > mailto:raengen@lumino.de > internet: http://www.lumino.de Hello The xilinx prom formatter permit you to create 2 bitstreams. The first bitstream will contain only the bit file of the main LCA. The second bitstream will contain the 2 bit files (main and optionnal LCA) Your mcs-file will contain the 2 bitstreams. I have never try this but this should work. I guess that you will need an parallel prom to store your mcs-file. You will download the prom from either the first address of the first bitstream or the first address of the second bitstream depending of your case. If your data pass through the microcontroller before going to the LCA, may you can use a serial prom by downloading the first bitstream inside the microcontroller without sending it to the LCA when you want to use only the second bitstream. You will output only the second bitstream outside the microcontroller in this case. The difficulty is to find when the second bitstream start in the serial prom. Hope this helps, Michel Le Mer Gerpi sa (Xilinx Xpert) 3, rue du Bosphore Alma city 35000 Rennes (France) (02 99 51 17 18) http://www.xilinx.com/company/consultants/partdatabase/europedatabase/gerpi.htmArticle: 16126
>Rolf Aengenendt wrote:
>>
>> We have a pcb using one main LCA Xc4010 and an additional (optinonal) LCA
>> device, which is only used and mounted in special cases. The devices are
>> configured in slave daisy chain mode by a microcontroller, so the "dout" of
>> the main LCA is connected to the "din" of the optinonal LCA and the other
>> controll-lines (done, prog, cclk) are connected together and routed to one
>> port of the mic.
>>
>> Until now, only the main LCA was placed on the pcb and so the mic saw only
>> one device. However, when you use two devices in chain, the xilinx prom
>> formatter builds *one* program mcs-file. But what we want to have are two
>> independent files, so while the system startup is going on, the mic could
>> decide weather to program only the main LCA, or -when present- build the
>> data stream for the main and the optional LCA on its own and program the
>> both devices.
>>
>> So we would link two independent mcs or binary LCA-files to our mic-code
>> (firmware)
>>
>> Does anybody have an idea how to create the combined bitstream?
>>
=3D=3D Urspr=FCngliche Mitteilung von Brian Boorman <XZY.bboorman@harris.com> am
4.05.99 15:48
>Urspr=FCngliche(r) Empf=E4nger:
>An: News:mail.lumino.de/comp.arch.fpga
>
>It is not as easy as just concatenating the two bitstreams. There is
>information at the beginning of the combined bitstreams that tell the
>first FPGA in the chain that it needs to continue clocking data after
>it is done and send the data to the second device. I believe that part
>of this is the length field in the first bitstream.
>
>I would suggest reading the Xilinx databook for your devices in
>particular the section on configuration and daisy chaining. Xilinx
>support should also be able to help.
>
>By the way, why not just always send the combined bitstream. If done
>properly the board can be wired so that the first FPGA doesn't care
>if the second one is there or not, just always spits out the data on
>the DOUT pin. Your only penalties are the increased time and memory
>requirements for the case of only one FPGA.
>
Thanks for the information, but we definitely would like to know how the
combined bitstream is made up.
One cause is that we want to have the uP software that performs the loading
of the FPGAs extract the length information from the bitstream(s) with. The
other, more important, cause is, that the two FPGA programs are created with
different software tools ("XDE" and "Foundation M1.5") and we have no idea
how to combine the output of those to a single bitstream.
_______________________________________________________________
Rolf Aengenendt, Lumino GmbH, Krefeld, Germany
fon: +49-2151-8196-76 fax: +49-2151-8196-6676
mailto:raengen@lumino.de
internet: http://www.lumino.de
Article: 16127Hai, I am research fellow from India. For one of my VHDL project I need a reciprocator. Like If I give Input 10, The out put should be 1/10 that is 0.1, For 3 it should be 0.33. For this I need a VHDL code, or implemented FPGA. This should be true for all numbers. Any suggestion or code is highly appreciable. Thanks in advance. Please communicate to my email:satish_me@hotmail.com -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 16128
Am I missing something here? Why not just set the mode pins for master parallel-up mode, connect the address & data lines and control lines properly and let the thing configure directly from the EPROM? Andy Peters wrote: > > Actually, Xilinx has an app note at http://www.xilinx.com/xapp/xapp079.pdf > that does just what you ask - it's called VSPROM, written in ABEL. It > targets the XC9536 and uses standard EPROMS. It also uses every macrocell > in the 9536. > <snip> > -- andy > ------------------------------------------ > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatories > 950 N Cherry Ave > Tucson, AZ 85719 > apeters@noao.edu -- Brian C. Boorman Harris RF Communications Rochester, NY 14610 XYZ.bboorman@harris.com <Remove the XYZ. for valid address>Article: 16129
How many bits accuracy do you need?, what is bit width of the input and output?. What is the required data rate and the available clocks (ie. how many clocks are allowed to do this). These parameters will greatly affect the implementation. satish_me@hotmail.com wrote: > Hai, > I am research fellow from India. For one of my VHDL project I need a > reciprocator. Like If I give Input 10, The out put should be 1/10 that is 0.1, > For 3 it should be 0.33. For this I need a VHDL code, or implemented FPGA. > This should be true for all numbers. > Any suggestion or code is highly appreciable. Thanks in advance. > Please communicate to my email:satish_me@hotmail.com > > -----------== Posted via Deja News, The Discussion Network ==---------- > http://www.dejanews.com/ Search, Read, Discuss, or Start Your Own -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 16130
Lars Rzymianowicz <larsrzy@ti.uni-mannheim.de> wrote:
>John Cooley wrote:
>> THE BASEMENT IS FLOODING: One of the bigger announcements Synopsys
>> made at SNUG'99 was the how they intended to keep adding more and more
>> parts to the basic Designware Foundation library. That is, as a piece
>> of IP becomes more mainstream in useage, Synopsys is just going to
>> automatically add it to the Foundation at no extra cost to users. In
>> this vein, Aart annouced that the DW PCI core and the DW 8051 were now
>> part of the DW Foundation library -- free to anyone already using that
>> library. This effectively means it's free to anyone using Design
>> Compiler due to its close ties to the DW Foundation lib! Way cool!
>
>Hi!
>First: Thanks for this "assembled newsletter" from SNUG99, John. Good job!
>
>A lot of good news, especially the one above: the DW PCI core models
>royalty-free in the Foundation lib. Great! But i couldn't find them
>mentioned in the Synopsys news about the new DW features in 1999.05.
>Will they appear in a later release?
>
>Lars
Lars, I don't know the details other than the fact that Synopsys was putting
the DW 8051 and DW PCI cores into the DW Foundation library. As far I as I
know, yes, this does mean they're royalty-free (because everything in the
DW Foundation lib is royalty-free) but that doesn't mean they're completely
free. You still have to *buy* the DW Foundation lib, if you want to use
it. (Most DC users do buy it, though.)
- John Cooley
the ESNUG guy
============================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 6000+ other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 16131Not at all :-). This design synthesizes to 9KG of .35u standard cell; the delay is reported at 80+ MHz and the FPGA at 40K gates /20MHz is only a prototype. Ray Andraka <randraka@ids.net> wrote: >why are you getting such poor performance? Are you bothering to design to the >architecture even a little bit? muzo Verilog, ASIC/FPGA and NT Driver Development Consulting (remove nospam from email)Article: 16132
Carl,
Thanks a lot. Since pulse_int was an internal signal (i thought I
made an attempt with it as an actual inout with a pin assignment) and
not used yet by another process, the compiler was over optimizing. I
can't thank you enough. I just started writing VHDL code for FPGA's
(I've only done simple PLD's before, and just wanted to get the first
process working. You saved me a lot of head scratching.
Garrick
Carlhermann Schlehaus wrote:
>
> Hi,
>
> > I am using the latest Altera compiler.
>
> Okay, let's have a look at the code:
>
> > ....
> > signal pulse_int : std_logic;
> >
> > begin
> >
> > pulse_chk: process (clk_0)
> > variable int_cnt : natural := 0;
> > begin
> > if rising_edge(clk_0) then
> > int_cnt := int_cnt + 1;
> > if int_cnt < 3000 then
> > pulse_int <= '0';
> > else
> > pulse_int <= '1';
> > int_cnt := 0;
> > end if;
> > end if;
> > end process pulse_chk;
> > ...
> >
>
> One thing I could imagine is, that perhaps you never use the 'pulse_int'
> signal in any other process or e.g. use it as an output. Altera compiler is
> very radical in reducing the logic, so if you generate the 'pulse_int' using
> the code above and do not use the 'pulse_int' anywhere in your design, the
> complete (above stated) code is ignored.
>
> As the variable 'int_cnt' is able to be counted to values greater 3000 the
> 'else' clause should execute, otherwise the process wouldn't do anything and
> would also be reduced to no code...
>
> Hope this helps, Carlhermann
Article: 16133Brian Boorman wrote in message <37303D7C.C1C62E47@harris.com>... >Am I missing something here? Why not just set the mode pins for master >parallel-up mode, connect the address & data lines and control lines >properly and let the thing configure directly from the EPROM? I'm using almost all of the I/O pins on the XC4005. For my current design, I've had to design three PCBs. Two of them have a single 4005; the third has two 4005s with identical configurations. The largest FPGA design fits into a 4005 and I figured that it was easier to order one part type and have extra space in the other FPGAs rather than ordering three different part types. Especially since my quantities are low - we're building only one instrument! Xilinx doesn't do me any favors in the quantity discount department... One of the designs is so simple that it DOES configure directly from the EPROM in master parallel mode. The other two designs use enough of the I/O to make parallel loading impossible. I'd thought about leaving space on the board for a serial PROM but I decided that it wasn't necessary. -- a ------------------------------------------ Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatories 950 N Cherry Ave Tucson, AZ 85719 apeters@noao.edu "Space, reconnaissance, weather, communications - you name it. We use space a lot today." -- Vice President Dan QuayleArticle: 16134
On 04 May 1999 18:00:34 PDT, muzok@nospam.pacbell.net (muzo) wrote: >that maybe true but it is irrelevant on two fronts. One is I have a >board for 10K already and I am not getting the speed I need out of >Virtex anyway. I tried v200fg456-4 part with my design and I got only >14.5 MHz with LeonardoSpectrum Level 3 (I don't have Synplify Xilinx >mapper) whereas I get 22.5 MHz from 10K100ABC600-1. I need at least 20 >MHz on this design. OK, Altera it is, but a few questions/comments. 1, You compare Altera's fastest with Xilinx's slowest 2, Is that figure post P&R or Spectrum's estimate? You may find Spectrum's timing estimates _highly_ pessimistic at the moment. 3, Comparing prices: EPF10K100ABC600-1 $581.45 each (Arrow) V200BG352-4 $246 each (Insight) V200BG352-5 $344 each (Insight) OK, so it's only for prototyping, but if cost wasn't the issue, how about an XCV1000-6BG560C at $5731 each from Insight? 4, I wonder what speed you would have gotten with a -6 post P&R? 5, Speaking from personal experience, and customer feedback, I have (up until just now) yet to see a Virtex design that didn't beat the fastest Altera have. Now that may be because too few people looked at Altera, or didn't drive tools right etc. etc. but that's the info I have. I guess I'll chalk your design up as one to Altera ;-) If anyone has some different facts, then please let me know. Cheers Stuart For Email remove "NOSPAM" from the addressArticle: 16135
Three reasons come immediately to mind:
1) Spartan devices don't support the parallel programming modes, wo if the
design is to be migrated don't do it.
2) Parallel mode configurations use lotsa pins. If the design is not pin
limited or has a bus that can be shared for the parallel load and you want to
put up with the pin assignment/multi-mode issues then great.
3) Parallel master mode is no faster than the serial master. Master modes
rely on the relatively slow internal configuration clock. By going to one of
the slave modes, you can configure faster, and you can configure several devices
in parallel rather than relying on the daisy chain. The slave peripheral
(parallel) mode is broken in some of the older devices. Specifically, the
4025Es before a date code about 2 years ago won't load in peripheral slave mode.
Brian Boorman wrote:
> Am I missing something here? Why not just set the mode pins for master
> parallel-up mode, connect the address & data lines and control lines
> properly and let the thing configure directly from the EPROM?
>
> Andy Peters wrote:
> >
> > Actually, Xilinx has an app note at http://www.xilinx.com/xapp/xapp079.pdf
> > that does just what you ask - it's called VSPROM, written in ABEL. It
> > targets the XC9536 and uses standard EPROMS. It also uses every macrocell
> > in the 9536.
> >
> <snip>
> > -- andy
> > ------------------------------------------
> > Andy Peters
> > Sr. Electrical Engineer
> > National Optical Astronomy Observatories
> > 950 N Cherry Ave
> > Tucson, AZ 85719
> > apeters@noao.edu
>
> --
> Brian C. Boorman
> Harris RF Communications
> Rochester, NY 14610
> XYZ.bboorman@harris.com
> <Remove the XYZ. for valid address>
--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka
Article: 16136What tool are you using for synthesis? I do this all the time with FPGA Express and Xilinx M1.x and never experience any problems. Lars Fomsgaard wrote: > Hello world > > I have the following problem with the netlister in the Foundation software > from Xilinx: > > In my VHDL-code I have defined an input as an 8 bit bus, but in the design > I only use the 7 most significant bits (at least after the last > modification). During syntax check and synthesis I get no warnings or > errors, during implementation the program terminates due to an unused > input. > > .... > > Thanks > LarsArticle: 16137
Xilinx has an app note detailing how to perform this function with a PLD (no software needed for a uC). I assume that other vendors would also have a similar app note. Todd Gary Desrosiers wrote: > Instead of the OTP 17256 PROM for config, I was thinking of using an old > 27256 EPROM. This way, an ordinary EPROM programmer could be used, yes? I > was also thinking of an uC to translate into appropriate serial sigs. Has > anyone done this before? > > Why the hell don't these manufacturers use standard I2C EEPROM? There has to > be a reason! > > GaryArticle: 16138
Hello, i am working on a small project using the 'Altera University Program'-board on which you can connect an PS/2-mouse. I have made a lot of research on the web, but i couldn't find the result on this question : do you need to initiate the mouse first before youcan start using it. In other words : do you first have to send some data (and which) to the mouse before the FLEX can receive data ? Tnx, a student pascal.buseyne@village.uunet.be PS : i know this hasn't almost no connection with FPGA's but maybe somebody has experiences with itArticle: 16139
Is there a source which might have a caveat list regarding bugs with latest place and route software for XLINX? I have heard of one user seeing problems with two nodes driving the same net after place and route. Maybe the list would have work-arounds. I can't imagine doing hand routing of CLBs anymore, or is that in fashion again? Past information indicates that other issues came up with tools and took pain to work around.... schedule delays.... etc.. No new release of s/w until June. Thanks. Have ASIC will travelArticle: 16140
Dear fellows, I am trying to implement an interface module between the 8 bits ISA bus standard and a modified version of 32 bits 80386 CPU bus. Currently I use the MAXPLUS II 9.01 patched to 9.04 to compile my VHDL design of the target interface module. I have lots of troubling in implementing the bus interface since the MAXPLUS II 9.01 for PC reports so many internal error(which means their bugs unhandled). Many of the errors are related to bit slice handling and 32 bit bidirectional data bus handling etc. Do you recommend the Altera MAXPLUS II 9.01 as a VHDL compiler for Altera FPGA implementation of your VHDL design? (I use Altera's EPF10KA50VBC356-2 FPGA) If not, what else can you recommend? I'd like to hear from you. With regards, YoungArticle: 16141
If you use pin locking in UCF file, how about to comment out for unused input pin. >In my VHDL-code I have defined an input as an 8 bit bus, but in the design >I only use the 7 most significant bits (at least after the last >modification). During syntax check and synthesis I get no warnings or >errors, during implementation the program terminates due to an unused >input.Article: 16142
ymlee schrieb: > > Dear fellows, > > I am trying to implement an interface module between > the 8 bits ISA bus standard and a modified version of 32 bits > 80386 CPU bus. > > Currently I use the MAXPLUS II 9.01 patched to 9.04 to compile > my VHDL design of the target interface module. > > I have lots of troubling in implementing the bus interface since > the MAXPLUS II 9.01 for PC reports so many internal error(which > means their bugs unhandled). > > Many of the errors are related to bit slice handling and 32 bit > bidirectional data bus handling etc. > > Do you recommend the Altera MAXPLUS II 9.01 as a VHDL compiler for Altera > FPGA implementation of your VHDL design? > (I use Altera's EPF10KA50VBC356-2 FPGA) > > If not, what else can you recommend? > > I'd like to hear from you. > > With regards, > > Young If you use relatively simple constructs, yes. If you want to use the full power of VHDL, better use Design-Compiler to generate a primitive Netlist in VHDL, and export this to MAX2 for fitting.Article: 16143
John Cooley wrote: > Lars, I don't know the details other than the fact that Synopsys was putting > the DW 8051 and DW PCI cores into the DW Foundation library. As far I as I > know, yes, this does mean they're royalty-free (because everything in the > DW Foundation lib is royalty-free) but that doesn't mean they're completely > free. You still have to *buy* the DW Foundation lib, if you want to use > it. (Most DC users do buy it, though.) > - John Cooley > the ESNUG guy That's clear. My question was: When will the 8051 and PCI core be part of the DW Foundation Lib? Are they available yet? Will they be added to the current 1999.05 version? Or will they appear in the next major release? I searched the Synopsys DW webpages, but couldn't find any news about it. Any infos about this? I can't wait to get my hands on the PCI core... ;-) Lars -- Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/Article: 16144
Hi, I'm looking for some kind of socket or other tool for bga device. Actually, I'm wondering how other people deal with BGA devices as well. regards romanArticle: 16145
On Thu, 06 May 1999 07:55:18 +0200, Emil Blaschek <emil.blaschek@siemens.at> wrote: >If you want to use the full power of VHDL, > better use Design-Compiler to generate a primitive Netlist in VHDL, > and export this to MAX2 for fitting. ROTFL !!!! Stuart For Email remove "NOSPAM" from the addressArticle: 16146
roman pollak <roman.pollak@Sun.COM> wrote in message news:373197BB.7986C450@Sun.COM... > Hi, > > I'm looking for some kind of socket or other tool for bga device. > Actually, I'm wondering how other people deal with BGA devices as well. Haven't used sockets since PGA. Solder them direct and get the board right first time. -- Stephen Maudsley mailto:Stephen.Maudsley@esgem.com Esgem Limited: embedded system design http://www.esgem.com Tel: +44-1453-521626 Mobile: +44-370-810991 Personal pages: http://www.esgem.com/people/Stephen.MaudsleyArticle: 16147
In article <373197BB.7986C450@Sun.COM>, roman pollak <roman.pollak@Sun.COM> wrote: > Hi, > > I'm looking for some kind of socket or other tool for bga device. > Actually, I'm wondering how other people deal with BGA devices as well. > > regards roman > I've never used the following product, but I am looking for bga prototyping devices also and I found a few web sites. You may want to check out this web site. http://www.emulation.com/catalog/off-the-shelf_solutions/prototyping_adapters/ I remember coming across a few other web sites but I disremember the addresses Craig Jacobs Automotive Systems Labs -----------== Posted via Deja News, The Discussion Network ==---------- http://www.dejanews.com/ Search, Read, Discuss, or Start Your OwnArticle: 16148
craig_jacobs@asl-tk.com wrote: > > In article <373197BB.7986C450@Sun.COM>, > roman pollak <roman.pollak@Sun.COM> wrote: > > Hi, > > > > I'm looking for some kind of socket or other tool for bga device. > > Actually, I'm wondering how other people deal with BGA devices as well. > > > > regards roman > > > > I've never used the following product, but I am looking for bga prototyping > devices also and I found a few web sites. You may want to check out this web > site. > > http://www.emulation.com/catalog/off-the-shelf_solutions/prototyping_adapters/ > > I remember coming across a few other web sites but I disremember the addresses > > Craig Jacobs > Automotive Systems Labs > Thanks, This exactly what I'm looking for. Any Idea about Prices ? regards romanArticle: 16149
Stephen Maudsley wrote in message <7gsd3h$sei$1@plutonium.btinternet.com>... > >roman pollak <roman.pollak@Sun.COM> wrote in message >news:373197BB.7986C450@Sun.COM... >> Hi, >> >> I'm looking for some kind of socket or other tool for bga device. >> Actually, I'm wondering how other people deal with BGA devices as >well. > >Haven't used sockets since PGA. Solder them direct and get the board >right first time. Amen. BGA, it takes balls...
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