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I need make a PWM in a cpld (abel code) TKS in advancedArticle: 23276
Rickman wrote in message <394ED629.7FE21705@yahoo.com>...
>I guess I was thinking that using the CE vs. might save power rather
>than asking if it used more power. But it sounds like the two methods
>are equivalent.
>
>From my past experiences, if you are doing HDL design, it can be hard to
>control whether the CE is used or not. Or in some cases like with FPGA
>Express which is the packaged VHDL compiler in the Foundation package,
>the CE can be overused. I found that if you put any type of conditional
>logic (if statements) inside the "if (risingedge(xxx))...endif"
>statement it would turn those other if statements in logic feeding the
>CE input. So it was not always easy to control when the CE got used or
>not.
>
>So if there is little difference in power consumption, I will structure
>all of my code to not use the CE unless I see a clear advantage in speed
>or LUT usage.
Rick,
What don't you like about the clock enable?
Given code like:
flop : process (clk, reset) is
begin
if reset = '1' then
q <= '0';
elsif rising_edge(clk) then
if enable = '1' then
q <= d;
end if;
end if;
end process flop;
the recirculating mux controlled by enable (CE) is what retains the value of
q when enable is not asserted. Don't forget that ALL of the Xilinx flops
have this mux -- not explicitly designating a clock enable signal implies
that the clock enable is always tied active.
The timing analyzer takes the mux delay into account.
-- andy
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 23277Hi, A FF even if it "see" the same input level does consume power as long as there is a clock. The only way to reduce the power of a group of FF's is by shuting down their clock meaning using clock enable. One example for using clock enable is for stand by purpose in cellualr phone, where the power source (battery) is limited. have a nice day Illan In article <394ED629.7FE21705@yahoo.com>, Rickman <spamgoeshere4@yahoo.com> wrote: > I guess I was thinking that using the CE vs. might save power rather > than asking if it used more power. But it sounds like the two methods > are equivalent. > > From my past experiences, if you are doing HDL design, it can be hard to > control whether the CE is used or not. Or in some cases like with FPGA > Express which is the packaged VHDL compiler in the Foundation package, > the CE can be overused. I found that if you put any type of conditional > logic (if statements) inside the "if (risingedge(xxx))...endif" > statement it would turn those other if statements in logic feeding the > CE input. So it was not always easy to control when the CE got used or > not. > > So if there is little difference in power consumption, I will structure > all of my code to not use the CE unless I see a clear advantage in speed > or LUT usage. > > Peter Alfke said in an email... > > CE-inputs in Xilinx FPGAs really do nothing to the clock. They control > > a multiplexer in front of the D input, so that the flip-flop loads its > > existing value. Thus there is no advantage in implementing CE in a LUT > > (and CE saves you either one or two LUT inputs ). > > > > XC4000, Spartan, and Virtex global clocks ar distributed along a > > horizontal "spine" with "ribs" going up and down in each column. The > > software is smart enough to drive a rib only if there is a clock > > destination in this column. Vertically aligning register etc banks can > > thus save power, and the carry structure automatically enforces that > > kind of alignment for counters and accumulators. > > > > Peter Alfke, Xilinx Applications > > ================================================ > > Rickman wrote: > > > > > On this issue, I have never figured out about using the CE vs. gating > > > the input with the LUT. Is there a difference in power consumption in > > > the two cases? That is does a FF use any more power if it is enabled, > > > but the input is the same as the current output so that it does not > > > change state? > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23278
--------------D4C4C136FDE5FA98D1F6D257
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit
This is what I just received from our databook-CD master.
Peter Alfke, Xilinx Applications
Xilinx Databook CD ROM Solutions.
We are presently working on a new method of creating a CD ROM
and will not be using the current/old "browser" mapping on future CDs.
An easy and quick fix. Post this somewhere for everyone to use:
When the CD ROM starts up, hit the 'ESC' key.
this stops the CD ROM from loading anything.
Then open the CD using Windows explorer.
Double-click on the databook.htm file and open with your browser
or double-click on the databook.pdf file and open in Adobe Reader.
Please post this infomation.
--------------D4C4C136FDE5FA98D1F6D257
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
This is what I just received from our databook-CD master.
<br>Peter Alfke, Xilinx Applications
<br>
<h2>
Xilinx Databook CD ROM Solutions.</h2>
<p><br>We are presently working on a new method of creating a CD ROM
<br>and will not be using the current/old "browser" mapping on future CDs.<b></b>
<p><b>An easy and quick fix. Post this somewhere for everyone to use:</b>
<p>When the CD ROM starts up, hit the 'ESC' key.
<br>
this stops the CD ROM from loading anything.
<br>Then open the CD using Windows explorer.
<br>Double-click on the databook.htm file and open with your browser
<br>or double-click on the databook.pdf file and open in Adobe Reader.
<p> Please post this infomation.
<br> </html>
--------------D4C4C136FDE5FA98D1F6D257--
Article: 23279One of the reasons the Spartan-II datasheet is protected (a feature of the datasheet) is to prevent anyone from making changes and mis-representing the specs. The hotline can send you an un-protected datasheet upon request or, if you would like the security password send me an email. Please include the reason that you would like to be able to do the copying. My email is robert.binkley@xilinx.com. Is there a better way or format that you would prefer to have the data? A new rev of the Datasheet is due out soon, so keep your eyes open. Robert Rick Collins wrote: > I noticed something about the Spartan II data sheet that I have only > seen in a few other PDF files before. I can not use the text cursor to > select and copy text from this document. Is something unique to my > computer and this data sheet, or does everyone have this problem? I have > done a quick check and found that I also have this problem with the > Spartan XL data sheet but not most of the other Xilinx data sheets. > > If this is a feature of the data sheet and not of my computer, does > anyone know if this is an accidental glitch or if Xilinx intended it? I > can't imagine why anyone would want to disable a text copy feature when > the data is available in the data sheet. Is there some feature that I am > missing in Acrobat? > > If anyone from Xilinx who could do something about this is reading, the > text copy feature is very useful in data sheets. If this is not my > machine, but rather a data sheet related issue, can you please turn it > back on in the next issue? > > -- > > Rick Collins > > rick.collins@XYarius.com > > remove the XY to email me. > > Arius, Inc. - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.comArticle: 23280
Eric, The 5 V Spartan devices may not be reliable at 2.5V, the power on reset trip voltage is set in the area of 2 V however it varies quite a bit from production lot to production lot. The 3 mA quiescent current spec for the Spartan devices is padded a little however it is very close. We would recommend that you look at the Spartan-XL for this type of application as it will work correctly (however slower) at 2.7V and probably down to your desired 2.5V. The current spec on the Spartan-XL device does not reflect where the device actually performs but reflects where the production test limits had been set. We have done a lot of testing and characterization here and have found the devices run more like 100-500 uA. If you need more info, send me an e-mail and I can get you some curves showing the Spartan-XL characteristics over temp and voltage. Rick Mitchell Spartan Apps Eric wrote: > Hi, > > I could not find any information about the behaviour of 5 V Spartan devices > regarding operation with battery backup. > > Namely, here's what I'm looking for : > > - does a 5V Spartan device reliably retain data at 2.5V (lithium cell / 2x AAA alkaline > battery at end of life voltage) ? > > - retention current specs (using the latest V1.5 data sheet) is somewhat unclear: > on page 36, it says max quiescent current (commercial temp) is 3 mA, with no typical > value. on page 45 (about 3V XL parts) it says that max current is 5 mA (typ 100uA), > and is the same with or without power down mode acrivated (?). > Looks strange that a 3v device with a "low power" mode might have a quiescent current > nearly twice as large as a similar 5V device. > So what are the real values, and what can be typically expected from a 5V unit backup > powered by a 3V cell ? > > - If the design does not use the internal oscilator (OSC4), is it disabled after configuration > and thus reduce consumption ? > > - What is the current consumption of an unconfigured Spartan ? does it help to keep > the "PROGRAM" input low (despite the pullup), is it better to keep "INIT" low ? > > During the time that the device is in battery backup mode, the chip goes idle (no internal > switching occurs) and all power preserving measures are taken (such as using "tie" option, > making sure all levels are clearly defined, etc ...) > > Any data (or your experience if you already designed a battery backed system with a 5V > Spartan device) would be greatly appreciated. > > Eric.Article: 23281
Try to floor plan for best flow (assuming DSP app) All nodes that change state uses power, longer wires use more than short. If the wire segment is shorter or has less loading from routing switches due to better floorplan you save power without changing the underlying logic. I once did this and to my surprise cut power by 50%. (that was probably extreme but anyway) :-) Harald Domagoj wrote: > > Hi, > I wonder, how could I decrease the power disipation in FPGA ? > Which methods are used mostly ? > > thanks, > ------------------------------------------- > - Domagoj - > - Domagoj@engineer.com - > -------------------------------------------Article: 23282
LOL!!! I know that FPGA marketing types are pretty ruthless, but I doubt that that even the slimiest would stoop to forging sub-par data sheets from the competition - the risks of getting caught are just too great. regards, tom Robert Binkley wrote: > > One of the reasons the Spartan-II datasheet is protected (a feature of the > datasheet) is to prevent anyone from making changes and mis-representing the > specs. -- Tom Burgess Digital Engineer Dominion Radio Astrophysical Observatory P.O. Box 248, Penticton, B.C. Canada V2A 6K3Article: 23283
Robert Binkley wrote:
>
> One of the reasons the Spartan-II datasheet is protected (a feature of the
> datasheet) is to prevent anyone from making changes and mis-representing the
> specs.
There is more control possible :
Adobe lists these options under Document Security
( This selects/copies OK, but is a Philips Data sheet, not a Xilinx one
:-)
Printing : Allowed
Changing the Document : Not allowed
Selecting Text and Graphics : Allowed
Adding or changing annotations and form fields : Not Allowed
So the obvious solution is to set the same rules for Xilinx Datasheets ?
- jg
Article: 23284Harald Vefling wrote: > Try to floor plan for best flow (assuming DSP app) > All nodes that change state uses power, longer wires use more than > short. If the wire segment is shorter or has less loading from routing > switches due to better floorplan you save power without changing the > underlying logic. A similar idea, but easier to implement: If your design is relatively slow ( and many battery-operated systems are) then use overly aggressive timespecs, forcing the software to generate a much "better" design than really required. That means shorter interconnects, less capacitance and thus lower power. Who says you have to be fair to the software? Make it work hard, and prevent it from spreading out the design, which it loves to do... Peter Alfke, Xilinx ApplicationsArticle: 23285
Andy Peters wrote:
> Rick,
>
> What don't you like about the clock enable?
>
> Given code like:
>
> flop : process (clk, reset) is
> begin
> if reset = '1' then
> q <= '0';
> elsif rising_edge(clk) then
> if enable = '1' then
> q <= d;
> end if;
> end if;
> end process flop;
>
> the recirculating mux controlled by enable (CE) is what retains the value of
> q when enable is not asserted. Don't forget that ALL of the Xilinx flops
> have this mux -- not explicitly designating a clock enable signal implies
> that the clock enable is always tied active.
>
> The timing analyzer takes the mux delay into account.
It is not that I don't like the CE. But rather I don't want to see logic
put in front of the CE that serves no purpose. I have written VHDL code
and had the synthesizer take every IF in the clocked part of a process
and turn it into a logic condition for the CE. Then it took these same
logic conditions and used them to set or clear the D input.
flop : process (clk, reset) is
begin
if reset = '1' then
q <= '0';
elsif rising_edge(clk) then
if enable = '1' then
if condition = '1' then
q <= A;
else if othercondition = '1' then
q <= B;
end if;
end if;
end if;
end process flop;
This would have put a LUT in front of the CE ANDing enable with the OR
of "condtion" and "othercondition". The D input would have gotten some
real mess gating these same terms with A and B and "enable". I didn't
write the synthesizer. But I had to use it!
I ended up taking all logic out of the clocked process and putting it
into a separate process or as combinational (concurrent?) code. I think
the compiler was FPGA Express. I was not a happy camper.
Now I just want to find out if there is a difference in power doing the
CE function in the LUT or the CE input. I am not saying that there is a
problem with using the CE, I am just collecting information. After all,
until I see some improvement in the synthesizers, I will continue to
code my HDL in schematics.
--
Rick Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design
Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX
Internet URL http://www.arius.com
Article: 23286Anybody know exsits library/IP implement FFT/IFFT with FPGA? The Xilinx's FFT/IFFT IP core only support Virtex, any solution support Spartan II? The altera's FFT core not free, any suggestion? Thanks a lot! Simon Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23287
iglasner@my-deja.com wrote: > > Hi, > > A FF even if it "see" the same input level does consume power as long > as there is a clock. > > The only way to reduce the power of a group of FF's is by shuting down > their clock meaning using clock enable. > > One example for using clock enable is for stand by purpose in cellualr > phone, where the power source (battery) is limited. > > have a nice day > > Illan The question is not does the FF use "any" power. But does the FF use less power? I would be willing to bet that most of the power in the FPGA is burned in toggling the ouput of a "slice" or CLB or whatever the correct term is for an output from a FF or LUT. I would be willing to bet that much less power is used to toggle a LUT that is only driving the FF in the same CLB. Even less power is likely used by a FF that is clocked, but the output does not change. Certainly internal nodes in a FF are switching anytime the clock switches. But the power used is very small since the capacitance of the internal nodes is very small. But to switch the output and the routed trace it connects to is likely the lion's share of where the power goes. So I would bet (not heavily since I have most of my money in the stock market and that is the biggest bet I have ever made) that there is very little power used by FFs which do not switch their outputs regardless of how that is accomplished; D input not changed, CE held low or clock turned off. Anyone care to wager a pint of your faviorite beverage (or Haagen Das in my case)? -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23288
Hi!
There is a new Virtex Development System from Avnet Design Services.
Have a look at:
http://www.avnetmarshall.com/dynamic/html/html/semi/marketing/xlx-19990526semw.html
Does anyone have experience with it?
It currently has a XCV300-BG432 mounted, but the datasheet mentions
also a XCV800 version. Is the larger one available?
TIA, Lars
--
Address: University of Mannheim; B6, 26; 68159 Mannheim, Germany
Tel: +(49) 621 181-2716, Fax: -2713
email: larsrzy@{ti.uni-mannheim.de, atoll-net.de, computer.org}
Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/
Article: 23289Peter Alfke <peter@xilinx.com> writes > > Xilinx Databook CD ROM Solutions. > Thank you for your workaround and fast response (as ever), I look forward to the new look CD regards, Dave McLeod dmac delete the obvious when replying by emailArticle: 23290
HI Younes ! Whats about the Xilinx distributors? You will find you chip on http://www.nuhorizons.com But I don't know the delivery time. BYE LarsArticle: 23291
Hi everybody! Since I need more internal memory on my VIRTEX I have to use the distributed RAM parallel to the block RAM. But I don't know how I can access the block RAM under VHDL. Can somebody help me - maybe with a sourcecode piece with value pre-initialization ? THX in advance, LarsArticle: 23292
Hi Brent,
Their is a company called MABEX that do a superb CBT tutorial
called VASCO (VHDL Application on Synthesis) they are about to compliment
this with a verilog version. I believe that you can purchase this product
from the Kanda website's online shop. http://www.kanda.com/
Enjoy
Pete
Brent <Fun@work.net> wrote in message news:##RhEZv1$GA.401@cpmsnbbsa08...
> Greetings everyone,
>
> I'm looking into learning FPGA and VHDL.
> I've recently been studying various HDL packages, such as Xilinx's
> foundation base, and Synplicity's Synplify.
>
> What I noticed is that they all mention they dont have Verilog and HDL
> synthesis.
>
> Does this mean that they dont actually have tools which enable me to
> write out an HDL file and compile it into a bitstream?
>
> Any response would be appreciated.
>
>
>
>
Article: 23293
Peter Alfke wrote:
> Hi, folks.
> Please send all comments on this subject - good, bad, and ugly- to me.
> You can be sure that they will be carefully studied, not only by me, but aso
> by the marketing department that's in charge of publishing data books etc.
> We have very exciting devices to describe ( I suppose you all agree ), and we
> want to do that in such a way that you get at the information as easily as
> possible.
> A 600 MB CD is an ideal medium to give you lots of data. But we have to
> format it right.
Peter,
One problem with a CD is that I cannot mark it up or hi-lite it in any way.
So I have to print the data sheet out anyway and then put it in a binder so I
don't lose it.
>
> Let's get all the irritants out of the way!
> We want you to design with Xilinx parts, not to get mad at documentation
> quirks.
>
> Peter Alfke, peter@xilinx.com
>
> ===============================
>
> Rickman wrote:
>
> > John Larkin wrote:
> > > This is all part of the current trend to totally capture, monitor, and
> > > manage the customer, in the manner and at the pace that some web-savvy
> > > marketing people consider proper. These are likely people who wouldn't
> > > notice an FPGA unless they stepped on one (preferably a PGA, pins up,
> > > barefoot).
> >
> > John, Don't hold back. Tell us how you really feel. ;)
> >
> >
> > > John
> > >
> > > (my next rant will be about the evils of 'web-enabled' EDA tools... stay
> > > tuned!)
> >
> > As you say, this is all part of a trend. Unfortunately Xilinx is a
> > leader in the marketing as well as the designing of FPGAs and tools. But
> > there is hope for change. Just like when they decided not to support
> > schematic based design for the Virtex parts. When enough people
> > screamed, they relented and added the support. We need to tell them that
> > a CD organized like the web site would not be a bad idea (assuming they
> > don't redo the web site to make it more "marketing friendly").
> >
> > So I guess we will put you down as a "NO" on "Likes the new Databook
> > CD".
> >
> > --
> >
> > Rick Collins
> >
> > rick.collins@XYarius.com
> >
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design
> >
> > Arius
> > 4 King Ave
> > Frederick, MD 21701-3110
> > 301-682-7772 Voice
> > 301-682-7666 FAX
> >
> > Internet URL http://www.arius.com
Article: 23294hi, I'm not into the betting arena and even the single night I spend in Vegas I prefered to walk arround than do gambling, but you might want to know that most cellular phone asic DO close the clock for lot's of FF's as well as mem and it DOES make a huge effect on the power consumption. The point that more power might be somewhere else have nothing to do with this point, as when you want to save power you save everywhere you can. To your comment that : "The question is not does the FF use "any" power. But does the FF use > less power? I would be willing to bet that most of the power in the FPGA" than the answer is yes the FF will use less power even tho' the capacitance look to you a small part, the amount of FF and the frequnacy make this small to be not so small. and yes clock gateing is a "sience" for itself and have big difficult of itself but it was done and will be done most likely in the future. have a nice day Illan In article <39505F5F.4A19D624@yahoo.com>, Rickman <spamgoeshere4@yahoo.com> wrote: > iglasner@my-deja.com wrote: > > > > Hi, > > > > A FF even if it "see" the same input level does consume power as long > > as there is a clock. > > > > The only way to reduce the power of a group of FF's is by shuting down > > their clock meaning using clock enable. > > > > One example for using clock enable is for stand by purpose in cellualr > > phone, where the power source (battery) is limited. > > > > have a nice day > > > > Illan > > The question is not does the FF use "any" power. But does the FF use > less power? I would be willing to bet that most of the power in the FPGA > is burned in toggling the ouput of a "slice" or CLB or whatever the > correct term is for an output from a FF or LUT. I would be willing to > bet that much less power is used to toggle a LUT that is only driving > the FF in the same CLB. Even less power is likely used by a FF that is > clocked, but the output does not change. > > Certainly internal nodes in a FF are switching anytime the clock > switches. But the power used is very small since the capacitance of the > internal nodes is very small. But to switch the output and the routed > trace it connects to is likely the lion's share of where the power goes. > > So I would bet (not heavily since I have most of my money in the stock > market and that is the biggest bet I have ever made) that there is very > little power used by FFs which do not switch their outputs regardless of > how that is accomplished; D input not changed, CE held low or clock > turned off. > > Anyone care to wager a pint of your faviorite beverage (or Haagen Das in > my case)? > > -- > > Rick Collins > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design > > Arius > 4 King Ave > Frederick, MD 21701-3110 > 301-682-7772 Voice > 301-682-7666 FAX > > Internet URL http://www.arius.com > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23295
Rickman wrote in message <39505DA7.CBFD36CB@yahoo.com>...
>It is not that I don't like the CE. But rather I don't want to see logic
>put in front of the CE that serves no purpose. I have written VHDL code
>and had the synthesizer take every IF in the clocked part of a process
>and turn it into a logic condition for the CE. Then it took these same
>logic conditions and used them to set or clear the D input.
>
> flop : process (clk, reset) is
> begin
> if reset = '1' then
> q <= '0';
> elsif rising_edge(clk) then
> if enable = '1' then
> if condition = '1' then
> q <= A;
> else if othercondition = '1' then
> q <= B;
> end if;
> end if;
> end if;
> end process flop;
>
>This would have put a LUT in front of the CE ANDing enable with the OR
>of "condtion" and "othercondition". The D input would have gotten some
>real mess gating these same terms with A and B and "enable". I didn't
>write the synthesizer. But I had to use it!
OK, I just ran that code through FPGA Express v3.3. It created two LUTs --
one for the CE and one for D. CE is asserted when enable is asserted AND
either condition or othercondition is asserted. That is what you'd expect,
actually -- those are the conditions that would cause q to change. Now,
perhaps what you were expecting was for the enable signal to drive CE
directly; however, that would cause the logic for the D input to get
bigger -- slower -- because it's now a more-complicated four-input function.
A mess, as you say.
Now, the D input equation is only a function of A, B and condition. D is
asserted when condition and A are true, or if condition is not true and B
is.
If you consider your code carefully, you'll see that the
if condition ...
elsif othercondition ...
code builds a priority encoder.
The synth knows that if condition is not true, then othercondition might be
true (and since CE would be asserted because othercondition true, then q
could be set), but if it's not, then the CE is killed, and q remains as is.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 23296Good news, Spartan/xl/II datasheets on our website were updated earlier today (pretty quick huh?). You got what you asked for. I just downloaded it, and you can highlight the text. Any other doc suggestions/complaints? :) Robert Binkley Xilinx Applications Jim Granville wrote: > Robert Binkley wrote: > > > > One of the reasons the Spartan-II datasheet is protected (a feature of the > > datasheet) is to prevent anyone from making changes and mis-representing the > > specs. > > There is more control possible : > > Adobe lists these options under Document Security > ( This selects/copies OK, but is a Philips Data sheet, not a Xilinx one > :-) > > Printing : Allowed > Changing the Document : Not allowed > Selecting Text and Graphics : Allowed > Adding or changing annotations and form fields : Not Allowed > > So the obvious solution is to set the same rules for Xilinx Datasheets ? > > - jgArticle: 23297
There is an example of this within my final thesis at http://www.arrakis.es/~jl.r/pfc/index.htm It described a test instrument for E1 (2048kbit/s) telecomm signals, transmitter and receiver. The design was fully tested and 100% working. Metastability issues between different clock domains (PC and FPGA) were considered. For historical reasons is password protected, but username="user" and password "1234" will work. Sorry, the body of the document is in spanish, but you can look at board schematics at http://www.arrakis.es/~jl.r/pfc/910refer/refer.htm#A_MAIN.SCH (block diagram) http://www.arrakis.es/~jl.r/pfc/910refer/refer.htm#A_FPGA.SCH (FPGA board) http://www.arrakis.es/~jl.r/pfc/910refer/refer.htm#A_BUS.SCH (BUS board) and at FPGA schematics http://www.arrakis.es/~jl.r/pfc/910refer/refer.htm#A_E1 (block diagram) http://www.arrakis.es/~jl.r/pfc/910refer/refer.htm#A__EPPREG (EPP peripheral) All the schematics are commented in english. The FPGA was a Xilinx XC4008E. The circuit used the paralel port to configure the LCA and then transfering data using the absolute minimum of hardware and signals (not even a single gate for -PROGRAM pin, just buffers). The configuration was in slave serial mode. The asynchronous parallel mode did not had any speed advantage, complicated the design and it did not allow to verify the bitstream loading with a CRC (hey, Peter Alfke, did you noticed that CRC could had been also calculated in paralel mode? ;-) The FPGA after configuration behaved to the PC as a fast bidirectional EPP (enhanced paralel port) peripheral, 8 bit wide. I also have available (not in the web) the source code of a W95 VXD that - configures the FPGA and - interfaces with the EPP peripheral inside the FPGA. Hope this helps Juan-Luis Lopez SpainArticle: 23298
steve@rsn-tech.demon.co.uk (Steve Rencontre) wrote in <memo.20000615030058.112C@steve.dircon.co.uk>: >In article <8F51E72E1shivawellcom@207.126.101.100>, shiva@well.com >(Kenneth Porter) wrote: > >> [posted and mailed] > >Mailed? To whom? Oh well, no matter... I cc'd to Altera tech support. They responded with a day. >The Jam player will do that. I forget the URL, but it's easy to find on >Altera's web site. They also recommended the same. URL is http://www.jamisp.com. Any idea how hard this is to set up? I see the .jam file appear as one of the Altera compiler outputs. Is it just a matter of plugging in the ByteBlaster and feeding the jam file as a command line argument to some JAM utility, or is there much more to it? I mostly want to get a feel for how much setup time is required.Article: 23299
Hey all, My company is interested in purchasing Leonardo Spectrum (2000 version with TimeCloser technology). Has anyone had a chance to use this (Beta, etc) tool, and can offer any comments (good, bad or otherwise) about it? The TimeCloser feature has caught our eye.... We have primarily used Synplify for FPGA synthesis (we have ver 5.3.1), and so I'm also looking for any other comments from people who are familiar with both the above version of Leonardo and how it compares feature wise and performance wise to Synplify. Thanks for your replies, Dave (email aoe_londonfog@hotmail.com or post here)
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