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Lucky for you, I posted the following on Fri-June-11-1999, and again on Sat-August-28-1999. This bug occurs during the very first exercise in the book, a 1 bit adder, which I assume is what you are doing. I love it when I can help. For your entertainment here it is, all fresh again. ============================== 6/11/1999 A friend and I have just been through exactly this problem: Student edition F1.5 hangs in the router. We also had crashes in the mapper. The solution to both was to apply BOTH the F1.5 service pack, and the version 2 hot fix to that service pack. Do not apply F1.5i service packs to version F1.5, it wont work. The main service pack is at ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/15_service_pack1_nt.zip and the increment is at ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/15_sp1_ftp2_nt.zip For ref, see this for warnings http://www.xilinx.com/techdocs/4897.htm Some of the problems seem to be related to having visual C++ V 6.0 on your system. Philip Freidin In article <nrqfkso00ap5oabn6qqh6rcf8be2lq5gg0@4ax.com>, Abdar Kerpal <me@somewhere.com> wrote: >I am a new user to the XILINX F1.5, I am currently trying to run a >simple project and I am in the implementation phase of the design, >when I go to compile my schematic that is targeted for the XILINX >4005XL technology, its gets to the Place and Route stage and just runs >and runs, for laughs I let it run for over two hours and it was still >running, I have tried everything to minimze PAR times, I am not using >the heartbeat indicator either. The program is not hanging up, it is >just running to no end. I also went ahead and used the system monitor >to see how much CPU is being used, it is using 100% of my pIII733. Is >this normal? or am I doing something wrong, or is there something in >the configuration that I need to set or unset???????? Please help, I >am totally perplexed!!!Article: 23126
Hi!! " Error: Delay path from '|bsp_in:73|bytedata_2_.Q' to '|bsp_in:73|intdata_2_.Q' is 4.2ns, but Clock skew is 2.9ns and hold time required for '|bsp_in:73|intdata_2_.Q' is 1.4ns - circuit cannot operate because Clock skew plus hold time of destination register exceeds register-to-register delay " I encounter this problem when i've finished compiling the project & doing the timing analysis. Most of the time, my design did not give me this error mesg but it happened ocassionally. I changed other part of the circuit but did not make any changes on the bsp_in portion. What can I do to ensure this won't happen again? How can i put any constraint and where i should put it? Thanks. I'm using Maxplus2 9.3 & Synplify 5.3.1 for my VHDL codes, running on PC, targetted at flex10k30e. Pls advice MKArticle: 23127
You need to specify more: Depth ( 16, 256, multiple k ?) Common clock or independent read/write clocks ( asynchronous FIFO) Max desired frequency Preferred FPGA family ( makes quite a difference: LUT-RAM, BlockRAM, just registers) If you don't specify, you end up with the lowest common denominator, i.e. useless stuff. Peter Alfke, Xilinx Applications ======================================== dave_admin@my-deja.com wrote: > Hi, > > Can somebody give me an example of FIFO design with width >1 ? > If it is parameterizable, even better. > VHDL is preferable, but Verilog is fine too. > > regards, > Dave. > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 23128
Xilinx in one of their presentations about Reed Solomon(RS) decoders claim that RS ASSP costs $20 and Xilinx RS in an FPGA costs < $10. On the same web site, in an another documentation about set top boxes they have shown the architecture of set top box. The architecture shows the utilization of RS from ASSP suppliers like Motorola. Xilinx has shown in that architecture where their devices can fit-in in a set-top box, the RS from xilinx is missing. So the whole point is why would someone do RS in FPGA? Why RS ASSP are expensive as compared to XIlinx FPGAs? Why Xilinx RS is missing in the set top box architecture, if the price difference is double? Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23129
Try to visit my memory cores page at http://www.geocities.com/SiliconValley/Pines/6639/ip/memory_cores.html You can also check http://www.opencores.org and http://www.free-ip.com You can find Free Open design cores Let me know if you are going to use my FIFO core Regards Jamil Khatib OpenCores Organization dave_admin@my-deja.com wrote: > Hi, > > Can somebody give me an example of FIFO design with width >1 ? > If it is parameterizable, even better. > VHDL is preferable, but Verilog is fine too. > > regards, > Dave. > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 23130
Hello, Has anyone heard of some open-source ro at least free device driver source code for PLX PCI bridge under Linux ? Thanks, StevenArticle: 23131
I was at a seminar this week where they said this problem can be caused by Intel's BX chip set. Is this what you have? -- Gary Watson gary@nexsan.sex (Change dot sex to dot com to reply!!!) Nexsan Technologies Ltd. Derby DE21 7BF ENGLAND http://www.nexsan.com Steven Derrien <sderrien@irisa.fr> wrote in message news:394795E3.51669350@irisa.fr... > Hello, > > This post might be a little bit off-topic, but I know that many people i > this group have been beating their head on PCI for a while, so I may get > an answer to my question... > > I'm using Virtex fpga on a PLX9080 based PCI board. My driver uses the > PLX SDK. > I'm trying to perform Slave DMA transfer to get decent IO performance, > however I can't get more than 30Mbytes/sec on my PIII 600 with DMA size > of 40kb (PCI->Local Bus). > > I've been trying to play around with the various DMA configuration > registers without success, besides i've implemented a simple spy > (counting successive write operation) on my FPGA and it seems that > almost no data burst occur during DMA transfer ... > > Any help or explanation would be greatly appreciated. > > Thanks > > Steven >Article: 23132
Gary Watson wrote: > I was at a seminar this week where they said this problem can be caused by > Intel's BX chip set. Is this what you have? Unfortunately yes I have a 440Bx chipset ... Do you hav more information on this ? StevenArticle: 23133
Hello,
I had a similar requirement for a project that I'm just
completing. The programmed Virtex FPGA could request
that a new configuration be loaded at any time. I placed
a CPLD (XC95OO family) between the configuration
sources, eight ISP PROMS, and the FPGA. The CPLD
controls the
configuration process, defaulting the first
configuration to a predetermined PROM, and then
under control of the FPGA switches the data path to the
specified PROM and re-loads the FPGA. The CPLD also had
a connection to a MultiLINX port which had priority over
the FPGA.
This allowed the user to override the configuration
loaded from the PROMs, which made debugging a whole lot
easier.
Alex Carreira wrote:
> Hello Everyone,
>
> I am extremely interested in partial
> dynamic reconfiguration of FPGAs. If anyone
> out there has knowledge of systems (particularly
> Virtex based) that reconfigure parts of the FPGA
> to accomplish different tasks at different points
> in system operation I would be glad to hear
> about it. I have seen the XILINX ap notes on
> the subject and have read of the CAL and XC6
> series parts/projects, so we can skip info on these.
>
> Thank you.
>
> Sincerely,
>
> Alex :)
--
/ /\/ Rick Ballantyne Senior Staff Engineer
\ \ Xilinx, Inc.
/ / 34 Hampel Cres. Phone:(613) 836 5255
\_\/\ Stittsville, Ontario Fax: (613) 836 5393
Canada K2S 1E4 E-Mail:rickb@xilinx.com
Xilinx's Web @ http://www.xilinx.com
Article: 23134
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This is a periodic posting to let readers of these newsgroups know
about several online resources that may be relevant:
[1] Embedded Systems Glossary
http://www.netrino.com/Publications/Glossary/
[2] Embedded Systems Bibliography
http://www.netrino.com/Publications/Bibliography/
These are online versions of the Glossary and Bibliography from my
book, "Programming Embedded Systems in C and C++" (O'Reilly and
Associates, ISBN 1-56592-354-5).
It is my intention to make occasional changes and updates to these
online versions. I would very much like to hear your constructive
feedback. Please send your suggestions to <webmaster@netrino.com>.
I have put a lot of work into writing the book and creating and
maintaining these online resources. I hope that they will be a
valuable contribution to the community of embedded systems hard-
ware and software designers.
Sincerely,
Michael Barr
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Article: 23135This is a cryptographically signed message in MIME format. --------------ms9BDA23A63B55C22D0263ABAA Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit David Brown wrote: > > Prof. Andrew Tanenbaum refers to a binary semaphore named "mutex" in > Operating Systems Design and Implementation (the book with the entire source > code to Minix, precursor and insperation for Linux, as an Appendix) in 1987. > The reference is to solve a buffer situation with three semaphores - "full" > and "empty" initialised to 0, and a binary semaphore "mutex" initialised to > 1 to ensure mutually exclusive access to the buffer. > > So the term "mutex" has probably been generalised from particular uses such > as this one. Tanenbaum was indeed one of my influences for including this term in the glossary (and using the term myself). I'm enjoying this thread, though. One of the most interesting things about creating a glossary and publishing it is the way it forces you to learn things you didn't know about the perspectives of others. Cheers, Michael --------------ms9BDA23A63B55C22D0263ABAA Content-Type: application/x-pkcs7-signature; name="smime.p7s" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="smime.p7s" Content-Description: S/MIME Cryptographic Signature MIIJngYJKoZIhvcNAQcCoIIJjzCCCYsCAQExCzAJBgUrDgMCGgUAMAsGCSqGSIb3DQEHAaCC ByowggP0MIIDXaADAgECAhBzrgKq88Z3SBSDBDv+0HnjMA0GCSqGSIb3DQEBBAUAMIHMMRcw FQYDVQQKEw5WZXJpU2lnbiwgSW5jLjEfMB0GA1UECxMWVmVyaVNpZ24gVHJ1c3QgTmV0d29y azFGMEQGA1UECxM9d3d3LnZlcmlzaWduLmNvbS9yZXBvc2l0b3J5L1JQQSBJbmNvcnAuIEJ5 IFJlZi4sTElBQi5MVEQoYyk5ODFIMEYGA1UEAxM/VmVyaVNpZ24gQ2xhc3MgMSBDQSBJbmRp dmlkdWFsIFN1YnNjcmliZXItUGVyc29uYSBOb3QgVmFsaWRhdGVkMB4XDTAwMDYxNTAwMDAw MFoXDTAwMDgxNDIzNTk1OVowggEDMRcwFQYDVQQKEw5WZXJpU2lnbiwgSW5jLjEfMB0GA1UE CxMWVmVyaVNpZ24gVHJ1c3QgTmV0d29yazFGMEQGA1UECxM9d3d3LnZlcmlzaWduLmNvbS9y ZXBvc2l0b3J5L1JQQSBJbmNvcnAuIGJ5IFJlZi4sTElBQi5MVEQoYyk5ODEeMBwGA1UECxMV UGVyc29uYSBOb3QgVmFsaWRhdGVkMSYwJAYDVQQLEx1EaWdpdGFsIElEIENsYXNzIDEgLSBO ZXRzY2FwZTEVMBMGA1UEAxQMTWljaGFlbCBCYXJyMSAwHgYJKoZIhvcNAQkBFhFtYmFyckBu ZXRyaW5vLmNvbTCBnzANBgkqhkiG9w0BAQEFAAOBjQAwgYkCgYEAs22Sadc8txV4tp246/HC pn2sIrN8xWABXMXRI6Dxpnlj+0VVCC6nL6bFrgBSrBxgnO5oBtcMOG23M9Mn693gPNAKNzKO UOS7cBDZQc5HL0bSF6tpTyPIb5PIPSOGvSuBz0eih80KOoaTz+ZAnJTTr3wLboL/S0dmc/5Y dLpiNxcCAwEAAaOBnDCBmTAJBgNVHRMEAjAAMEQGA1UdIAQ9MDswOQYLYIZIAYb4RQEHAQgw KjAoBggrBgEFBQcCARYcaHR0cHM6Ly93d3cudmVyaXNpZ24uY29tL3JwYTARBglghkgBhvhC AQEEBAMCB4AwMwYDVR0fBCwwKjAooCagJIYiaHR0cDovL2NybC52ZXJpc2lnbi5jb20vY2xh c3MxLmNybDANBgkqhkiG9w0BAQQFAAOBgQBsD0PdbPd8t+RySLQgdEINe0jxvzJh8nSDbI9U mo86FQEKXtpJ8MtZ/kvZhoKAcp+wJtxMZ+KiL2OQYIKJCdSb1FJjEM+14pQCdatXFAwhTkby ZrZSEC4fRAMz7JztSGSkmmbUCj221l20pXrKg8aFFaAXvvupU5Ge/81u9NBjPDCCAy4wggKX oAMCAQICEQDSdi6NFAw9fbKoJV2v7g11MA0GCSqGSIb3DQEBAgUAMF8xCzAJBgNVBAYTAlVT MRcwFQYDVQQKEw5WZXJpU2lnbiwgSW5jLjE3MDUGA1UECxMuQ2xhc3MgMSBQdWJsaWMgUHJp bWFyeSBDZXJ0aWZpY2F0aW9uIEF1dGhvcml0eTAeFw05ODA1MTIwMDAwMDBaFw0wODA1MTIy MzU5NTlaMIHMMRcwFQYDVQQKEw5WZXJpU2lnbiwgSW5jLjEfMB0GA1UECxMWVmVyaVNpZ24g VHJ1c3QgTmV0d29yazFGMEQGA1UECxM9d3d3LnZlcmlzaWduLmNvbS9yZXBvc2l0b3J5L1JQ QSBJbmNvcnAuIEJ5IFJlZi4sTElBQi5MVEQoYyk5ODFIMEYGA1UEAxM/VmVyaVNpZ24gQ2xh c3MgMSBDQSBJbmRpdmlkdWFsIFN1YnNjcmliZXItUGVyc29uYSBOb3QgVmFsaWRhdGVkMIGf MA0GCSqGSIb3DQEBAQUAA4GNADCBiQKBgQC7WkSKBBa7Vf0DeootlE8VeDa4DUqyb5xUv7zo dyqdufBou5XZMUFweoFLuUgTVi3HCOGEQqvAopKrRFyqQvCCDgLpL/vCO7u+yScKXbawNkIz tW5UiE+HSr8Z2vkV6A+HthzjzMaajn9qJJLj/OBluqexfu/J2zdqyErICQbkmQIDAQABo3ww ejARBglghkgBhvhCAQEEBAMCAQYwRwYDVR0gBEAwPjA8BgtghkgBhvhFAQcBATAtMCsGCCsG AQUFBwIBFh93d3cudmVyaXNpZ24uY29tL3JlcG9zaXRvcnkvUlBBMA8GA1UdEwQIMAYBAf8C AQAwCwYDVR0PBAQDAgEGMA0GCSqGSIb3DQEBAgUAA4GBAIi4Nzvd2pQ3AK2qn+GBAXEekmpt L/bxndPKZDjcG5gMB4ZbhRVqD7lJhaSV8Rd9Z7R/LSzdmkKewz60jqrlCwbe8lYq+jPHvhnX U0zDvcjjF7WkSUJj7MKmFw9dWBpJPJBcVaNlIAD9GCDlX4KmsaiSxVhqwY0DPOvDzQWikK5u MYICPDCCAjgCAQEwgeEwgcwxFzAVBgNVBAoTDlZlcmlTaWduLCBJbmMuMR8wHQYDVQQLExZW ZXJpU2lnbiBUcnVzdCBOZXR3b3JrMUYwRAYDVQQLEz13d3cudmVyaXNpZ24uY29tL3JlcG9z aXRvcnkvUlBBIEluY29ycC4gQnkgUmVmLixMSUFCLkxURChjKTk4MUgwRgYDVQQDEz9WZXJp U2lnbiBDbGFzcyAxIENBIEluZGl2aWR1YWwgU3Vic2NyaWJlci1QZXJzb25hIE5vdCBWYWxp ZGF0ZWQCEHOuAqrzxndIFIMEO/7QeeMwCQYFKw4DAhoFAKCBsTAYBgkqhkiG9w0BCQMxCwYJ KoZIhvcNAQcBMBwGCSqGSIb3DQEJBTEPFw0wMDA2MTUxMzM1MTdaMCMGCSqGSIb3DQEJBDEW BBRdag4Lh30CAMoniaOVZpZq1XCHVTBSBgkqhkiG9w0BCQ8xRTBDMAoGCCqGSIb3DQMHMA4G CCqGSIb3DQMCAgIAgDAHBgUrDgMCBzANBggqhkiG9w0DAgIBQDANBggqhkiG9w0DAgIBKDAN BgkqhkiG9w0BAQEFAASBgITvwOWJFuXkI4WtjoOgR4NWmab8zz+wDYd+3YoaSzbsxk0etLYr FRIbU+koOZK9Tao1xGqZFluuJJtn4TNevagq/3hQtAuBepAj8cjsz2N7zSuQdrjUWGnN3Xi5 26G0RrjTT2bmROWngpP96U4+pe8WZIdA9VyU1xOyjV+4zQXk --------------ms9BDA23A63B55C22D0263ABAA--Article: 23136
Hi everybody. I created a "Single Port Block Memory" with the F2.1 Core Generator. -Design Entry: VHDL -Vendor: Foundation -Family: Virtex -no behavioral simulation Now I try to implement the created Object RAM0 in my VHDL Code. But the Synthesis let appear this warning: Cannot link cell 'MemProj/Mem' to its reference design 'RAM0'. Ohh.. a little second question! To simulate this RAM via behavioral simulation I must install ModelSim. Is this right? I hope somebody can help me. Thanks in advance. LarsArticle: 23137
> bkk411@my-deja.com wrote: to Ray including the following > > I think the problem I'm having did not quite come across: > > The problem I'm having is that FPGA compilers, treat > > RAMs and CoreGen block as black boxes, AND do NOT know > > ANY timing constraints from those black boxes. > > So it does NOT optimise the data path to and from the RAMs. > > Synopsys does not show any path to/from the memory. > > Even when I try to define a new timing constraint, the IOs of > > the RAMs are not listed as a valid choice. "Ray Andraka" <ray@andraka.com> wrote back > You're right, I missed the point of your post. So how wide are the > combinatorial functions leading into your block RAM??? If it's less than 5 > bits then the path should optimise fine with the Xilinx mapper regardless > of what synopsis is doing. I have hit problems when Leonardo ModGen bugs failed to produce deep RAM's correctly. To work around the problem I instantiated 8 or more CoreGen RAM's. The resulting design had hundreds of loads on some signals (address?) and Xilinx was unable to route these without considerable delay. If Leonardo Knew these signals were a problem it could have added drivers in parallel etc. To achieve this the preferred approach was said to be to pass the EDIF for the CoreGen to Leonardo marked "Do NOT Touch". This will allow it to determine the number of loads and parallel up the drivers etc. to meet the timing. bkk has suggested that The RAM4_XXXX would also need to be passed to the Synthesis tool as it is instantiated in the CoreGen EDIF. But I thought this was a basic element like Adders, and Muxes which are not part of CoreGen and are understood by the Synthesis tools. This whole problem is due to be addressed by the arriving closer integration between Synthesis and PAR where black boxes are PAR'ed and passed back to Synthesis to allow it to optimise around them. Andrew InceArticle: 23138
Dude, thanks alot, the service pack did the trick, I can now assign pin constraints to any pin I want! I really want to thank everyone who added their input to my dilema, all was very, very useful!! On 15 Jun 2000 02:08:17 GMT, fliptron@netcom.com (Philip Freidin) wrote: >Lucky for you, I posted the following on Fri-June-11-1999, >and again on Sat-August-28-1999. > >This bug occurs during the very first exercise in the book, a 1 bit >adder, which I assume is what you are doing. > >I love it when I can help. > >For your entertainment here it is, all fresh again. > > >============================== 6/11/1999 >A friend and I have just been through exactly this problem: Student >edition F1.5 hangs in the router. We also had crashes in the mapper. > >The solution to both was to apply BOTH the F1.5 service pack, and the >version 2 hot fix to that service pack. Do not apply F1.5i service packs >to version F1.5, it wont work. > >The main service pack is at > ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/15_service_pack1_nt.zip > >and the increment is at > ftp://ftp.xilinx.com/pub/swhelp/M1.5_updates/15_sp1_ftp2_nt.zip > >For ref, see this for warnings > http://www.xilinx.com/techdocs/4897.htm > > >Some of the problems seem to be related to having visual C++ V 6.0 on >your system. > >Philip Freidin > > > >In article <nrqfkso00ap5oabn6qqh6rcf8be2lq5gg0@4ax.com>, >Abdar Kerpal <me@somewhere.com> wrote: >>I am a new user to the XILINX F1.5, I am currently trying to run a >>simple project and I am in the implementation phase of the design, >>when I go to compile my schematic that is targeted for the XILINX >>4005XL technology, its gets to the Place and Route stage and just runs >>and runs, for laughs I let it run for over two hours and it was still >>running, I have tried everything to minimze PAR times, I am not using >>the heartbeat indicator either. The program is not hanging up, it is >>just running to no end. I also went ahead and used the system monitor >>to see how much CPU is being used, it is using 100% of my pIII733. Is >>this normal? or am I doing something wrong, or is there something in >>the configuration that I need to set or unset???????? Please help, I >>am totally perplexed!!! >Article: 23139
dave_admin@my-deja.com wrote: > Can somebody give me an example of FIFO design with width >1 ? > If it is parameterizable, even better. > VHDL is preferable, but Verilog is fine too. Go to The Free-IP Project, http://www.free-ip.com, and follow the links to the Free-RAM core. That VHDL core includes many FIFO's that are all parameterized and portable to several different FPGA's (Well, A to Z really). David Kessner davidk@free-ip.comArticle: 23140
Hi Lars Lotzenburger a écrit : > > Hi everybody. > > I created a "Single Port Block Memory" with the F2.1 Core Generator. > -Design Entry: VHDL > -Vendor: Foundation > -Family: Virtex > -no behavioral simulation > > Now I try to implement the created Object RAM0 in my VHDL Code. > But the Synthesis let appear this warning: > > Cannot link cell 'MemProj/Mem' to its reference design 'RAM0'. I don't think this is a problem (this is only a warning, not an error message). You need to have the memory .edn files (generated with CoreGen) in the same directory as your other design files. After synthesis, they will be incorporated in your design during "implementation" (that's how Xilinx calls it I think) > Ohh.. a little second question! > To simulate this RAM via behavioral simulation I must install > ModelSim. Is this right? ModelSim or any other HDL simulator -- Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel +33 1 46 67 51 11 92400 COURBEVOIE Fax +33 1 46 67 51 01 FRANCEArticle: 23141
I need the VHDL to make a PWN (12 bits) Thanks in advancedArticle: 23142
david garnett <dave.garnett@metapurple.co.uk> wrote in article <8i9sjp$4hm$1@lure.pipex.net>... > I've seen similar effects using the AMCC PCI chips. My best guess is that it > is something to do with the bridge controller between the PCI bus and Local > bus. I note that performance is much better running under DOS than NT, so I > guess that what may be happening is that the bus bridge is giving priority > to cache 'refills'. NT has a much bigger 'idle loop' than DOS, so > consequently needs much more cache refill activity, Why would an 'idle loop' not run entirely out of cache? > which translates into > less available bandwidth for everyone else ... > > If you look at the PCI bus signals with a scope (digital) you will easily > get a general picture of what is going on - you don't need a logic analyser > at this level. Though I don't disagree you can get some indication as to what is going on with a scope, PCI development is much easier with a PCI extender card, and almost all (if not all) of them have logic analyzer hookups. They are hardly expensive (like a few hundred dollars). Decent logic analyzers are pretty cheap these days too... > regards > Dave > > Austin Franklin <austin@darkr88oom.com> wrote in message > news:01bfd63f$9eb72670$250bf7a5@drt1... > > > Austin Franklin wrote: > > > > > > > > I'm using Virtex fpga on a PLX9080 based PCI board. My driver uses > > the > > > > > PLX SDK. > > > > > > > > If you did not re-write your driver, the PLX driver does double > > buffering, > > > > which is slow. Are you using NT? > > > > > > I use NT, to perform the DMA, I use the physically contiguous > > > memory buffer provided by the function PlxPciCommonBufferGet > > > > > > Since the physical address for this buffer is given, this is the one > > > I use for programming the plx DMA controler. The "double buffering" > > > is hence handled in my program which copy the appropriate data into this > > > buffer. > > > > We found the PLX driver to not come close to providing the performance we > > needed, so we re-wrote it, to not double buffer (which was not an easy > > task, BTW)...since we had to stream data, and the double buffering really > > slowed things down. > > > > > > > I'm trying to perform Slave DMA transfer to get decent IO > > performance, > > > > > > > > What is slave DMA? The PLX chip can become a PCI bus Master, which is > > what > > > > you want, I would assume. > > > > > > Sorry, my explanation were not very clear. > > > In my case, the plx chip is programmed form the PCI/host side (not the > > FPGA > > > side) to > > > start a DMA transfer as a busmaster to perform PCI to local bus DMA. > > > > > > Strangely, I have 30Mb when doing PCI to Local bus DMA, but I can reach > > 60Mb > > > when doing Local to PCI (still with PLX as busmaster). > > > > That's not untypical, believe it or not. > > > > Sounds to me like you need to look at the PCI bus with a logic analyzer to > > see what is happening. I wish I could give you a one line 'ta da' fix... > > Do you know that your back end can keep up with the PCI bus? > > > > I'll look over our NT driver and see if there is anything obvious that I > > can come up with that might cause the problem you are having... > > > > > > >Article: 23143
I am about to finish my Master (thesis work in VHDL/FPGA related matters) and I'm considering different options for my professional career. I wonder if becoming an FPGA/VHDL freelance engineer would be a good alternative to more classical jobs. I would appreciate any advice you could give me. Do you know if there is any web site where engineers can meet companies looking for freelance designers? Thanks for your time AB Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23144
Hi Lars, when you synthesize a COREGEN component, you are doing so as a "black box." This means that you have specified the component declaration, and instantiated that component in your architecture, but the synthesis tool does not have the VHDL code for the underlying netlist of that component. This warning is letting you know that. However, during implementation, the tools will look for the underlying netlist of that component, an EDIF file in this case, and link that to the design. This is why you must have the netlist file(s) from COREGEN in the same directory as your top-level netlist during implementation. Also, it would be true to say that the Xilinx tool set does not include a functional HDL simulator. However, MODELSIM is one of many third-party vendors who offer a tool that does do functional HDL simulation. I hope this information helps. Regards, Scott - Xilinx AppsArticle: 23145
In article <393588df@patience.ibsystems.com>, "Saqib." <saqib_khursheed@yahoo.com> wrote: > > Hi all, > Please answer me the following questions and obligue: > > 1. I have to design a Isochronous Fifo, so will that be made exactly the > way as Asynchrous fifo (ie by using cs_B signal) or by using a clock (ie > clock will be necessary here or not)??? I think you mean asynchronous FIFO vs. synchronous FIFO, and yes you will need a clock for the synchronous case. > > 2. Is high impedence signal and dont care signal (ie 1'bz and 1'bx) > are synthesizible or not?? They are: 1'bz is used to infer tristate drivers and 1'bx is used to let the synthesizer know of a don't care condition so it can reduce some logic possibly. > > Thanx, > BYE. > Cheers! Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23146
Gary, "don't do that". You are trying to shoe-horn an output delay between 7 and 16 ns. That is not only dangerous, it is hopeless. IC delays vary over the temperature range ( by >20%) over supply voltage ( >10%) an due to processing variations ( another 30% or even more ). The manufacturer guarantees the absolute max delay under the worst combination ( high temp, low voltage, slow processing) and you can trust that value. But there is no way to control, and even less chance to guarantee, the shortest delay, except for saying its no less than 25% of the guaranteed max delay ( That's what we here at Xilinx say, and Altera cannot be any different. We all use the same silicon. Altera just cannot afford to answer this newsgroup. Poor devils...). So, rethink your approach, maybe you need to specify a faster part, be creative. But don't expect IC delay parameters to have a small spread. Peter Alfke, Xilinx Applications ============================================== Gary Cook wrote: > Hi, > > Using Maxplus-II to do output delay timing estimation for > a given design gives a value of something like 16ns .... on the > actual chip it's more like 7ns ... is the 16ns an absolute > maximum and what I'm getting is a typical value? > > Unfortunately I need more that 7ns delay .. I could clock > the outputs with negedge clock, and hope that I always get > 7ns ... but if I start getting 16ns then I'm back in trouble ... > any ideas? > > Cheers, > > Gary Cook.Article: 23147
Thanks. That clears up a lot for me. <kayrock@geocities.com> wrote in message news:8i8sit$h5e$1@nnrp1.deja.com... > In article <XNG%4.6388$uj6.340332@news1.rdc1.on.wave.home.com>, > "John Smith" <jsmith@home.com> wrote: > > Hi > > > > What are the differences (if any) between an fpga and an epld? > > > Assuming this is a real question I'll go ahead and give a brief > answer. I'm sure this is in a FAQ somewhere. > > In general FPGA's have higher density than EPLD's. ELPDs are good at > high speed state machines while FPGA's are better at datapath > operations. EPLD's are commonly non-volitile, while FPGA's often are. > EPLD's often have high current requirements even with no clock, while > FPGA's often have only leakage currents (uA's) with no clock. > > Cheers! > > > Sent via Deja.com http://www.deja.com/ > Before you buy.Article: 23148
Peter is 100% correct. If anything, he understates the risk you're contemplating. The only parameter on which you can reasonably expect tight tolerances is in the *matching* of similar delays on a single piece of silicon. Sometimes this can be used to your advantage. If this problem arises in a device to be built in volume, you really need to address the fundamental timing issue on the board. In the world of synchronous design, there is *usually* a very clean and bulletproof solution that doesn't demand an exorbitant price. It is well worth the effort to fix the problem at the fundamental level, and then move on to the next design adventure. Life is too short (and too much fun) to be spent fretting and betting on the chip-to-chip (and voltage and temp) differences in AC characteristics. Post the missing details of the problem to this newsgroup. This is the sort of problem that serves as a good example to the readers, illustrating design analysis and solution techniques. This is one of the primary needs addressed by these technical newsgroups. You'll also see (usually) an incredible diversity of solutions and analysis methods! -- Bob Elkind Peter Alfke wrote: > > Gary, > "don't do that". > You are trying to shoe-horn an output delay between 7 and 16 ns. > That is not only dangerous, it is hopeless. > IC delays vary over the temperature range ( by >20%) over supply > voltage ( >10%) an due to processing variations ( another 30% or > even more ). The manufacturer guarantees the absolute max delay > under the worst combination ( high temp, low voltage, slow > processing) and you can trust that value. But there is no way to > control, and even less chance to guarantee, the shortest delay, > except for saying its no less than 25% of the guaranteed max delay ( > That's what we here at Xilinx say, and Altera cannot be any > different. We all use the same silicon. Altera just cannot afford to > answer this newsgroup. Poor devils...). > So, rethink your approach, maybe you need to specify a faster part, > be creative. > But don't expect IC delay parameters to have a small spread. > > Peter Alfke, Xilinx Applications > ============================================== > Gary Cook wrote: > > > Hi, > > > > Using Maxplus-II to do output delay timing estimation for > > a given design gives a value of something like 16ns .... on the > > actual chip it's more like 7ns ... is the 16ns an absolute > > maximum and what I'm getting is a typical value? > > > > Unfortunately I need more that 7ns delay .. I could clock > > the outputs with negedge clock, and hope that I always get > > 7ns ... but if I start getting 16ns then I'm back in trouble ... > > any ideas? > > > > Cheers, > > > > Gary Cook.Article: 23149
Greetings everyone, I'm looking into learning FPGA and VHDL. I've recently been studying various HDL packages, such as Xilinx's foundation base, and Synplicity's Synplify. What I noticed is that they all mention they dont have Verilog and HDL synthesis. Does this mean that they dont actually have tools which enable me to write out an HDL file and compile it into a bitstream? Any response would be appreciated.
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