Messages from 23075

Article: 23075
Subject: Re: Altera vs Xilinx
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Tue, 13 Jun 2000 11:32:28 GMT
Links: << >> << T >> << A >>

Hello,

I am a big Xilinx fan. I feel that if a designer has good knowledge of the
tools, then this will outweigh the differences between the companies. I have
no experience with Altera and as such I can not compare them to Xilinx.
Sorry.

I am interested in video scaling. I am self employed and sell, 'video frame
grabbers'.

http://www.pixelsmart.com

Are you working on a commercial product / academic work / personal interest
etc ?

Do you have a web page ?

Sincerely
Daniel DeConinck

Article: 23076
Subject: DLL in virtex fpga
From: Christophe Heyert <heyertc@rsd.bel.alcatel.be>
Date: Tue, 13 Jun 2000 15:50:14 +0200
Links: << >> << T >> << A >>

Hi Everybody,

thanks to Mark for the advice, but now I have another problem.
Th simutor only seems to divide by 2 while I need divisions of 2, 8 and
16.
I have some prblems setting the attributes.
Can someone help me with this problem

thanx

christophe

Article: 23077
Subject: Re: Virtex IRDY and TRDY
From: Scott <>
Date: Tue, 13 Jun 2000 07:08:40 -0700
Links: << >> << T >> << A >>

Hi David, what happens in the PAD reports is that all special purpose pins are listed regardless of whether they are used in your design or not. These pins are used for PCI functions. Seeing them in the PAD reports only indicates which pin locations these functions are found at, and does not mean that your design has included them. Hope this helps.

Regards,
Scott - Xilinx Apps

Article: 23078
Subject: Re: Virtex-EM and F2.1
From: Scott <>
Date: Tue, 13 Jun 2000 07:21:10 -0700
Links: << >> << T >> << A >>

Hi Lars, did you try to manually edit the .FAM file as was described in the solution record #9248 ? Once you edit this file, and add the lines as described, you should have access to this device. Hope this helps.

Regards,
Scott - Xilinx Apps

Article: 23079
Subject: Harddisk <--> FPGA <--> PC
From: Claas Richter <clri@gmx.de>
Date: Tue, 13 Jun 2000 17:33:02 +0200
Links: << >> << T >> << A >>

Hallo!

Hat jemand schon einmal eine Festplatte mit einem FPGA verbunden (mit
entsprechender Schaltung) ?
Ich möchte die Daten 'on the fly' zw. PC und Festplatte abändern und
habe da so meine Probleme (spzielle mit dem Signal IORDY).

Claas

Article: 23080
Subject: Re: Virtex IRDY and TRDY
From: Brian Boorman <brian_boorman@my-deja.com>
Date: Tue, 13 Jun 2000 17:05:23 GMT
Links: << >> << T >> << A >>

In article <3945B203.9E2D7D15@tigger.jvnc.net>,
  David Brown <dbrown@tigger.jvnc.net> wrote:
> Hi all,
>
> Does anyone know why the pad report from par for a XCV300 design
> includes pins TRDY and IRDY ?  These pins are not found in my VHDL
> source. They are only briefly mentioned in the Virtex-E datasheet (and
> not described), but not at all in the Virtex datasheet.
>
> Does this indicate that there is something that I'm inadvertently
> activating that calls for these pins?
>
> Thanks,
> Dave Brown
>

Xilinx is getting worse as far as the quality of their datasheets goes.
I am presently using a Spartan II (after having just done an Actel
design). These pins are also present on the Spartan II, but nowhere in
the datasheet are they described. All I know is that they have to do
with PCI.

Even worse (for me) is I wanted to use the powerdown feature (PWDN pin)
on the Spartan II. This is **NOT described at all** in the Spartan II
datasheet. On a hunch I checked an old Spartan datasheet and found a
description which said that using that mode would assert the GSR and
reset all the flip-flops, which was not acceptable for my application. I
ended up changing my approach.

Perhaps someone from Xilinx would care to address in a meaningful form
the increasing lack of important information from the newer datasheets.

--
Brian C. Boorman
Design Engineer
Harris RF Communications
Rochester, NY 14610

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Article: 23081
Subject: Re: Altera vs Xilinx
From: kayrock@geocities.com
Date: Tue, 13 Jun 2000 17:16:26 GMT
Links: << >> << T >> << A >>

In article <8i3knp$noq$1@nnrp1.deja.com>,
  swfpga@my-deja.com wrote:
> Not to start a religious war, but I am in the process of choosing
> between Altera(Apex/Flex) and Xilinx(Virtex/Spartan) for our design.
> Can someone post a message of what the advantages and disadvantage  of
> their FPGA's are?  e.g. cost, support, performance, ease of use, ...
> We will use Verilog, BTW.
> We are going to implement a video scaling application.
>
> thanks

Either vendor probably has a part that would work for your app.  You
didn't mention the volume of your app and this leads to a point I think
you might consider.

If the volume is low, then part cost is not such a big issue and you'll
probably just want tools that are fast and easy to use.  IMHO Altera
has the lead on this one with Max Plus.

However, if you do have some good volume, I suggest you let the two
vendors bid for your business.  Create a technology neutral design in
Verilog and give it to the FAE's for both vendors and ask them to place
and route your design to their most cost competative part and give you
a quote on it.  Along similar lines you could try do your board with a
FPGA footprint that would work for either vendors parts and use the guy
that gives you the best pricing.

Regarding your particular app, multipliers are big, line memories are
bigger, and everything else is small change.  If you are doing bilinear
interpolation, use the algorithm that uses one multiplier per
dimension.  Consider decimation for its size benefits (no multipliers,
no line memories).  Think about off chip memory, sometimes you really
pay a premium for sram bits in an FPGA, especially if your lines are
long.

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Article: 23082
Subject: Re: Please,give me solution for "serious pad to pad delay" in Xilinx.
From: kayrock@geocities.com
Date: Tue, 13 Jun 2000 17:30:12 GMT
Links: << >> << T >> << A >>

In article <39404C24.2E883821@telpia.com>,
  =?EUC-KR?B?wNPA58iv?= <jhlim@telpia.com> wrote:
> Hi everyone!
>
> I have problem for serious pad to pad delay in Virtex.
>
> My development environment is following.
>
> software: Foundation 2.1i
> device : Virtex
> language : VHDL
>
> In my design, there is a part which only receive the external clock
and
> bypass to output pad.
>
> In vhdl source, it appears like a following.
>
> ENTITY MyDesign IS
>   PORT(
>   ClkIn: IN STD_LOGIC;
>   ClkOut : Out STD_LOGIC;
>     .
>     .
>     .
>   );
> END ;
>
> ARCHITECTURE arch_MyDesign OF MyDesign IS
> BEGIN
>         Clkout <=  Clkin;
>         .
>         .
>         .
> END;
>
> In timing simulator, Clkout appears as delayed Clkin.
> But Delay is 15ns ,although My Clkin is 25MHz.
> So My Design does not operate properly.
>
> Why does this serious pad delay occur?
> How can I reduce this pad delay?
>

This is an easy, and I think someone else might have already said it.
Just don't do that.  You're going against the architecture of the part
and the basic rules of synchronous design.  If the requirements change
so late in the development, you're going to incure a time penalty,
thats life.
>


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Article: 23083
Subject: Re: Virtex questions
From: Utku Ozcan <ozcan@netas.com.tr>
Date: Tue, 13 Jun 2000 20:48:24 +0300
Links: << >> << T >> << A >>

> [snip]
> 3. How to use the LUT as shift reg.

Please look at SRL16 and SRL16E element in the Libraries Guide.
For more info, Alliance or Foundation 2.1i Java-based document
interface on http://support.xilinx.com and go to Software Manuals.

Utku

--
I feel better than James Brown.

Article: 23084
Subject: Re: Altera vs Xilinx
From: Steve Dewey <steve@s-dewey123.demon.co.uk>
Date: Tue, 13 Jun 2000 21:31:28 +0100
Links: << >> << T >> << A >>


I only know Altera. Be sure to read their datasheets _very_ carefully.
The APEX documentation implies at the start that all APEX -e grade parts
have LVDS I/O. In fact when you dig deep into the datasheet only the
20K300E and bigger parts have it, and then only in the BGA packages.

In article <8i3knp$noq$1@nnrp1.deja.com>, swfpga@my-deja.com writes
>Not to start a religious war, but I am in the process of choosing
>between Altera(Apex/Flex) and Xilinx(Virtex/Spartan) for our design.
>Can someone post a message of what the advantages and disadvantage  of
>their FPGA's are?  e.g. cost, support, performance, ease of use, ...
>We will use Verilog, BTW.
>We are going to implement a video scaling application.
>
>thanks
>
>SW
>
>
>Sent via Deja.com http://www.deja.com/
>Before you buy.


-- 
Steve Dewey
A pissed altera user. (remove 123 for email)

Article: 23085
Subject: Re: Free tools "OpenTech cdrom"
From: "Domagoj" <domagoj@engineer.com>
Date: Wed, 14 Jun 2000 01:23:42 +0200
Links: << >> << T >> << A >>


> From the downloader's point of view: which ISP is free? And who wants to
> spend ages downloading 650Mb (a CD's worth) over the net. Even at
> 30Kbytes a second (the fastest I've ever got anything over the net, even
> with a fixed connection) that would take 6 hours. And for us poor ppl
> with 56Kbit modems, its at least 26 hours. Since I rarely get better
> than 28.8, it would be quicker and cheaper for somebody to post me a CD.

    but, you still can use wget, lftp, ncftp on unix. it can take days, but
never mind, it can run in the background. the next day you burn your cd
on the work .
-------------------------------------------
-             Domagoj              -
- Domagoj@engineer.com -
-------------------------------------------


> -- Andrew MacCormack                      email:  andrewm@cadence.com
> -- Senior Design Engineer
> -- Cadence Design Systems, Alba Campus, Livingston EH54 7HH, Scotland
> -- Phone: +44 1506 595360                        Fax: +44 1506 595959

Article: 23086
Subject: ASIC DESIGN
From: ramesh_z@my-deja.com
Date: Wed, 14 Jun 2000 01:03:49 GMT
Links: << >> << T >> << A >>

Dear friends,

            I want to know whether rtl is the
front end of all asic design. I am intrested to
know the different steps in asic design . How
this is different from design using logic
synthesis tools.
Please suggest some points and references.

Thank you
ramesh


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Article: 23087
Subject: Re: Virtex questions
From: "Domagoj" <domagoj@engineer.com>
Date: Wed, 14 Jun 2000 03:19:07 +0200
Links: << >> << T >> << A >>

Hi,
    I was looking there for a new library guide pdf, but couldn't find it.
Is it available at all ??

--

-------------------------------------------
-             Domagoj              -
- Domagoj@engineer.com -
-------------------------------------------
Utku Ozcan <ozcan@netas.com.tr> wrote in message
news:394673E8.8C22A74B@netas.com.tr...
> > [snip]
> > 3. How to use the LUT as shift reg.
>
> Please look at SRL16 and SRL16E element in the Libraries Guide.
> For more info, Alliance or Foundation 2.1i Java-based document
> interface on http://support.xilinx.com and go to Software Manuals.
>
> Utku
>
> --
> I feel better than James Brown.
>
>
>

Article: 23088
Subject: delay variation
From: baneshwar_s@my-deja.com
Date: Wed, 14 Jun 2000 02:04:55 GMT
Links: << >> << T >> << A >>

dear sir,

        I have designed some fast multiipliers
in vhdl. I have synthesized both the pipelined
and the non pipelined (without pipeling)
version of fast multipliers.But What I found out after pipelining
my design and then synthesizing it the delay
had reduced by 6ns, which instead should have
increased because of pipelined registers which
I have added. I used the constraint optimize for speed for the
pipelined and the non pipelined(without pipelining) carry save
multiplier. I am using
viewsynthesis and technology mapping of xc4000.
I want to know the reason for this.

THANK YOU,
BANESHWAR.S



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Article: 23089
Subject: FS: AsicGuru.com DOMAIN on EBAY
From: "Robert L. Metcalf" <rlm@kauai.mv.com>
Date: Tue, 13 Jun 2000 22:23:14 -0400
Links: << >> << T >> << A >>

http://cgi.ebay.com/aw-cgi/eBayISAPI.dll?ViewItem&item=357200030

Article: 23090
Subject: FS: FpgaGuru.com DOMAIN
From: "Robert L. Metcalf" <rlm@kauai.mv.com>
Date: Tue, 13 Jun 2000 22:32:44 -0400
Links: << >> << T >> << A >>

http://cgi.ebay.com/aw-cgi/eBayISAPI.dll?ViewItem&item=357196271

Article: 23091
Subject: Re: FS: FpgaGuru.com DOMAIN
From: bobperl@best_no_spam_thanks.com (Bob Perlman)
Date: Wed, 14 Jun 2000 04:54:51 GMT
Links: << >> << T >> << A >>

On Tue, 13 Jun 2000 22:32:44 -0400, "Robert L. Metcalf"
<rlm@kauai.mv.com> wrote:

>http://cgi.ebay.com/aw-cgi/eBayISAPI.dll?ViewItem&item=357196271
>

Golly, bidding starts at $5k...what a bargain!

I assume you're keeping the MoneyForNothing domain for yourself.

Bob Perlman

-----------------------------------------------------
Bob Perlman
Cambrian Design Works
Digital Design, Signal Integrity
http://www.best.com/~bobperl/cdw.htm
Send e-mail replies to best<dot>com, username bobperl
-----------------------------------------------------

Article: 23092
Subject: Re: FS: FpgaGuru.com DOMAIN
From: Phil Hays <spampostmaster@sprynet.com>
Date: Tue, 13 Jun 2000 22:10:42 -0700
Links: << >> << T >> << A >>

Bob Perlman wrote:

> I assume you're keeping the MoneyForNothing domain for yourself.

What about ChicksForFree?


-- 
Phil Hays
Clues for sale or rent.
Hints for just 50 cents.

Article: 23093
Subject: FPGA Express & MAX+PLUS II Using ?
From: "ÀÌº´¿í" <bwlee@kuic.kyonggi.ac.kr>
Date: Wed, 14 Jun 2000 15:25:01 +0900
Links: << >> << T >> << A >>

Dear friends,

    I want to know what is the best options in designing with FPGA Express
and MAX+PLUS II ?

these day, I code the design whit VHDL,
synthesize and optimize the design with FPGA Express
and then recompile and P&R with Max+plus II.

i don't know what is the best options in FPGA Express and Max+plus.
I try to find the best option in my design flow, but it is very hard.

could you explain the best options in design flow with FPGA Express and
Max+plus II ?

Thank you for reading

Byung-Wook, LEE , mailto : bwlee@kuic.kyonggi.ac.kr

Article: 23094
Subject: Req: Source for Filter Design
From: Heinrich Fonfara <fonfarah@ibmt.fhg.de>
Date: Wed, 14 Jun 2000 10:34:29 +0200
Links: << >> << T >> << A >>

Could someone please tell me a source for information about filter
design
with FPGAs, especially simple filters that don`t need any multiplication

(e.g. comb filter, sinc filter)
Thanks for any help

Heinrich Fonfara
Fraunhofer IBMT
Ensheimer Str. 48
66386 St. Ingbert

Tel.:+49 6894 980-212
Fax.:+49 6894 980-400

Article: 23095
Subject: Re: Free tools "OpenTech cdrom"
From: Patrick Schulz <schulz@rumms.uni-mannheim.de>
Date: Wed, 14 Jun 2000 11:46:38 +0200
Links: << >> << T >> << A >>

Domagoj wrote:
> 
> > From the downloader's point of view: which ISP is free? And who wants to
> > spend ages downloading 650Mb (a CD's worth) over the net. Even at
> > 30Kbytes a second (the fastest I've ever got anything over the net, even
> > with a fixed connection) that would take 6 hours. And for us poor ppl
> > with 56Kbit modems, its at least 26 hours. Since I rarely get better
> > than 28.8, it would be quicker and cheaper for somebody to post me a CD.
> 
>     but, you still can use wget, lftp, ncftp on unix. it can take days, but
> never mind, it can run in the background. the next day you burn your cd
> on the work .

Domagoj,
I fully agree to that. All universities and most of the big companies have permanent connections to
the web.

Patrick

-- 
Patrick Schulz (schulz@rumms.uni-mannheim.de, pschulz@ieee.org)
University of Mannheim - Dep. of Computer Architecture
68161 Mannheim - GERMANY / http://mufasa.informatik.uni-mannheim.de
Phone: +49-621-181-2720     Fax: +49-621-181-2713

Article: 23096
Subject: for my students
From: laurent <lcrozier@iutsoph.unice.fr>
Date: 14 Jun 2000 10:58:06 GMT
Links: << >> << T >> << A >>


Hello,

I'm looking for a calculator programmed in FPGA to give to my students.

I don't have time to do it.
Thank u for your help

   Laurent.

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
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Le : Wed Jun 14 12:58:06 2000 depuis l'IP : gtr305p3.unice.fr [VIP 3556928]

Article: 23097
Subject: for my students + my E-mail
From: laurent <lcrozier@iutsoph.unice.fr>
Date: 14 Jun 2000 10:59:04 GMT
Links: << >> << T >> << A >>


Hello,

I'm looking for a calculator programmed in FPGA to give to my students.

I don't have time to do it.
Thank u for your help

   Laurent.


Please send it by E-mail : lcrozier@iutsoph.unice.fr

=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Article poste via Voila News - http://www.news.voila.fr
Le : Wed Jun 14 12:59:04 2000 depuis l'IP : gtr305p3.unice.fr [VIP 3556928]

Article: 23098
Subject: Re: DLL in virtex fpga
From: "B. Joshua Rosen" <bjrosen@polybus.com>
Date: Wed, 14 Jun 2000 09:54:54 -0400
Links: << >> << T >> << A >>

Here's an example for dividing by 4 in verilog,

CLKDLL #(4) clkdll_c4_1
	(

		.CLKIN                           (clk_2x),
		.CLKFB                           (clk_4x),
		.RST                             (lock_dly),
		.CLK0                            (srcclk_b),
		.CLK90                           (xxxclk[4]),
		.CLK180                          (xxxclk[5]),
		.CLK270                          (xxxclk[6]),
		.CLK2X                           (srcclk4x),
		.CLKDV                           (clk_dv_src),
		.LOCKED                          (lock_b)
	);

> 
> Hi Everybody,
> 
> thanks to Mark for the advice, but now I have another problem.
> Th simutor only seems to divide by 2 while I need divisions of 2, 8 and
> 16.
> I have some prblems setting the attributes.
> Can someone help me with this problem
> 
> thanx
> 
> christophe

Article: 23099
Subject: aeos - ebusiness
From: swally4771@my-deja.com
Date: Wed, 14 Jun 2000 14:04:20 GMT
Links: << >> << T >> << A >>

has anyone out there heard or know anything about a new product called
aeos any information on this software product would be glady accepted
by yours truly

cheers

swally


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