Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
On Sun, 25 Jun 2000 17:33:57 +0200, Claas Richter <clri@gmx.de> wrote: >Hello! > >Does anyone have any experience in the use of FPGAs for connecting to >the IDE-Bus? > >Or has anybody implemented an IDE/ATA-Bus-Interface for FPGAs ?? >I need it to read and write to a harddisk. > >Thank you >Claas > I think you will find this VERY handy: http://www.cs.tamu.edu/course-info/cpsc483/spring98/rabi/xilinx/toc.html check out chapter 24. The other chapters are nice too! Beware, some of the word docs are HUGE. And if you want bleeding edge data with complete timing charts, IBM is nice enough to put their OEM data sheets online -- for the Deskstar 75GXP, no less, at ATA100 speeds. http://www.storage.ibm.com/techsup/hddtech/prodspec/dtla_spw.pdf beware, that's a 2MB PDF. --Beware, shameless profiteering follows... If you found the info useful, do us both a favor and sign up to get paid to surf at: (hey, it's about $50 a month combined when maxed out!) http://www.getpaid4.com/?bryguy2000 http://www.alladvantage.com/go.asp?refid=MDE768Article: 23476
> For example, until V2.2 of PCI, you did not know how long you had > between reset and first operation of the bus. This was a problem for > many PCI Core designs. I'll only address this one issue here... I have designed more PCI cores that probably most anyone, and I NEVER ran into this 'supposed' problem, though I have heard a lot of yammering about it. I do not disagree that there is a hole in the PCI 2.1 spec for characterizing the reset signal on the PCI bus, but is this consequential? I do not believe it is, or at least in all the PCI interfaces I've designed, it hasn't been an issue. There are two types of PCI systems. Embedded, which you have almost full control over what happens in the system, and System based PCI busses. Typically, embedded can be the worst case, since the CPU can start doing configuration very quickly...but typically, in this situation, the entire system is being designed, and then the designers have control over this. It is simply a matter of characterizing it, and properly designing the 'system'. In, say, an x86 PC (and any Alpha system too...), there is SOOOO much time before the PCI configuration process takes place. The BIOS is booting from FLASH, then it has to run tests, then check for a graphics card, then test memory... All this takes FAR longer than the programming time for the FPGA, which is on the order of 1 second tops (XCV400 at 2.5Mbits at 2.5MHz). I would be curious if anyone REALLY ran into this as an issue in a commercial system. If so, I would like to know the details of the system board. I know that upon first glance, good engineering dictates being aware of this as a potential issue, and since it's uncharacterized, it is certainly a red flag to raise...but in reality, for me, it has been a non-issue. Anyway, the issue you mention was not a reset issue, this was an FPGA configuration time issue...will the FPGA be programmed before the system asks it to do something.Article: 23477
"R. T. Finch" wrote: > > The confusing aspect is the difference between the number of bits of storage > available and the number of possible states this storage may represent. 40 > bits of storage (16+16+8) may have one of 2^40 _possible_ values. However, > it is important to note that it may have only _one_ of these values. IE 40 > bits of stoarage can't represent every different possible state at the same > time, only one at a time! ...snip... > The best approach may be to simply state that given x inputs, one of y > different output (states) can be produced. If you wnat to take functions to > the extreme you could claim that an infinite number of functions can be > handled, because you can define the function to be as complex as you like, > however all of these functions would reduce to "given x inputs, one of y > different output (states) can be produced". > > If I got the right answer, do I get a prize - pizza would be good :) ? > Rob > > > > Inputs Number of memory bits Functions > > > > 1 2 4 > > > > 2 4 16 > > > > 3 8 256 > > > > 4 16 65536 > > > > N 2^N 2^(2^N) I don't know who typed in this table, but it is correct for a general logic function. If you have N inputs, you will have 2^N input combinations. There are 2^N different ways the inputs can be connected and each one can produce an independant output value. So you have 2^N output values which can each be one of two states. So you have 2^(2^N) possible functions that map the N inputs and 2^N input combinations to the output. Example: 1 input function | Output IN| 0 1 2 3 --|-------- 0 | 0 0 1 1 1 | 0 1 0 1 With one input there are 2^N input combinations (0, 1) and 2^(2^N) or 4 functions. 2 input function IN | Outputs A B| 0 1 2 3 4 5 6 7 8 9 A B C D E F ------------------------------------ 0 0| 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1| 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0| 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1| 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Here there are 2 inputs, 4 input combinations and 16 functions. In fact it is a standard way of specifying the function in logic analysis to use the number from such a table since it completely specifies a function. This number is what gets loaded into the LUT RAM in a Xilinx FPGA. So you don't get the pizza. Sorry :( -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23478
Rob, you have it all wrong.
The question was: How many different "black-box" circuit can be implemented
with a look-up table.
And the answer is 2 exp(2exp.n) which means 16 different functions for a
2-input LUT. ( Nobody ever claimed 256 for this. You got that wrong, too)
There are the basic functions like: and, or, xor, but then there are possible
"bubbles" on the input(s) and/or the outputs, and then there is deMorgan... And
there is the "ignore" function...
It's much simpler to look at it as black box: You can test the behavior of a
combinatorial black box with two inputs exhaustively by applying four test
vectors (neither more nor less), and observing the four results.
Obviously, there are 16 different response patterns. ( and there are 256 for 3
inputs, 64K for 4 inputs, 16million for 5 inputs etc)
I have used these questions to interview many hundreds of applicants for
applications engineer jobs, over the past 20 years. Anybody who could not
(finally) answer these questions satisfactorily never got an applications job
at Fairchild, Zilog, AMD and now Xilinx. The smart candidates usually "got it"
in a few minutes.
Greetings
Peter Alfke
"R. T. Finch" wrote:
> The confusing aspect is the difference between the number of bits of storage
> available and the number of possible states this storage may represent. 40
> bits of storage (16+16+8) may have one of 2^40 _possible_ values. However,
> it is important to note that it may have only _one_ of these values. IE 40
> bits of stoarage can't represent every different possible state at the same
> time, only one at a time!
>
> I think you have the right idea. To calculate the potential number of
> "states" shouldn't it be 2 * (n+1) not 2 ^ (n+1), because not all the
> combinations can be active at the same time (there is only one output). IE.
> you're not combining state 0000 and 0001, but just counting them. For
> example with a two input function (under the same constraints), there are
> eight basic functions (and, or, xor, andc) * 2 for possibly inverting the
> output, _not_ 2^(2+1) = 256 functions. Note that as a black box, with two
> inputs and a single output, we could model all possible states using a truth
> table with just four entries. It all depends what you want to consider to be
> a function. I could call this a single function (sigma) or I could claim it
> represents eight different functions. However I think we could define a
> function, at a minimum, as something that produces a different output than
> any other 'function'.
> Thus the 9-input Xilinx 4+4+3 FGH tree would result in 2 * (3 + 1) = 8
> states for the 3-LUT times(I think this is a product operation here) 2 * 2 *
> (4 + 1) = 20 for the two four LUTs which results in a total of 160 possible
> states.
> This is certainly far less than the 2^40 number (but I'm not comparing
> apples to apples here).
> We know for certain we cannot have more than 2^(9+1) (1024) states because
> there is only nine inputs and all possible outcomes can be represented in
> 2^10 values. (IE think of a black box with 9 inputs and a single output) 160
> possibilities is pretty darn good considering the small amount of ram used.
> Note: I think we have to distinguish between the number of possible
> functions implemented and the number of possible functions implemented with
> unique results. I think the number of possible states may represent the
> number of possible functions with unique results (but don't quote me). The
> possible number of functions implemented may be quite large (although I
> seriously doubt it's anywhere near 2^25), however the number of unique
> results they produce (160) is quite limited.
> What can be said is that for any possible combination of inputs, there is
> only one of 160 states selected. Compare that to the 1024 that would be
> available with a 512 bit ram.
>
> The best approach may be to simply state that given x inputs, one of y
> different output (states) can be produced. If you wnat to take functions to
> the extreme you could claim that an infinite number of functions can be
> handled, because you can define the function to be as complex as you like,
> however all of these functions would reduce to "given x inputs, one of y
> different output (states) can be produced".
>
> If I got the right answer, do I get a prize - pizza would be good :) ?
> Rob
>
> "Tom Burgess" <tom.burgess@home.com> wrote in message
> news:39555A39.5345F956@home.com...
> > I withdraw the conjecture as stated. If true, one could implement a 512x1
> ROM in
> > a single CLB which is obviously not the case, darn it.
> >
> > post in haste, regret at leisure,
> > tom
> >
> > Tom Burgess wrote:
> > >
> > > Assertion: for an n-input LUT, with input swapping permitted,
> > > there are 2^(n+1) possible unique functions possible.
> > >
> > > Nor-rigorous proof: For n inputs, there are n+1 possible unique states
> available,
> > > e.g. for 4 inputs, the 5 unique states are {0000, 0001, 0011, 0111,
> 1111}.
> > > (with swapping allowed, 0001 is is equivalent to 1000, 0100, and 0010)
> > > Since the n inputs to the LUT can only assume n+1 states, and the
> contents of
> > > each LUT entry are either 0 or 1, there are therefore 2^(n+1) possible
> > > unique LUT patterns (functions) available. So the result for n=4 is 32.
> > >
> > > Conjecture: the internal structure of the LUT is not important. With
> input
> > > swapping permitted, any function of n inputs is possible. So a single
> > > 512x1 LUT is equivalent to the 9-input Xilinx 4+4+3 FGH tree. Both can
> > > therefore implement 2^(9+1) = 1024 unique functions. The proof is left
> as
> > > exercise for the student :)
> > >
> > > regards, tom
> > >
> > > Philip Freidin wrote:
> > > >
> > > > In article <8j2b2o$ar3$1@news.ust.hk>,
> > > > WU Chi Hang FOX <eefox@uxmail.ust.hk> wrote:
> > > > > First, thanks Rickman. However, I am really stucked at that, I
> am
> > > > >not asking about HW questions, I really want to count how many
> fuctions
> > > > >that a cascaded LUTs can implement.
> > > > > For 1-bit LUT, I know there are 4 functions
> > > > >
> > > > > Output
> > > > > Input Function 1 2 3 4
> > > > > 0 0 0 1 1
> > > > > 1 0 1 0 1
> > > >
> > > > Fine. You have enumerated all the functions of a 1 input LUT
> > > >
> > > > Inputs Number of memory bits Functions
> > > > 1 2 4
> > > > 2 4 16
> > > > 3 8 256
> > > > 4 16 65536
> > > > N 2^N 2^(2^N)
> > > >
> > > > >Function 1 is a zero function, Function 2 is follower, Function 3 is
> NOT
> > > > >Function 4 is a one function.
> > > >
> > > > So depending on your view of life, not all of these are 'interesting'.
> > > >
> > > > Function 1 and 4 ignore the input, function 2 is a wire, and function
> 3
> > > > is an inverter. Maybe only the inverter case is interesting, depends
> what
> > > > you had for breakfast.
> > > >
> > > > > However, what I am concerning is that, even there are 4
> functions,
> > > > >utimatelly, it is only 0 and 1 pass into the LUT, so, it does not
> matter.
> > > > >So, what I think is, no-matter it is cascaded or not, the maximum
> > > > >function is determined by the last LUT, so for this case, the no. of
> functions
> > > > >is 2^4.
> > > >
> > > > For this case maybe, but remember that in the following LUT, it too
> has
> > > > cases where the inputs are ignored, or the output is the inversion or
> > > > pass thru of one input, and other inputs are ignored. Which do you
> > > > consider interesting?
> > > >
> > > > > Then bringing back to the XC4000, if that is the case, then
> why
> > > > >the total number of funtions is 2^40 instead of 2^8 ?
> > > >
> > > > Since the XC4000 CLB has 40 bits total in the two 4-LUTs, and the one
> > > > 3-LUT, there are exactly 2^40 possible configurations.
> > > >
> > > > I believe they are not all interesting, because MANY of these ignore
> some
> > > > of the inputs, or are synonyms of each other, with just the input
> signals
> > > > swapped. The reason that the pin swaped equivalent functions are not
> > > > interesting, is because the place and route software does this pin
> > > > swapping all the time, and permutes the LUT contents to account for
> the
> > > > pin swapping. I wouldn't be surpised if the number of unique patterns
> is
> > > > less than 2^25. The only way to find out the real number may be
> through
> > > > an exhaustive search.
> > > >
> > > > Philip Freidin
Article: 23479John Fielden wrote in message <8j8hg4$ek0$2@schbbs.mot.com>... >I'm looking for a Virtex demonstration board. Something that has at least >one of the larger parts (1000 or 1000E, and above). I would prefer an E >part. > >Does anyone know who makes such a thing? > >Thanks, > >John Fielden > There's quite a good list at the Programmable Logic Jumpstation website - just click on the Boards button: http://www.optimagic.com/ Regards, Tony Burch www.BurchED.com.auArticle: 23480
I am looking at what it will take to use JTAG boundry scan on my next DSP board. I expect the board to have several FPGAs, one TI DSP and possibly a 16 bit microController, all with JTAG. I would like to string all of these devices in line to allow software to use the boundry scan features to test the interconnections on the board. But I have read from several people who have had problems with this approach. The biggest one seem to be that adding other devices to the JTAG path interferes with the operation of the XDS-510 emulator. Does anyone have any experience with this? Have you done this and did it work? Were there any special design features I need to know about, like does the DSP need to be first in the chain (or the last)? I don't expect to be using the FPGA JTAG ports in any other way. But I may want to use the JTAG to program Flash on the microController. I have not selected the micro just yet, but is this expected to be a problem? -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23481
In article <3957C016.55A113AE@xilinx.com>, Peter Alfke
<peter@xilinx.com> writes
>
>
>louis_reginaldjean@my-deja.com wrote:
>
>> I'm in this field, so I'm a little bit confuse. Why FPGA publicity said
>> something that it's "better than doing ASIC" or something like that, .
>> I learned that ASIC mean Aplication Specific Integrate Circuit (if I'm
>> not wrong). Why, what's the big differecne (and what can we called ASIC
>> anyway?) ?
>
>Acronyms are dangerous. they take on a life of their own.
>
>RAM for example stands for random access ( which every ROM also has), but
>now means read-write memory.
>
>Most people use the name ASIC for circuits that are customized ( through
>metal masks) by the chip manufacturer.
>Dedicated chips ( like ethernet controllers, hard disc controllers etc)
>are NOT called ASICs, although they are very much applications
>specific...)
>
>Who says names should be logical?
>
>Peter Alfke
>
The company I used to work for went through a phase of calling them
Customer Specific Integrated Circuits (CSIC), but that didn't sound very
pleasant in English.
Alan
--
Alan Fitch
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, BH24 1AW, Hampshire, UK
Tel: +44 (0)1425 471 223 Email: alan.fitch@doulos.com
Fax: +44 (0)1425 471 573
** Visit THE WINNING EDGE www.doulos.com **
Article: 23482Brian Drummond wrote: > The BDSL files seem to have the pinouts in a relatively > machine-digestible format, without going to quite such lengths. > I haven't had cause to automate it yet, just noted the possibility. > > - Brian From what I remember the BSDL files don't have banking info, LVDS pairs, info on special pins e.g. config, JTAG etc. In effect the process I described is now completely automated. All I have to do is feed in the device, package type, and the max number of IOs. I can then use this to generate, among other things, a schematic symbol.Article: 23483
Who knows about electronic drivers for Permanent-Magnet Brushless D.C. Motors ? Where and how to place Hall-effect sensors ? How to work SENSORLESS ? PWM regulation ?Article: 23484
Claas Richter wrote:
> Hello!
>
> Does anyone have any experience in the use of FPGAs for connecting to
> the IDE-Bus?
>
> Or has anybody implemented an IDE/ATA-Bus-Interface for FPGAs ??
> I need it to read and write to a harddisk.
>
> Thank you
> Claas
We implemented the full ATA spec last year in our MIPS system controller.
Basically the old-fashioned DMA modes are easy both single & multi - just
steal the normal Intel IORD/IOWR statemachines. The hard part comes with
UDMA where
o The protocol & hence the state machine is tediously complicated.
o There's a lot of async stuff to keep under control.
o You need to generate a 16 bit parallel CRC on the data for each data
burst and then send it back to the IDE
drive which does the checking. I think there's a description of how
to generate this in the ATA spec or the IBM data sheet.
Article: 23485Hi, Can someone tell me what I am doing wrong? I am trying to implement a simple PN generator using a Spartan chip as a learning exercise. I am using OSC4 to clock a number of FD_1 flip flops with a XNOR FB. The problem I am having is that it all works fine using the simulator but when I download it to the hardware I get no output. OSC4 is working as I get output from that but that is all, I get nothing out of the shift registers. Obviously I have omitted to do something but what? - CharlesArticle: 23486
Hi all, To simplify my design it is split into four different levels. The highest level is the testbench, then the fpga (=second level), the third level is a component (= another .vhd file) and in this third level a RAM block is created using the Xilinx CoreGenerator. Following the steps to do this there should also be a configuration for this RAM block : -- configuration <cfg_my_design> of <my_design> is -- for <my_arch_name> -- <Insert CONFIGURATION Declaration here> -- end for; -- end <cfg_my_design>; Then, in the next level up, the following text should appear in that file -- configuration <cfg> of <next_level> is -- for <arch_name> -- for all : <my_design> use configuration <cfg_my_design>; -- end for; -- end for; -- end <cfg>; However, this does not seem to work, and the compiler gives an error such as : (when compiling the second level) **Error: LINE 302 *** no formal corresponding to actual SAMPLECLK. (compiler/analyzer/3) It has something to do with the different levels in my design and how to link one to another, but I can't find out what it is. thanks christopheArticle: 23487
Hi Rick,
Rickman wrote:
> I am looking at what it will take to use JTAG boundry scan on my next
> DSP board. I expect the board to have several FPGAs, one TI DSP and
> possibly a 16 bit microController, all with JTAG. I would like to string
> all of these devices in line to allow software to use the boundry scan
> features to test the interconnections on the board.
Assuming all components are IEEE 1149.1 compatible, it *should* be OK.
> But I have read from several people who have had problems with this
> approach. The biggest one seem to be that adding other devices to the
> JTAG path interferes with the operation of the XDS-510 emulator. Does
> anyone have any experience with this? Have you done this and did it
> work? Were there any special design features I need to know about, like
> does the DSP need to be first in the chain (or the last)?
The idea is that you cannot directly use the emulator on your JTAG chain
because the resulting bitstream is not understood well by the emulation
software. What must first be done is a small text file to indicate the
emulation software the length of the JTAG instruction register of every
device placed before and after the DSP(s).
Thus, each non-DSP component will be placed in BYPASS (by shifting an all-1
pattern for the appropriate number of bits) and will only add a data bit (0)
to the chain. Based on this info, the emulation software will discard
irrelevant data and should work OK.
As for the position in the chain, I remember some people in c.a.fpga stating
that some positions (i.e. DSP being first) worked better. Was it pure
coincidence, a design issue or just a flaky JTAG compatibility, I couldn't
say.
Two TI documents are quite useful when discussing issues about emulation &
JTAG: "spdu079a.pdf" and "spra439.pdf"; they're worth a look (if you haven't
done it already).
Regards,
Étienne.
--
______ ______
*****/ ____// _ \_\*************************************************
* / /_/_ / /_/ / / Etienne Racine, Hardware Designer *
* / ____// __ /_/ Visual Systems Engineering *
* / /_/_ / / /\ \ \ CAE Electronics Ltd. *
*/_____//_/_/**\_\_\*************************************************
Article: 23488Hi Rick... I just got back from a jtag seminar by http://www.jtag.com. If you want to program flash in a timely manner, you should probably research the tools before you tapeout your design. The above mentioned folks can increase flash programming speed dramatically with a small circuit tweaks. Eric Pearson >I don't expect to be using the FPGA JTAG ports in any other way. But I >may want to use the JTAG to program Flash on the microController. I have >not selected the micro just yet, but is this expected to be a problem? > >Rick Collins > >rick.collins@XYarius.com > >Ignore the reply address. To email me use the above address with the XY >removed.Article: 23489
This is a multi-part message in MIME format. --------------AD154BE35A075027360FDCD6 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit XESS Corp. is releasing the first section of its "myCSoC" tutorial for free downloading at http://www.xess.com/myCSoC-CDROM.html. We will release a new section each week. Each section describes a design example for the Triscend configurable system-on-chip device (CSoC). The Triscend TE505 CSoC integrates an 8051 microcontroller core with a programmable logic array to create a chip whose software and hardware are both reprogrammable. The tutorial examples show how the Triscend FastChip development software is used to configure the TE505's programmable logic into peripheral functions that cooperate with the microcontroller core. -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 || --------------AD154BE35A075027360FDCD6 Content-Type: text/x-vcard; charset=us-ascii; name="devb.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Dave Vanden Bout Content-Disposition: attachment; filename="devb.vcf" begin:vcard n:Vanden Bout;Dave tel;fax:(919) 387-1302 tel;work:(919) 387-0076 x-mozilla-html:FALSE url:http://www.xess.com org:XESS Corp. adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA version:2.1 email;internet:devb@xess.com title:FPGA Product Manager x-mozilla-cpt:;-16464 fn:Dave Vanden Bout end:vcard --------------AD154BE35A075027360FDCD6--Article: 23490
>I am trying to implement a simple PN generator using a Spartan >chip as a learning exercise. > >I am using OSC4 to clock a number of FD_1 flip flops with a XNOR FB. > >The problem I am having is that it all works fine using the simulator >but when I download it to the hardware I get no output. > >OSC4 is working as I get output from that but that is all, I get nothing out >of the shift registers. > 1. You get no output means that I/O pins are in tristate or they simply don't switch ? 2. ( if I/O pins are in tristate ) How is DONE pin connected in your test board ? It's floating or it has a pull-up ? It's possible that you configured the startup sequence to wait for DONE pin to go high but the pin is floating and the FPGA doesn't enable the I/O pins; since this is an open drain pin it requires a pullup to bring it to a high state whan the FPGA has configured and releases it. 3. If you have a spare I/O pin, try to connect it to OSC4 signal and check if the clock is running.Article: 23491
Rascal wrote: > > >I am trying to implement a simple PN generator using a Spartan > >chip as a learning exercise. > > > >I am using OSC4 to clock a number of FD_1 flip flops with a XNOR FB. > > > >The problem I am having is that it all works fine using the simulator > >but when I download it to the hardware I get no output. > > > >OSC4 is working as I get output from that but that is all, I get nothing > out > >of the shift registers. > > > > 1. > You get no output means that I/O pins are in tristate or they simply don't > switch ? > > 2. ( if I/O pins are in tristate ) > How is DONE pin connected in your test board ? It's floating or it has a > pull-up ? > It's possible that you configured the startup sequence to wait for DONE pin > to go high but the pin is floating and the FPGA doesn't enable the I/O pins; > since this is an open drain pin it requires a pullup to bring it to a high > state whan the FPGA has configured and releases it. > > 3. > If you have a spare I/O pin, try to connect it to OSC4 signal and check if > the clock is running. Thanks for the reply, Take point 3 first, I have done that and it works. The pin I am outputing to works, because if you gate it with the clock you get clock out. What appears not to be happening is that the OSC4 won't clock the flip-flops. I simplified the circuit to drive a single flip-flop and that does not work either. I just looked at the CCT and the DONE pin appears to be floating, I will investigate that futher. - CharlesArticle: 23492
I will bet you a nickel that you need to send a few more CCLK pulses to the chip. You didn't say how you are loading it, but if you are not using the Xchecker cable or some other known good method the chip may not be getting fully out of config. When all of the data bits have been sent to the FPGA, it enters the "Start-Up" sequence. This requires a small number of clocks to cycle through the process of enabling the IOs and clearing the GSR (reset) to all of the FFS and bringing the DONE signal high. These can be done in any order (pretty much). But you have to have a clock to make it work. By using the OSC4 clock for your designed circuit, you may not be getting clocks through to the startup block. I am not sure of the details on how to use the programmable startup features and the Spartan doc doesn't detail it clearly. Try reading the XC4000 documentation, it is much better on this. I think that you actually have to change options in the bitstream generation to muck it up. If you didn't do that, I believe the entire startup operates from the CCLK by default. So try driving an extra CCLK or two (or ten) and see if your circuit starts working. If you are using the Xchecker cable, then... nevermind. Charles Brain wrote: > > Rascal wrote: > > > > >I am trying to implement a simple PN generator using a Spartan > > >chip as a learning exercise. > > > > > >I am using OSC4 to clock a number of FD_1 flip flops with a XNOR FB. > > > > > >The problem I am having is that it all works fine using the simulator > > >but when I download it to the hardware I get no output. > > > > > >OSC4 is working as I get output from that but that is all, I get nothing > > out > > >of the shift registers. > > > > > > > 1. > > You get no output means that I/O pins are in tristate or they simply don't > > switch ? > > > > 2. ( if I/O pins are in tristate ) > > How is DONE pin connected in your test board ? It's floating or it has a > > pull-up ? > > It's possible that you configured the startup sequence to wait for DONE pin > > to go high but the pin is floating and the FPGA doesn't enable the I/O pins; > > since this is an open drain pin it requires a pullup to bring it to a high > > state whan the FPGA has configured and releases it. > > > > 3. > > If you have a spare I/O pin, try to connect it to OSC4 signal and check if > > the clock is running. > > Thanks for the reply, > > Take point 3 first, I have done that and it works. > > The pin I am outputing to works, because if you gate it with the clock you get clock out. > > What appears not to be happening is that the OSC4 won't clock the flip-flops. > > I simplified the circuit to drive a single flip-flop and that does not work either. > > I just looked at the CCT and the DONE pin appears to be floating, I will investigate that futher. > > - Charles -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 23493
Christophe Heyert wrote in message <39587DEA.CADBFEEC@rsd.bel.alcatel.be>...
>Hi all,
>
>To simplify my design it is split into four different levels. The
>highest level is the testbench, then the fpga (=second level), the third
>level is a component (= another .vhd file) and in this third level a RAM
>block is created using the Xilinx CoreGenerator.
>Following the steps to do this there should also be a configuration for
>this RAM block :
>
>-- configuration <cfg_my_design> of <my_design> is
>-- for <my_arch_name>
>-- <Insert CONFIGURATION Declaration here>
>-- end for;
>-- end <cfg_my_design>;
>
>Then, in the next level up, the following text should appear in that
>file
>
>-- configuration <cfg> of <next_level> is
>-- for <arch_name>
>-- for all : <my_design> use configuration <cfg_my_design>;
>-- end for;
>-- end for;
>-- end <cfg>;
>
>However, this does not seem to work, and the compiler gives an error
>such as :
>(when compiling the second level)
>
>**Error: LINE 302 *** no formal corresponding to actual SAMPLECLK.
>(compiler/analyzer/3)
>
>It has something to do with the different levels in my design and how to
>link one to another, but I can't find out what it is.
sounds like you didn't completely specify the ports on the CORE RAM --
specifically, is the clock hooked up? Is it a valid signal? Make sure your
RAM instantiation is correct.
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"A sufficiently advanced technology is indistinguishable from magic"
--Arthur C. Clarke
Article: 23494Rickman wrote: > > I will bet you a nickel that you need to send a few more CCLK pulses to > the chip. You didn't say how you are loading it, but if you are not > > If you are using the Xchecker cable, then... nevermind. > Hello, I am using the parallel cable from Xilinx and Foundation 1.5i, I have already discovered that you need the Xchecher to verify the download, that caught me out! I am using the Insight FPGA board H/W not the Xilinx one. I think it is something to do with the start-up as it is only flip-flops that seem to be affected normal logic is fine. I have no start-up block in the Schematic I was hoping the default action would be enough. I have read most of the documentation that came with it, but I have ground to a halt, maybe I should try clocking it from an external source instead ? And I thought this was going to be easy! - CharlesArticle: 23495
Hi, in short and concise, as you can find much more in most power electoronics and motion control books. brushless motor while they are working as DC motor have no brush and your interface to them is like to a 3 phase motor (even tho' the concept of operation is differnt), so most drivers are base on 6 transistors which usually are POWER-MOSFET/MOSFET or IGBT. the hall sensors will usually position in 120 degree one from each other. to work sensorless usually mean that instead of using sensors for feedback to the controler of the driver you use a current sense to determine the position. PWM is short for ulse Width Modulation that in basic mean that you work in same amplitude and same frequancy and you change the duty-cycle to get differenet effective value. BTW I'm not sure this is the best site for this question, you might try to find a more suitable site for motion control issues. have a nice day Illan In article <8j9pim$fo$1@trex.antw.online.be>, "DHULST" <kf000514@online.be> wrote: > Who knows about electronic drivers for Permanent-Magnet Brushless D.C. > Motors ? > Where and how to place Hall-effect sensors ? > How to work SENSORLESS ? > PWM regulation ? > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 23496
Mere semantics, but Actel claims there parts are FPGAs, which they are. The definition of FPGA does not claim to be "re-configurable"--it is just "configurable" by the user (Field-Programmable-Logic-Device.) Jason On Mon, 26 Jun 2000 23:24:44 +0200, "Carlhermann Schlehaus" <carlhermann.schlehaus@t-online.de> wrote: >Hi, > ><louis_reginaldjean@my-deja.com> schrieb im Newsbeitrag >news:8j88se$olq$1@nnrp1.deja.com... >> I'm in this field, so I'm a little bit confuse. Why FPGA publicity said >> something that it's "better than doing ASIC" or something like that, . >> I learned that ASIC mean Aplication Specific Integrate Circuit (if I'm >> not wrong). Why, what's the big differecne (and what can we called ASIC >> anyway?) ? > >An FPGA is a reconfigurable IC, thus by changing the configuration >information (what's often done by changing the configuration Eprom) >you can at anytime change the IC functionality. >It's somewhat an "ASIC", as it's functionality depends on the >user written (Thus Application specific) code. >But, while the FPGA is reconfigurable an ASIC isn't reconfigurable >at all. The functionality of an ASIC is hardware coded. The >information of the configuration an FPGA derives from it's EPROM >is coded in the chip's layers. >Thus an ASIC isn't your choice if you have to change something, >but for high volume production it's the cheaper solution. > >HTH, Carlhermann Schlehaus > > Jason T. Wright Cygnion CorpArticle: 23497
I do a little of both; create a simple sim model (which Leonardo would
optimize out), and then tell Leonardo where I want the buffers. E.g.,
set_attribute -port c48mhz -name PAD -value BUFGP
set_attribute -net usb_clk -name PAD -value BUFGPINT
Jason
On Mon, 26 Jun 2000 22:40:37 +0100, "Mike Johnson" <mikej@freeuk.com>
wrote:
>It's no great problem to instantiate a global buffer - just create a
>component called BUFG (See library guide for port details) and drop it in.
>I create my own simple simulation model for these primitive's as well,
>rather than relying on the large, slow Xilinx provided libs.
>
>Although you can probably persuade the synthesiser, In the past I've found
>this easier and quicker than trying to find the magic incantation (which
>often it seems to ignore anyway)!
>
>mikej@REMOVEfreeuk.com
>
>Matt Gavin <mtgavin@collins.rockwell.com> wrote in message
>news:3957B1CA.A2FEC324@collins.rockwell.com...
>> FPGA gurus,
>>
>> I am a Synplicity user who is trying Leonardo for the first time.
>> I am wondering if Leonardo will infer/place global buffers
>> on internal clocks your design, even if the design
>> doesn't explicitly place the buffer in the VHDL. (Synplify does this
>> inferrence well.)
>>
>> I have run Leonardo once already, and it placed global buffers
>> on the three clocks that are on external pins. However, I have one
>> internally-generated clock which needs to use the fourth buffer in my
>> virtex part. Leonardo didn't find it and place a buffer on it. Again,
>> I want the tool to infer the buffer so I don't have to place it in the
>> VHDL
>> code.
>>
>> Can Leonardo do this inferrence? Can I tell it to do this? If not, I
>> will have to stick
>> with Synplify, as I would rather not manually instantiate global buffers
>> in
>> my VHDL.
>>
>> Thanks in advance,
>>
>> Matt
>>
>
>
Jason T. Wright
Cygnion Corp
Article: 23498I should point out that I was not discussing the number of functions available from an n-input LUT (2^(2^n)), but the number of "unique" functions, i.e. those which cannot be generated from another function by arbitrarily permuting (swapping) the input pins - which I believe to be 2^(n+1). The difference is that while n inputs can assume 2^n binary states, only n+1 of those states are unique in this sense. Apologies for any confusion this may have caused, Tom Burgess "R. T. Finch" wrote: > <snipped> > I think you have the right idea. To calculate the potential number of > "states" shouldn't it be 2 * (n+1) not 2 ^ (n+1), because not all the > combinations can be active at the same time (there is only one output). IE. >Article: 23499
I'm new to FPGA/HDL, and assigned to a "proof of concept" project porting legacy C code to FPGA, hoping for significant execution speed improvements. What books/hardware/software tools can anyone recommend to help us get reportable results soonest/cheapest? Thanks for all your help, Eliot
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z