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As I recall, the 386 coprocessor interface was incredibly clunky. I wouldn't be surprised if a large chunk of the gates went just to this. Add on another hefty chunk to meet the finicky, exception-ridden IEEE mathematical spec, which alas went way over the heads of most application writers, at least until they learned how to disable underflow, NAN exceptions, and whatever else crashed their demos. regards, tom Peter wrote: > > >We are currently involved in a project to create an 80C187 replacement ASIC > >with the > >intermediate design to be tested in an FPGA. At last count about 600K+ gates > >in a Virtex 800 part and 15 months of effort and counting . A license from > >Intel > >is also required and not cheap. > > I bet the 8087 wasn't anywhere near 600k gates. > > Peter. > -- > Return address is invalid to help stop junk mail. > E-mail replies to zX80@digiYserve.com but remove the X and the Y. > Please do NOT copy usenet posts to email - it is NOT necessary.Article: 22851
dear friends,
Please suggest me the best way of implementing wallace
trees since there are many ways of writing it. I am intrested only in
simulation and synthesis and find the resulting delay and I am not
intrested in its implementation. I also want to implement the mplr
using counters and compressors. Please suggest which is better and
which method results in a smaller delay.
email: baneshwar.s@mailcity.com
thanks in advance,
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 22852On Tue, 16 May 2000 15:50:22 +0800, "JX" <jiangx1@asme.org> wrote: >Hi, All, > > My supervisor ask me to design some USB inferace with >FPGA, where can I find any resource to implement that? > >Thanks a lot! >Jesse Here are a couple of USB resources from my bokmark file. As far as I remember the second one offers a low cost USB interface development kit http://www.lvr.com/usb.htm http://www.activewireinc.com/ - BrianArticle: 22853
myself wrote: > > Simple 256k Dram tester code > Hi I would like to program a FPGA to write to and read from an older > 256k Dram. > This is to check for errors i.e. data in should = data out unless a > cell is damaged or upset from environmental testing > > I would need to generate RAS, CAS, the address (a0 to a8)(512 rows x > 512 column=262144 cells), and data (one bit hi or low). > I will use up counters to provide the address and data decoding. > > Should I use a state machine or just multiplex the addressing? > Does anyone have some VHDL code that I could refer to or adapt for my > application? > > I am looking for a simple way to do this. > > Thanks > M P Brown. > > Ps if code is to big to post it can be emailed to: mpbrown@magma.ca You will need to multiplex the addresses AND use a state machine. The DRAM needs several strobes as you are aware with rather complex timing constraints with the address. The best way I have found to generate all of this timing is with a state machine (FSM) with at least 6 states. Then you will need another FSM to control the higher level process of writing and reading of multiple values and patterns. Once you have selected the exact tests you wish to run (walking ones/zeros, checkerboard, address, reverse address...), it should not be a terribly difficult task to design the control circuitry to run these tests and then perform compares. In fact it sounds like a fun project and might be a good one for a class or a novice FPGA designer. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 22854
I had written two programs on WebPack. They're compiled & simulated successfully, but I can't fit them on CPLD device. The fit process reaches about 80% and doesn't continue. So I can't see what really happens - are there any mistakes and so on. If anyone had the same problem, I would be thankfull to read an advice. Neli Dimitrova Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22855
Hi, I'm new to FPGA design, and looking for a hardware vendor in Germany where I can buy FPGAs in very small (single) quantities. I thought of a Xilinx Spartan-II or Atmel AT40Kxx to start playing with, but I'd appreciate any other suggestions (for learning purpose; low budget, low I/O count, simple configuration process). Thanks, Jan LellmannArticle: 22856
The German distributors for Xilinx are Insight ( formely called Metronik ) with 9 locations and Avnet, with 8 locations. The addresses are in the back of our printed data books, but strangely enough not on the web version. I'll fix that, soon. 2.5-V Spartan-II is a good choice, with lots of systems features, like DLL and dual-ported 4096-bit RAMs. But since it's a brand new family, ( derived from the more expensive Virtex family ) availability is presently limited. 3.3-V Spartan-XL may be a better choice. No DLL, no big RAM, but mature, fast and easy to use. Viel Spaß beim Tüfteln ! Peter Alfke, Xilinx Applications =================================== Jan Lellmann wrote: > Hi, > > I'm new to FPGA design, and looking for a hardware vendor in Germany where I > can buy FPGAs in very small (single) quantities. > I thought of a Xilinx Spartan-II or Atmel AT40Kxx to start playing with, but > I'd appreciate any other suggestions (for learning purpose; low budget, low > I/O count, simple configuration process). > > Thanks, > Jan LellmannArticle: 22857
Hello,
Cypress write on web (http://www.cypress.com/pld/cores/index.html ):
"Cypress PCI Cores are available free of charge through your Cypress field
applications engineer. Click here to find a Cypress office near you " .
I writed E-mail on nad@cypress.com (Europe Cypress Semiconductor Intl. ),
but not received any answer !
Can anybody help me and send me by E-mail only small file from
free Cypress Package BASIC TARGET (VHDL) Version 3.4:
Target Source Code VHDL (only *.vhd files) ?
Regards,
Roman E-mail:
roman_inin@yahoo.com
Article: 22858
MAPLD 2000 Registration is now open.
Abstracts for oral presentations are due June 9, 2000.
Select papers to be published in
THE JOURNAL OF SPACECRAFT AND ROCKETS
===================================================================
Registration and Call for Papers
2000 MAPLD International Conference
Kossiakoff Conference Center
The Johns Hopkins University - Applied Physics Laboratory
11100 Johns Hopkins Road
Laurel, Maryland 20723-6099
September 26-28, 2000
The 3rd annual Military and Aerospace Applications of
Programmable Devices and Technologies International Conference
will address devices, technologies, usage, reliability, fault
tolerance, radiation susceptibility, and applications of
programmable devices and adaptive computing systems in military
and aerospace systems. The program will consist of oral and
poster technical presentations and industrial exhibits. The
majority of the conference is open to US and foreign
participation and is unclassified. There will be one
classified session at the secret level, for U.S. citizens only.
For conference information, please see the Programmable
Technologies Web Site (http://rk.gsfc.nasa.gov) or the
conference www home page at:
http://rk.gsfc.nasa.gov/richcontent/MAPLDCon00/MAPLDCon00.html
Abstracts are being solicited in all aspects of the use of
programmable elements, devices, and systems for military and
aerospace applications. These include: PALs, FPGAs, PROMs,
Programmable Substrates, FPIC, Programmable Analog Circuits,
adaptive computing systems and related technologies.
Invited speakers for the conference include:
Keynote Address:
Henry Spencer - SP Systems
"Faster, Better, but Most Important, Much Much Cheaper"
History Invited Talk:
Eldon Hall, MIT Instrumentation Lab
"The Apollo Guidance Computer - A Designer's View"
Dinner Speaker:
Dr. Thomas Jones, NASA Astronaut Office
"ISS: The Exploration Proving Ground"
Lloyd Massengill, Vanderbilt University
"Single Event Modeling on Emerging Commercial Technologies"
Dr. Mark Jones, Virginia Tech
"High-Level Programming Issues for Large Reconfigurable
Computing Systems"
AIAA Invited Talk:
James Kinnison, Johns Hopkins University/Applied Physics Lab
"System Level Radiation Tolerance"
http://rk.gsfc.nasa.gov/richcontent/MAPLDCon00/InvitedSpeakers00.html
contains abstracts for the invited speakers. Several invited
talks will be added as some details are being finalized.
Conference proceedings will be published and will consist of all
presentations (oral and poster) as well as written papers. Papers
may be submitted in one of two categories: "Select" or "Contributed."
Select papers will be subject to a peer-review and will be published
in a special edition of the AIAA Journal of Spacecraft and Rockets as
well as the conference proceedings. Contributed papers will be
subject to a less stringent review.
We are again including tours this year. Guided tours will be
given at the NASA Goddard Space Flight Center, the National Security
Agency's National Cryptologic Museum, and the Applied Physics
Laboratory. For additional tour information, please see:
http://rk.gsfc.nasa.gov/richcontent/MAPLDCon00/Tours.htm
Conference topics include (but are not limited to) the following:
System on a Chip
Advanced Devices, Technologies, and Software and Their
Impact on Critical System Reliability
Programmable Technologies and State-of-the-Art Devices and
Programmable Elements
Low-Power Design Techniques
High-Speed Design Techniques
Arithmetic and Signal Processing
Adaptive Computing Systems
Evolvable Hardware
Radiation Effects, Device Reliability and Element
Characteristics
Device Architecture, Performance, and Capabilities
Applications and Novel Techniques for Military and
Spaceflight Circuits.
Use of COTS Devices in the Military and Spaceflight Environment
Testing and Analysis Techniques
Software Tools for Design/Analysis - HDLs, Synthesis, Design
Entry Systems
Translation from High Level Languages
Intellectual Property
Advanced Packaging including Known-Good-Die, MCMs, and
Chip-scale packaging.
Military Applications
Aeronautics and Space Applications
Encryption Systems
Experience and "Lessons Learned" from Mission Experience
The conference is sponsored by:
NASA Goddard Space Flight Center
JHU/Applied Physics Laboratory
National Security Agency
NASA Electronics Radiation Characterization Project
Military & Aerospace Programmable Logic Users Group
American Institute of Aeronautics and Astronautics
IEEE Aerospace & Electronic Systems Society (AESS)
For more information see http://rk.gsfc.nasa.gov or contact:
Richard Katz - Conference Chair
NASA Goddard Space Flight Center
rich.katz@gsfc.nasa.gov
Tel: (301) 286-9705
Alan W. Hunsberger - Conference Co-Chair
National Security Agency
awhunsb@afterlife.ncsc.mil
Tel: (301) 688-0245
Ann Darrin - Conference Co-Chair
Johns Hopkins University
Applied Physics Laboratory
ann.darrin@jhuapl.edu
Tel: (240) 228-4952
Tanya Vladimirova - Conference Co-Chair
University of Surrey
T.Vladimirova@ee.surrey.ac.uk
+44(0)1483 879137
Abstracts should be approximately 2 pages long and are due
June 9, 2000. Please send abstracts to
maplug@pop700.gsfc.nasa.gov. If your abstract is in an
attached file, please name the file in the following format:
LastName_A.ext - where last name is the name of the first
author - e.g., Katz_A.txt. Please include first author
information (name, affiliation, phone number, and email
address) as well as whether an open or classified presentation
is desired. Additionally, please specify whether you will be
submitting your paper for a peer-reviewed publication or a
symposium publication. All abstracts should be unclassified
when sent over email. If you can not submit an unclassified
abstract, please contact Alan Hunsberger.
Industrial exhibit reservations should be sent to
maplug@pop700.gsfc.nasa.gov and should include company name
and contact information (phone and email). Please see
http://rk.gsfc.nasa.gov:80/richcontent/MAPLDCon00/Industrial_Exhibits.htm
for additional information.
Technical Committee
===================
Ray Andraka The Andraka Group
Neil Bergmann Queensland University of Technology
Ben Cohen Hughes Aircraft/Raytheon Systems Company
Lew Cohn Defense Threat Reduction Agency
Marty Fraeman Johns Hopkins University
Creigh Gordon Air Force Research Laboratory/VSSE
Sandi Habinc European Space Agency
David Hepner US Army Research Laboratory
Brad Hutchings Brigham Young University
Ralph Kohler Air Force Research Laboratory
Ken LaBel NASA Goddard Space Flight Center
Thomas D. Milnes Johns Hopkins University
John McHenry National Security Agency
Robert Reed NASA Goddard Space Flight Center
Michael Regula Dornier Satellitensysteme GmbH
Hans Tiggeler University of Surrey
Frank R. Stott Jet Propulsion Laboratory
Tanya Vladimirova University of Surrey
Article: 22859LSI logic has a plan to offer ASIC embeddable FPGA core sometime in this year - check their web site or press release about it. And several startup companies are working on ASIC embeddable FPGA cores. Hope this helps. HT Oliver Maischberger wrote: > > Do there exist some IP cores which implement FPGA functionality? > I do not mean FPGA dies for MCMs, but integrating the functionality > together with custom logic into a single die. > > OliverArticle: 22860
Hi,
I have a problem whith an addition of four std_logic_vector variables.
Each variable is 8 bit. And the maximum in decimal is 255. 4*255=1020, I
have to use a 10 bit vector to store the value.
But when i syntesis the VHDL code, I recive an error message: "Target
......... is incompatible with assigned value.
If I use an 8 bit vector, there will be an overflow, but the synthesis
workes with 8 bit vector, not with 10 bits...........
Do anyone know how to solve this problem?
insignal: inout STD_LOGIC_VECTOR(7 DOWNTO 0);
.
.
.
signal glattning: std_logic_vector(9 downto 0);
signal sampel1,sampel2,sampel3: std_logic_vector(7 downto 0);
glattning<=sampel1+sampel2+sampel3+insignal;
Thankful for help
Björn Lindegren
Article: 22861"Björn Lindegren" wrote: > > Hi, > > I have a problem whith an addition of four std_logic_vector variables. > Each variable is 8 bit. And the maximum in decimal is 255. 4*255=1020, I > have to use a 10 bit vector to store the value. > > But when i syntesis the VHDL code, I recive an error message: "Target > ......... is incompatible with assigned value. > > If I use an 8 bit vector, there will be an overflow, but the synthesis > workes with 8 bit vector, not with 10 bits........... > > Do anyone know how to solve this problem? > > insignal: inout STD_LOGIC_VECTOR(7 DOWNTO 0); > . > . > . > signal glattning: std_logic_vector(9 downto 0); > signal sampel1,sampel2,sampel3: std_logic_vector(7 downto 0); > > glattning<=sampel1+sampel2+sampel3+insignal; > > Thankful for help > > Björn Lindegren In order to add these values without overflow, you must first first typecast them to 10 bit slvs. Then they can be added and the result will be a 10 bit slv which is compatible with the signal receiving the result. It has been a while since I have written any VHDL so I don't remember the syntax for a typecast, but it is done inline in the assignment statement. -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 22862
Hi Jan, Perhaps you could consider buying an FPGA proto kit which includes the FPGA. Since it is for learning, this will get you up and running quickly. We sell low cost, easy-to-use FPGA proto kits at Burch Electronic Designs www.BurchED.com.au The courier we use will ship to Germany. We have a choice of kits: Xilinx (Spartan), Atmel (AT40K05), Altera, Actel and Lucent. To check out what else is available on the market in terms of proto kits, go to the Optimagic website: www.optimagic.com There's a list in the "Boards" section. Regards Tony Burch www.BurchED.com.au Jan Lellmann wrote in message <8gp7t5$1pp3n$1@fu-berlin.de>... >Hi, > >I'm new to FPGA design, and looking for a hardware vendor in Germany where I >can buy FPGAs in very small (single) quantities. >I thought of a Xilinx Spartan-II or Atmel AT40Kxx to start playing with, but >I'd appreciate any other suggestions (for learning purpose; low budget, low >I/O count, simple configuration process). > >Thanks, > Jan Lellmann > >Article: 22863
Hi, I am looking for a VirtexE prototype board with at least 1 million gates capability (1 VirtexE1000 or bigger) and PCI interface. regards, Dave. Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22864
On Mon, 29 May 2000 08:59:34 +1000, "Tony Burch" <tony@BurchED.com.au> wrote: >We sell low cost, easy-to-use FPGA proto kits at >Burch Electronic Designs www.BurchED.com.au >The courier we use will ship to Germany. >We have a choice of kits: >Xilinx (Spartan), Atmel (AT40K05), Altera, Actel >and Lucent. > >To check out what else is available on the >market in terms of proto kits, go to the >Optimagic website: >www.optimagic.com >There's a list in the "Boards" section. Lots of prototyping area there and the price seems very good, too. That and XESS's stuff should cover most anyone's early needs. Thanks for the reference. JonArticle: 22865
--Extend the operands to 10 bits by prepending two '0' msbs the operands
glattning <= ("00" & sample1) + ("00" & sample2) + ("00" & sample3) + ("00"
& insignal);
"Björn Lindegren" <b.j.l@swipnet.se> wrote in message
news:pIeY4.1989$b55.5025@nntpserver.swip.net...
> Hi,
>
> I have a problem whith an addition of four std_logic_vector variables.
> Each variable is 8 bit. And the maximum in decimal is 255. 4*255=1020,
I
> have to use a 10 bit vector to store the value.
>
> But when i syntesis the VHDL code, I recive an error message: "Target
> ......... is incompatible with assigned value.
>
> If I use an 8 bit vector, there will be an overflow, but the synthesis
> workes with 8 bit vector, not with 10 bits...........
>
> Do anyone know how to solve this problem?
>
> insignal: inout STD_LOGIC_VECTOR(7 DOWNTO 0);
> .
> .
> .
> signal glattning: std_logic_vector(9 downto 0);
> signal sampel1,sampel2,sampel3: std_logic_vector(7 downto 0);
>
> glattning<=sampel1+sampel2+sampel3+insignal;
>
> Thankful for help
>
> Björn Lindegren
>
>
>
Article: 22866
Hi everyone.
Back in late February I posted a message in order to gain some insight
in designing a digital phase-locked loop (DPLL) for frequency
synthesis to be used as the master clock of an FPGA system. I had
received a number of useful replies (thanks to all who provided
feedback) and links to some application notes that have helped me to
better understand the design of a PLL. I have consulted some other
references on PLL design as well, including Gardner's and Rohde's
books.
Starting this week, I will begin implementing my PLL in an Altera
FLEX10K100A using VHDL. Although I have narrowed down my options to 2
choices, I would like to get some comments on the feasibility of both
structures, from personal experience or other.
(I have tried to detail the two proposed structures below, although
ascii drawings are not my strong point. For clarity, please view the
figures using a fixed font such as courier size 10.)
1st Structure:
--------------
All-analog 2nd order PLL, with a digital phase/frequency comparator
and digital loop divider, i.e.,
Digital Analog Voltage-Controlled
Fref --> Phase/ --> 1st Order --> Crystal Oscillator
Frequency Active (VCXO) - Analog
Comparator Loop Filter | (100MHz)
/|\ |
| |
| |
------- Divide-by-4 <----------
(Digital)
The digital Phase/Frequency Comparator is the same one shown in
Xilinx Application Note XAPP028 (Dec 2 1996)
http://www.xilinx.com/xapp/xapp028.pdf
and Lattice's application note AN8017 located at
http://www.latticesemi.com/lit/docs/designexamples/cpld/an8017.pdf
The internal divider has been set to 4 so that its nominal output will
be 25MHz.
2nd Structure:
--------------
Mostly digital 2nd order PLL, with only the VCXO and some other
components being analog.
Digital Digital DAC followed by 100MHz
Fref --> Phase/ --> 1st Order --> an Analog Low --> VCXO
Frequency Active Pass Filter (analog)
Comparator Loop Filter |
/|\ |
| |
| |
------- Divide-by-4 <--------------------------
(Digital)
-DAC: Digital-to-Analog Converter
-The analog Low Pass Filter can be a simple RC network to smooth out
the DAC staircase output.
-If I use the Phase/Frequency Comparator shown in the Xilinx or
Lattice AppNotes, I probably need to include something between it and
the digital loop filter, since the comparator produces only high and
low levels, not actual values that are needed at the loop filter
inputs. I propose a counter of some sort but I am open to other
suggestions.
-The phase/frequency comparator is the same as the one shown in the
Xilinx and Lattice AppNotes (see 1st structure above).
Although the 2nd choice will offer more versatility in terms of
controlling the loop parameters on the fly (if it does work), I fear
that it may be difficult to realize with an FPGA. However, I will be
really happy if does work.
My design specifications are the following:
- 100MHz VCXO nominal frequency with a +/-30kHz tuning range.
- 25MHz reference frequency
- Jitter as low as possible (this has not been clearly defined yet)
- The reference frequency is generated independently from a separate
source using a crystal oscillator (XO) of 100MHz divided by 4.
- There is a +/-25ppm for the VCXO and the XO (although for the
purposes of my question, assume the devices ideal).
All your suggestions are very much appreciated. Thanks in advance,
Nestor
nestor@ece.concordia.ca
P.S.: As a side question, I am thinking of implementing the PLL to
synthesize the system's clock without always having the reference
frequency present. This requires the freezing of the comparator
outputs or the loop filter outputs, as well as a periodic refresh by
retransmitting the reference at regular intervals. I am not sure,
though, if this can cause the loop to temporarily lose lock or
possibly cause it to start up anew using a completely different phase
value. However, I think the frequency should not vary much. Any
comments?
Article: 22867
Hi,
"The Elftmanns" <elftmann@pacbell.net> schrieb im Newsbeitrag
news:LEjY4.1140$M72.378282@news.pacbell.net...
> --Extend the operands to 10 bits by prepending two '0' msbs the operands
>
> glattning <= ("00" & sample1) + ("00" & sample2) + ("00" & sample3) +
("00"
> & insignal);
>
As Bjoern didn't told us if he's working with signed
values, I would recommend to do the extension with
the right sign (otherwise he'll loose negative values
if he's working with two's complement):
glattning <= (sample1(7)&sample1(7)&sample1) +
(sample2(7)&sample2(7)&sample2) +...
CU, Carlhermann
Article: 22868I took a look at a book I have by Roland E. Best called "Phase Locked Loops". It covers most of the types pretty well although I have never built one from it. He describes several types of digital PLLs, but none of them would be easy to use at the high frequencies you are describing. They all need a digital clock that runs at rates much higher than your 100 MHz. I think your second design with a digital loop filter will have the same problem. To use a counter as you describe, I think you will need a very fast clock that can count many cycles in the 40 nS period of your reference clock. Best does describe one circuit that uses a "Zero Crossing" Phase Detector (PD) that uses the reference clock to ADC sample the input signal (assuming it is not a digital clock but a sinewave). The resulting digital sample stream can be converted back to analog and used as the VCXO control signal. The filter block can be a simple averaging filter which can be easily done in the FPGA with an accumulator and a delay block, or as an IIR filter with only an accumulator. BTW, I don't think in your digital loop filter circuit that you need an analog filter after the DAC. At this point the DAC output is the control signal and any filtering will just add a delay to the loop and possibly make it unstable. The normal purpose of a loop filter is to average an AC signal to eliminate fluctuations within a cycle. Too much filtering is bad. The small steps you will expect from a digital loop filter should not cause problems in your VCXO. If you really need to disconnect your refrence from the circuit for extended periods of time, a digital loop filter will allow you to implement a better "hold" circuit than an analog filter. You simply hold the last VCXO control signal to the DAC. The hard part will be detecting that your reference is gone before the PLL starts to hunt. I assume you would have control over this and put it into hold mode before the signal goes away. nestor@ece.concordia.ca wrote: > > Hi everyone. > > Back in late February I posted a message in order to gain some insight > in designing a digital phase-locked loop (DPLL) for frequency > synthesis to be used as the master clock of an FPGA system. I had > received a number of useful replies (thanks to all who provided > feedback) and links to some application notes that have helped me to > better understand the design of a PLL. I have consulted some other > references on PLL design as well, including Gardner's and Rohde's > books. ...snip... > All your suggestions are very much appreciated. Thanks in advance, > > Nestor > nestor@ece.concordia.ca > > P.S.: As a side question, I am thinking of implementing the PLL to > synthesize the system's clock without always having the reference > frequency present. This requires the freezing of the comparator > outputs or the loop filter outputs, as well as a periodic refresh by > retransmitting the reference at regular intervals. I am not sure, > though, if this can cause the loop to temporarily lose lock or > possibly cause it to start up anew using a completely different phase > value. However, I think the frequency should not vary much. Any > comments? I think that reconnecting the reference will cause a disruption in the output frequency as the circuit locks in. But I don't think you will come to a different phase value unless the reference freq has changed. If I understand these things properly, the VCXO is like a spring on the gas pedal. To go a given speed, you will always be pressing the spring a certain amount (the phase error in this case). To go faster, you will need a larger phase error which presses on the pedal harder. The only way around this is to use an integrator function in the loop and then you will have to damp oscillations. I hope I am not coming across like an expert at this, I am not. This is just free advice, so it is likely worth what you are paying. ;) -- Rick Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 22869
Hello, I start working in VHDL and I purchase a free PCB programmer for programming CPLD or FPGA chip(Xillinx, Altera, Cypress...) Thank you for any information. B.Bertrand bertrand@olfac.univ-lyon1.frArticle: 22870
In article <8gp70i$c6j$1@nnrp1.deja.com>, neli_dimitrova@my-deja.com wrote: > I had written two programs on WebPack. They're compiled & simulated > successfully, but I can't fit them on CPLD device. The fit process reaches > about 80% and doesn't continue. So I can't see what really happens - are > there any mistakes and so on. If anyone had the same problem, I would be > thankfull to read an advice. > > Neli Dimitrova > > Sent via Deja.com http://www.deja.com/ > Before you buy. > Sometimes fitting takes really long, so I would let it running for at least 15 min. You can : - try to fit it for the largest device availabe, so you can see how many resources it needs. It's easy to make a mistake and describe a module in a way the compiler needs to create a very complex netlist. - do not use Pin and timing constraints at the beginning - try the Webfitter over the Internet. - split you design and try to implement only a part. Hope this helps -- Klaus Falser Durst Phototechnik AG I-39042 Brixen Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22871
If you are looking at an analog PLL with a digital feedback, you might try an 88915 (IDT, motorola), which is a fairly standard low cost vanilla PLL made for clock replication. It has the VCO, phase comparator and loop filter in one 20 pin(?) SOIC package along with low skew outputs for 2x, 5 1x and a halx x output. Since the feedback and reference input is external, it is easy to add dividers in the feedback and reference paths to permit frequency synthesis. I've put the dividers as well as monitoring circuits in both FPGAs and CPLDs with good results. The only external component needed for the loop filter is a ceramic cap, so the parts count is low and there is no design tweaking. With the buffered low skew outputs, you may have enough clock drivers for your whole system, and you get the 1x,2x and 1/2x outputs already made and deskewed for you. nestor@ece.concordia.ca wrote: > > > My design specifications are the following: > - 100MHz VCXO nominal frequency with a +/-30kHz tuning range. > - 25MHz reference frequency > - Jitter as low as possible (this has not been clearly defined yet) > - The reference frequency is generated independently from a separate > source using a crystal oscillator (XO) of 100MHz divided by 4. > - There is a +/-25ppm for the VCXO and the XO (although for the > purposes of my question, assume the devices ideal). > > All your suggestions are very much appreciated. Thanks in advance, > > Nestor > nestor@ece.concordia.ca > > P.S.: As a side question, I am thinking of implementing the PLL to > synthesize the system's clock without always having the reference > frequency present. This requires the freezing of the comparator > outputs or the loop filter outputs, as well as a periodic refresh by > retransmitting the reference at regular intervals. I am not sure, > though, if this can cause the loop to temporarily lose lock or > possibly cause it to start up anew using a completely different phase > value. However, I think the frequency should not vary much. Any > comments? You don't want to use the VCO in a freee running mode like this. It is not a very stable source without a reference, so it will drift considerably. You might be able to construct a simple DPLL to replicate/synthesize the reference from a crystal source and then use the PLL to multiply that reference up to your system clock. The DPLL could then be used to discover the correct count values and then hold those counts when the reference dissappears. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 22872
Hallo ! I have problem with implementing a construction with a extern RAM in my Xilinx XC4010XL. The problem is when I read from the external RAM and give the internal side the value 'Z'. The implimentation-tool tells me: "Storing a 'Z' value to an 'inout' port for more than 1 clock cycle is not yet supported." And I only give it the value for one cycle, can anybody plese tell me what to do. Plese help me ! Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22873
Hallo ! I have problem with implementing a construction with a extern RAM in my Xilinx XC4010XL. The problem is when I read from the external RAM and give the internal side the value 'Z'. The implimentation-tool tells me: "Storing a 'Z' value to an 'inout' port for more than 1 clock cycle is not yet supported." And I only give it the value for one cycle, can anybody plese tell me what to do. Plese help me ! Sent via Deja.com http://www.deja.com/ Before you buy.Article: 22874
Hi Nestor, I don't have your original request for info and so have lost track of your intended application but offer some info from what you have given. I have not used type 2 but have used type 1 extensively with success. It is a superbly simple circuit and so wins hands down in my book - you could have the basics working in no time. I notice that you are intending a comparison frequency of 25MHz in the phase comparator section. I would avoid this - notice that Peter's Xil Apps note uses a comparison freq of around 5kHz. The benefits of this are jitter reduction, filter simplicity (audio range) and simpler stability calcs. A lower comparison frequency is easily achieved by dividing the reference and feedback paths by the same amount. Peter also mentions the MC4040 apps notes - our cicuit was developed with the help of Philips Apps notes for the 4046 (I think) which also came with a floppy <arc> containing a filter stability analysis prog - no refs I'm afraid. For the record I never could get the a circuit with an active integrator in it to stabilize. We used a purely passive arrangement. Remember that a simple passive filter is an over- simplification and that various leads and lags will be required to stabilize the loop. You aren't losing (tracking) response time by having a lower comparison frequency. In my experience, regular VCXOs are well slugged (for stability?) and only to input changes below <forgets> say 100Hz - 1kHz range. Watch out also for the type of VCXO used. At the frequency you are talking, the mfr may use a lower rate item with a freq tripler stage. Ours did - I think 'cos we wanted a big spread (+/-250ppm) - this will have greater jitter. 3rd overtone VCXO (the alternative) has, I think, lower pull range. As you are looking for +/-300ppm, watch out. If you can reduce the spread, do, as lower spread oscs will be better behaved and easier (cheaper) to procure. No comments on your clock loss. Hope this helps. Regards, Dave ps. email is valid if you remove the obvious -- dmac
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