Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
THe problem is the design you've done in the FPGA. The maximum clock speed of a particular FPGA design depends on the design implementation as much or even more than the data sheet 'system clock' rate parameter. In the case of the counter, the design is probably using the fast carry chain for a ripple carry between synchronous counter stages. The Logiblox updown counter macro is not a very efficient implementation, as it requires two levels of logic, plus it uses an OR gate on the common clock enable input. The design is already somewhat floorplanned. For maximum performance, you would probably want to redo the counter design using only the features you really need. If you want a loadable up-down, it will be two levels of logic, but in that case you can move the load logic (if you are cute about how you do it) to the input side of the carry chain so that is not in the critical carry path. For 30 MHz performance, you probably don't have to do that. The propagation delay between registers determines your performance, and as such the performance is dependent on the number of bits in the counter. If the counter has many bits, you can pipeline the carry between two smaller counters at the cost of more latency from count enable to output. For the 30 MHz performance, most likely all you will need to do is reduce the levels of logic in the controls. Register the up-down control and floorplan its location so that the register is immediately adjacent to the LSB of the counter. Your critical path is probably through that up-down logic, to one of the LSBs then up the carry chain to the msb and then to the register. BY keeping that path local, you'll eliminate long routing delays. If you are using the CE, clear or other controls, you'll also want to register those close to the counter for the same reason. You can get a better feel of where the problems are if you run TRCE (the timing analyzer) with the reporting options set for no limit and the report for failures (in the timing analysis GUI, set limit=none under the options menu then under the analysis menu select timing analysis-> paths failing timing constraints. Also, If you have not set timing constraints, you should do that before doing redesign or floorplanning. you may be able to get it to go at 30 MHz just by doing that if you don't already have a constraint. A simple period constraint will probably be sufficient. redbens@my-deja.com wrote: > Hello, > > I have a little design (a Logiblox updown counter plus a vhdl based > macro to give the updown signal to the counter). > The functional simulation works fine but when I use the timing > simulation I have a setup and hold time violation with a clock > frequency of 30 MHz. When I use a clock of 20Mhz the design works fine! > > I know from the data book that the fpga I am targeting (XC4000E) can be > clocked up to 80MHz. So what is the problem here and what can I do to > resolve it. > > Thank you in advance for your answer. > > Red. > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21976
Hello,
I'm trying to create a bit stream using xact 5.21 makebits utility.
The circuit was created using cadence 9402 schematic capture. I have
modified the circuit and need a bit stream to program a part via
parallel cable. What are the necessary options in the makebits
command?
I have tried the following: makebits -o x1.bit
makebits -0 x1.bit -b
I then use foundation 2.1i to attempt to program the device and
get the following error:
"The bitstream file could not be opened or is invalid. Check if
the file is readable and contains valid bitstream information."
What does valid, readable bitstream data look like?
thanks in advance,
-smr
Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 21977
redbens@my-deja.com wrote in message <8ct1db$9u7$1@nnrp1.deja.com>...
>Hello,
>
>I have a little design (a Logiblox updown counter plus a vhdl based
>macro to give the updown signal to the counter).
>The functional simulation works fine but when I use the timing
>simulation I have a setup and hold time violation with a clock
>frequency of 30 MHz. When I use a clock of 20Mhz the design works fine!
>
>I know from the data book that the fpga I am targeting (XC4000E) can be
>clocked up to 80MHz. So what is the problem here and what can I do to
>resolve it.
What signals are failing to meet setup/hold requirements?
When you implemented the design, did you tell it any timing constraints?
Did you look at the results of the place and route with the Timing Analyzer
or trce?
-- a
-----------------------------------------
Andy Peters
Sr Electrical Engineer
National Optical Astronomy Observatories
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) noao \dot\ edu
"Money is property; it is not speech."
-- Justice John Paul Stevens
Article: 21978> Hi all, > > For my design, there is a global clock, some input signals, some output > signals (clocked by external source). > > When input signals come in(synchronized by global clock), the central > controller will collect, organize, manipulate & store in buffer. > The output port interface portion will at intervals (ctrl by external clk) > request data from buffer. > During my design, I encounter hundreds of design warning by max+plus2 (i'm > using synplify vhdl sythesizer) saying sth like this > "Design Dr warning: flipflop or synchronous memory 'q_data_7' receives data > that is synchronized by another clock at flipflop or synchronous memory > 'subc_datareq' " > & > "Design Dr warning: inverting delay chain starting at primitive > 'cntr_1_lut_5' feeds primitive 'statemachine_cntr_i_0' " > > & my project fails to work during timing simulation. > Can somebody pls shed some light on how to properly design a multiple clock > system that meets all setup time, hold time....??? > or is there any good reference that stress on this area of design? > > Any help is much appreciated. Thanks in advance. > > > Rgds > MK > > > > > >Article: 21979
Hello, What programator should I have if i would like to programm circuits of xilinx (virtex,xc4000xl,l,xv). With regards Tomasz Brychcy tbrychcy@sensor.ime.pz.zgora.plArticle: 21980
Xilinx FPGAs are loaded with a bitstream each time the device is powered up. The parts are not programmed as part of manufacture of the boards. You don't need a programmer for these parts, however, the bitstream will have to be stored somewhere in your system. Typically this is done either using serial eproms or combined with a program for a microprocessor on the board. You will need an appropriate programmer for what ever method you use to store the bitstream. Tomasz Brychcy wrote: > Hello, > > What programator should I have if i would like to programm circuits of > xilinx (virtex,xc4000xl,l,xv). > > With regards > > Tomasz Brychcy > > tbrychcy@sensor.ime.pz.zgora.pl -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randrakaArticle: 21981
In article <8ct1db$9u7$1@nnrp1.deja.com>, redbens@my-deja.com wrote: > Hello, > > I have a little design (a Logiblox updown counter plus a vhdl based > macro to give the updown signal to the counter). > The functional simulation works fine but when I use the timing > simulation I have a setup and hold time violation with a clock > frequency of 30 MHz. When I use a clock of 20Mhz the design works fine! > > I know from the data book that the fpga I am targeting (XC4000E) can be > clocked up to 80MHz. So what is the problem here and what can I do to > resolve it. > > Thank you in advance for your answer. > > Red. > > Sent via Deja.com http://www.deja.com/ > Before you buy. > You have to add timing constrains (through the constraint editor or adding them directly to the UCF file). This directs the fitter to place the signals in a way certain maxium delays are respected. The simplest timing constraint is # NET form of the PERIOD timing constraints (no TSidentifier) NET <clock name> PERIOD = 33 ns ; Greetings -- Klaus Falser Durst Phototechnik AG I-39042 Brixen Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21982
In article <38F20BA1.DADE9E72@imec.be>, Steven Sanders <sanders@imec.be> wrote: > This is a multi-part message in MIME format. > --------------37A3AB7D837387977E36224F > Content-Type: text/plain; charset=us-ascii > Content-Transfer-Encoding: 7bit > > Hello, > > When I try to implement a simple design (completely HDL), I get > following error message: > "logical blok xxxx is unexpanded". I already checked support.xilinx.com > for an answer but no solution there. Any advice? > > Thanx!!! > > --------------37A3AB7D837387977E36224F > Content-Type: text/x-vcard; charset=us-ascii; > name="sanders.vcf" > Content-Transfer-Encoding: 7bit > Content-Description: Card for Steven Sanders > Content-Disposition: attachment; > filename="sanders.vcf" > > begin:vcard > n:Sanders;Steven > x-mozilla-html:FALSE > org:imec ;DTS > adr:;;Flanders Language Valley 44;Ieper;;8900;Belgium > version:2.1 > email;internet:sanders@imec.be > fn:Steven Sanders > end:vcard > > --------------37A3AB7D837387977E36224F-- > > This should not be an error if it comes from the HDL-compiler, but says simply that some instanced module were not found by the compiler. You can include this module later at the fitting phase, where it must be found in NGD format (if the module was a LogiBlox module for example). Or you did forgot to add the source file for the missing module to the project and it was not compiled. Best regards -- Klaus Falser Durst Phototechnik AG I-39042 Brixen Sent via Deja.com http://www.deja.com/ Before you buy.Article: 21983
Hello, Why occur the errors during synthesis: The pad mapping optimization can not determine the type of pad to insert at the port D<7>. The pad mapping optimization can not determine the type of pad to insert at the port D<6>. The pad mapping optimization can not determine the type of pad to insert at the port D<5>. The pad mapping optimization can not determine the type of pad to insert at the port D<4>. The pad mapping optimization can not determine the type of pad to insert at the port D<3>. The pad mapping optimization can not determine the type of pad to insert at the port D<2>. The pad mapping optimization can not determine the type of pad to insert at the port D<1>. The pad mapping optimization can not determine the type of pad to insert at the port D<0>. What should I do? below it's code of my model: module COUNTER(CLK,GATE,D,WR,RD,A,OUT); input CLK; input GATE; input WR; input RD; input A; inout [7:0] D; output OUT; endmodule With regards Tomek Please send me reply for: tbrychcy@sensor.ime.pz.zgora.plArticle: 21984
Christian Mautner wrote: > > Steven Sanders <sanders@imec.be> writes: > > > > When I try to implement a simple design (completely HDL), I get > > following error message: > > "logical blok xxxx is unexpanded". I already checked support.xilinx.com > > for an answer but no solution there. Any advice? > > > > We might be able to help you if you would post your code and the full > error message. > > That "... is unexpanded" messages is usually due to library problems. > > chm. > > -- > cmautner@ - Christian Mautner > utanet.at - Vienna/Austria/Europe This means that the tools have reached the bottom of you design heirarchy and have not found primitive elements, i.e. Xilinx building blocks. -- ---------------------------------------------------------------------- Jon Harrison | BAE SYSTEMS | SSD (Crewe Toll) | Edinburgh EH5 2XS _@_ Tel: 0131 343 4746 ______________--(\_/)--______________ FAX: 0131 343 4124 x (_) x |_|( o )|_| x (_) x e-mail: jon.harrison@gecm.com `-' ----------------------------------------------------------------------Article: 21985
Robert Binkley wrote: > Hi Jaime, > > Have you considered the userid register in the Virtex/Spartan-II devices? It is > a dedicated 32 bit register accessible via the JTAG TAP and the value is set at > bitgen (the final step in implementation). It would be possible to write a > script to automatically calculate a value to be placed in that register by > invoking bitgen with the request. > > More information about this register can be found in xapp139. > http://support.xilinx.com/xapp/xapp139.pdf > or by typing bitgen -help virtex at the command line. > > Robert Binkley > Xilinx Applications ... and you could combine this with Evan's suggestion since RAM/ROM initialisation values can be set in the .xdl file. It will be easier this way since you could search for the ROM by name in the xdl file & not have to put it in fixed position.Article: 21986
Hello, During implementation process (exactly translation) occur that error: ERROR:NgdHelpers:313 - logical root block "counter" of type "counter" is unexpanded. My code is below: module COUNTER(D,WR,OUT); input [7:0] D; input WR; output OUT; reg [15:0] CR; reg LSB_LOADED; reg [1:0] READ_WRITE_MODE; reg FIRST_BYTE; reg OUT; always @(posedge WR) if (D[7:4]!=4'b1100) READ_WRITE_MODE=D[5:4]; @(posedge WR) if (READ_WRITE_MODE==2'b11) FIRST_BYTE=1'b0; else FIRST_BYTE=1'b1; always @(posedge WR) if (READ_WRITE_MODE==2'b01) CR[7:0]=D; else if (READ_WRITE_MODE==2'b10) CR[15:8]=D; else if (READ_WRITE_MODE==2'b11 && FIRST_BYTE==1'b0) begin CR[7:0]=D; LSB_LOADED=1'b1; end else if (READ_WRITE_MODE==2'b11 && LSB_LOADED==1'b1) begin CR[15:8]=D; LSB_LOADED=1'b0; end endmodule Why does error occur? Tomek tbrychcy@sensor.ime.pz.zgora.plArticle: 21987
Hi All, Does anyone on this group know the output impedance of a Virtex E pad using LVTTL standard and the influence of the drive current on this impedance ? Thanks -- J-P GOGLIO GETRIS S.A. 13 Chemin des Prés 38240 Meylan Tel : (+33) 4 76 18 52 10 E-mail : goglio@getris.com Fax : (+33) 4 76 18 52 01Article: 21988
LUTs, what are they? Can I consider them as ROMs? what is the difference between LUT and function generators in Xilinx FPGAs. what is teh number of outputs of LUTs? ThanksArticle: 21989
LUTs, what are they? Can I consider them as ROMs? what is the difference between LUT and function generators in Xilinx FPGAs. what is teh number of outputs of LUTs? ThanksArticle: 21990
LUTs, what are they? Can I consider them as ROMs? what is the difference between LUT and function generators in Xilinx FPGAs. what is teh number of outputs of LUTs? ThanksArticle: 21991
LUTs, what are they? Can I consider them as ROMs? what is the difference between LUT and function generators in Xilinx FPGAs. what is teh number of outputs of LUTs? ThanksArticle: 21992
Look at the Virtex I/V curves on page 14-64 of the 1999 Xilinx data book. The first graph describes LVTTL. You can use these Virtex curves also for Virtex-E. Peter Alfke, Xilinx Applications ========================================= Jean-Paul GOGLIO wrote: > Hi All, > > Does anyone on this group know the output impedance of a Virtex E pad using > LVTTL standard and the influence of the drive current on this impedance ? > > Thanks > > -- > J-P GOGLIO > GETRIS S.A. > 13 Chemin des Prés > 38240 Meylan > Tel : (+33) 4 76 18 52 10 > E-mail : goglio@getris.com > Fax : (+33) 4 76 18 52 01Article: 21993
Jamil Khatib a écrit : > > LUTs, what are they? > Can I consider them as ROMs? > what is the difference between LUT and function generators in Xilinx > FPGAs. > what is teh number of outputs of LUTs? LUT stands for Look-Up Table. It is a small SRAM array which is loaded during FPGA configuration. The values loaded in the LUT are the output values for every input values. Supposing you have a 4 inputs LUT, you can have 16 input values so the LUT is a 16 bits SRAM. In non-reconfigurable FPGAs, the LUTs are ROM cells. Xilinx allows the LUTs to be used as SRAM cells but it is a patented feature so other vendors cannot offer it without paying. Xilinx LUTs are called function generators (maybe not every LUTs) A LUT usually has 1 output. -- Nicolas MATRINGE DotCom S.A. Conception electronique 16 rue du Moulin des Bruyeres Tel 00 33 1 46 67 51 11 92400 COURBEVOIE Fax 00 33 1 46 67 51 01 FRANCEArticle: 21994
LUT stands for look-up-table, which can also be called read-only memory. Most FPGA LUTs are 16-bit ROMs, i.e. they have four inputs and one output. They are also called function generators, since they can generate any logical function of its inputs. A 4-input LUT can generate any one of the 64k functions of 4 variables. With Xilinx XC4000, Spartan, and Virtex devices, the LUT can also be used as a very fast RAM, since the user can write into the 16 bits of the LUT. In that sense, calling it ROM is slightly incorrect. Peter Alfke, Xilinx Applications Jamil Khatib wrote: > LUTs, what are they? > Can I consider them as ROMs? > what is the difference between LUT and function generators in Xilinx > FPGAs. > what is teh number of outputs of LUTs? > > ThanksArticle: 21995
On Tue, 11 Apr 2000 15:49:02 +0200, "Jean-Paul GOGLIO"
<goglio@getris.com> wrote:
>Hi All,
>
>Does anyone on this group know the output impedance of a Virtex E pad using
>LVTTL standard and the influence of the drive current on this impedance ?
>
>Thanks
Hi -
I downloaded the (just-about-brand-new) Virtex-E IBIS files from:
http://www.xilinx.com/support/sw_ibis.htm
I then did a quick and dirty output impedance calculation for the
LVTTL outputs:
LOW HIGH
typ min max typ min max
------------------------------------------------
LVTTL2S 131 197 103 157 245 117
LVTTL4S 64 96 51 81 125 61
LVTTL8S 26 39 21 42 64 32
LVTTL16S 16 23 13 24 37 18
LVTTL24S 10 14 8 15 22 11
The file also contains information for a couple other driver
strengths, but I got tired.
Please note that the IBIS file itself is an approximation, having been
generated from Spice models. I got the impedances by dividing the 1V
Pullup and Pulldown table entries by the corresponding currents, which
is also an approximation. So the table represents an approximation of
an approximation.
Note that:
1) Roughly speaking, the impedances are inversely proportional to the
driver current rating, which makes sense.
2) Logic HIGH impedances are somewhat higher than the corresponding
logic LOW impedances.
Bob Perlman
-----------------------------------------------------
Bob Perlman
Cambrian Design Works
Digital Design, Signal Integrity
http://www.best.com/~bobperl/cdw.htm
Send e-mail replies to best<dot>com, username bobperl
-----------------------------------------------------
Article: 21996Looking over your code, your inout 'D' never drives an output. It is just used as an input. That message is just a warning which means that it cannot realize a bidirectional use for that pad. I surmise it has probably optimized this out to be just an input. Best regards, Chris Dunlap Xilinx ApplicationsArticle: 21997
Hi Adams, The XCS10 can be configured through jtag or master/slave serial (if you have a prom). The option is yours. If using jtag, ignore the other pins. If doing serial configuration, ignore the jtag pins. Best regards, Chris Dunlap Xilinx ApplicationsArticle: 21998
This is a multi-part message in MIME format. --------------421BAC0AE0A347A21C31C786 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit All, We know how to specify PCI buffers in Virtex and Virtex E. We put the statement: set_attribute -port "outchan1_bp(2)" -name buffer_sig -value OBUF_PCI33_3 in the synthesis script and it passes the attribute to the backend. The problem is that we want to use a PCI compliant buffer on an XLA part. The docs say that it supports it, but we cannot figure out how to implement it. To check if the architecture does support it, I pulled up the constraints editor after choosing an XLA part. When I click on I/O standards, I only have the option to set drive strength, slew rate, but not the I/O standard. If you do this with a Virtex part, a new column appears called "I/O standards" which has all the I/O options, LVTTL, SSTL, PCI etc. The libraries guide on the Xilinx web site does not show support for XLA that we can find. We tried using the above statement for the XLA architecture, but it is not valid. The datasheet goes to great lengths to say the XLA has these PCI compiant buffers, but does not say how to implement them. Please help!!! Do we just implement LVTTL buffers with 12ma of drive strength and that is PCI compliant....it can't be that easy.....??? BTW, we are using Alliance 2.1i. Tom --------------421BAC0AE0A347A21C31C786 Content-Type: text/x-vcard; charset=us-ascii; name="tomm.vcf" Content-Transfer-Encoding: 7bit Content-Description: Card for Tom McLaughlin Content-Disposition: attachment; filename="tomm.vcf" begin:vcard n:McLaughlin;Tom tel;fax:314-935-7302 tel;work:314-935-7198 x-mozilla-html:FALSE url:http://www.arl.wustl.edu/~tomm org:Washington University;Applied Research Lab version:2.1 email;internet:tomm@arl.wustl.edu title:Research Associate adr;quoted-printable:;;One Brookings Drive=0D=0ACampus Box 1045-ARL;St. Louis;MO;63130;USA x-mozilla-cpt:;0 fn:Tom McLaughlin end:vcard --------------421BAC0AE0A347A21C31C786--Article: 21999
Hey all, I need to create a small clock divider circuit that divides a 77.76MHz clock downto 1.544MHz, and I need to have the resultant 1.544MHz clock to be as close to a 50/50 duty cycle as possible (as precise as possible), so that I don't have alot of jitter. Any suggestions? Thanks, Dave
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z