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Nial Stewart wrote: > > Ray Andraka wrote: > > > > Yep, somewhere around 15 million marketing gates worth this past year, all in > ^^^^^^^^^^^^^^^ > > How many real gates is that then Ray? > > Nial. Since I use a lot simple logic I count 1 gate per logic element. Considering that marketing counts block ram as gates who knows. But then with the largest FPG's several $K's each they want to sell the biggest ones possible. -- "We do not inherit our time on this planet from our parents... We borrow it from our children." "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk Now with schematics.Article: 33126
I want to build a simple state machine to control some counters I have which
measure the "high" time and "low" time of a square wave signal input
(Source).
The basic operation is as follows:
1) I pulse a "1" to an input port (Start) to enable, or prime, the
mechanism, which will....
2) Wait for the next rising edge transition of "Source";
3) When "Source" does go high, an output to enable a counter
(HighCounterEn) goes high;
4) On the falling edge transition of "Source", "HighCounterEn" goes low to
stop the counter used to count how long the signal was high for, and another
counter enable signal, "LowCounterEn", goes high. This signal enables a
counter to run as long as the signal source is low;
5) When the NEXT rising edge transition of "Source" occurs, "LowCounterEn"
goes low to disable the counter used to tell us how long the signal was low
for, and then output port "Ready" is set to 1 to tell us that the cycle is
complete and that we can now read the counters. The system comes to a dead
stop, and we need to pulse "Start" again to repeat the process. When we
pulse "Start" the counter contents and "Ready" signal should be
asynchronously cleared to 0.
This way, we can get the +ve and +ve pulse widths of "Source" by hitting
"Start" and polling "Ready" and then reading the high and low counters. Bit
like using the good old A/D converter.
I know that there's bugger all in this, but I'm not familiar enough yet with
VHDL to do this. I've gotten this far:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity state_machine is
port (
Start: in std_logic; -- Start input
Source: in std_logic; --Signalsource
Ready: out std_logic; -- Count ready signal
HighCounterEn: out std_logic; -- Enable line for +ve counter
LowCounterEn: out std_logic -- Enable line for -ve counter
);
end state_machine;
architecture state_machine_arch of state_machine is
begin
end decoder_arch;
But I'm not skilled enough yet to do the rest. I've built it out of
flip-flops in the schematic editor in WebPACK, but I've got some timing
glitches so thought the best way is to design a VHDL block that can be
inserted into the schematic. That way the behaviour can be specified
exactly.
Article: 33127Antonio, We think that the DDS is not currently supported Virtex2, I might be wrong? While you are in the Xilinx CORE Generator Program, try this: Under Project option, check the "family", make sure it is not set to Virtex2? (virtex or other is fine.) DDS (Direct Digital Synthesis) Verson 2.0 should be ready to use in the Modulation Building Block. No ideas on the Virtex2? Anyone? Good lucks, HongArticle: 33128
Jim Granville wrote:
>
> David Wright wrote:
> >
> > Has anyone had a working logic design in VHDL other than a few Cypress and
> > Xilinx insiders?
> >
> > Logic was never this complicated before!
> >
> > What a total waste of human intelligence.
> >
> > It is far easier to build with discrete MSI/LSI parts or code in computer
> > language than get even something simple into a small CPLD or FPGA.
>
> VHDL does have its frustrations :-), but there are other entry schemes,
> or even a mix.
>
> For the simpler end of the spectrum, we favour CUPL ( or Abel / AHDL /
> PHDL ),
> these HDL's are less abstract than VHDL, and allow more direct
> control/mapping
> to the resource, which becomes more important on the smaller devices.
>
> Taking the CUPL example, you have dot extensions, to connect to
> registers,
> and good field and macro structures, plus conditional compile
> preprocessor.
>
> As an examlple, this is snipped from a design on the desk:
>
> This CUPL code creates a 4 bit, saturating UP counter...
This is the same kind of thing in AHDL:
SUBDESIGN Sat_cntr(
CLK: input;
Dout[3..0]: output;
)
variable
cntr[3..0]: DFF;
BEGIN
cntr[].clk=CLK;
if(cntr[]!=H"f")
then
cntr[]=cntr[]+1;
else
cntr[]=cntr[];
end if;
Dout[]=cntr[];
END;
You could also just use a library macro function.
--
___ ___
/ /\ / /\
/ /__\ / /\/\
/__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/
\ \ / Victoria, Australia, Down-Under \ \/\/
\__\/ \__\/
Article: 33129Hi all, With this bit of code: SUBDESIGN Test( Ain: input; Dout: output; ) variable link: node; BEGIN link=Ain; Dout=link; END; After i compiled it and load the nodes into the waveform editor, buried nodes such as 'link' aren't there. On bigger designs, lots of buried nodes aren't there. How do i get them too? -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 33130
Jeff, AFAIK you cannot freeze routing with the floorplanner, only placements. > If you are have not finalized your HDL and need to resynthesize, you're in > trouble. As a FAE explained to me (and correct me if I'm wrong) the P&R > tools use a random seed to start mapping the design into the chip following > translation. I'm not sure this is true. I always get the same results for a given input design. > even if you did freeze the P&R w/floorplanner, resynthesis > renames nets and there's the source of the problem with that approach. My synthesis toll (Synplify) renames the nets in a deterministic way (No change in the hierarchy -> no net names changed). If your design changes a lot you may try using the floorplanner UCF flow. Regards, Rotem. "Jeffrey Vallier" <jvallier_nospam_@gibson.com> wrote in message news:<lEH47.1143$3h5.52516@news.pacbell.net>... > "Rotem Gazit" <rotemg@mysticom.com> wrote in message > news:86b060d0.0107160944.73e343@posting.google.com... > > Hi, > > Is there a simple way to fix manual or automatic routing so that on > > the next PR cycle it would not change ? > > The only way I know to do this is by instantiating predefined macro > > and I am looking for an easier way. > > Thanks, > > > > Rotem. > > > > Rotem Gazit > > MystiCom LTD > > mailto:rotemg@mysticom.com > > http://www.mysticom.com/ > > > > If you are done with your code and only playing with P&R, you can freeze the > design with the floorplanner and have the tools use that placement for > subsequent P&R iterations. there's various options dialog boxes, depending > on which flavour of tools you are using. > > If you are have not finalized your HDL and need to resynthesize, you're in > trouble. As a FAE explained to me (and correct me if I'm wrong) the P&R > tools use a random seed to start mapping the design into the chip following > translation. even if you did freeze the P&R w/floorplanner, resynthesis > renames nets and there's the source of the problem with that approach. > > If your HDL is solid, some judicious use of constraints in the UCF can be > very helpful. > > regards, > > jeff > > *********************************************** > Jeffrey Vallier Sr. FW Engineer > Gibson Guitar Corp. GMICS Division > 1283 F Old Mtn View/Alviso Rd. > Sunnyvale, CA 94089 408 734 4394 > *********************************************** Rotem Gazit MystiCom LTD mailto:rotemg@mysticom.com http://www.mysticom.com/Article: 33133
Thanks, I'll try it. Rotem. > I actually had good success a while back with nets defined in my guide file > for a Spartan-II design (Virtex architecture). I got rid of the nets I > didn't care about with the FPGA editor and manually routed the net I > wanted. The results were pretty consistent for this critical net. Newer > service packs have eliminated the need for this particular net's hand > routing, producing better results all around. > > The only big troubles I could see is if the synthesis tool used renames > elements in the guide file. This is the biggest problem in getting a > "minimum change" design. If all I want is to add two test points I end up > with 20% of my edif elements renamed. I hate it when that happens! > > - JohnArticle: 33134
Hi all, Can anyone direct me to a useful webpage as to exactly how one might implement a project into FPGA. This may seem an ambiguous question, so I'll explain. I started using FPGA's about 2-3 months ago as microcontrollers were not quick enough for what I wanted to do. Since there was no one around me who had used an FPGA before, I went through one or two tutorials, and started designing using schematic entries. Now I have finished design, all in schematic, and want to implement. Am I missing something here? No VHDL yet? AdrianArticle: 33135
Hi Russell, try to do a functional compilation and simulation, which doesn't give you timing information but preserves all combinatorial nodes. In the MAX+plus II compiler go to PROCESSING and turn on FUNCTIONAL SNF EXTRACTOR. The following is from the solutions database on the Altera web. I searched for "node simulation" Problem Why can't I find my node name during simulation? Solution There are two reasons your node may not appear in the simulation file: 1) Your node may not appear in the simulation file if it has been renamed by the MAX+PLUSŪ II software. To prevent the MAX+PLUS II software from changing node names, turn on the Preserve All Node Name Synonyms command (Processing menu) in the MAX+PLUS II Compiler and recompile your project. For functional simulation, all nodes are visible if this option is turned on 2) The Compiler combines combinatorial nodes into logic cells during synthesis. Therefore, some combinatorial nodes will not be available during timing simulation. Regards Wolfgang Loewer http://www.elca.de Russell Shaw <rjshaw@iprimus.com.au> wrote in message news:3B551BCA.7B5F13BD@iprimus.com.au... > Hi all, > > With this bit of code: > > > SUBDESIGN Test( > Ain: input; > Dout: output; > ) > > variable > link: node; > > BEGIN > link=Ain; > Dout=link; > END; > > > After i compiled it and load the nodes into the waveform editor, > buried nodes such as 'link' aren't there. On bigger designs, lots > of buried nodes aren't there. How do i get them too? > > > -- > ___ ___ > / /\ / /\ > / /__\ / /\/\ > /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ > \ \ / Victoria, Australia, Down-Under \ \/\/ > \__\/ \__\/Article: 33136
Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3B54C211.513A@designtools.co.nz>... > bugbear wrote: > > > > This question seems to fall somewhere between circuit design > > and compiler design, so I'm hoping the denizens of this group > > may be able to address it. > > > > This expression is "clearly" replaceable by a single "false" > > > > (a eq 10 and a eq 30) > > > > Is there a name for this optimisation? > > In the Programmable Logic Devices field, this is called 'Logic > Minimisation' I've been trawling the web. In compiler circles it's grouped under "algebraic simplifictation" I'll search on "logic minimisation" when I've done this post ;-) > > > Is it commonly implemented? > > In PLD tools, yes. > In Compiler tools, less commonly, tho I have seen compilers that would > take > IF ConstantExpression THEN > .. block of code.. > END; > and remove completely the block of code, if ConstantExpression > evaluated to false. Yep. That one's common enough that I've explicitly relied on it. It's called "dead code elimination" BugBearArticle: 33137
basically the footsteps are as follows: 1. design entry (vhdl/verilog/schemetics) 2. synthesize your design by using synthesis tool (synopsys, synplicity or others), you will get a netlist file of your design 3. Functionally simulate your design by using ModelSim or other simulators. 4. Place & Route the design by using Place&Route tools (Xilinx foundation or others) 5. Verify the design by deploying Timing analysis. This can be done by using Timing Analyzer or ModelSim. You need to modify your design to meet the timing and physical constraints untill the result fulfill your requirements. If you have Xilinx Foundationi series software, You can simply follow the flowchart in the GUI environment and build your own FPGA. Wish this could give you a clue. good luck Jianyong Noddy <g9731642@campus.ru.ac.za> wrote in message news:995443296.498698@turtle.ru.ac.za... > Hi all, > > Can anyone direct me to a useful webpage as to exactly how one might > implement a project into FPGA. This may seem an ambiguous question, so I'll > explain. > > I started using FPGA's about 2-3 months ago as microcontrollers were not > quick enough for what I wanted to do. Since there was no one around me who > had used an FPGA before, I went through one or two tutorials, and started > designing using schematic entries. Now I have finished design, all in > schematic, and want to implement. Am I missing something here? No VHDL yet? > > Adrian > > >Article: 33139
Tom Wyckoff wrote:
> I purchased Atmels' AT40K FPGA starter kit after reading that it "includes
> everything you need to get started......" It didn't. It came with a
Yep. The statement above was true a year ago, but since the company that
was making inexpensive synthesizer got acquired.. Good news below.
> trial
> license for a synthesizer, but it was expired. I have the open cores
> CDROMs. What, if anything, can I install from the CDROM to make this
> device useful? I have an idea for a simple project, but I am missing an
> essential piece of the software puzzle.
>
> Thanks,
>
> Tom Wyckoff
>
>
Actually I have got the same kit and I have not used my license yet. I am
using Icarus Verilog (www.icarus.com) to which I wrote an edif output
module (volodya-project.sourceforge.com). It works as long as you stay away
from anywhere complex behavioral stuff - as iverilog sythesis module cannot
properly handle "for" and "if" yet. This stuff is GPL.
I would certainly appreciate some help as I am quite new to the hardware
part and it sometimes it takes a while to tell whether the error is in my
code, or that hardware is working differently from what I think..
Vladimir Dergachev
Article: 33140Hi, We are starting out on a new design for an airborne application, which will employ a large numer of Virtex-E/II FPGAs. The issue of safety classification has raised it's head, and whether the volatility of SRAM FPGAs constitutes an intrinsic hazard. Conventionaly with SRAM devices which hold program information in microprocessor based systems this is addressed by the use of continuous memory testing and checksumming. Has anyone else crossed this thorny issue yet ? Guidance as to any procedures / processes followed would be useful. We would propose to address this issue by using device readback to allow checksumming of the configuration data - has this been found to be acceptable eleswhere ? Cheers, JonArticle: 33141
Hello As a newbie, who has to decide between these devices, I found the following differencies: Altera advantages: -Better design tool (allows schematic entry) -Chips are mask programmable (by third party) Xilinx advantages: -Cheaper boot proms Has anyone compared these two devices and can give me further hints about advantages / disadvantages? The amount of RAM and Logic blocks, the pricing and even the archictecture seem to be almost the same for both devices. Is that right? ThomasArticle: 33142
Hi everyone, I was wondering if anyone can tell me how a MAX device can be programmed apart from using JTAG. I know that we can do show with the bitblaster (or byteblaster) but the thing is that while the bitblaster has 2 configuration modes (Passive Serial - JTAG) it only uses JTAG in order to program MAX devices. I'm trying to program a MAX device (not one in specific) via an embeded processor WITHOUT using the JTAG port. Thanks in advance Dionysis.Article: 33143
Noddy wrote: > Hi all, > > Can anyone direct me to a useful webpage as to exactly how one might > implement a project into FPGA. This may seem an ambiguous question, so I'll > explain. > > I started using FPGA's about 2-3 months ago as microcontrollers were not > quick enough for what I wanted to do. Since there was no one around me who > had used an FPGA before, I went through one or two tutorials, and started > designing using schematic entries. Now I have finished design, all in > schematic, and want to implement. Am I missing something here? No VHDL yet? > > Adrian It's fine to use only schematics when you are just beginning or when the project is small. As your designs get larger, you will start to use VHDL and/or Verilog. There was a discussion of design entry methods in this group over the past few days. Which FPGA and development software are you using: Xilinx+Foundation? Altera+Maxplus2? or something else? If you are using Xilinx, you might try looking at a few chapters of our online text at http://www.xess.com/pragmatic-2_1.html. It goes through a pretty explicit explanation of how to get some schematic and VHDL-based designs compiled for XILINX FPGAs and CPLDs using the Foundation software. -- || Dr. Dave Van den Bout XESS Corp. (919) 387-0076 || || devb@xess.com 2608 Sweetgum Dr. (800) 549-9377 || || http://www.xess.com Apex, NC 27502 USA FAX:(919) 387-1302 ||Article: 33144
I have a simple VHDL code like:
process(addr) begin
q <= x"84ff"; -- not impl loop
case addr is
when x"0000" => q <= x"8200"; -- nop
when x"0002" => q <= x"d2ff"; -- iconst_m1
when x"0003" => q <= x"d200"; -- iconst_0
when x"0004" => q <= x"d201"; -- iconst_1
when x"0005" => q <= x"d202"; -- iconst_2
....
to implement a ROM.
But WebPACK produces LUT's and does not use the internal ram blocks.
As a result the design does not fit.
Any suggestion how to give the sysnth. or map tool a hint to use the ram
block?
Thanks
Martin
--
Whant to see the evolution of a Java processor?
http://www.jopdesign.com
Article: 33145Schematics get difficult for things like state machines etc, but maxplus2 has AHDL which is easy to learn and use before stepping to vhdl/verilog if needed. Acex 1k devices seem to only have one flash configuration device available (EPC2); the rest are otp. Xilinx seem to have more flash configuration devices. thomas daehler wrote: > > Hello > > As a newbie, who has to decide between these devices, > I found the following differencies: > Altera advantages: > -Better design tool (allows schematic entry) > -Chips are mask programmable (by third party) > Xilinx advantages: > -Cheaper boot proms > > Has anyone compared these two devices and can give me > further hints about advantages / disadvantages? > The amount of RAM and Logic blocks, the pricing and even > the archictecture seem to be almost the same for both devices. > Is that right? > > Thomas -- ___ ___ / /\ / /\ / /__\ / /\/\ /__/ / Russell Shaw, B.Eng, M.Eng(Research) /__/\/\/ \ \ / Victoria, Australia, Down-Under \ \/\/ \__\/ \__\/Article: 33146
The configuration memory in FPGAs is more robust than typical SRAM, so you will see less frequent upsets for a give exposure level. Still, in a safety critical application where you would normally monitor a circuit's health, you'll want to verify that the chip is operating correctly. This can be done through a combination of test vectors, redundancy (voting) and configuration readback. There is a considerable amount written about this in various space electronics journals/conference proceedings. You generally will see data path upsets before you see configuration upsets. Configuration upsets can also be reduced by using a QPRO part, which has an epi layer. Of course that means you are limited to essentially a Virtex1000-4 (no E, no II), but if safety is your prime concern this is probably the way to go. For configuration readback, there are some gotchas you will need to be aware of in Virtex-E, which I am not sure got fixed in virtexII. As stated in the data sheet, you can't readback Block RAM while it is being used, and you can't read CLBRAM or SRL16s while the write enable is high. Additionally, reading back cells configured with SRL16's or CLBRAM while the clock is running corrupts the configuration of the CLB (not just the memory contents). If you are using the SRL16's and/or CLBRAM, you need to be very careful to not readback columns containing those elements while the clock is running. I a current design slated for a low earth orbit, we are getting around that by running test vectors through the design between valid data packets. Processed data is not used until after the next test vector validation cycle ompletes, verifying the circuit was not corrupted during the processing. You could also use triple mode redundancy to detect circuit/data problems and correct based on that... in our case the available number of logic cells and available power did not permit the TMR. Jon Harrison wrote: > Hi, > > We are starting out on a new design for an airborne application, which will > employ a large numer of Virtex-E/II FPGAs. The issue of safety > classification has raised it's head, and whether the volatility of SRAM > FPGAs constitutes an intrinsic hazard. Conventionaly with SRAM devices which > hold program information in microprocessor based systems this is addressed > by the use of continuous memory testing and checksumming. > > Has anyone else crossed this thorny issue yet ? Guidance as to any > procedures / processes followed would be useful. > > We would propose to address this issue by using device readback to allow > checksumming of the configuration data - has this been found to be > acceptable eleswhere ? > > Cheers, > > Jon -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33147
The XC2S30 has 216 CLBs which is equivalent to 864 Altera Logic Elements or LEs (Xilinx claims 972 LEs). The EP1K30 has twice as many, 1728 LEs. Embedded RAM is about the same, while the XC2S30 also offers distributed RAM which however further reduces the available logic resources. The EP1K30 ist just a little to big for the EPC1441 so you would either need to use two EPC1441, one EPC1 (OTP) or an EPC2 (re-programmable/ISP) - Wolfgang thomas daehler <thomas.daehler@beb.ch> wrote in message news:3B557BD0.3C042F84@beb.ch... > Hello > > As a newbie, who has to decide between these devices, > I found the following differencies: > Altera advantages: > -Better design tool (allows schematic entry) > -Chips are mask programmable (by third party) > Xilinx advantages: > -Cheaper boot proms > > Has anyone compared these two devices and can give me > further hints about advantages / disadvantages? > The amount of RAM and Logic blocks, the pricing and even > the archictecture seem to be almost the same for both devices. > Is that right? > > Thomas > >Article: 33148
> As a newbie, who has to decide between these devices, > I found the following differencies: > Altera advantages: > -Better design tool (allows schematic entry) I think Xilinx's WebPack is better (and has schematic entry too). JanArticle: 33149
thomas daehler wrote: > Hello > > As a newbie, who has to decide between these devices, > I found the following differencies: > Altera advantages: > -Better design tool (allows schematic entry) Xilinx also allows schematic entry, and also gives you better control over the implementation (floorplanning, device editor) when needed. > > -Chips are mask programmable (by third party) > Xilinx advantages: > -Cheaper boot proms > > Has anyone compared these two devices and can give me > further hints about advantages / disadvantages? > The amount of RAM and Logic blocks, the pricing and even > the archictecture seem to be almost the same for both devices. > Is that right? Depends on how you use it. The SpartanII architecture has some significant advantages over the Altera architecture for heavily arithmetic designs, for designs that use many small delay queues, and for certain designs with high bandwidth I/O. See the FAQ, question 14 at http://www.fpga-faq.com/FAQ_Pages/0014_Xilinx_vs_Altera.htm > > > Thomas -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com
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